Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7771721 |
1 |
|
|
T32 |
75187 |
|
T33 |
1124 |
|
T34 |
304 |
auto[1] |
5800785 |
1 |
|
|
T32 |
60548 |
|
T34 |
283 |
|
T20 |
17 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11192005 |
1 |
|
|
T32 |
113062 |
|
T33 |
1124 |
|
T34 |
436 |
auto[1] |
2380501 |
1 |
|
|
T32 |
22673 |
|
T34 |
151 |
|
T20 |
12 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7836065 |
1 |
|
|
T32 |
76662 |
|
T33 |
1124 |
|
T34 |
292 |
auto[1] |
5736441 |
1 |
|
|
T32 |
59073 |
|
T34 |
295 |
|
T20 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1667574 |
1 |
|
|
T32 |
17839 |
|
T34 |
61 |
|
T20 |
4 |
auto[1] |
auto[0] |
auto[1] |
1188954 |
1 |
|
|
T32 |
11034 |
|
T34 |
61 |
|
T20 |
10 |
auto[1] |
auto[1] |
auto[0] |
1688366 |
1 |
|
|
T32 |
18561 |
|
T34 |
83 |
|
T20 |
4 |
auto[1] |
auto[1] |
auto[1] |
1191547 |
1 |
|
|
T32 |
11639 |
|
T34 |
90 |
|
T20 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |