Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7839206 |
1 |
|
|
T32 |
73800 |
|
T33 |
1124 |
|
T34 |
266 |
| auto[1] |
5733300 |
1 |
|
|
T32 |
61935 |
|
T34 |
321 |
|
T20 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11188234 |
1 |
|
|
T32 |
112405 |
|
T33 |
1124 |
|
T34 |
403 |
| auto[1] |
2384272 |
1 |
|
|
T32 |
23330 |
|
T34 |
184 |
|
T20 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7808093 |
1 |
|
|
T32 |
74486 |
|
T33 |
1124 |
|
T34 |
273 |
| auto[1] |
5764413 |
1 |
|
|
T32 |
61249 |
|
T34 |
314 |
|
T20 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1696129 |
1 |
|
|
T32 |
18448 |
|
T34 |
52 |
|
T20 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1197871 |
1 |
|
|
T32 |
11383 |
|
T34 |
58 |
|
T20 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1684012 |
1 |
|
|
T32 |
19471 |
|
T34 |
78 |
|
T20 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1186401 |
1 |
|
|
T32 |
11947 |
|
T34 |
126 |
|
T26 |
3294 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |