Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7840980 |
1 |
|
|
T32 |
76067 |
|
T33 |
1124 |
|
T34 |
262 |
| auto[1] |
5731526 |
1 |
|
|
T32 |
59668 |
|
T34 |
325 |
|
T20 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11185294 |
1 |
|
|
T32 |
112743 |
|
T33 |
1124 |
|
T34 |
471 |
| auto[1] |
2387212 |
1 |
|
|
T32 |
22992 |
|
T34 |
116 |
|
T20 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7831005 |
1 |
|
|
T32 |
75592 |
|
T33 |
1124 |
|
T34 |
348 |
| auto[1] |
5741501 |
1 |
|
|
T32 |
60143 |
|
T34 |
239 |
|
T20 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1692661 |
1 |
|
|
T32 |
19814 |
|
T34 |
58 |
|
T20 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1204595 |
1 |
|
|
T32 |
11893 |
|
T34 |
48 |
|
T20 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1661628 |
1 |
|
|
T32 |
17337 |
|
T34 |
65 |
|
T20 |
12 |
| auto[1] |
auto[1] |
auto[1] |
1182617 |
1 |
|
|
T32 |
11099 |
|
T34 |
68 |
|
T20 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |