Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7787832 |
1 |
|
|
T32 |
75169 |
|
T33 |
1124 |
|
T34 |
381 |
| auto[1] |
5784674 |
1 |
|
|
T32 |
60566 |
|
T34 |
206 |
|
T20 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11198308 |
1 |
|
|
T32 |
113379 |
|
T33 |
1124 |
|
T34 |
515 |
| auto[1] |
2374198 |
1 |
|
|
T32 |
22356 |
|
T34 |
72 |
|
T20 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7836526 |
1 |
|
|
T32 |
77284 |
|
T33 |
1124 |
|
T34 |
371 |
| auto[1] |
5735980 |
1 |
|
|
T32 |
58451 |
|
T34 |
216 |
|
T20 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1683548 |
1 |
|
|
T32 |
18478 |
|
T34 |
85 |
|
T20 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1184160 |
1 |
|
|
T32 |
10947 |
|
T34 |
44 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1678234 |
1 |
|
|
T32 |
17617 |
|
T34 |
59 |
|
T20 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1190038 |
1 |
|
|
T32 |
11409 |
|
T34 |
28 |
|
T20 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |