Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7815978 |
1 |
|
|
T32 |
77306 |
|
T33 |
1124 |
|
T34 |
296 |
| auto[1] |
5756528 |
1 |
|
|
T32 |
58429 |
|
T34 |
291 |
|
T20 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11187389 |
1 |
|
|
T32 |
112274 |
|
T33 |
1124 |
|
T34 |
444 |
| auto[1] |
2385117 |
1 |
|
|
T32 |
23461 |
|
T34 |
143 |
|
T20 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7808937 |
1 |
|
|
T32 |
74996 |
|
T33 |
1124 |
|
T34 |
309 |
| auto[1] |
5763569 |
1 |
|
|
T32 |
60739 |
|
T34 |
278 |
|
T20 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1694574 |
1 |
|
|
T32 |
19774 |
|
T34 |
60 |
|
T26 |
4445 |
| auto[1] |
auto[0] |
auto[1] |
1195357 |
1 |
|
|
T32 |
12162 |
|
T34 |
82 |
|
T26 |
3258 |
| auto[1] |
auto[1] |
auto[0] |
1683878 |
1 |
|
|
T32 |
17504 |
|
T34 |
75 |
|
T26 |
4860 |
| auto[1] |
auto[1] |
auto[1] |
1189760 |
1 |
|
|
T32 |
11299 |
|
T34 |
61 |
|
T20 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |