Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7831168 |
1 |
|
|
T32 |
73489 |
|
T33 |
1124 |
|
T34 |
283 |
| auto[1] |
5741338 |
1 |
|
|
T32 |
62246 |
|
T34 |
304 |
|
T20 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11182697 |
1 |
|
|
T32 |
112419 |
|
T33 |
1124 |
|
T34 |
408 |
| auto[1] |
2389809 |
1 |
|
|
T32 |
23316 |
|
T34 |
179 |
|
T20 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7806471 |
1 |
|
|
T32 |
74584 |
|
T33 |
1124 |
|
T34 |
221 |
| auto[1] |
5766035 |
1 |
|
|
T32 |
61151 |
|
T34 |
366 |
|
T20 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1693579 |
1 |
|
|
T32 |
18525 |
|
T34 |
110 |
|
T20 |
6 |
| auto[1] |
auto[0] |
auto[1] |
1196700 |
1 |
|
|
T32 |
11552 |
|
T34 |
80 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1682647 |
1 |
|
|
T32 |
19310 |
|
T34 |
77 |
|
T20 |
18 |
| auto[1] |
auto[1] |
auto[1] |
1193109 |
1 |
|
|
T32 |
11764 |
|
T34 |
99 |
|
T20 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |