Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7795362 |
1 |
|
|
T32 |
75740 |
|
T33 |
1124 |
|
T34 |
159 |
| auto[1] |
5777144 |
1 |
|
|
T32 |
59995 |
|
T34 |
428 |
|
T20 |
56 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11206959 |
1 |
|
|
T32 |
113029 |
|
T33 |
1124 |
|
T34 |
465 |
| auto[1] |
2365547 |
1 |
|
|
T32 |
22706 |
|
T34 |
122 |
|
T20 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7859495 |
1 |
|
|
T32 |
76516 |
|
T33 |
1124 |
|
T34 |
320 |
| auto[1] |
5713011 |
1 |
|
|
T32 |
59219 |
|
T34 |
267 |
|
T20 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1669640 |
1 |
|
|
T32 |
18120 |
|
T34 |
46 |
|
T20 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1179179 |
1 |
|
|
T32 |
11278 |
|
T34 |
36 |
|
T20 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1677824 |
1 |
|
|
T32 |
18393 |
|
T34 |
99 |
|
T26 |
4641 |
| auto[1] |
auto[1] |
auto[1] |
1186368 |
1 |
|
|
T32 |
11428 |
|
T34 |
86 |
|
T20 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |