Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7803293 |
1 |
|
|
T32 |
77092 |
|
T33 |
1124 |
|
T34 |
302 |
| auto[1] |
5769213 |
1 |
|
|
T32 |
58643 |
|
T34 |
285 |
|
T20 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11189456 |
1 |
|
|
T32 |
112969 |
|
T33 |
1124 |
|
T34 |
481 |
| auto[1] |
2383050 |
1 |
|
|
T32 |
22766 |
|
T34 |
106 |
|
T20 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7816240 |
1 |
|
|
T32 |
77218 |
|
T33 |
1124 |
|
T34 |
357 |
| auto[1] |
5756266 |
1 |
|
|
T32 |
58517 |
|
T34 |
230 |
|
T20 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1691292 |
1 |
|
|
T32 |
17724 |
|
T34 |
51 |
|
T26 |
5485 |
| auto[1] |
auto[0] |
auto[1] |
1193674 |
1 |
|
|
T32 |
11155 |
|
T34 |
42 |
|
T20 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1681924 |
1 |
|
|
T32 |
18027 |
|
T34 |
73 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[1] |
1189376 |
1 |
|
|
T32 |
11611 |
|
T34 |
64 |
|
T20 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |