Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7816879 |
1 |
|
|
T32 |
74371 |
|
T33 |
1124 |
|
T34 |
291 |
| auto[1] |
5755627 |
1 |
|
|
T32 |
61364 |
|
T34 |
296 |
|
T20 |
61 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12843568 |
1 |
|
|
T32 |
127770 |
|
T33 |
1124 |
|
T34 |
501 |
| auto[1] |
728938 |
1 |
|
|
T32 |
7965 |
|
T34 |
86 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7824007 |
1 |
|
|
T32 |
72917 |
|
T33 |
1124 |
|
T34 |
176 |
| auto[1] |
5748499 |
1 |
|
|
T32 |
62818 |
|
T34 |
411 |
|
T20 |
41 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2516511 |
1 |
|
|
T32 |
27140 |
|
T34 |
117 |
|
T20 |
16 |
| auto[1] |
auto[0] |
auto[1] |
365474 |
1 |
|
|
T32 |
4062 |
|
T34 |
30 |
|
T20 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2503050 |
1 |
|
|
T32 |
27713 |
|
T34 |
208 |
|
T20 |
24 |
| auto[1] |
auto[1] |
auto[1] |
363464 |
1 |
|
|
T32 |
3903 |
|
T34 |
56 |
|
T26 |
997 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |