Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7843926 |
1 |
|
|
T32 |
74012 |
|
T33 |
1124 |
|
T34 |
307 |
| auto[1] |
5728580 |
1 |
|
|
T32 |
61723 |
|
T34 |
280 |
|
T20 |
59 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12838556 |
1 |
|
|
T32 |
128163 |
|
T33 |
1124 |
|
T34 |
537 |
| auto[1] |
733950 |
1 |
|
|
T32 |
7572 |
|
T34 |
50 |
|
T20 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7780348 |
1 |
|
|
T32 |
75815 |
|
T33 |
1124 |
|
T34 |
333 |
| auto[1] |
5792158 |
1 |
|
|
T32 |
59920 |
|
T34 |
254 |
|
T20 |
37 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2548807 |
1 |
|
|
T32 |
26882 |
|
T34 |
75 |
|
T20 |
12 |
| auto[1] |
auto[0] |
auto[1] |
370558 |
1 |
|
|
T32 |
3842 |
|
T34 |
15 |
|
T26 |
1103 |
| auto[1] |
auto[1] |
auto[0] |
2509401 |
1 |
|
|
T32 |
25466 |
|
T34 |
129 |
|
T20 |
24 |
| auto[1] |
auto[1] |
auto[1] |
363392 |
1 |
|
|
T32 |
3730 |
|
T34 |
35 |
|
T20 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |