Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 942
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T94 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3465850233 Aug 11 06:40:06 PM PDT 24 Aug 11 06:40:06 PM PDT 24 16787373 ps
T107 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2717117336 Aug 11 06:39:55 PM PDT 24 Aug 11 06:39:56 PM PDT 24 33635017 ps
T767 /workspace/coverage/cover_reg_top/40.gpio_intr_test.846988298 Aug 11 06:40:10 PM PDT 24 Aug 11 06:40:11 PM PDT 24 28639668 ps
T768 /workspace/coverage/cover_reg_top/39.gpio_intr_test.463835495 Aug 11 06:40:07 PM PDT 24 Aug 11 06:40:08 PM PDT 24 14192926 ps
T769 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.134564579 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:57 PM PDT 24 51224140 ps
T108 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4029590666 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:57 PM PDT 24 114580385 ps
T770 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3479110048 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:57 PM PDT 24 135767095 ps
T771 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2953254222 Aug 11 06:39:52 PM PDT 24 Aug 11 06:39:53 PM PDT 24 23528640 ps
T109 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2378266326 Aug 11 06:39:57 PM PDT 24 Aug 11 06:39:58 PM PDT 24 21398932 ps
T772 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3024343386 Aug 11 06:40:03 PM PDT 24 Aug 11 06:40:04 PM PDT 24 14048202 ps
T773 /workspace/coverage/cover_reg_top/25.gpio_intr_test.97282690 Aug 11 06:40:04 PM PDT 24 Aug 11 06:40:05 PM PDT 24 25022215 ps
T774 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3067528632 Aug 11 06:40:02 PM PDT 24 Aug 11 06:40:03 PM PDT 24 119290131 ps
T110 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3451685574 Aug 11 06:40:03 PM PDT 24 Aug 11 06:40:04 PM PDT 24 156879012 ps
T775 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2793116152 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:57 PM PDT 24 11145989 ps
T776 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3511368840 Aug 11 06:40:00 PM PDT 24 Aug 11 06:40:01 PM PDT 24 15924971 ps
T95 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2204510854 Aug 11 06:39:53 PM PDT 24 Aug 11 06:39:54 PM PDT 24 13599295 ps
T54 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2683856094 Aug 11 06:39:55 PM PDT 24 Aug 11 06:39:56 PM PDT 24 186883340 ps
T777 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1207174310 Aug 11 06:39:55 PM PDT 24 Aug 11 06:39:56 PM PDT 24 33649968 ps
T778 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1789761879 Aug 11 06:39:53 PM PDT 24 Aug 11 06:39:54 PM PDT 24 18445396 ps
T779 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1233691594 Aug 11 06:39:53 PM PDT 24 Aug 11 06:39:57 PM PDT 24 275398601 ps
T780 /workspace/coverage/cover_reg_top/4.gpio_intr_test.178029925 Aug 11 06:39:55 PM PDT 24 Aug 11 06:39:56 PM PDT 24 16218057 ps
T781 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.128835725 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:57 PM PDT 24 38375259 ps
T782 /workspace/coverage/cover_reg_top/6.gpio_intr_test.4121264991 Aug 11 06:39:58 PM PDT 24 Aug 11 06:39:59 PM PDT 24 75026256 ps
T783 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3035532337 Aug 11 06:39:57 PM PDT 24 Aug 11 06:39:58 PM PDT 24 43346954 ps
T784 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.524683772 Aug 11 06:40:02 PM PDT 24 Aug 11 06:40:04 PM PDT 24 581626914 ps
T785 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2260852050 Aug 11 06:39:55 PM PDT 24 Aug 11 06:39:56 PM PDT 24 18944541 ps
T786 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4017124565 Aug 11 06:41:06 PM PDT 24 Aug 11 06:41:07 PM PDT 24 29480894 ps
T787 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1844815039 Aug 11 06:39:55 PM PDT 24 Aug 11 06:39:56 PM PDT 24 139146845 ps
T788 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2107457255 Aug 11 06:40:03 PM PDT 24 Aug 11 06:40:04 PM PDT 24 125384567 ps
T789 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3425826517 Aug 11 06:40:22 PM PDT 24 Aug 11 06:40:23 PM PDT 24 29222752 ps
T790 /workspace/coverage/cover_reg_top/31.gpio_intr_test.549910823 Aug 11 06:40:09 PM PDT 24 Aug 11 06:40:10 PM PDT 24 15528105 ps
T791 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3841254147 Aug 11 06:39:58 PM PDT 24 Aug 11 06:39:59 PM PDT 24 102779912 ps
T792 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1874104391 Aug 11 06:39:53 PM PDT 24 Aug 11 06:39:54 PM PDT 24 33227996 ps
T793 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1291677515 Aug 11 06:39:50 PM PDT 24 Aug 11 06:39:51 PM PDT 24 81127584 ps
T794 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3277273168 Aug 11 06:39:54 PM PDT 24 Aug 11 06:39:55 PM PDT 24 57832196 ps
T795 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3100931515 Aug 11 06:40:07 PM PDT 24 Aug 11 06:40:08 PM PDT 24 20452072 ps
T796 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3935887263 Aug 11 06:39:57 PM PDT 24 Aug 11 06:39:59 PM PDT 24 53458728 ps
T113 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3116340094 Aug 11 06:40:03 PM PDT 24 Aug 11 06:40:05 PM PDT 24 572675980 ps
T797 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2256426023 Aug 11 06:39:57 PM PDT 24 Aug 11 06:39:58 PM PDT 24 94429767 ps
T798 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.948015552 Aug 11 06:40:03 PM PDT 24 Aug 11 06:40:04 PM PDT 24 111298424 ps
T799 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1448041089 Aug 11 06:40:04 PM PDT 24 Aug 11 06:40:06 PM PDT 24 41791677 ps
T800 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.448009884 Aug 11 06:39:55 PM PDT 24 Aug 11 06:39:56 PM PDT 24 75379083 ps
T96 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1593509777 Aug 11 06:39:55 PM PDT 24 Aug 11 06:39:56 PM PDT 24 12397342 ps
T801 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3959576934 Aug 11 06:40:08 PM PDT 24 Aug 11 06:40:09 PM PDT 24 40304237 ps
T802 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1511347320 Aug 11 06:39:58 PM PDT 24 Aug 11 06:39:59 PM PDT 24 59608347 ps
T803 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1278062096 Aug 11 06:39:59 PM PDT 24 Aug 11 06:39:59 PM PDT 24 42144221 ps
T804 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1259898103 Aug 11 06:39:56 PM PDT 24 Aug 11 06:40:00 PM PDT 24 118297756 ps
T52 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.907008174 Aug 11 06:39:57 PM PDT 24 Aug 11 06:39:58 PM PDT 24 723751666 ps
T805 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4215749181 Aug 11 06:41:06 PM PDT 24 Aug 11 06:41:07 PM PDT 24 38694802 ps
T806 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3647358212 Aug 11 06:40:52 PM PDT 24 Aug 11 06:40:54 PM PDT 24 27262513 ps
T807 /workspace/coverage/cover_reg_top/24.gpio_intr_test.549919844 Aug 11 06:40:05 PM PDT 24 Aug 11 06:40:05 PM PDT 24 41621082 ps
T808 /workspace/coverage/cover_reg_top/47.gpio_intr_test.824528190 Aug 11 06:40:13 PM PDT 24 Aug 11 06:40:14 PM PDT 24 36765914 ps
T809 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1435094627 Aug 11 06:39:58 PM PDT 24 Aug 11 06:39:59 PM PDT 24 44294647 ps
T810 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3713131059 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:57 PM PDT 24 64952096 ps
T811 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1560548374 Aug 11 06:40:03 PM PDT 24 Aug 11 06:40:05 PM PDT 24 155960697 ps
T812 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.447237625 Aug 11 06:39:53 PM PDT 24 Aug 11 06:39:54 PM PDT 24 42204652 ps
T813 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3712907439 Aug 11 06:39:58 PM PDT 24 Aug 11 06:39:59 PM PDT 24 129416591 ps
T814 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2307626750 Aug 11 06:40:01 PM PDT 24 Aug 11 06:40:02 PM PDT 24 508357210 ps
T815 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2918205848 Aug 11 06:39:58 PM PDT 24 Aug 11 06:40:01 PM PDT 24 176572268 ps
T816 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3443550681 Aug 11 06:40:17 PM PDT 24 Aug 11 06:40:17 PM PDT 24 10728410 ps
T817 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2719436273 Aug 11 06:40:06 PM PDT 24 Aug 11 06:40:07 PM PDT 24 61249323 ps
T818 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4043959728 Aug 11 06:39:55 PM PDT 24 Aug 11 06:39:55 PM PDT 24 26905877 ps
T819 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2887484202 Aug 11 06:40:04 PM PDT 24 Aug 11 06:40:05 PM PDT 24 59307327 ps
T99 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.639631426 Aug 11 06:40:08 PM PDT 24 Aug 11 06:40:08 PM PDT 24 39844777 ps
T820 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1609109522 Aug 11 06:39:47 PM PDT 24 Aug 11 06:39:48 PM PDT 24 26901896 ps
T821 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.61313684 Aug 11 06:39:57 PM PDT 24 Aug 11 06:39:58 PM PDT 24 150103053 ps
T822 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1181299886 Aug 11 06:40:05 PM PDT 24 Aug 11 06:40:05 PM PDT 24 16960883 ps
T823 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1116081133 Aug 11 06:39:59 PM PDT 24 Aug 11 06:40:00 PM PDT 24 107641295 ps
T824 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1400183488 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:57 PM PDT 24 56479822 ps
T825 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1434847160 Aug 11 06:39:57 PM PDT 24 Aug 11 06:39:58 PM PDT 24 149422691 ps
T826 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2916182477 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:56 PM PDT 24 26870386 ps
T827 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2715506726 Aug 11 06:40:06 PM PDT 24 Aug 11 06:40:07 PM PDT 24 16325004 ps
T828 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3135508956 Aug 11 06:40:08 PM PDT 24 Aug 11 06:40:09 PM PDT 24 45217620 ps
T55 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1455972658 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:57 PM PDT 24 441588135 ps
T829 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.208933750 Aug 11 06:40:05 PM PDT 24 Aug 11 06:40:08 PM PDT 24 167754853 ps
T830 /workspace/coverage/cover_reg_top/26.gpio_intr_test.512235533 Aug 11 06:40:07 PM PDT 24 Aug 11 06:40:08 PM PDT 24 56639629 ps
T831 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2575010073 Aug 11 06:40:00 PM PDT 24 Aug 11 06:40:01 PM PDT 24 74662263 ps
T832 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.813425708 Aug 11 06:40:00 PM PDT 24 Aug 11 06:40:03 PM PDT 24 1016244047 ps
T833 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3073866810 Aug 11 06:39:57 PM PDT 24 Aug 11 06:40:00 PM PDT 24 316524613 ps
T100 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.127085638 Aug 11 06:39:59 PM PDT 24 Aug 11 06:40:02 PM PDT 24 266895528 ps
T97 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3251393527 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:57 PM PDT 24 11020600 ps
T834 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1618940306 Aug 11 06:39:50 PM PDT 24 Aug 11 06:39:51 PM PDT 24 20811567 ps
T835 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3897351084 Aug 11 06:40:01 PM PDT 24 Aug 11 06:40:04 PM PDT 24 115901927 ps
T836 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1657527607 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:57 PM PDT 24 57045086 ps
T837 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4282759411 Aug 11 06:39:48 PM PDT 24 Aug 11 06:39:49 PM PDT 24 64144711 ps
T838 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2489544601 Aug 11 06:40:09 PM PDT 24 Aug 11 06:40:10 PM PDT 24 22737877 ps
T98 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2175879314 Aug 11 06:39:55 PM PDT 24 Aug 11 06:39:56 PM PDT 24 13753036 ps
T839 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.449467754 Aug 11 06:39:57 PM PDT 24 Aug 11 06:40:01 PM PDT 24 224413137 ps
T56 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2630650757 Aug 11 06:40:00 PM PDT 24 Aug 11 06:40:01 PM PDT 24 212757094 ps
T840 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1529473341 Aug 11 06:40:09 PM PDT 24 Aug 11 06:40:10 PM PDT 24 64910562 ps
T841 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3786198318 Aug 11 06:39:56 PM PDT 24 Aug 11 06:39:58 PM PDT 24 53865140 ps
T842 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.4094560310 Aug 11 06:39:58 PM PDT 24 Aug 11 06:39:59 PM PDT 24 65384316 ps
T843 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1420735827 Aug 11 07:00:58 PM PDT 24 Aug 11 07:00:59 PM PDT 24 107616701 ps
T844 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3636949583 Aug 11 07:01:04 PM PDT 24 Aug 11 07:01:06 PM PDT 24 521534420 ps
T845 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3379656158 Aug 11 07:01:00 PM PDT 24 Aug 11 07:01:01 PM PDT 24 234032278 ps
T846 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3109759000 Aug 11 07:00:42 PM PDT 24 Aug 11 07:00:43 PM PDT 24 96143211 ps
T847 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1908307995 Aug 11 07:00:48 PM PDT 24 Aug 11 07:00:50 PM PDT 24 51192553 ps
T848 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2694804022 Aug 11 07:01:08 PM PDT 24 Aug 11 07:01:09 PM PDT 24 1526518811 ps
T849 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.668636017 Aug 11 07:01:00 PM PDT 24 Aug 11 07:01:01 PM PDT 24 117024700 ps
T850 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2088542011 Aug 11 07:00:49 PM PDT 24 Aug 11 07:00:50 PM PDT 24 169062583 ps
T851 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1236405099 Aug 11 07:00:42 PM PDT 24 Aug 11 07:00:43 PM PDT 24 51245200 ps
T852 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.311484864 Aug 11 07:00:48 PM PDT 24 Aug 11 07:00:49 PM PDT 24 37318428 ps
T853 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.863699789 Aug 11 07:01:09 PM PDT 24 Aug 11 07:01:11 PM PDT 24 690900456 ps
T854 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1992837924 Aug 11 07:00:53 PM PDT 24 Aug 11 07:00:54 PM PDT 24 170176817 ps
T855 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3613865321 Aug 11 07:01:05 PM PDT 24 Aug 11 07:01:06 PM PDT 24 297639255 ps
T856 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4160693128 Aug 11 07:00:33 PM PDT 24 Aug 11 07:00:34 PM PDT 24 215109071 ps
T857 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3732544281 Aug 11 07:00:57 PM PDT 24 Aug 11 07:00:58 PM PDT 24 40641403 ps
T858 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3745081197 Aug 11 07:00:53 PM PDT 24 Aug 11 07:00:54 PM PDT 24 43866520 ps
T859 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.845401881 Aug 11 07:00:59 PM PDT 24 Aug 11 07:01:00 PM PDT 24 40945147 ps
T860 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1763499969 Aug 11 07:00:54 PM PDT 24 Aug 11 07:00:55 PM PDT 24 267353378 ps
T861 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1652970158 Aug 11 07:00:54 PM PDT 24 Aug 11 07:00:55 PM PDT 24 37137723 ps
T862 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.61792267 Aug 11 07:00:43 PM PDT 24 Aug 11 07:00:44 PM PDT 24 37148710 ps
T863 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3628211566 Aug 11 07:00:30 PM PDT 24 Aug 11 07:00:31 PM PDT 24 180248931 ps
T864 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.514549155 Aug 11 07:00:42 PM PDT 24 Aug 11 07:00:43 PM PDT 24 243983987 ps
T865 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.359454991 Aug 11 07:00:32 PM PDT 24 Aug 11 07:00:33 PM PDT 24 239421936 ps
T866 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3722486495 Aug 11 07:01:04 PM PDT 24 Aug 11 07:01:06 PM PDT 24 68764840 ps
T867 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2362129700 Aug 11 07:01:06 PM PDT 24 Aug 11 07:01:07 PM PDT 24 62158430 ps
T868 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.415036842 Aug 11 07:00:40 PM PDT 24 Aug 11 07:00:42 PM PDT 24 220456861 ps
T869 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.302943577 Aug 11 07:00:37 PM PDT 24 Aug 11 07:00:39 PM PDT 24 260352989 ps
T870 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2535205817 Aug 11 07:01:19 PM PDT 24 Aug 11 07:01:21 PM PDT 24 78423560 ps
T871 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3596136910 Aug 11 07:00:52 PM PDT 24 Aug 11 07:00:53 PM PDT 24 93025685 ps
T872 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.220863308 Aug 11 07:00:42 PM PDT 24 Aug 11 07:00:43 PM PDT 24 45632128 ps
T873 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1886580040 Aug 11 07:01:06 PM PDT 24 Aug 11 07:01:08 PM PDT 24 613313032 ps
T874 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.463387051 Aug 11 07:00:46 PM PDT 24 Aug 11 07:00:48 PM PDT 24 375847813 ps
T875 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1037083339 Aug 11 07:01:05 PM PDT 24 Aug 11 07:01:06 PM PDT 24 52404723 ps
T876 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1887953589 Aug 11 07:01:04 PM PDT 24 Aug 11 07:01:06 PM PDT 24 74677616 ps
T877 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.250089009 Aug 11 07:00:36 PM PDT 24 Aug 11 07:00:37 PM PDT 24 63788206 ps
T878 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3825621407 Aug 11 07:00:49 PM PDT 24 Aug 11 07:00:50 PM PDT 24 57018802 ps
T879 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3023382564 Aug 11 07:00:53 PM PDT 24 Aug 11 07:00:54 PM PDT 24 106913471 ps
T880 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2204571624 Aug 11 07:00:46 PM PDT 24 Aug 11 07:00:48 PM PDT 24 124307630 ps
T881 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2479688995 Aug 11 07:00:43 PM PDT 24 Aug 11 07:00:44 PM PDT 24 74920849 ps
T882 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.945644907 Aug 11 07:00:46 PM PDT 24 Aug 11 07:00:47 PM PDT 24 33027232 ps
T883 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1060010262 Aug 11 07:01:00 PM PDT 24 Aug 11 07:01:01 PM PDT 24 31433168 ps
T884 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2566738531 Aug 11 07:00:36 PM PDT 24 Aug 11 07:00:36 PM PDT 24 84558792 ps
T885 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2358216582 Aug 11 07:00:34 PM PDT 24 Aug 11 07:00:36 PM PDT 24 177895727 ps
T886 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3123574477 Aug 11 07:00:49 PM PDT 24 Aug 11 07:00:50 PM PDT 24 191939933 ps
T887 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3262356973 Aug 11 07:00:59 PM PDT 24 Aug 11 07:01:00 PM PDT 24 80653952 ps
T888 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3368736580 Aug 11 07:00:47 PM PDT 24 Aug 11 07:00:48 PM PDT 24 124465712 ps
T889 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.291375494 Aug 11 07:00:29 PM PDT 24 Aug 11 07:00:30 PM PDT 24 43456817 ps
T890 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.954187885 Aug 11 07:00:59 PM PDT 24 Aug 11 07:00:59 PM PDT 24 22298925 ps
T891 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3855111682 Aug 11 07:01:04 PM PDT 24 Aug 11 07:01:06 PM PDT 24 434450189 ps
T892 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1458495914 Aug 11 07:01:04 PM PDT 24 Aug 11 07:01:05 PM PDT 24 24155279 ps
T893 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1656684980 Aug 11 07:01:05 PM PDT 24 Aug 11 07:01:07 PM PDT 24 292709776 ps
T894 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.919646049 Aug 11 07:00:47 PM PDT 24 Aug 11 07:00:48 PM PDT 24 87098055 ps
T895 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4038786809 Aug 11 07:00:35 PM PDT 24 Aug 11 07:00:37 PM PDT 24 327064487 ps
T896 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3907102876 Aug 11 07:00:30 PM PDT 24 Aug 11 07:00:31 PM PDT 24 70401943 ps
T897 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3849351903 Aug 11 07:00:59 PM PDT 24 Aug 11 07:01:00 PM PDT 24 46234085 ps
T898 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3125154312 Aug 11 07:01:11 PM PDT 24 Aug 11 07:01:12 PM PDT 24 29760570 ps
T899 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3601102660 Aug 11 07:00:53 PM PDT 24 Aug 11 07:00:54 PM PDT 24 71110490 ps
T900 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2227084121 Aug 11 07:01:14 PM PDT 24 Aug 11 07:01:15 PM PDT 24 751173342 ps
T901 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2454440560 Aug 11 07:00:42 PM PDT 24 Aug 11 07:00:43 PM PDT 24 74508298 ps
T902 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2566295741 Aug 11 07:00:47 PM PDT 24 Aug 11 07:00:48 PM PDT 24 83018122 ps
T903 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1976284217 Aug 11 07:00:47 PM PDT 24 Aug 11 07:00:48 PM PDT 24 617333407 ps
T904 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2314357215 Aug 11 07:00:54 PM PDT 24 Aug 11 07:00:55 PM PDT 24 96818390 ps
T905 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.89171344 Aug 11 07:00:35 PM PDT 24 Aug 11 07:00:36 PM PDT 24 248350068 ps
T906 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2149329424 Aug 11 07:00:53 PM PDT 24 Aug 11 07:00:54 PM PDT 24 174304032 ps
T907 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4267306350 Aug 11 07:00:55 PM PDT 24 Aug 11 07:00:56 PM PDT 24 149243283 ps
T908 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2863717134 Aug 11 07:01:09 PM PDT 24 Aug 11 07:01:10 PM PDT 24 49323288 ps
T909 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2602913773 Aug 11 07:00:29 PM PDT 24 Aug 11 07:00:30 PM PDT 24 130031993 ps
T910 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3383498707 Aug 11 07:01:05 PM PDT 24 Aug 11 07:01:06 PM PDT 24 43262455 ps
T911 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4187483116 Aug 11 07:00:59 PM PDT 24 Aug 11 07:01:01 PM PDT 24 148334257 ps
T912 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3515871928 Aug 11 07:00:48 PM PDT 24 Aug 11 07:00:49 PM PDT 24 79181348 ps
T913 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3807626356 Aug 11 07:00:28 PM PDT 24 Aug 11 07:00:30 PM PDT 24 53703115 ps
T914 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2294834294 Aug 11 07:00:48 PM PDT 24 Aug 11 07:00:49 PM PDT 24 76632468 ps
T915 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.764299069 Aug 11 07:00:55 PM PDT 24 Aug 11 07:00:56 PM PDT 24 74795328 ps
T916 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2979282810 Aug 11 07:00:34 PM PDT 24 Aug 11 07:00:35 PM PDT 24 166737458 ps
T917 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2793000060 Aug 11 07:00:47 PM PDT 24 Aug 11 07:00:48 PM PDT 24 337550253 ps
T918 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.248621783 Aug 11 07:00:39 PM PDT 24 Aug 11 07:00:41 PM PDT 24 329152285 ps
T919 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.4073598518 Aug 11 07:00:39 PM PDT 24 Aug 11 07:00:40 PM PDT 24 28781137 ps
T920 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.881491667 Aug 11 07:00:42 PM PDT 24 Aug 11 07:00:43 PM PDT 24 34381007 ps
T921 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1625785691 Aug 11 07:01:08 PM PDT 24 Aug 11 07:01:09 PM PDT 24 294072261 ps
T922 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2635720867 Aug 11 07:00:48 PM PDT 24 Aug 11 07:00:50 PM PDT 24 1811849333 ps
T923 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.596473910 Aug 11 07:00:42 PM PDT 24 Aug 11 07:00:43 PM PDT 24 104168572 ps
T924 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2980301900 Aug 11 07:00:55 PM PDT 24 Aug 11 07:00:56 PM PDT 24 37426161 ps
T925 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3088259422 Aug 11 07:01:05 PM PDT 24 Aug 11 07:01:06 PM PDT 24 214598881 ps
T926 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2232998088 Aug 11 07:00:52 PM PDT 24 Aug 11 07:00:53 PM PDT 24 89500074 ps
T927 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3779925712 Aug 11 07:00:40 PM PDT 24 Aug 11 07:00:41 PM PDT 24 55776837 ps
T928 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.348907060 Aug 11 07:00:59 PM PDT 24 Aug 11 07:01:00 PM PDT 24 25578619 ps
T929 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2489724149 Aug 11 07:00:59 PM PDT 24 Aug 11 07:01:00 PM PDT 24 183655927 ps
T930 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3913132187 Aug 11 07:00:41 PM PDT 24 Aug 11 07:00:42 PM PDT 24 29813257 ps
T931 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1842829957 Aug 11 07:01:08 PM PDT 24 Aug 11 07:01:09 PM PDT 24 98356258 ps
T932 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3477042005 Aug 11 07:01:04 PM PDT 24 Aug 11 07:01:05 PM PDT 24 52001667 ps
T933 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1968533415 Aug 11 07:01:00 PM PDT 24 Aug 11 07:01:01 PM PDT 24 290153459 ps
T934 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4269070295 Aug 11 07:01:05 PM PDT 24 Aug 11 07:01:06 PM PDT 24 50035605 ps
T935 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1378982981 Aug 11 07:00:53 PM PDT 24 Aug 11 07:00:54 PM PDT 24 31052991 ps
T936 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1198813417 Aug 11 07:01:05 PM PDT 24 Aug 11 07:01:07 PM PDT 24 254909453 ps
T937 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3333279754 Aug 11 07:01:04 PM PDT 24 Aug 11 07:01:06 PM PDT 24 96492216 ps
T938 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4159026254 Aug 11 07:00:42 PM PDT 24 Aug 11 07:00:43 PM PDT 24 346934551 ps
T939 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3821739124 Aug 11 07:00:52 PM PDT 24 Aug 11 07:00:53 PM PDT 24 33492369 ps
T940 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3928065646 Aug 11 07:00:54 PM PDT 24 Aug 11 07:00:55 PM PDT 24 65590242 ps
T941 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.159398075 Aug 11 07:00:39 PM PDT 24 Aug 11 07:00:40 PM PDT 24 35946940 ps
T942 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.995431124 Aug 11 07:00:35 PM PDT 24 Aug 11 07:00:37 PM PDT 24 45106489 ps

Test location /workspace/coverage/default/28.gpio_stress_all.1952410967
Short name T26
Test name
Test status
Simulation time 2134545809 ps
CPU time 54.2 seconds
Started Aug 11 06:12:40 PM PDT 24
Finished Aug 11 06:13:34 PM PDT 24
Peak memory 198604 kb
Host smart-a6efa330-8688-4fe5-9242-235ef2a3686f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952410967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1952410967
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3897647972
Short name T33
Test name
Test status
Simulation time 62927568 ps
CPU time 2.54 seconds
Started Aug 11 06:11:47 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 198632 kb
Host smart-6e52aa9e-0cea-462f-a36b-34fd50cb0c61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897647972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3897647972
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1617278682
Short name T8
Test name
Test status
Simulation time 33696564899 ps
CPU time 431.41 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:19:53 PM PDT 24
Peak memory 198880 kb
Host smart-24ef01db-d298-4554-bfdd-ffde053e9f8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1617278682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1617278682
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1271689478
Short name T45
Test name
Test status
Simulation time 184490712 ps
CPU time 0.97 seconds
Started Aug 11 06:11:54 PM PDT 24
Finished Aug 11 06:11:55 PM PDT 24
Peak memory 215536 kb
Host smart-ae13fbeb-c415-4499-a4af-ea65077f70ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271689478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1271689478
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.206197006
Short name T85
Test name
Test status
Simulation time 60826885 ps
CPU time 0.83 seconds
Started Aug 11 06:39:49 PM PDT 24
Finished Aug 11 06:39:50 PM PDT 24
Peak memory 196508 kb
Host smart-c4b48d60-4b05-4074-b421-1f8b4be15a5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206197006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.206197006
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3074889698
Short name T41
Test name
Test status
Simulation time 463825407 ps
CPU time 1.39 seconds
Started Aug 11 06:39:54 PM PDT 24
Finished Aug 11 06:39:55 PM PDT 24
Peak memory 198800 kb
Host smart-957e32ae-c701-4979-8ad2-dfff34b9579c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074889698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3074889698
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2586435338
Short name T48
Test name
Test status
Simulation time 258466748 ps
CPU time 0.6 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:41 PM PDT 24
Peak memory 194668 kb
Host smart-685ca5ca-dc6a-410d-8961-da69cfde7c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586435338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2586435338
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_full_random.4225461631
Short name T20
Test name
Test status
Simulation time 80465972 ps
CPU time 1 seconds
Started Aug 11 06:11:58 PM PDT 24
Finished Aug 11 06:11:59 PM PDT 24
Peak memory 197560 kb
Host smart-813fecd1-e815-4c34-8976-324db205b320
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225461631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.4225461631
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.92589393
Short name T101
Test name
Test status
Simulation time 67104470 ps
CPU time 0.84 seconds
Started Aug 11 06:40:01 PM PDT 24
Finished Aug 11 06:40:02 PM PDT 24
Peak memory 197084 kb
Host smart-061d1771-c5e4-490b-bb7e-dc96e5ec5b71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92589393 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.gpio_same_csr_outstanding.92589393
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2887553342
Short name T43
Test name
Test status
Simulation time 248053230 ps
CPU time 1.09 seconds
Started Aug 11 06:39:59 PM PDT 24
Finished Aug 11 06:40:00 PM PDT 24
Peak memory 198664 kb
Host smart-eb818bce-31a9-4e87-b55d-6a4985003490
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887553342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2887553342
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1291677515
Short name T793
Test name
Test status
Simulation time 81127584 ps
CPU time 1.16 seconds
Started Aug 11 06:39:50 PM PDT 24
Finished Aug 11 06:39:51 PM PDT 24
Peak memory 198768 kb
Host smart-4a0d1d4b-d796-42e3-9fba-0a4f4ec80952
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291677515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1291677515
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3250357994
Short name T115
Test name
Test status
Simulation time 49071176277 ps
CPU time 91.81 seconds
Started Aug 11 06:11:56 PM PDT 24
Finished Aug 11 06:13:28 PM PDT 24
Peak memory 192064 kb
Host smart-0b0eb09d-1c31-4186-90d6-753cd88e24c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250357994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3250357994
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3151362789
Short name T91
Test name
Test status
Simulation time 232591995 ps
CPU time 0.87 seconds
Started Aug 11 06:39:53 PM PDT 24
Finished Aug 11 06:39:54 PM PDT 24
Peak memory 196812 kb
Host smart-80a0c19f-6323-477b-ab41-f7d9ad06287c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151362789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3151362789
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1381200223
Short name T90
Test name
Test status
Simulation time 337535608 ps
CPU time 3.43 seconds
Started Aug 11 06:39:59 PM PDT 24
Finished Aug 11 06:40:03 PM PDT 24
Peak memory 198592 kb
Host smart-84a1b9ef-348c-40cb-a776-ca2118360607
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381200223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1381200223
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3268743971
Short name T751
Test name
Test status
Simulation time 35764211 ps
CPU time 0.65 seconds
Started Aug 11 06:39:53 PM PDT 24
Finished Aug 11 06:39:54 PM PDT 24
Peak memory 195796 kb
Host smart-d45d9d03-f6ec-4cf8-8ccf-2f093fd9f060
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268743971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3268743971
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1609109522
Short name T820
Test name
Test status
Simulation time 26901896 ps
CPU time 1.2 seconds
Started Aug 11 06:39:47 PM PDT 24
Finished Aug 11 06:39:48 PM PDT 24
Peak memory 198828 kb
Host smart-cb56b050-0d52-407c-8a38-f9149b4b9598
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609109522 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1609109522
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2793116152
Short name T775
Test name
Test status
Simulation time 11145989 ps
CPU time 0.56 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 194116 kb
Host smart-eca5e6b0-8b42-4fd5-8880-c5fd7817e394
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793116152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2793116152
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1172874721
Short name T731
Test name
Test status
Simulation time 35736472 ps
CPU time 0.64 seconds
Started Aug 11 06:39:54 PM PDT 24
Finished Aug 11 06:39:55 PM PDT 24
Peak memory 194804 kb
Host smart-f4381e85-1067-4c6b-b148-3e972403542f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172874721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1172874721
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4282759411
Short name T837
Test name
Test status
Simulation time 64144711 ps
CPU time 0.78 seconds
Started Aug 11 06:39:48 PM PDT 24
Finished Aug 11 06:39:49 PM PDT 24
Peak memory 197064 kb
Host smart-13b52100-7a67-4d72-81c4-02fa3050b86b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282759411 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.4282759411
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3786198318
Short name T841
Test name
Test status
Simulation time 53865140 ps
CPU time 1.54 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 198828 kb
Host smart-6c3370e5-ede3-4be1-b720-305c18d7006e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786198318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3786198318
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1434847160
Short name T825
Test name
Test status
Simulation time 149422691 ps
CPU time 0.86 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 197976 kb
Host smart-c8b23062-0585-4aa5-b605-09f57c38c28c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434847160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1434847160
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3841254147
Short name T791
Test name
Test status
Simulation time 102779912 ps
CPU time 0.77 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 197448 kb
Host smart-b4bcc039-5f83-4707-bada-317910403f13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841254147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3841254147
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.127085638
Short name T100
Test name
Test status
Simulation time 266895528 ps
CPU time 2.05 seconds
Started Aug 11 06:39:59 PM PDT 24
Finished Aug 11 06:40:02 PM PDT 24
Peak memory 197396 kb
Host smart-f3df543c-bb78-4510-b26f-86a1d1d8cca1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127085638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.127085638
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.4098080501
Short name T93
Test name
Test status
Simulation time 39543682 ps
CPU time 0.59 seconds
Started Aug 11 06:39:59 PM PDT 24
Finished Aug 11 06:40:00 PM PDT 24
Peak memory 195424 kb
Host smart-227b46a5-2bb0-4712-ad8f-1e939cd77474
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098080501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.4098080501
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2093327760
Short name T758
Test name
Test status
Simulation time 18672745 ps
CPU time 0.67 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 198520 kb
Host smart-bc783c7e-8ddd-41b0-8154-3c6e6b8889dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093327760 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2093327760
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2855048120
Short name T89
Test name
Test status
Simulation time 47460533 ps
CPU time 0.6 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 195580 kb
Host smart-784ae577-8590-43b6-ad1e-58e88544af2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855048120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2855048120
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3511368840
Short name T776
Test name
Test status
Simulation time 15924971 ps
CPU time 0.62 seconds
Started Aug 11 06:40:00 PM PDT 24
Finished Aug 11 06:40:01 PM PDT 24
Peak memory 194528 kb
Host smart-113b86c3-a6a4-4463-8bd7-041c06cd8448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511368840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3511368840
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.133908395
Short name T735
Test name
Test status
Simulation time 88259952 ps
CPU time 1.9 seconds
Started Aug 11 06:40:02 PM PDT 24
Finished Aug 11 06:40:04 PM PDT 24
Peak memory 198816 kb
Host smart-872a4e72-9ee1-4498-94a6-01904a0f992c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133908395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.133908395
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.61313684
Short name T821
Test name
Test status
Simulation time 150103053 ps
CPU time 0.87 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 197700 kb
Host smart-42718ca6-870f-4a33-8e0a-33e07bec52bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61313684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_tl_intg_err.61313684
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2256426023
Short name T797
Test name
Test status
Simulation time 94429767 ps
CPU time 0.98 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 198600 kb
Host smart-e033528f-f87f-46d4-855f-037770a8ce6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256426023 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2256426023
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2204510854
Short name T95
Test name
Test status
Simulation time 13599295 ps
CPU time 0.67 seconds
Started Aug 11 06:39:53 PM PDT 24
Finished Aug 11 06:39:54 PM PDT 24
Peak memory 196088 kb
Host smart-084b86ea-2947-4b6f-adbd-554943a7e069
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204510854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2204510854
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1340555300
Short name T722
Test name
Test status
Simulation time 52307554 ps
CPU time 0.58 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 194580 kb
Host smart-4ddd559b-31a0-4534-a3a5-9bce30bcfbd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340555300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1340555300
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2976719325
Short name T106
Test name
Test status
Simulation time 55933764 ps
CPU time 0.77 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 196696 kb
Host smart-62d43a88-8d77-4ddf-8805-20f67743841f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976719325 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2976719325
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1187265630
Short name T750
Test name
Test status
Simulation time 190251714 ps
CPU time 1.19 seconds
Started Aug 11 06:41:04 PM PDT 24
Finished Aug 11 06:41:05 PM PDT 24
Peak memory 198580 kb
Host smart-d889d6f6-ff72-469d-8a78-438e2eb88738
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187265630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1187265630
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.134564579
Short name T769
Test name
Test status
Simulation time 51224140 ps
CPU time 0.88 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 198656 kb
Host smart-68f91bc9-6fca-4ed2-92aa-25b37e1bb91d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134564579 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.134564579
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1579905363
Short name T92
Test name
Test status
Simulation time 49176356 ps
CPU time 0.64 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 195376 kb
Host smart-aa193be7-dc9b-48f4-b34d-88c3c6adbe8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579905363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1579905363
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2260852050
Short name T785
Test name
Test status
Simulation time 18944541 ps
CPU time 0.61 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 195096 kb
Host smart-d3a9cf09-e9e4-4fcc-9e7c-beff17743a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260852050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2260852050
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4029590666
Short name T108
Test name
Test status
Simulation time 114580385 ps
CPU time 0.84 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 196916 kb
Host smart-131adf64-bb2e-4bdb-b610-9e47503dc5f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029590666 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.4029590666
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2673808196
Short name T723
Test name
Test status
Simulation time 740811381 ps
CPU time 2.44 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 198720 kb
Host smart-a7c510b0-f0ec-4bfb-97db-96f68fbae799
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673808196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2673808196
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1049301081
Short name T53
Test name
Test status
Simulation time 53376710 ps
CPU time 0.9 seconds
Started Aug 11 06:39:59 PM PDT 24
Finished Aug 11 06:40:00 PM PDT 24
Peak memory 197880 kb
Host smart-67f010b1-f284-44be-800d-793e83c0b020
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049301081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1049301081
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3712907439
Short name T813
Test name
Test status
Simulation time 129416591 ps
CPU time 1 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 198664 kb
Host smart-83927fdd-3520-407c-837c-fcdfad71514e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712907439 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3712907439
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1593509777
Short name T96
Test name
Test status
Simulation time 12397342 ps
CPU time 0.61 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 196000 kb
Host smart-0ff75c13-e3b4-4f1c-826b-0240e9cbae9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593509777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1593509777
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1529473341
Short name T840
Test name
Test status
Simulation time 64910562 ps
CPU time 0.63 seconds
Started Aug 11 06:40:09 PM PDT 24
Finished Aug 11 06:40:10 PM PDT 24
Peak memory 194536 kb
Host smart-57a2d76d-19ef-4075-bd32-7ba4e6cab5fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529473341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1529473341
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3647358212
Short name T806
Test name
Test status
Simulation time 27262513 ps
CPU time 0.75 seconds
Started Aug 11 06:40:52 PM PDT 24
Finished Aug 11 06:40:54 PM PDT 24
Peak memory 194792 kb
Host smart-b63c3f21-81f0-428e-985f-4ad6357c6605
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647358212 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3647358212
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.449467754
Short name T839
Test name
Test status
Simulation time 224413137 ps
CPU time 3.21 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:40:01 PM PDT 24
Peak memory 198808 kb
Host smart-778a526a-fb33-49ff-a2d7-6a7e459f7c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449467754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.449467754
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1747348242
Short name T744
Test name
Test status
Simulation time 153845489 ps
CPU time 0.8 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 198548 kb
Host smart-5f45ec2b-341a-424c-8713-8de39dedc229
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747348242 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1747348242
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1435094627
Short name T809
Test name
Test status
Simulation time 44294647 ps
CPU time 0.6 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 195756 kb
Host smart-078af358-15e7-4114-b9bf-d53500e33872
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435094627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1435094627
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1207174310
Short name T777
Test name
Test status
Simulation time 33649968 ps
CPU time 0.55 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 194416 kb
Host smart-efa84056-386c-499e-ae35-8c153f1562d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207174310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1207174310
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.4094560310
Short name T842
Test name
Test status
Simulation time 65384316 ps
CPU time 0.88 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 197752 kb
Host smart-a72d8aef-39b1-4ac4-8fa4-8f0261ad26e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094560310 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.4094560310
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3935887263
Short name T796
Test name
Test status
Simulation time 53458728 ps
CPU time 1.12 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 198680 kb
Host smart-6c61f4d1-45a8-41fe-886a-8c64d7533785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935887263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3935887263
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2630650757
Short name T56
Test name
Test status
Simulation time 212757094 ps
CPU time 1.38 seconds
Started Aug 11 06:40:00 PM PDT 24
Finished Aug 11 06:40:01 PM PDT 24
Peak memory 198788 kb
Host smart-003da31c-073f-43c1-aeb7-dd9b93af752b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630650757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2630650757
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1116081133
Short name T823
Test name
Test status
Simulation time 107641295 ps
CPU time 0.83 seconds
Started Aug 11 06:39:59 PM PDT 24
Finished Aug 11 06:40:00 PM PDT 24
Peak memory 198608 kb
Host smart-840c49b2-6140-414e-be9d-0716cb7ec0c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116081133 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1116081133
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.639631426
Short name T99
Test name
Test status
Simulation time 39844777 ps
CPU time 0.61 seconds
Started Aug 11 06:40:08 PM PDT 24
Finished Aug 11 06:40:08 PM PDT 24
Peak memory 195212 kb
Host smart-84ade3f0-b045-4d62-b021-408d76c30579
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639631426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.639631426
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1278062096
Short name T803
Test name
Test status
Simulation time 42144221 ps
CPU time 0.56 seconds
Started Aug 11 06:39:59 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 195120 kb
Host smart-fa1f59b5-1689-4512-a949-94ed896cdb80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278062096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1278062096
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.128835725
Short name T781
Test name
Test status
Simulation time 38375259 ps
CPU time 0.88 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 197628 kb
Host smart-c7018a89-abe3-4f95-8c3c-bbf4cc74fc27
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128835725 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.128835725
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2925873686
Short name T727
Test name
Test status
Simulation time 192972992 ps
CPU time 1.51 seconds
Started Aug 11 06:39:52 PM PDT 24
Finished Aug 11 06:39:54 PM PDT 24
Peak memory 198752 kb
Host smart-05c1a3da-46a4-4995-835b-9273d7ba18f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925873686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2925873686
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3792432558
Short name T40
Test name
Test status
Simulation time 256988035 ps
CPU time 1.03 seconds
Started Aug 11 06:39:52 PM PDT 24
Finished Aug 11 06:39:53 PM PDT 24
Peak memory 198788 kb
Host smart-99ae8f86-4b54-403f-9371-11d5619e8966
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792432558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3792432558
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.193486651
Short name T737
Test name
Test status
Simulation time 18840587 ps
CPU time 0.68 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:55 PM PDT 24
Peak memory 197444 kb
Host smart-416a5910-c6fa-488c-9594-310215d326a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193486651 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.193486651
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2175879314
Short name T98
Test name
Test status
Simulation time 13753036 ps
CPU time 0.59 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 194608 kb
Host smart-1a85cc6f-f8dd-4fb2-bae5-42157f882e5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175879314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2175879314
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1657527607
Short name T836
Test name
Test status
Simulation time 57045086 ps
CPU time 0.57 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 194428 kb
Host smart-99bb92a2-fa6b-4c01-b2f8-badb0ff6001d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657527607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1657527607
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1341141456
Short name T102
Test name
Test status
Simulation time 49216053 ps
CPU time 0.75 seconds
Started Aug 11 06:40:01 PM PDT 24
Finished Aug 11 06:40:02 PM PDT 24
Peak memory 195760 kb
Host smart-82a49dfa-1cab-403a-96c3-283fb33da216
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341141456 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1341141456
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1560548374
Short name T811
Test name
Test status
Simulation time 155960697 ps
CPU time 1.69 seconds
Started Aug 11 06:40:03 PM PDT 24
Finished Aug 11 06:40:05 PM PDT 24
Peak memory 198848 kb
Host smart-66d891c4-2985-4bc3-8a2d-fb047b9bd1f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560548374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1560548374
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2683856094
Short name T54
Test name
Test status
Simulation time 186883340 ps
CPU time 1.14 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 198760 kb
Host smart-d9cf7a6d-f5bc-4b46-a6eb-c5ed8e4de536
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683856094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2683856094
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.255493907
Short name T717
Test name
Test status
Simulation time 67553334 ps
CPU time 1.22 seconds
Started Aug 11 06:40:03 PM PDT 24
Finished Aug 11 06:40:05 PM PDT 24
Peak memory 198884 kb
Host smart-1e7b47bb-c179-47c7-af54-80a1ac4236e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255493907 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.255493907
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4281726971
Short name T87
Test name
Test status
Simulation time 14130311 ps
CPU time 0.64 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 195656 kb
Host smart-93bb8ee4-e5b1-4489-9e78-8e8685feaaba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281726971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.4281726971
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2662128904
Short name T729
Test name
Test status
Simulation time 54820580 ps
CPU time 0.59 seconds
Started Aug 11 06:40:02 PM PDT 24
Finished Aug 11 06:40:03 PM PDT 24
Peak memory 195072 kb
Host smart-dc3cba69-f960-46a9-bad1-84eaefdab9cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662128904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2662128904
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.948015552
Short name T798
Test name
Test status
Simulation time 111298424 ps
CPU time 0.76 seconds
Started Aug 11 06:40:03 PM PDT 24
Finished Aug 11 06:40:04 PM PDT 24
Peak memory 197160 kb
Host smart-47885926-11de-40b5-8edd-13c77325660a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948015552 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.948015552
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1448041089
Short name T799
Test name
Test status
Simulation time 41791677 ps
CPU time 2.07 seconds
Started Aug 11 06:40:04 PM PDT 24
Finished Aug 11 06:40:06 PM PDT 24
Peak memory 198800 kb
Host smart-93e9209a-3059-4118-b984-c10b84b3c719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448041089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1448041089
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.62310434
Short name T51
Test name
Test status
Simulation time 252510502 ps
CPU time 1.17 seconds
Started Aug 11 06:40:03 PM PDT 24
Finished Aug 11 06:40:04 PM PDT 24
Peak memory 198772 kb
Host smart-35694ebf-8c79-4878-8ca7-59e8df820686
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62310434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.gpio_tl_intg_err.62310434
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3855146179
Short name T740
Test name
Test status
Simulation time 19232516 ps
CPU time 0.96 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 198604 kb
Host smart-cb2da5f9-423f-43bb-8dc5-f8591338b9ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855146179 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3855146179
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2170385680
Short name T764
Test name
Test status
Simulation time 16093518 ps
CPU time 0.59 seconds
Started Aug 11 06:40:02 PM PDT 24
Finished Aug 11 06:40:03 PM PDT 24
Peak memory 194588 kb
Host smart-cf736ad1-36c0-40ce-b893-27ee2d049167
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170385680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2170385680
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.30773048
Short name T718
Test name
Test status
Simulation time 21172567 ps
CPU time 0.59 seconds
Started Aug 11 06:40:03 PM PDT 24
Finished Aug 11 06:40:04 PM PDT 24
Peak memory 195140 kb
Host smart-78606a46-15f6-4826-a3ad-2701642562df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30773048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.30773048
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2887484202
Short name T819
Test name
Test status
Simulation time 59307327 ps
CPU time 0.78 seconds
Started Aug 11 06:40:04 PM PDT 24
Finished Aug 11 06:40:05 PM PDT 24
Peak memory 196860 kb
Host smart-359f195a-9121-4f2f-927e-a8c35ed739c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887484202 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2887484202
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2918205848
Short name T815
Test name
Test status
Simulation time 176572268 ps
CPU time 2.1 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:40:01 PM PDT 24
Peak memory 198788 kb
Host smart-6aee4cc4-6a36-4399-abdd-eb13a326f319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918205848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2918205848
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3116340094
Short name T113
Test name
Test status
Simulation time 572675980 ps
CPU time 1.38 seconds
Started Aug 11 06:40:03 PM PDT 24
Finished Aug 11 06:40:05 PM PDT 24
Peak memory 198712 kb
Host smart-99596676-433b-4531-a865-73c7be9b04ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116340094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3116340094
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2719436273
Short name T817
Test name
Test status
Simulation time 61249323 ps
CPU time 0.88 seconds
Started Aug 11 06:40:06 PM PDT 24
Finished Aug 11 06:40:07 PM PDT 24
Peak memory 198676 kb
Host smart-def3f27d-c8a8-4e1d-b3d6-137b74410cc9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719436273 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2719436273
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3465850233
Short name T94
Test name
Test status
Simulation time 16787373 ps
CPU time 0.59 seconds
Started Aug 11 06:40:06 PM PDT 24
Finished Aug 11 06:40:06 PM PDT 24
Peak memory 195192 kb
Host smart-cfd71bf7-834c-4db6-b0ee-489359a89a29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465850233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3465850233
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2107457255
Short name T788
Test name
Test status
Simulation time 125384567 ps
CPU time 0.61 seconds
Started Aug 11 06:40:03 PM PDT 24
Finished Aug 11 06:40:04 PM PDT 24
Peak memory 194448 kb
Host smart-327f04b0-2bf1-4b82-a582-e70ccfb9ed84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107457255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2107457255
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2575010073
Short name T831
Test name
Test status
Simulation time 74662263 ps
CPU time 0.83 seconds
Started Aug 11 06:40:00 PM PDT 24
Finished Aug 11 06:40:01 PM PDT 24
Peak memory 197084 kb
Host smart-8b224f50-d67f-4108-9ccd-368aeac7cbf6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575010073 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2575010073
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.524683772
Short name T784
Test name
Test status
Simulation time 581626914 ps
CPU time 2.49 seconds
Started Aug 11 06:40:02 PM PDT 24
Finished Aug 11 06:40:04 PM PDT 24
Peak memory 198732 kb
Host smart-0888faed-15db-4a1b-9280-0bbc5fac0490
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524683772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.524683772
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.14518147
Short name T42
Test name
Test status
Simulation time 70519787 ps
CPU time 1.15 seconds
Started Aug 11 06:40:04 PM PDT 24
Finished Aug 11 06:40:05 PM PDT 24
Peak memory 198744 kb
Host smart-ac29ece1-4595-4d5f-99ce-cec31b976a2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14518147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.gpio_tl_intg_err.14518147
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3695036960
Short name T745
Test name
Test status
Simulation time 27559805 ps
CPU time 0.82 seconds
Started Aug 11 06:40:04 PM PDT 24
Finished Aug 11 06:40:10 PM PDT 24
Peak memory 198628 kb
Host smart-8119075c-c82d-4991-89f6-0897be9fa891
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695036960 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3695036960
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2489544601
Short name T838
Test name
Test status
Simulation time 22737877 ps
CPU time 0.64 seconds
Started Aug 11 06:40:09 PM PDT 24
Finished Aug 11 06:40:10 PM PDT 24
Peak memory 195368 kb
Host smart-3992337c-a9e3-4844-8650-305e8df63280
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489544601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2489544601
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3135508956
Short name T828
Test name
Test status
Simulation time 45217620 ps
CPU time 0.59 seconds
Started Aug 11 06:40:08 PM PDT 24
Finished Aug 11 06:40:09 PM PDT 24
Peak memory 194420 kb
Host smart-be6e2b2f-9357-4d6e-aa94-6fa78136a9c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135508956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3135508956
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3451685574
Short name T110
Test name
Test status
Simulation time 156879012 ps
CPU time 0.73 seconds
Started Aug 11 06:40:03 PM PDT 24
Finished Aug 11 06:40:04 PM PDT 24
Peak memory 196852 kb
Host smart-fab75f13-de89-4bb7-98c0-e75edea8c193
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451685574 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3451685574
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.208933750
Short name T829
Test name
Test status
Simulation time 167754853 ps
CPU time 2.75 seconds
Started Aug 11 06:40:05 PM PDT 24
Finished Aug 11 06:40:08 PM PDT 24
Peak memory 198848 kb
Host smart-3b55db44-acd0-4cb8-a354-3b88d443479e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208933750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.208933750
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3067528632
Short name T774
Test name
Test status
Simulation time 119290131 ps
CPU time 0.82 seconds
Started Aug 11 06:40:02 PM PDT 24
Finished Aug 11 06:40:03 PM PDT 24
Peak memory 197788 kb
Host smart-e850976f-bf67-4c98-b6ac-d8d228463205
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067528632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3067528632
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3479110048
Short name T770
Test name
Test status
Simulation time 135767095 ps
CPU time 0.74 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 195628 kb
Host smart-cbec5aba-60c2-4b72-93f4-5b742a46dbd0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479110048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3479110048
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1852074189
Short name T761
Test name
Test status
Simulation time 753431317 ps
CPU time 3.36 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:40:00 PM PDT 24
Peak memory 198744 kb
Host smart-236c219d-7ea2-4fa2-9faa-2adde9cb4962
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852074189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1852074189
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2395166196
Short name T88
Test name
Test status
Simulation time 39018665 ps
CPU time 0.62 seconds
Started Aug 11 06:39:52 PM PDT 24
Finished Aug 11 06:39:52 PM PDT 24
Peak memory 195400 kb
Host smart-19cbe721-d9f0-4ff2-8c4a-acbf05376b01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395166196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2395166196
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3175373236
Short name T733
Test name
Test status
Simulation time 41162299 ps
CPU time 0.83 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 198612 kb
Host smart-ba083cde-0e67-45ac-98c5-d036e07f9820
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175373236 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3175373236
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3277273168
Short name T794
Test name
Test status
Simulation time 57832196 ps
CPU time 0.63 seconds
Started Aug 11 06:39:54 PM PDT 24
Finished Aug 11 06:39:55 PM PDT 24
Peak memory 196068 kb
Host smart-308e4cb6-5a37-4a31-9b9a-05058ac1affc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277273168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3277273168
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.4133862276
Short name T747
Test name
Test status
Simulation time 23803640 ps
CPU time 0.6 seconds
Started Aug 11 06:39:52 PM PDT 24
Finished Aug 11 06:39:53 PM PDT 24
Peak memory 194600 kb
Host smart-b70c04ad-252c-4eb5-aeda-75eabdff11e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133862276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.4133862276
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3713131059
Short name T810
Test name
Test status
Simulation time 64952096 ps
CPU time 0.64 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 196136 kb
Host smart-7d57b4ca-6547-44ff-84cc-f5f9c4d0d846
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713131059 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3713131059
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1511347320
Short name T802
Test name
Test status
Simulation time 59608347 ps
CPU time 1.29 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 198808 kb
Host smart-e0110e39-5cdf-4bd5-960d-946a818b56fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511347320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1511347320
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.447237625
Short name T812
Test name
Test status
Simulation time 42204652 ps
CPU time 0.89 seconds
Started Aug 11 06:39:53 PM PDT 24
Finished Aug 11 06:39:54 PM PDT 24
Peak memory 197592 kb
Host smart-e736dd51-4050-47a7-bf09-c3191fe62480
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447237625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.447237625
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3024343386
Short name T772
Test name
Test status
Simulation time 14048202 ps
CPU time 0.63 seconds
Started Aug 11 06:40:03 PM PDT 24
Finished Aug 11 06:40:04 PM PDT 24
Peak memory 195096 kb
Host smart-7731f7c3-4c94-4165-b784-86731dfa0f6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024343386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3024343386
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2715506726
Short name T827
Test name
Test status
Simulation time 16325004 ps
CPU time 0.59 seconds
Started Aug 11 06:40:06 PM PDT 24
Finished Aug 11 06:40:07 PM PDT 24
Peak memory 194496 kb
Host smart-c2ffde32-cea0-47ad-95d3-bde12350f851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715506726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2715506726
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3791432924
Short name T721
Test name
Test status
Simulation time 38925693 ps
CPU time 0.56 seconds
Started Aug 11 06:40:06 PM PDT 24
Finished Aug 11 06:40:07 PM PDT 24
Peak memory 194460 kb
Host smart-b5628672-e910-46c5-b536-1e5cdb07e68c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791432924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3791432924
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3443550681
Short name T816
Test name
Test status
Simulation time 10728410 ps
CPU time 0.57 seconds
Started Aug 11 06:40:17 PM PDT 24
Finished Aug 11 06:40:17 PM PDT 24
Peak memory 194452 kb
Host smart-2f755ede-73bc-4bf3-98bd-895a412576db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443550681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3443550681
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.549919844
Short name T807
Test name
Test status
Simulation time 41621082 ps
CPU time 0.57 seconds
Started Aug 11 06:40:05 PM PDT 24
Finished Aug 11 06:40:05 PM PDT 24
Peak memory 194492 kb
Host smart-0afd6d68-2441-4412-b68d-6144de9eb8d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549919844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.549919844
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.97282690
Short name T773
Test name
Test status
Simulation time 25022215 ps
CPU time 0.58 seconds
Started Aug 11 06:40:04 PM PDT 24
Finished Aug 11 06:40:05 PM PDT 24
Peak memory 194448 kb
Host smart-63068502-76de-4d35-a282-4e6f79f0c671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97282690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.97282690
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.512235533
Short name T830
Test name
Test status
Simulation time 56639629 ps
CPU time 0.63 seconds
Started Aug 11 06:40:07 PM PDT 24
Finished Aug 11 06:40:08 PM PDT 24
Peak memory 194636 kb
Host smart-bc61c1e1-fdd6-4f61-94ac-5513c6dcc0b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512235533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.512235533
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.4169331271
Short name T720
Test name
Test status
Simulation time 15639654 ps
CPU time 0.63 seconds
Started Aug 11 06:40:04 PM PDT 24
Finished Aug 11 06:40:04 PM PDT 24
Peak memory 194680 kb
Host smart-2db5c7b0-1805-4e8a-8a0b-3711dce12334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169331271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4169331271
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1181299886
Short name T822
Test name
Test status
Simulation time 16960883 ps
CPU time 0.67 seconds
Started Aug 11 06:40:05 PM PDT 24
Finished Aug 11 06:40:05 PM PDT 24
Peak memory 195148 kb
Host smart-c3c08439-ef94-4da6-a33a-5aa376cb055d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181299886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1181299886
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2198183323
Short name T719
Test name
Test status
Simulation time 31067328 ps
CPU time 0.61 seconds
Started Aug 11 06:40:06 PM PDT 24
Finished Aug 11 06:40:06 PM PDT 24
Peak memory 194608 kb
Host smart-275c92fd-a51d-446f-a51a-3414d67ab5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198183323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2198183323
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.813425708
Short name T832
Test name
Test status
Simulation time 1016244047 ps
CPU time 3.34 seconds
Started Aug 11 06:40:00 PM PDT 24
Finished Aug 11 06:40:03 PM PDT 24
Peak memory 198192 kb
Host smart-dda8182c-af2f-4a87-85d4-eee2b3af937a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813425708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.813425708
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1400183488
Short name T824
Test name
Test status
Simulation time 56479822 ps
CPU time 0.6 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 195064 kb
Host smart-7c6a19bd-8ade-4a4e-a20f-d6199d64b131
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400183488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1400183488
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2517117530
Short name T724
Test name
Test status
Simulation time 27725060 ps
CPU time 0.82 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 198648 kb
Host smart-6e106323-3ebd-4e7c-8231-5735c358cbe0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517117530 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2517117530
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1618940306
Short name T834
Test name
Test status
Simulation time 20811567 ps
CPU time 0.57 seconds
Started Aug 11 06:39:50 PM PDT 24
Finished Aug 11 06:39:51 PM PDT 24
Peak memory 195224 kb
Host smart-f7e941dc-46f5-4e97-bacb-1458b0817fc7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618940306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1618940306
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2953254222
Short name T771
Test name
Test status
Simulation time 23528640 ps
CPU time 0.64 seconds
Started Aug 11 06:39:52 PM PDT 24
Finished Aug 11 06:39:53 PM PDT 24
Peak memory 194492 kb
Host smart-2fe3077d-3a18-47e3-98e6-47d6d44e3c4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953254222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2953254222
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3915586563
Short name T103
Test name
Test status
Simulation time 205755584 ps
CPU time 0.76 seconds
Started Aug 11 06:39:53 PM PDT 24
Finished Aug 11 06:39:54 PM PDT 24
Peak memory 196992 kb
Host smart-4bcfe0f5-4827-4bf3-bd5e-b5bdd854b396
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915586563 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3915586563
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2686976196
Short name T760
Test name
Test status
Simulation time 29300167 ps
CPU time 1.41 seconds
Started Aug 11 06:39:54 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 198812 kb
Host smart-40bff2db-bd12-4855-90e2-8bfba96736cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686976196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2686976196
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.907008174
Short name T52
Test name
Test status
Simulation time 723751666 ps
CPU time 1.38 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 198764 kb
Host smart-392bfb79-d915-49fb-b953-48e2ff3fbb57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907008174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.907008174
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.466785881
Short name T749
Test name
Test status
Simulation time 42840170 ps
CPU time 0.59 seconds
Started Aug 11 06:40:03 PM PDT 24
Finished Aug 11 06:40:04 PM PDT 24
Peak memory 194488 kb
Host smart-925e4ff1-b04e-4fc1-9df5-69a25522b804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466785881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.466785881
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.549910823
Short name T790
Test name
Test status
Simulation time 15528105 ps
CPU time 0.61 seconds
Started Aug 11 06:40:09 PM PDT 24
Finished Aug 11 06:40:10 PM PDT 24
Peak memory 195160 kb
Host smart-7b4dd30f-ccbd-41f3-bd15-02652bf2fcb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549910823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.549910823
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3959576934
Short name T801
Test name
Test status
Simulation time 40304237 ps
CPU time 0.59 seconds
Started Aug 11 06:40:08 PM PDT 24
Finished Aug 11 06:40:09 PM PDT 24
Peak memory 194508 kb
Host smart-7934cce2-e9d2-438c-90bb-ccdaebc2f5d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959576934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3959576934
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.691757397
Short name T736
Test name
Test status
Simulation time 188027402 ps
CPU time 0.59 seconds
Started Aug 11 06:40:34 PM PDT 24
Finished Aug 11 06:40:35 PM PDT 24
Peak memory 194476 kb
Host smart-d8d3733f-a20a-4372-82d4-f0cffdb316e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691757397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.691757397
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1075265087
Short name T759
Test name
Test status
Simulation time 15395762 ps
CPU time 0.58 seconds
Started Aug 11 06:40:07 PM PDT 24
Finished Aug 11 06:40:08 PM PDT 24
Peak memory 195164 kb
Host smart-642db301-b7ab-40e7-923d-17b8eabc3116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075265087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1075265087
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1237311101
Short name T739
Test name
Test status
Simulation time 222246230 ps
CPU time 0.58 seconds
Started Aug 11 06:40:08 PM PDT 24
Finished Aug 11 06:40:09 PM PDT 24
Peak memory 194508 kb
Host smart-706874af-9519-4976-b031-79dcb1c652b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237311101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1237311101
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.213036028
Short name T762
Test name
Test status
Simulation time 61375377 ps
CPU time 0.61 seconds
Started Aug 11 06:40:08 PM PDT 24
Finished Aug 11 06:40:08 PM PDT 24
Peak memory 194516 kb
Host smart-0c740d9e-bf40-4cc6-a295-f1a04176ca4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213036028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.213036028
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3100931515
Short name T795
Test name
Test status
Simulation time 20452072 ps
CPU time 0.6 seconds
Started Aug 11 06:40:07 PM PDT 24
Finished Aug 11 06:40:08 PM PDT 24
Peak memory 194484 kb
Host smart-b0fed406-291d-4f1a-8ca5-ae100d974c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100931515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3100931515
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2468236059
Short name T732
Test name
Test status
Simulation time 24988957 ps
CPU time 0.6 seconds
Started Aug 11 06:40:26 PM PDT 24
Finished Aug 11 06:40:27 PM PDT 24
Peak memory 194464 kb
Host smart-961e23de-3f42-4835-9536-a126e603174a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468236059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2468236059
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.463835495
Short name T768
Test name
Test status
Simulation time 14192926 ps
CPU time 0.6 seconds
Started Aug 11 06:40:07 PM PDT 24
Finished Aug 11 06:40:08 PM PDT 24
Peak memory 194500 kb
Host smart-a79edf99-6079-49fe-ba4d-f67be597ba6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463835495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.463835495
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2916182477
Short name T826
Test name
Test status
Simulation time 26870386 ps
CPU time 0.74 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 196356 kb
Host smart-bdaae2ad-2b5f-4cc6-bed2-e69610601f9a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916182477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2916182477
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3073866810
Short name T833
Test name
Test status
Simulation time 316524613 ps
CPU time 3.02 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:40:00 PM PDT 24
Peak memory 197988 kb
Host smart-e804eea5-f668-49dc-ba91-9ca7997c4400
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073866810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3073866810
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.4215749181
Short name T805
Test name
Test status
Simulation time 38694802 ps
CPU time 0.61 seconds
Started Aug 11 06:41:06 PM PDT 24
Finished Aug 11 06:41:07 PM PDT 24
Peak memory 195852 kb
Host smart-61e36b92-9577-4d1a-98a7-114b75938958
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215749181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.4215749181
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.448009884
Short name T800
Test name
Test status
Simulation time 75379083 ps
CPU time 0.88 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 198624 kb
Host smart-83b920fb-8601-425d-a481-f7624265d64a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448009884 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.448009884
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4043959728
Short name T818
Test name
Test status
Simulation time 26905877 ps
CPU time 0.61 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:55 PM PDT 24
Peak memory 195604 kb
Host smart-5f74467a-376c-4668-85bf-6fab4dd7f094
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043959728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.4043959728
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.178029925
Short name T780
Test name
Test status
Simulation time 16218057 ps
CPU time 0.57 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 194544 kb
Host smart-474674f1-bd7f-419f-8a4c-896751278131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178029925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.178029925
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2717117336
Short name T107
Test name
Test status
Simulation time 33635017 ps
CPU time 0.66 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 195540 kb
Host smart-4c8a8c84-49bb-45c7-b4c9-e1a87210cafd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717117336 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2717117336
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1233691594
Short name T779
Test name
Test status
Simulation time 275398601 ps
CPU time 2.93 seconds
Started Aug 11 06:39:53 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 198812 kb
Host smart-713c9891-ffdd-44da-b756-a2b496edb5cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233691594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1233691594
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3418835391
Short name T743
Test name
Test status
Simulation time 72506287 ps
CPU time 1.17 seconds
Started Aug 11 06:39:50 PM PDT 24
Finished Aug 11 06:39:51 PM PDT 24
Peak memory 198960 kb
Host smart-44692c99-b960-4da0-9259-72480609c75d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418835391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3418835391
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.846988298
Short name T767
Test name
Test status
Simulation time 28639668 ps
CPU time 0.63 seconds
Started Aug 11 06:40:10 PM PDT 24
Finished Aug 11 06:40:11 PM PDT 24
Peak memory 195172 kb
Host smart-4ba1b79a-d21b-4923-84cf-04f1abffd548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846988298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.846988298
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1273137866
Short name T726
Test name
Test status
Simulation time 58690284 ps
CPU time 0.61 seconds
Started Aug 11 06:40:09 PM PDT 24
Finished Aug 11 06:40:10 PM PDT 24
Peak memory 194584 kb
Host smart-409e5a70-6f3d-4e18-a260-46eb3110d44d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273137866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1273137866
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2934285038
Short name T765
Test name
Test status
Simulation time 22043300 ps
CPU time 0.61 seconds
Started Aug 11 06:40:08 PM PDT 24
Finished Aug 11 06:40:08 PM PDT 24
Peak memory 195248 kb
Host smart-cb4fc053-96fa-42cf-bbb6-59f645772a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934285038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2934285038
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1120926228
Short name T730
Test name
Test status
Simulation time 41578512 ps
CPU time 0.57 seconds
Started Aug 11 06:40:20 PM PDT 24
Finished Aug 11 06:40:20 PM PDT 24
Peak memory 195068 kb
Host smart-a26346b1-8460-483a-acec-c93197479235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120926228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1120926228
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2118003861
Short name T741
Test name
Test status
Simulation time 32777428 ps
CPU time 0.62 seconds
Started Aug 11 06:40:15 PM PDT 24
Finished Aug 11 06:40:16 PM PDT 24
Peak memory 195188 kb
Host smart-7e62bb87-6e41-4afd-a0ae-e8a255d6c5af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118003861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2118003861
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1502016658
Short name T753
Test name
Test status
Simulation time 41735543 ps
CPU time 0.63 seconds
Started Aug 11 06:40:16 PM PDT 24
Finished Aug 11 06:40:17 PM PDT 24
Peak memory 195428 kb
Host smart-d54f2dd4-acf9-47fc-ab18-a8abf9581bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502016658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1502016658
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.407421092
Short name T755
Test name
Test status
Simulation time 26400528 ps
CPU time 0.59 seconds
Started Aug 11 06:40:25 PM PDT 24
Finished Aug 11 06:40:26 PM PDT 24
Peak memory 194520 kb
Host smart-bbc84b98-78b8-49ff-963e-1839af22e9d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407421092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.407421092
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.824528190
Short name T808
Test name
Test status
Simulation time 36765914 ps
CPU time 0.58 seconds
Started Aug 11 06:40:13 PM PDT 24
Finished Aug 11 06:40:14 PM PDT 24
Peak memory 194456 kb
Host smart-13e3f5ac-d27c-41aa-9629-70c13b88b629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824528190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.824528190
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3425826517
Short name T789
Test name
Test status
Simulation time 29222752 ps
CPU time 0.6 seconds
Started Aug 11 06:40:22 PM PDT 24
Finished Aug 11 06:40:23 PM PDT 24
Peak memory 195160 kb
Host smart-c3244f50-e065-460f-b192-fd81c39782c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425826517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3425826517
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3944219783
Short name T742
Test name
Test status
Simulation time 77624123 ps
CPU time 0.6 seconds
Started Aug 11 06:40:35 PM PDT 24
Finished Aug 11 06:40:36 PM PDT 24
Peak memory 194416 kb
Host smart-a49233a8-44e2-4953-bf3b-24ec6cb01342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944219783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3944219783
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3768073201
Short name T734
Test name
Test status
Simulation time 42311770 ps
CPU time 1.02 seconds
Started Aug 11 06:39:54 PM PDT 24
Finished Aug 11 06:39:55 PM PDT 24
Peak memory 198596 kb
Host smart-57992423-16c8-4ae0-98bf-3df877ce6c24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768073201 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3768073201
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1789761879
Short name T778
Test name
Test status
Simulation time 18445396 ps
CPU time 0.64 seconds
Started Aug 11 06:39:53 PM PDT 24
Finished Aug 11 06:39:54 PM PDT 24
Peak memory 195532 kb
Host smart-3bbdfbc7-0baf-449c-9f96-a92481a85295
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789761879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1789761879
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3133198883
Short name T728
Test name
Test status
Simulation time 11219307 ps
CPU time 0.6 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 194520 kb
Host smart-b34b9a08-d1ff-490a-b12c-61607c95b81a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133198883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3133198883
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1465815250
Short name T105
Test name
Test status
Simulation time 19639153 ps
CPU time 0.81 seconds
Started Aug 11 06:39:50 PM PDT 24
Finished Aug 11 06:39:51 PM PDT 24
Peak memory 197696 kb
Host smart-4b28de08-960a-4458-8f72-660caded91e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465815250 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1465815250
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3897351084
Short name T835
Test name
Test status
Simulation time 115901927 ps
CPU time 2.42 seconds
Started Aug 11 06:40:01 PM PDT 24
Finished Aug 11 06:40:04 PM PDT 24
Peak memory 198748 kb
Host smart-5a0bd16f-1123-43a8-9b56-6bdb787a6705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897351084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3897351084
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2255357108
Short name T746
Test name
Test status
Simulation time 82544546 ps
CPU time 0.88 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 197488 kb
Host smart-c1a27135-378e-454b-8774-19c4021137cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255357108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2255357108
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4286853059
Short name T766
Test name
Test status
Simulation time 30345616 ps
CPU time 1.36 seconds
Started Aug 11 06:39:54 PM PDT 24
Finished Aug 11 06:39:55 PM PDT 24
Peak memory 198784 kb
Host smart-f83cd79d-5fbc-49f8-b843-f604d6827afc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286853059 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.4286853059
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1632909370
Short name T86
Test name
Test status
Simulation time 42247755 ps
CPU time 0.62 seconds
Started Aug 11 06:40:02 PM PDT 24
Finished Aug 11 06:40:03 PM PDT 24
Peak memory 195376 kb
Host smart-6dfe6911-8187-4d08-9f91-b5ee5e0d4f8e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632909370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1632909370
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.4121264991
Short name T782
Test name
Test status
Simulation time 75026256 ps
CPU time 0.62 seconds
Started Aug 11 06:39:58 PM PDT 24
Finished Aug 11 06:39:59 PM PDT 24
Peak memory 194532 kb
Host smart-7d015aa2-421d-41b1-9ccf-a95a862a93cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121264991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.4121264991
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2378266326
Short name T109
Test name
Test status
Simulation time 21398932 ps
CPU time 0.65 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 195880 kb
Host smart-f14be232-57a1-4742-950d-7a6d15649e6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378266326 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2378266326
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3491691362
Short name T754
Test name
Test status
Simulation time 102401247 ps
CPU time 1.47 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 198740 kb
Host smart-26da44c4-7d55-432e-b757-873a256342ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491691362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3491691362
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2054145320
Short name T50
Test name
Test status
Simulation time 353670698 ps
CPU time 1.43 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 198788 kb
Host smart-b6562a9b-f2c2-4485-af60-9971574b3118
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054145320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2054145320
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2307626750
Short name T814
Test name
Test status
Simulation time 508357210 ps
CPU time 0.83 seconds
Started Aug 11 06:40:01 PM PDT 24
Finished Aug 11 06:40:02 PM PDT 24
Peak memory 198636 kb
Host smart-e095c8b2-9a62-401d-a4e4-f3c23d627391
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307626750 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2307626750
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3251393527
Short name T97
Test name
Test status
Simulation time 11020600 ps
CPU time 0.61 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 195036 kb
Host smart-12a72f02-c2a7-4582-9024-8126bf78f034
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251393527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3251393527
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1730326285
Short name T725
Test name
Test status
Simulation time 18797498 ps
CPU time 0.63 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 194564 kb
Host smart-0def8338-1306-448d-836b-aed659090366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730326285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1730326285
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4063206499
Short name T104
Test name
Test status
Simulation time 17560816 ps
CPU time 0.76 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 196744 kb
Host smart-0caf2018-77cc-4e06-80cd-45d85b97cd0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063206499 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.4063206499
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1259898103
Short name T804
Test name
Test status
Simulation time 118297756 ps
CPU time 3.21 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:40:00 PM PDT 24
Peak memory 198784 kb
Host smart-149a0d25-339d-4fb2-a9b8-f13804e9526a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259898103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1259898103
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1844815039
Short name T787
Test name
Test status
Simulation time 139146845 ps
CPU time 0.98 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:56 PM PDT 24
Peak memory 198628 kb
Host smart-44544c5d-55b5-4386-a7f1-dc9a33121079
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844815039 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1844815039
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2693560162
Short name T738
Test name
Test status
Simulation time 164986793 ps
CPU time 0.59 seconds
Started Aug 11 06:39:54 PM PDT 24
Finished Aug 11 06:39:54 PM PDT 24
Peak memory 194704 kb
Host smart-c5380469-7b6e-4950-9ebe-13154c6cbebe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693560162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2693560162
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.379104986
Short name T752
Test name
Test status
Simulation time 61790186 ps
CPU time 0.6 seconds
Started Aug 11 06:39:51 PM PDT 24
Finished Aug 11 06:39:52 PM PDT 24
Peak memory 194548 kb
Host smart-db076e4c-7c32-41e4-b466-461ef2719717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379104986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.379104986
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1874104391
Short name T792
Test name
Test status
Simulation time 33227996 ps
CPU time 0.87 seconds
Started Aug 11 06:39:53 PM PDT 24
Finished Aug 11 06:39:54 PM PDT 24
Peak memory 197916 kb
Host smart-8d5f908b-df5f-4c7c-af24-afe2ea10903a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874104391 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1874104391
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.166868672
Short name T757
Test name
Test status
Simulation time 120859168 ps
CPU time 1.73 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 198840 kb
Host smart-5f30caff-86ea-45c5-a919-44bcc727127d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166868672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.166868672
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3035532337
Short name T783
Test name
Test status
Simulation time 43346954 ps
CPU time 0.85 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 197916 kb
Host smart-c3031cad-7f7f-4460-b690-10cfe70651d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035532337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3035532337
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1027978691
Short name T716
Test name
Test status
Simulation time 158538685 ps
CPU time 0.92 seconds
Started Aug 11 06:39:57 PM PDT 24
Finished Aug 11 06:39:58 PM PDT 24
Peak memory 198624 kb
Host smart-2ed82f62-5314-4422-b211-6150c5502239
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027978691 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1027978691
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.666561460
Short name T756
Test name
Test status
Simulation time 11325102 ps
CPU time 0.62 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 194756 kb
Host smart-d2f6da43-1820-4aff-abca-57c7c85abb91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666561460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.666561460
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.506896429
Short name T748
Test name
Test status
Simulation time 16974512 ps
CPU time 0.64 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:55 PM PDT 24
Peak memory 195144 kb
Host smart-438d2a63-6657-47ee-8d79-1d2f8bee2c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506896429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.506896429
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4017124565
Short name T786
Test name
Test status
Simulation time 29480894 ps
CPU time 0.71 seconds
Started Aug 11 06:41:06 PM PDT 24
Finished Aug 11 06:41:07 PM PDT 24
Peak memory 197100 kb
Host smart-67a0701c-5bf8-458d-9c92-34a5068d8083
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017124565 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.4017124565
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1334745066
Short name T763
Test name
Test status
Simulation time 106241976 ps
CPU time 1.59 seconds
Started Aug 11 06:39:55 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 198848 kb
Host smart-964cbda7-3008-4141-b757-a308b9527f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334745066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1334745066
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1455972658
Short name T55
Test name
Test status
Simulation time 441588135 ps
CPU time 1.12 seconds
Started Aug 11 06:39:56 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 198784 kb
Host smart-2075aabf-7d9a-431b-90c4-d0d9a8666120
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455972658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1455972658
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.505477409
Short name T313
Test name
Test status
Simulation time 15673969 ps
CPU time 0.57 seconds
Started Aug 11 06:11:26 PM PDT 24
Finished Aug 11 06:11:26 PM PDT 24
Peak memory 194504 kb
Host smart-48bc117f-2797-4d37-a7db-20ba9126ad09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505477409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.505477409
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.847589800
Short name T79
Test name
Test status
Simulation time 76517672 ps
CPU time 0.82 seconds
Started Aug 11 06:11:45 PM PDT 24
Finished Aug 11 06:11:46 PM PDT 24
Peak memory 195976 kb
Host smart-e2849c20-b787-4db8-a1bf-063acc5e925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847589800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.847589800
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.411945780
Short name T252
Test name
Test status
Simulation time 423910043 ps
CPU time 6.8 seconds
Started Aug 11 06:11:42 PM PDT 24
Finished Aug 11 06:11:49 PM PDT 24
Peak memory 198488 kb
Host smart-3b8fd71d-921c-4cb4-96ee-e648a5faf5bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411945780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.411945780
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2438611452
Short name T438
Test name
Test status
Simulation time 67174934 ps
CPU time 0.89 seconds
Started Aug 11 06:11:39 PM PDT 24
Finished Aug 11 06:11:40 PM PDT 24
Peak memory 197824 kb
Host smart-eec5d580-769c-497d-a253-50840f394328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438611452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2438611452
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3560178366
Short name T166
Test name
Test status
Simulation time 31176098 ps
CPU time 0.79 seconds
Started Aug 11 06:11:41 PM PDT 24
Finished Aug 11 06:11:42 PM PDT 24
Peak memory 196100 kb
Host smart-f2388da9-d01d-45a0-bbb8-3b38b1858ac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560178366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3560178366
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3281376358
Short name T590
Test name
Test status
Simulation time 157610202 ps
CPU time 1.07 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 195876 kb
Host smart-7c4d3e1f-a33c-46ec-915f-6ab84778bde4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281376358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3281376358
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.899924023
Short name T222
Test name
Test status
Simulation time 29275931 ps
CPU time 0.71 seconds
Started Aug 11 06:11:44 PM PDT 24
Finished Aug 11 06:11:45 PM PDT 24
Peak memory 195920 kb
Host smart-ef2024d0-d2c6-4e4e-a0bc-7b29b527e654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899924023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.899924023
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.4285846421
Short name T488
Test name
Test status
Simulation time 22325040 ps
CPU time 0.71 seconds
Started Aug 11 06:11:35 PM PDT 24
Finished Aug 11 06:11:36 PM PDT 24
Peak memory 196652 kb
Host smart-7e81f422-e9a7-4728-bcff-c6b64dc9e26b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285846421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.4285846421
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1658403102
Short name T286
Test name
Test status
Simulation time 107684229 ps
CPU time 1.27 seconds
Started Aug 11 06:11:37 PM PDT 24
Finished Aug 11 06:11:38 PM PDT 24
Peak memory 198424 kb
Host smart-f721d37f-3cfd-45c6-9cfe-41882b303f09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658403102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1658403102
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2061680408
Short name T57
Test name
Test status
Simulation time 75143981 ps
CPU time 0.8 seconds
Started Aug 11 06:11:41 PM PDT 24
Finished Aug 11 06:11:47 PM PDT 24
Peak memory 214408 kb
Host smart-c5134dd9-52f7-4c9c-9250-dc618b885439
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061680408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2061680408
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.112043161
Short name T161
Test name
Test status
Simulation time 78064439 ps
CPU time 1.32 seconds
Started Aug 11 06:11:36 PM PDT 24
Finished Aug 11 06:11:37 PM PDT 24
Peak memory 198520 kb
Host smart-8db93ddf-e05c-4dd9-b53f-f4ac983f7146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112043161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.112043161
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.93719251
Short name T563
Test name
Test status
Simulation time 124006361 ps
CPU time 1.19 seconds
Started Aug 11 06:11:38 PM PDT 24
Finished Aug 11 06:11:40 PM PDT 24
Peak memory 197232 kb
Host smart-bd469336-18e3-49c9-8aaf-6c655e6e3ec0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93719251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.93719251
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1161890489
Short name T6
Test name
Test status
Simulation time 9656264663 ps
CPU time 57.72 seconds
Started Aug 11 06:11:45 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 198756 kb
Host smart-d1ae3c1f-a5a2-46f5-b845-ace98b2f26ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161890489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1161890489
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3653634187
Short name T604
Test name
Test status
Simulation time 15539471 ps
CPU time 0.61 seconds
Started Aug 11 06:11:36 PM PDT 24
Finished Aug 11 06:11:37 PM PDT 24
Peak memory 194712 kb
Host smart-d8ad2ac3-8290-438a-9d08-54aac927277e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653634187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3653634187
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2610801392
Short name T671
Test name
Test status
Simulation time 24753508 ps
CPU time 0.81 seconds
Started Aug 11 06:11:32 PM PDT 24
Finished Aug 11 06:11:33 PM PDT 24
Peak memory 196664 kb
Host smart-cc431f30-a69d-42a7-ac9d-ccef8a2ef211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610801392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2610801392
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3371270561
Short name T63
Test name
Test status
Simulation time 585175679 ps
CPU time 4.06 seconds
Started Aug 11 06:11:50 PM PDT 24
Finished Aug 11 06:11:55 PM PDT 24
Peak memory 196544 kb
Host smart-50baee46-a864-44f3-95d4-45c367a960de
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371270561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3371270561
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.88064985
Short name T146
Test name
Test status
Simulation time 288873163 ps
CPU time 0.95 seconds
Started Aug 11 06:11:51 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 198540 kb
Host smart-19a9f946-d213-4819-ab7a-19b623adad40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88064985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.88064985
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.4232582645
Short name T354
Test name
Test status
Simulation time 34701906 ps
CPU time 0.77 seconds
Started Aug 11 06:11:43 PM PDT 24
Finished Aug 11 06:11:44 PM PDT 24
Peak memory 196120 kb
Host smart-242bcc75-283d-4f07-972a-7ae060d44275
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232582645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.4232582645
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1696023410
Short name T598
Test name
Test status
Simulation time 327743867 ps
CPU time 3.28 seconds
Started Aug 11 06:11:43 PM PDT 24
Finished Aug 11 06:11:46 PM PDT 24
Peak memory 198448 kb
Host smart-717fa82e-6ecd-4680-8975-7ffa0a2224c7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696023410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1696023410
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3765261239
Short name T360
Test name
Test status
Simulation time 29532734 ps
CPU time 1.1 seconds
Started Aug 11 06:11:46 PM PDT 24
Finished Aug 11 06:11:47 PM PDT 24
Peak memory 196264 kb
Host smart-24263f21-2079-47ed-aed6-f330a888fbb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765261239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3765261239
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1183960990
Short name T699
Test name
Test status
Simulation time 57409896 ps
CPU time 0.71 seconds
Started Aug 11 06:11:53 PM PDT 24
Finished Aug 11 06:11:53 PM PDT 24
Peak memory 195844 kb
Host smart-1d7ca283-5408-40a4-862d-6838b72d5a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183960990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1183960990
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.9223839
Short name T278
Test name
Test status
Simulation time 36317132 ps
CPU time 1.25 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 197580 kb
Host smart-07ece275-39f5-43c0-a01c-86d356b75d31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9223839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_pu
lldown.9223839
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3894840567
Short name T333
Test name
Test status
Simulation time 824703172 ps
CPU time 2.55 seconds
Started Aug 11 06:11:46 PM PDT 24
Finished Aug 11 06:11:48 PM PDT 24
Peak memory 198520 kb
Host smart-bd79c2a4-6ea0-4d4a-bb64-cf3b6672e286
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894840567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3894840567
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3967772658
Short name T58
Test name
Test status
Simulation time 34404371 ps
CPU time 0.81 seconds
Started Aug 11 06:11:50 PM PDT 24
Finished Aug 11 06:11:51 PM PDT 24
Peak memory 214516 kb
Host smart-05c45c09-f2c5-4449-b976-27d37f25a023
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967772658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3967772658
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3133896193
Short name T440
Test name
Test status
Simulation time 65089839 ps
CPU time 1.28 seconds
Started Aug 11 06:11:44 PM PDT 24
Finished Aug 11 06:11:46 PM PDT 24
Peak memory 197384 kb
Host smart-6ef86bc5-6f2e-4f6b-8cee-34c432fb1926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133896193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3133896193
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2238680844
Short name T350
Test name
Test status
Simulation time 328380562 ps
CPU time 1.19 seconds
Started Aug 11 06:11:54 PM PDT 24
Finished Aug 11 06:11:56 PM PDT 24
Peak memory 196448 kb
Host smart-d261970a-15f5-448e-b93c-b93420cabde7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238680844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2238680844
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3257021428
Short name T521
Test name
Test status
Simulation time 6119938958 ps
CPU time 157.98 seconds
Started Aug 11 06:11:47 PM PDT 24
Finished Aug 11 06:14:25 PM PDT 24
Peak memory 198744 kb
Host smart-76360608-c2f6-455f-805f-194f68cb17a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257021428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3257021428
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3138244563
Short name T687
Test name
Test status
Simulation time 79369130 ps
CPU time 0.57 seconds
Started Aug 11 06:11:53 PM PDT 24
Finished Aug 11 06:11:54 PM PDT 24
Peak memory 194656 kb
Host smart-d7c03e06-1672-4575-aebc-b987a9467e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138244563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3138244563
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.807890351
Short name T541
Test name
Test status
Simulation time 53466670 ps
CPU time 0.69 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:11:57 PM PDT 24
Peak memory 194608 kb
Host smart-d4ce39d9-15dc-4921-8c5c-a6ef48f508c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807890351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.807890351
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2543087653
Short name T520
Test name
Test status
Simulation time 400465558 ps
CPU time 12.5 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:12:10 PM PDT 24
Peak memory 198552 kb
Host smart-53fb72d3-2480-4f0d-a64f-7f540e1fd849
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543087653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2543087653
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.875838145
Short name T21
Test name
Test status
Simulation time 42525411 ps
CPU time 0.72 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 196456 kb
Host smart-ec71f469-67e3-46a3-97b2-5cbf2bb340d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875838145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.875838145
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2734847486
Short name T233
Test name
Test status
Simulation time 119137422 ps
CPU time 1.06 seconds
Started Aug 11 06:12:08 PM PDT 24
Finished Aug 11 06:12:09 PM PDT 24
Peak memory 196500 kb
Host smart-d17773f8-83fe-401f-b30c-306ad3942cf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734847486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2734847486
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.312011303
Short name T642
Test name
Test status
Simulation time 259066265 ps
CPU time 2.18 seconds
Started Aug 11 06:11:58 PM PDT 24
Finished Aug 11 06:12:01 PM PDT 24
Peak memory 198540 kb
Host smart-f481bfb9-a704-4fd5-a61d-720f896844de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312011303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.312011303
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2713868252
Short name T666
Test name
Test status
Simulation time 458864038 ps
CPU time 3.79 seconds
Started Aug 11 06:11:54 PM PDT 24
Finished Aug 11 06:11:58 PM PDT 24
Peak memory 197876 kb
Host smart-f4e4c840-b1e1-4382-b17a-ff6c266174ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713868252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2713868252
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1628851625
Short name T605
Test name
Test status
Simulation time 72994093 ps
CPU time 1.29 seconds
Started Aug 11 06:11:54 PM PDT 24
Finished Aug 11 06:11:55 PM PDT 24
Peak memory 198612 kb
Host smart-27e3c01b-80f7-40e9-97e2-c360762cffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628851625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1628851625
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.95337725
Short name T509
Test name
Test status
Simulation time 236647310 ps
CPU time 1.23 seconds
Started Aug 11 06:12:03 PM PDT 24
Finished Aug 11 06:12:04 PM PDT 24
Peak memory 197584 kb
Host smart-56e6c3a7-a2bc-468d-abc5-d281406e9d02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95337725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup_
pulldown.95337725
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2227803487
Short name T435
Test name
Test status
Simulation time 124476333 ps
CPU time 5.67 seconds
Started Aug 11 06:11:50 PM PDT 24
Finished Aug 11 06:11:55 PM PDT 24
Peak memory 198788 kb
Host smart-745dcd27-4217-4571-a801-7ea7538c74f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227803487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2227803487
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2585307308
Short name T510
Test name
Test status
Simulation time 89214406 ps
CPU time 1.33 seconds
Started Aug 11 06:12:12 PM PDT 24
Finished Aug 11 06:12:13 PM PDT 24
Peak memory 197392 kb
Host smart-6fca2c30-4e96-467e-b80b-37acc7b3e3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585307308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2585307308
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.4216466211
Short name T29
Test name
Test status
Simulation time 142033387 ps
CPU time 1.09 seconds
Started Aug 11 06:11:55 PM PDT 24
Finished Aug 11 06:11:56 PM PDT 24
Peak memory 196412 kb
Host smart-c3b767a2-452e-4280-af9e-b8e95ec6b425
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216466211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.4216466211
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1475817961
Short name T326
Test name
Test status
Simulation time 103284556121 ps
CPU time 125.25 seconds
Started Aug 11 06:11:45 PM PDT 24
Finished Aug 11 06:13:50 PM PDT 24
Peak memory 198748 kb
Host smart-b8e6bee5-3427-41a8-b535-3555ca47e3cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475817961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1475817961
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1632041687
Short name T612
Test name
Test status
Simulation time 37377603 ps
CPU time 0.57 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:11:58 PM PDT 24
Peak memory 193292 kb
Host smart-3457ddf4-6cde-4326-99de-db077a4b7f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632041687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1632041687
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2012290775
Short name T185
Test name
Test status
Simulation time 652423203 ps
CPU time 0.84 seconds
Started Aug 11 06:11:51 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 196684 kb
Host smart-1a23b3c4-0969-4e04-b818-a4c5952dd087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012290775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2012290775
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3795603929
Short name T13
Test name
Test status
Simulation time 710564585 ps
CPU time 20.23 seconds
Started Aug 11 06:11:55 PM PDT 24
Finished Aug 11 06:12:15 PM PDT 24
Peak memory 196136 kb
Host smart-91c1682b-e325-44cd-85a0-12cf5c3e26df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795603929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3795603929
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1801874371
Short name T129
Test name
Test status
Simulation time 54984572 ps
CPU time 0.92 seconds
Started Aug 11 06:11:50 PM PDT 24
Finished Aug 11 06:11:51 PM PDT 24
Peak memory 197112 kb
Host smart-a5ab79e1-203f-414e-b10d-6a15ef38490a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801874371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1801874371
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.234115872
Short name T127
Test name
Test status
Simulation time 409017210 ps
CPU time 1.34 seconds
Started Aug 11 06:11:47 PM PDT 24
Finished Aug 11 06:11:49 PM PDT 24
Peak memory 197756 kb
Host smart-8b06d129-39b7-42ce-aebb-7d148b38bfd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234115872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.234115872
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.736270839
Short name T677
Test name
Test status
Simulation time 323515238 ps
CPU time 1.45 seconds
Started Aug 11 06:11:50 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 198788 kb
Host smart-a8e5ee86-cba3-4d53-8a5c-ab2cddfcf5b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736270839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.736270839
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1397773094
Short name T163
Test name
Test status
Simulation time 198192443 ps
CPU time 2.84 seconds
Started Aug 11 06:11:54 PM PDT 24
Finished Aug 11 06:11:57 PM PDT 24
Peak memory 197692 kb
Host smart-cd13d9ef-82d2-4a6f-aea9-778db1754333
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397773094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1397773094
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2303507485
Short name T448
Test name
Test status
Simulation time 81836518 ps
CPU time 1.28 seconds
Started Aug 11 06:11:51 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 197512 kb
Host smart-75ed7aca-3fc0-4581-9be3-6d285d71682a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303507485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2303507485
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2749171218
Short name T336
Test name
Test status
Simulation time 45547032 ps
CPU time 0.71 seconds
Started Aug 11 06:11:54 PM PDT 24
Finished Aug 11 06:11:55 PM PDT 24
Peak memory 195976 kb
Host smart-53d5408b-c429-4f9d-b4f1-c72cf0b97b3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749171218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2749171218
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.484569705
Short name T143
Test name
Test status
Simulation time 897720220 ps
CPU time 4.11 seconds
Started Aug 11 06:12:10 PM PDT 24
Finished Aug 11 06:12:14 PM PDT 24
Peak memory 198520 kb
Host smart-b515fdb6-49d9-4797-8a09-279f2651ec3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484569705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.484569705
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2819976491
Short name T35
Test name
Test status
Simulation time 74299083 ps
CPU time 1.25 seconds
Started Aug 11 06:11:56 PM PDT 24
Finished Aug 11 06:11:57 PM PDT 24
Peak memory 196404 kb
Host smart-d626d74c-5d81-4775-acb2-887f173fb6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819976491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2819976491
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2692709165
Short name T450
Test name
Test status
Simulation time 40450624 ps
CPU time 0.79 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:11:58 PM PDT 24
Peak memory 196564 kb
Host smart-1ce92d9e-8dcc-404b-a8f6-65f89ed645fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692709165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2692709165
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3220092208
Short name T210
Test name
Test status
Simulation time 5324127141 ps
CPU time 76.03 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:13:13 PM PDT 24
Peak memory 198692 kb
Host smart-89f665e9-325d-4dcd-8731-ed8df111f6f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220092208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3220092208
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1159794648
Short name T348
Test name
Test status
Simulation time 22359015 ps
CPU time 0.57 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:11:49 PM PDT 24
Peak memory 195220 kb
Host smart-0cf83cb7-b7d3-401c-a0a7-07255f23b3c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159794648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1159794648
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1051821473
Short name T243
Test name
Test status
Simulation time 16589113 ps
CPU time 0.71 seconds
Started Aug 11 06:11:55 PM PDT 24
Finished Aug 11 06:11:56 PM PDT 24
Peak memory 194668 kb
Host smart-260bdd11-73d4-45c0-a632-dc782657714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051821473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1051821473
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.4017814810
Short name T316
Test name
Test status
Simulation time 700590891 ps
CPU time 22.22 seconds
Started Aug 11 06:11:59 PM PDT 24
Finished Aug 11 06:12:21 PM PDT 24
Peak memory 197640 kb
Host smart-e26bd343-1c74-4f71-87bc-64880811fb48
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017814810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.4017814810
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2724171283
Short name T376
Test name
Test status
Simulation time 89592485 ps
CPU time 1.11 seconds
Started Aug 11 06:11:53 PM PDT 24
Finished Aug 11 06:11:55 PM PDT 24
Peak memory 198464 kb
Host smart-2d390c04-5526-4023-8749-6e2ab9e7ed5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724171283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2724171283
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2133120230
Short name T209
Test name
Test status
Simulation time 98066122 ps
CPU time 1.3 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:11:58 PM PDT 24
Peak memory 197264 kb
Host smart-0d9258a0-9a95-4131-a2f4-0ed9eaeedfe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133120230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2133120230
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3858910320
Short name T351
Test name
Test status
Simulation time 307307747 ps
CPU time 2.11 seconds
Started Aug 11 06:11:54 PM PDT 24
Finished Aug 11 06:11:57 PM PDT 24
Peak memory 196900 kb
Host smart-089d2dbb-349e-4fe1-8030-609bc6851f4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858910320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3858910320
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1748700094
Short name T126
Test name
Test status
Simulation time 136955461 ps
CPU time 3.08 seconds
Started Aug 11 06:12:04 PM PDT 24
Finished Aug 11 06:12:08 PM PDT 24
Peak memory 197600 kb
Host smart-1096478e-1708-4c8f-906f-077a1178e2f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748700094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1748700094
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.559897514
Short name T557
Test name
Test status
Simulation time 412803430 ps
CPU time 1.3 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 197472 kb
Host smart-2f063275-d2d6-442d-8d5f-f3eead6d88b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559897514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.559897514
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.513592060
Short name T341
Test name
Test status
Simulation time 50453382 ps
CPU time 1.12 seconds
Started Aug 11 06:12:17 PM PDT 24
Finished Aug 11 06:12:18 PM PDT 24
Peak memory 196348 kb
Host smart-1170c01e-c1c9-4b62-b8e7-61cf1f88e9bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513592060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.513592060
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2444701436
Short name T342
Test name
Test status
Simulation time 199619412 ps
CPU time 2.49 seconds
Started Aug 11 06:12:05 PM PDT 24
Finished Aug 11 06:12:08 PM PDT 24
Peak memory 198576 kb
Host smart-cb658e7a-9553-488e-b4f4-c7e92d084935
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444701436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2444701436
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2938056
Short name T293
Test name
Test status
Simulation time 284124150 ps
CPU time 1.33 seconds
Started Aug 11 06:11:58 PM PDT 24
Finished Aug 11 06:12:00 PM PDT 24
Peak memory 196132 kb
Host smart-ad741399-d414-4304-ba20-0e80ab4c0cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2938056
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1558757508
Short name T28
Test name
Test status
Simulation time 30500316 ps
CPU time 0.93 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:11:58 PM PDT 24
Peak memory 197072 kb
Host smart-1d3c1645-61ca-4961-bf97-06ff9ad4ea8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558757508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1558757508
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2771391760
Short name T284
Test name
Test status
Simulation time 18396953984 ps
CPU time 104.25 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:13:42 PM PDT 24
Peak memory 198772 kb
Host smart-034a8554-4657-4559-ad97-d0b5146be268
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771391760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2771391760
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3761631627
Short name T371
Test name
Test status
Simulation time 22728690 ps
CPU time 0.56 seconds
Started Aug 11 06:12:22 PM PDT 24
Finished Aug 11 06:12:23 PM PDT 24
Peak memory 194468 kb
Host smart-6c14d51a-0ff5-4d96-9863-c0ff0942eb8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761631627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3761631627
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3229172231
Short name T626
Test name
Test status
Simulation time 36910003 ps
CPU time 0.75 seconds
Started Aug 11 06:12:13 PM PDT 24
Finished Aug 11 06:12:14 PM PDT 24
Peak memory 196584 kb
Host smart-eff162c4-de33-4565-8d97-3fed2c3bbd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229172231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3229172231
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3503966877
Short name T169
Test name
Test status
Simulation time 522554843 ps
CPU time 15.24 seconds
Started Aug 11 06:12:03 PM PDT 24
Finished Aug 11 06:12:18 PM PDT 24
Peak memory 196856 kb
Host smart-f8d40a1c-bd64-46fb-bee2-a8f064207d3d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503966877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3503966877
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2112596620
Short name T116
Test name
Test status
Simulation time 234916160 ps
CPU time 1.08 seconds
Started Aug 11 06:12:12 PM PDT 24
Finished Aug 11 06:12:13 PM PDT 24
Peak memory 196364 kb
Host smart-aacfe8b0-f465-41be-aa6e-9b5275c1e338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112596620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2112596620
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2971994285
Short name T125
Test name
Test status
Simulation time 628608760 ps
CPU time 3.54 seconds
Started Aug 11 06:12:02 PM PDT 24
Finished Aug 11 06:12:05 PM PDT 24
Peak memory 198528 kb
Host smart-2537463b-db7c-4d48-ac68-4d458f07f5fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971994285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2971994285
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1355742333
Short name T574
Test name
Test status
Simulation time 250307590 ps
CPU time 1.04 seconds
Started Aug 11 06:12:18 PM PDT 24
Finished Aug 11 06:12:19 PM PDT 24
Peak memory 195872 kb
Host smart-9b36b66e-0f67-49b0-a527-e1e5b0329a6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355742333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1355742333
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2129505184
Short name T300
Test name
Test status
Simulation time 109402165 ps
CPU time 1.15 seconds
Started Aug 11 06:12:01 PM PDT 24
Finished Aug 11 06:12:03 PM PDT 24
Peak memory 197832 kb
Host smart-25b0d5db-1c34-497c-8587-eb7387b3a3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129505184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2129505184
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2940436266
Short name T190
Test name
Test status
Simulation time 277452727 ps
CPU time 1.18 seconds
Started Aug 11 06:12:00 PM PDT 24
Finished Aug 11 06:12:01 PM PDT 24
Peak memory 196476 kb
Host smart-c9e3db75-5018-4efe-a14a-4bbf42cd615f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940436266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2940436266
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4117328950
Short name T647
Test name
Test status
Simulation time 2145011650 ps
CPU time 6.56 seconds
Started Aug 11 06:11:59 PM PDT 24
Finished Aug 11 06:12:05 PM PDT 24
Peak memory 198572 kb
Host smart-1027d1bc-92c4-459d-aec6-7b15ed7ed5a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117328950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4117328950
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.43054678
Short name T392
Test name
Test status
Simulation time 242963625 ps
CPU time 1.09 seconds
Started Aug 11 06:11:58 PM PDT 24
Finished Aug 11 06:12:00 PM PDT 24
Peak memory 197136 kb
Host smart-84d15b77-4ca2-4a2e-b66f-f898132f9faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43054678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.43054678
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3678487335
Short name T83
Test name
Test status
Simulation time 54955454 ps
CPU time 0.78 seconds
Started Aug 11 06:11:54 PM PDT 24
Finished Aug 11 06:11:55 PM PDT 24
Peak memory 195804 kb
Host smart-a714f164-508d-4aaa-ada1-d726462abad9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678487335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3678487335
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.4099169981
Short name T530
Test name
Test status
Simulation time 108127298951 ps
CPU time 845.52 seconds
Started Aug 11 06:11:59 PM PDT 24
Finished Aug 11 06:26:05 PM PDT 24
Peak memory 199072 kb
Host smart-0aec9b35-d4a6-44e2-96b5-6b1187eddd74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4099169981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.4099169981
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.20663800
Short name T280
Test name
Test status
Simulation time 81058713 ps
CPU time 0.6 seconds
Started Aug 11 06:11:59 PM PDT 24
Finished Aug 11 06:12:00 PM PDT 24
Peak memory 195156 kb
Host smart-386fab5e-e27e-4262-b341-7e6bcc8360ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20663800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.20663800
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.921224529
Short name T214
Test name
Test status
Simulation time 101264654 ps
CPU time 0.84 seconds
Started Aug 11 06:11:58 PM PDT 24
Finished Aug 11 06:11:59 PM PDT 24
Peak memory 196788 kb
Host smart-8e8e2917-95ce-47a3-a904-1aa79a4c6de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921224529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.921224529
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2150788975
Short name T121
Test name
Test status
Simulation time 645845083 ps
CPU time 19.2 seconds
Started Aug 11 06:11:56 PM PDT 24
Finished Aug 11 06:12:16 PM PDT 24
Peak memory 196868 kb
Host smart-31af2d8e-579e-4b91-b65b-dd0e2b3b7af5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150788975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2150788975
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1549159921
Short name T513
Test name
Test status
Simulation time 138231118 ps
CPU time 0.95 seconds
Started Aug 11 06:12:00 PM PDT 24
Finished Aug 11 06:12:01 PM PDT 24
Peak memory 198224 kb
Host smart-e96e734b-9dfb-41c6-87c3-42f70d4fce62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549159921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1549159921
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3492705791
Short name T12
Test name
Test status
Simulation time 163346541 ps
CPU time 0.82 seconds
Started Aug 11 06:12:09 PM PDT 24
Finished Aug 11 06:12:10 PM PDT 24
Peak memory 196692 kb
Host smart-74fb4103-367d-4547-a8b1-9f86300e543d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492705791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3492705791
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.256565697
Short name T643
Test name
Test status
Simulation time 278173129 ps
CPU time 2.83 seconds
Started Aug 11 06:12:07 PM PDT 24
Finished Aug 11 06:12:10 PM PDT 24
Peak memory 198604 kb
Host smart-4334bad5-4997-4c8f-993a-d72097e6ef77
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256565697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.256565697
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3896169900
Short name T294
Test name
Test status
Simulation time 358198206 ps
CPU time 2.71 seconds
Started Aug 11 06:12:16 PM PDT 24
Finished Aug 11 06:12:24 PM PDT 24
Peak memory 198596 kb
Host smart-9708cd4f-e1b7-40f6-acd9-d5b319c7623d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896169900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3896169900
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.869591375
Short name T429
Test name
Test status
Simulation time 170664785 ps
CPU time 1.04 seconds
Started Aug 11 06:11:58 PM PDT 24
Finished Aug 11 06:12:00 PM PDT 24
Peak memory 196672 kb
Host smart-41408214-851f-4cb4-8eda-5254a73b1a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869591375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.869591375
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3058618025
Short name T345
Test name
Test status
Simulation time 98308387 ps
CPU time 1.08 seconds
Started Aug 11 06:12:07 PM PDT 24
Finished Aug 11 06:12:08 PM PDT 24
Peak memory 197388 kb
Host smart-e90004f1-d882-405b-8e29-71ba6d34b49a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058618025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3058618025
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3544002340
Short name T572
Test name
Test status
Simulation time 129218346 ps
CPU time 1.67 seconds
Started Aug 11 06:11:58 PM PDT 24
Finished Aug 11 06:12:00 PM PDT 24
Peak memory 198524 kb
Host smart-7691d115-f57a-49f8-bc62-d4f397d22f27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544002340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3544002340
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3783550745
Short name T237
Test name
Test status
Simulation time 181830907 ps
CPU time 1.03 seconds
Started Aug 11 06:11:58 PM PDT 24
Finished Aug 11 06:11:59 PM PDT 24
Peak memory 197256 kb
Host smart-0345e442-cc40-4fe7-a485-86e6e080044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783550745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3783550745
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3316835264
Short name T389
Test name
Test status
Simulation time 192628219 ps
CPU time 1.31 seconds
Started Aug 11 06:12:14 PM PDT 24
Finished Aug 11 06:12:16 PM PDT 24
Peak memory 198580 kb
Host smart-b6246b32-adde-43d3-858e-cf0cc8bacaf4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316835264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3316835264
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2951574310
Short name T225
Test name
Test status
Simulation time 2885764342 ps
CPU time 82.26 seconds
Started Aug 11 06:12:17 PM PDT 24
Finished Aug 11 06:13:39 PM PDT 24
Peak memory 198696 kb
Host smart-573360d8-83ad-40c8-958c-787e5103904e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951574310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2951574310
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1274242104
Short name T377
Test name
Test status
Simulation time 16612480 ps
CPU time 0.59 seconds
Started Aug 11 06:12:07 PM PDT 24
Finished Aug 11 06:12:07 PM PDT 24
Peak memory 194484 kb
Host smart-1a9f9389-e5f8-445a-83c2-d4e43fe32c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274242104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1274242104
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.141430576
Short name T480
Test name
Test status
Simulation time 56279188 ps
CPU time 0.75 seconds
Started Aug 11 06:12:02 PM PDT 24
Finished Aug 11 06:12:03 PM PDT 24
Peak memory 195328 kb
Host smart-3f610be1-3f1b-4c63-bc8d-144f74fc30eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141430576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.141430576
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.676215241
Short name T220
Test name
Test status
Simulation time 157134713 ps
CPU time 8.58 seconds
Started Aug 11 06:12:17 PM PDT 24
Finished Aug 11 06:12:26 PM PDT 24
Peak memory 197496 kb
Host smart-7b56c68a-0184-4b89-8929-618ab6e59229
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676215241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.676215241
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2529913288
Short name T445
Test name
Test status
Simulation time 138487656 ps
CPU time 0.74 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:11:58 PM PDT 24
Peak memory 195180 kb
Host smart-d008b381-33d3-4106-939f-5ef9125f7aaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529913288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2529913288
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2838444548
Short name T696
Test name
Test status
Simulation time 53824580 ps
CPU time 1.02 seconds
Started Aug 11 06:12:12 PM PDT 24
Finished Aug 11 06:12:13 PM PDT 24
Peak memory 196324 kb
Host smart-c91ccdb4-4d70-4949-a731-3802a2792644
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838444548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2838444548
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1547699893
Short name T242
Test name
Test status
Simulation time 794625346 ps
CPU time 2.58 seconds
Started Aug 11 06:12:13 PM PDT 24
Finished Aug 11 06:12:16 PM PDT 24
Peak memory 197028 kb
Host smart-b32340bf-e3da-47e2-9b05-8c6baaf9bdb3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547699893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1547699893
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.839929729
Short name T162
Test name
Test status
Simulation time 346822376 ps
CPU time 3.36 seconds
Started Aug 11 06:12:02 PM PDT 24
Finished Aug 11 06:12:06 PM PDT 24
Peak memory 197628 kb
Host smart-56b429ee-d3e7-47df-bb32-ea5e5e79b765
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839929729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
839929729
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3194869155
Short name T274
Test name
Test status
Simulation time 67730511 ps
CPU time 0.67 seconds
Started Aug 11 06:12:25 PM PDT 24
Finished Aug 11 06:12:26 PM PDT 24
Peak memory 194860 kb
Host smart-42ba7b2c-632a-44ca-aa6b-d1b4ea273420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194869155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3194869155
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2403923405
Short name T412
Test name
Test status
Simulation time 196045881 ps
CPU time 0.81 seconds
Started Aug 11 06:12:02 PM PDT 24
Finished Aug 11 06:12:03 PM PDT 24
Peak memory 196676 kb
Host smart-8e3ce4e1-bda8-4a8c-8199-bc784332250c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403923405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2403923405
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2752223378
Short name T627
Test name
Test status
Simulation time 107873698 ps
CPU time 4.3 seconds
Started Aug 11 06:12:22 PM PDT 24
Finished Aug 11 06:12:27 PM PDT 24
Peak memory 198432 kb
Host smart-c362b1ec-71ee-46e4-8bab-31c581670910
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752223378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2752223378
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3388452364
Short name T151
Test name
Test status
Simulation time 434012609 ps
CPU time 1.02 seconds
Started Aug 11 06:11:59 PM PDT 24
Finished Aug 11 06:12:01 PM PDT 24
Peak memory 196056 kb
Host smart-4757fe9f-6194-47bc-b113-052b0006118d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388452364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3388452364
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1015074742
Short name T701
Test name
Test status
Simulation time 276078999 ps
CPU time 1.35 seconds
Started Aug 11 06:11:58 PM PDT 24
Finished Aug 11 06:12:00 PM PDT 24
Peak memory 196204 kb
Host smart-e0036f68-be0e-494b-b958-5a4670dfac3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015074742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1015074742
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.543529508
Short name T402
Test name
Test status
Simulation time 10015715005 ps
CPU time 63.13 seconds
Started Aug 11 06:12:18 PM PDT 24
Finished Aug 11 06:13:22 PM PDT 24
Peak memory 198680 kb
Host smart-588198f7-a28d-4e4a-9225-04e3ce07ea3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543529508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.543529508
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2753431893
Short name T249
Test name
Test status
Simulation time 16977236 ps
CPU time 0.58 seconds
Started Aug 11 06:12:26 PM PDT 24
Finished Aug 11 06:12:27 PM PDT 24
Peak memory 195368 kb
Host smart-4554551a-c4d8-413e-9c08-929afcaa7680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753431893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2753431893
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2399422230
Short name T432
Test name
Test status
Simulation time 30738990 ps
CPU time 0.8 seconds
Started Aug 11 06:12:07 PM PDT 24
Finished Aug 11 06:12:09 PM PDT 24
Peak memory 196644 kb
Host smart-393c2c83-5145-4bbe-ba65-861a8d22a1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399422230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2399422230
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.562673927
Short name T223
Test name
Test status
Simulation time 1586650831 ps
CPU time 28.42 seconds
Started Aug 11 06:12:06 PM PDT 24
Finished Aug 11 06:12:35 PM PDT 24
Peak memory 198528 kb
Host smart-14326d31-482b-4d4a-97c2-3bcac84eaeae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562673927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.562673927
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1689958274
Short name T65
Test name
Test status
Simulation time 282602460 ps
CPU time 1.01 seconds
Started Aug 11 06:12:19 PM PDT 24
Finished Aug 11 06:12:20 PM PDT 24
Peak memory 198568 kb
Host smart-d0312235-6dd5-4dcf-b95a-87fbb0e6f1da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689958274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1689958274
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.249158437
Short name T489
Test name
Test status
Simulation time 126271149 ps
CPU time 1.15 seconds
Started Aug 11 06:12:09 PM PDT 24
Finished Aug 11 06:12:10 PM PDT 24
Peak memory 196732 kb
Host smart-4ab0f697-2e29-4712-8714-56c58aa66553
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249158437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.249158437
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2067106401
Short name T325
Test name
Test status
Simulation time 141620231 ps
CPU time 2.78 seconds
Started Aug 11 06:12:08 PM PDT 24
Finished Aug 11 06:12:11 PM PDT 24
Peak memory 198596 kb
Host smart-d9193f62-96c8-4ad7-836c-121d00f93473
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067106401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2067106401
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3227459682
Short name T514
Test name
Test status
Simulation time 112474917 ps
CPU time 2.3 seconds
Started Aug 11 06:12:08 PM PDT 24
Finished Aug 11 06:12:11 PM PDT 24
Peak memory 198612 kb
Host smart-2b55727c-f052-4570-bd82-fc7ac9fa7f63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227459682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3227459682
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.495336876
Short name T285
Test name
Test status
Simulation time 236338627 ps
CPU time 1.3 seconds
Started Aug 11 06:12:25 PM PDT 24
Finished Aug 11 06:12:26 PM PDT 24
Peak memory 198544 kb
Host smart-359ddccb-e317-4b14-b041-557e14664a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495336876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.495336876
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1171558994
Short name T620
Test name
Test status
Simulation time 41346506 ps
CPU time 0.91 seconds
Started Aug 11 06:12:07 PM PDT 24
Finished Aug 11 06:12:08 PM PDT 24
Peak memory 196488 kb
Host smart-343bee0d-a0db-4bb8-a3f2-edd63177e1a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171558994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1171558994
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2620127763
Short name T490
Test name
Test status
Simulation time 3872609298 ps
CPU time 4.36 seconds
Started Aug 11 06:12:16 PM PDT 24
Finished Aug 11 06:12:26 PM PDT 24
Peak memory 198528 kb
Host smart-5780a15f-2336-47c7-a68f-3b15cb2e342e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620127763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2620127763
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2204144812
Short name T554
Test name
Test status
Simulation time 246561446 ps
CPU time 1.09 seconds
Started Aug 11 06:12:27 PM PDT 24
Finished Aug 11 06:12:28 PM PDT 24
Peak memory 196112 kb
Host smart-e41b31bc-99b4-4df0-b593-869afa78443a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204144812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2204144812
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3084155570
Short name T583
Test name
Test status
Simulation time 39799444 ps
CPU time 0.84 seconds
Started Aug 11 06:12:18 PM PDT 24
Finished Aug 11 06:12:19 PM PDT 24
Peak memory 196660 kb
Host smart-549daa95-b2d3-4737-85c3-1434c674a316
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084155570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3084155570
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3861435536
Short name T288
Test name
Test status
Simulation time 14591705406 ps
CPU time 199.84 seconds
Started Aug 11 06:12:17 PM PDT 24
Finished Aug 11 06:15:37 PM PDT 24
Peak memory 198744 kb
Host smart-2984ba15-ab23-43be-8135-b1f4b012dbd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861435536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3861435536
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.4294270045
Short name T68
Test name
Test status
Simulation time 97927041933 ps
CPU time 1480.66 seconds
Started Aug 11 06:12:04 PM PDT 24
Finished Aug 11 06:36:45 PM PDT 24
Peak memory 198884 kb
Host smart-4557cbe3-c8bc-43a3-9980-dc9da594e95a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4294270045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.4294270045
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.102506770
Short name T434
Test name
Test status
Simulation time 13909836 ps
CPU time 0.61 seconds
Started Aug 11 06:12:20 PM PDT 24
Finished Aug 11 06:12:21 PM PDT 24
Peak memory 194452 kb
Host smart-7af00055-9d0e-4d89-ba16-df38fb3efe39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102506770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.102506770
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2331607937
Short name T262
Test name
Test status
Simulation time 365855061 ps
CPU time 0.78 seconds
Started Aug 11 06:12:06 PM PDT 24
Finished Aug 11 06:12:06 PM PDT 24
Peak memory 195808 kb
Host smart-b8c67bbd-c03c-49ce-ac92-8f7eee59e8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331607937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2331607937
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2654367565
Short name T499
Test name
Test status
Simulation time 295676095 ps
CPU time 4.98 seconds
Started Aug 11 06:12:10 PM PDT 24
Finished Aug 11 06:12:15 PM PDT 24
Peak memory 197188 kb
Host smart-352eec97-502d-45eb-aeb3-46383145f7b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654367565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2654367565
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.569656415
Short name T444
Test name
Test status
Simulation time 149206787 ps
CPU time 0.97 seconds
Started Aug 11 06:12:11 PM PDT 24
Finished Aug 11 06:12:12 PM PDT 24
Peak memory 197512 kb
Host smart-66083385-0b16-4133-8c14-dcd88ea4c3f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569656415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.569656415
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3115778868
Short name T481
Test name
Test status
Simulation time 51563444 ps
CPU time 0.66 seconds
Started Aug 11 06:12:04 PM PDT 24
Finished Aug 11 06:12:05 PM PDT 24
Peak memory 194848 kb
Host smart-453d289c-a714-4838-b77c-b74a07f6f7c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115778868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3115778868
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2901826960
Short name T410
Test name
Test status
Simulation time 159998994 ps
CPU time 1.38 seconds
Started Aug 11 06:12:26 PM PDT 24
Finished Aug 11 06:12:27 PM PDT 24
Peak memory 197124 kb
Host smart-6f6cf604-564b-4178-8689-67739d61471d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901826960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2901826960
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.397075145
Short name T176
Test name
Test status
Simulation time 410551467 ps
CPU time 2.4 seconds
Started Aug 11 06:12:06 PM PDT 24
Finished Aug 11 06:12:08 PM PDT 24
Peak memory 197508 kb
Host smart-390a9b3f-a883-4f82-887d-a6fd80fcbcd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397075145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
397075145
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.485582028
Short name T679
Test name
Test status
Simulation time 66079443 ps
CPU time 1.22 seconds
Started Aug 11 06:12:05 PM PDT 24
Finished Aug 11 06:12:07 PM PDT 24
Peak memory 197700 kb
Host smart-5cc1e3f0-726c-49c2-b0b8-f0771b48a11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485582028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.485582028
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1538581498
Short name T312
Test name
Test status
Simulation time 71738523 ps
CPU time 0.89 seconds
Started Aug 11 06:12:23 PM PDT 24
Finished Aug 11 06:12:24 PM PDT 24
Peak memory 197216 kb
Host smart-b772050c-f3ce-4835-80e3-562147e67910
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538581498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1538581498
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.4018513092
Short name T439
Test name
Test status
Simulation time 413757364 ps
CPU time 5.02 seconds
Started Aug 11 06:12:08 PM PDT 24
Finished Aug 11 06:12:13 PM PDT 24
Peak memory 198536 kb
Host smart-d698d210-954c-4e1a-8a1c-a6e72270e8f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018513092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.4018513092
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.972022583
Short name T335
Test name
Test status
Simulation time 133976977 ps
CPU time 1.31 seconds
Started Aug 11 06:12:18 PM PDT 24
Finished Aug 11 06:12:19 PM PDT 24
Peak memory 198472 kb
Host smart-93bc8e90-efc8-42d4-9e36-87fedaf4a10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972022583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.972022583
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1214318634
Short name T114
Test name
Test status
Simulation time 120802377 ps
CPU time 1.13 seconds
Started Aug 11 06:12:09 PM PDT 24
Finished Aug 11 06:12:10 PM PDT 24
Peak memory 196916 kb
Host smart-15ebd43f-330b-4cc5-8a9f-13bd1be52b20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214318634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1214318634
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2551184079
Short name T236
Test name
Test status
Simulation time 4693304238 ps
CPU time 136.07 seconds
Started Aug 11 06:12:14 PM PDT 24
Finished Aug 11 06:14:30 PM PDT 24
Peak memory 198788 kb
Host smart-0672cf33-fba9-40a2-bc41-11107b44d0ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551184079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2551184079
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3442043422
Short name T276
Test name
Test status
Simulation time 17266965 ps
CPU time 0.62 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:12:39 PM PDT 24
Peak memory 195180 kb
Host smart-2a027b5b-5bc1-438b-970d-be2f926b05d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442043422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3442043422
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2807643935
Short name T505
Test name
Test status
Simulation time 119866285 ps
CPU time 0.83 seconds
Started Aug 11 06:12:12 PM PDT 24
Finished Aug 11 06:12:13 PM PDT 24
Peak memory 196500 kb
Host smart-c816bd9b-5efe-4072-815c-5587f06df6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807643935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2807643935
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1416675904
Short name T283
Test name
Test status
Simulation time 907170542 ps
CPU time 18.39 seconds
Started Aug 11 06:12:17 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 197340 kb
Host smart-c6455eb9-ba11-4ac1-9441-a9c98c27c961
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416675904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1416675904
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3270100765
Short name T224
Test name
Test status
Simulation time 33747448 ps
CPU time 0.76 seconds
Started Aug 11 06:12:26 PM PDT 24
Finished Aug 11 06:12:27 PM PDT 24
Peak memory 196536 kb
Host smart-6c42f4ee-0c19-4559-8770-a05f877e90f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270100765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3270100765
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2110808285
Short name T552
Test name
Test status
Simulation time 90153504 ps
CPU time 1.39 seconds
Started Aug 11 06:12:11 PM PDT 24
Finished Aug 11 06:12:13 PM PDT 24
Peak memory 196480 kb
Host smart-0baf73a3-8b2c-48dc-9e9f-04e6ae3b4f27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110808285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2110808285
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1920721108
Short name T14
Test name
Test status
Simulation time 436980651 ps
CPU time 2.93 seconds
Started Aug 11 06:12:11 PM PDT 24
Finished Aug 11 06:12:14 PM PDT 24
Peak memory 198652 kb
Host smart-e4c316cf-6f90-48d3-85bf-9d3a0d51e53e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920721108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1920721108
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2243343213
Short name T715
Test name
Test status
Simulation time 36242599 ps
CPU time 1.18 seconds
Started Aug 11 06:12:11 PM PDT 24
Finished Aug 11 06:12:12 PM PDT 24
Peak memory 197020 kb
Host smart-b6641c82-5076-488a-8d13-8179f7de4da7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243343213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2243343213
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.4286541305
Short name T668
Test name
Test status
Simulation time 130576995 ps
CPU time 0.8 seconds
Started Aug 11 06:12:28 PM PDT 24
Finished Aug 11 06:12:29 PM PDT 24
Peak memory 197020 kb
Host smart-e9794a51-c384-4b81-9625-1803856dc6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286541305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.4286541305
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2663009342
Short name T491
Test name
Test status
Simulation time 65023921 ps
CPU time 0.64 seconds
Started Aug 11 06:12:25 PM PDT 24
Finished Aug 11 06:12:26 PM PDT 24
Peak memory 194840 kb
Host smart-468b4c17-76d4-45b9-bd0a-e03afc0abd81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663009342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2663009342
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.319766759
Short name T397
Test name
Test status
Simulation time 156150700 ps
CPU time 3.88 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 198576 kb
Host smart-d08dc75d-b344-43ec-902e-97244557fa7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319766759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.319766759
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2874393
Short name T145
Test name
Test status
Simulation time 145846467 ps
CPU time 0.81 seconds
Started Aug 11 06:12:25 PM PDT 24
Finished Aug 11 06:12:26 PM PDT 24
Peak memory 195892 kb
Host smart-85893a40-8067-4afa-8598-210cb4a0527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2874393
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3032120059
Short name T207
Test name
Test status
Simulation time 121847181 ps
CPU time 1.21 seconds
Started Aug 11 06:12:09 PM PDT 24
Finished Aug 11 06:12:10 PM PDT 24
Peak memory 196356 kb
Host smart-c131dddb-d347-4e65-ae14-a345fed079f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032120059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3032120059
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.679646880
Short name T529
Test name
Test status
Simulation time 51671250815 ps
CPU time 164.29 seconds
Started Aug 11 06:12:28 PM PDT 24
Finished Aug 11 06:15:12 PM PDT 24
Peak memory 198704 kb
Host smart-9043930a-0d08-4d4d-b179-e6dee7bb2d6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679646880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.679646880
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1025228089
Short name T587
Test name
Test status
Simulation time 44426499 ps
CPU time 0.57 seconds
Started Aug 11 06:12:36 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 195380 kb
Host smart-f8bab8b2-c996-4f94-95e5-0bd681e7de97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025228089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1025228089
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1103755740
Short name T16
Test name
Test status
Simulation time 20952051 ps
CPU time 0.7 seconds
Started Aug 11 06:12:30 PM PDT 24
Finished Aug 11 06:12:31 PM PDT 24
Peak memory 195728 kb
Host smart-dbf37305-af11-4166-971e-a85d439117ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103755740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1103755740
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1263666337
Short name T549
Test name
Test status
Simulation time 249361580 ps
CPU time 12.19 seconds
Started Aug 11 06:12:10 PM PDT 24
Finished Aug 11 06:12:23 PM PDT 24
Peak memory 197664 kb
Host smart-66054ac9-453f-4a51-8949-d797bcb6e29c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263666337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1263666337
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1280962400
Short name T631
Test name
Test status
Simulation time 627412479 ps
CPU time 1.04 seconds
Started Aug 11 06:12:17 PM PDT 24
Finished Aug 11 06:12:18 PM PDT 24
Peak memory 196960 kb
Host smart-3bd3980b-3ba4-4d3b-b66c-6e7dfd8ab7be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280962400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1280962400
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3233769803
Short name T477
Test name
Test status
Simulation time 83831514 ps
CPU time 0.76 seconds
Started Aug 11 06:12:25 PM PDT 24
Finished Aug 11 06:12:26 PM PDT 24
Peak memory 195896 kb
Host smart-69afadfc-b0b3-4cc4-9f5a-f5a8e12de56d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233769803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3233769803
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3989272427
Short name T152
Test name
Test status
Simulation time 69153065 ps
CPU time 2.63 seconds
Started Aug 11 06:12:14 PM PDT 24
Finished Aug 11 06:12:16 PM PDT 24
Peak memory 197108 kb
Host smart-1ac4043a-3866-4342-b823-731aa190cf2f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989272427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3989272427
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.146769906
Short name T124
Test name
Test status
Simulation time 720134593 ps
CPU time 2.22 seconds
Started Aug 11 06:12:07 PM PDT 24
Finished Aug 11 06:12:09 PM PDT 24
Peak memory 197340 kb
Host smart-d8958977-02f8-4d01-9af4-c4e8d7b6eeeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146769906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
146769906
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4141028964
Short name T181
Test name
Test status
Simulation time 93774242 ps
CPU time 1.32 seconds
Started Aug 11 06:12:12 PM PDT 24
Finished Aug 11 06:12:13 PM PDT 24
Peak memory 197580 kb
Host smart-f118f24d-522d-40f3-ad37-fed03647f289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141028964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4141028964
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3053430337
Short name T148
Test name
Test status
Simulation time 56507424 ps
CPU time 1.25 seconds
Started Aug 11 06:12:22 PM PDT 24
Finished Aug 11 06:12:23 PM PDT 24
Peak memory 198644 kb
Host smart-1504aa91-1312-48c6-a7af-de332977a8a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053430337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3053430337
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.880519001
Short name T484
Test name
Test status
Simulation time 274730573 ps
CPU time 4.44 seconds
Started Aug 11 06:12:16 PM PDT 24
Finished Aug 11 06:12:20 PM PDT 24
Peak memory 198592 kb
Host smart-31379ba6-015f-47c6-8872-9b7298092b90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880519001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.880519001
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1974464655
Short name T621
Test name
Test status
Simulation time 23925640 ps
CPU time 0.7 seconds
Started Aug 11 06:12:09 PM PDT 24
Finished Aug 11 06:12:10 PM PDT 24
Peak memory 194756 kb
Host smart-cf9d9f65-48a3-4237-a6c4-23250dba3bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974464655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1974464655
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3259822526
Short name T697
Test name
Test status
Simulation time 64798583 ps
CPU time 1.11 seconds
Started Aug 11 06:12:25 PM PDT 24
Finished Aug 11 06:12:26 PM PDT 24
Peak memory 196312 kb
Host smart-0acafc67-3e2b-49d1-a09e-0d27f1e2c8f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259822526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3259822526
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2897813486
Short name T328
Test name
Test status
Simulation time 34048330004 ps
CPU time 141.58 seconds
Started Aug 11 06:12:26 PM PDT 24
Finished Aug 11 06:14:47 PM PDT 24
Peak memory 198736 kb
Host smart-ccdc22b9-644c-4fe2-a560-55a23edba640
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897813486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2897813486
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.4197651277
Short name T672
Test name
Test status
Simulation time 59333811 ps
CPU time 0.57 seconds
Started Aug 11 06:11:52 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 194688 kb
Host smart-930ba11f-69d7-4071-a2a5-538278c8c132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197651277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.4197651277
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.221493558
Short name T714
Test name
Test status
Simulation time 45944752 ps
CPU time 0.57 seconds
Started Aug 11 06:11:40 PM PDT 24
Finished Aug 11 06:11:41 PM PDT 24
Peak memory 194488 kb
Host smart-8c123d9b-8657-4a03-8171-3b6e965059b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221493558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.221493558
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.434804592
Short name T136
Test name
Test status
Simulation time 1831890099 ps
CPU time 23.78 seconds
Started Aug 11 06:11:38 PM PDT 24
Finished Aug 11 06:12:02 PM PDT 24
Peak memory 197528 kb
Host smart-e1bd449d-dde8-4eea-b908-96b53cffe7d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434804592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.434804592
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3411731010
Short name T447
Test name
Test status
Simulation time 1033536719 ps
CPU time 1.02 seconds
Started Aug 11 06:11:56 PM PDT 24
Finished Aug 11 06:11:57 PM PDT 24
Peak memory 197288 kb
Host smart-3753692f-980d-458f-905d-3d3cbda6c1f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411731010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3411731010
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1378126918
Short name T27
Test name
Test status
Simulation time 217834083 ps
CPU time 1.4 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:11:49 PM PDT 24
Peak memory 197704 kb
Host smart-f9a788f5-69f9-4f9d-a382-2ffbe65b5d81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378126918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1378126918
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2888175200
Short name T305
Test name
Test status
Simulation time 113619801 ps
CPU time 2.26 seconds
Started Aug 11 06:11:51 PM PDT 24
Finished Aug 11 06:11:54 PM PDT 24
Peak memory 198604 kb
Host smart-4743617c-de13-4404-a2be-97b5fc09f43e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888175200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2888175200
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2902919014
Short name T183
Test name
Test status
Simulation time 51452661 ps
CPU time 1.21 seconds
Started Aug 11 06:11:41 PM PDT 24
Finished Aug 11 06:11:43 PM PDT 24
Peak memory 196048 kb
Host smart-9a68f114-a50a-4db6-bbc1-9fe440504c68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902919014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2902919014
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2524925447
Short name T585
Test name
Test status
Simulation time 84048469 ps
CPU time 0.88 seconds
Started Aug 11 06:11:42 PM PDT 24
Finished Aug 11 06:11:43 PM PDT 24
Peak memory 196316 kb
Host smart-99d25f72-fe57-45ab-aa42-8023295283b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524925447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2524925447
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.4031579692
Short name T506
Test name
Test status
Simulation time 24845844 ps
CPU time 0.74 seconds
Started Aug 11 06:11:47 PM PDT 24
Finished Aug 11 06:11:47 PM PDT 24
Peak memory 196668 kb
Host smart-2e8c523f-14c2-47cc-bd6e-c748e470c038
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031579692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.4031579692
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3065737969
Short name T665
Test name
Test status
Simulation time 155269582 ps
CPU time 3.29 seconds
Started Aug 11 06:11:42 PM PDT 24
Finished Aug 11 06:11:45 PM PDT 24
Peak memory 198568 kb
Host smart-01f67909-fb49-4583-9ec3-a9e35f3a9fcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065737969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3065737969
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.2335889657
Short name T400
Test name
Test status
Simulation time 171279720 ps
CPU time 1.23 seconds
Started Aug 11 06:11:46 PM PDT 24
Finished Aug 11 06:11:47 PM PDT 24
Peak memory 196404 kb
Host smart-b36e43c4-9469-4cea-8a83-74d6bb357c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335889657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2335889657
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2833107284
Short name T144
Test name
Test status
Simulation time 29524583 ps
CPU time 0.77 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 195692 kb
Host smart-e4aab865-0d10-4a71-aefb-5b5352ff4e1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833107284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2833107284
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.147885214
Short name T330
Test name
Test status
Simulation time 31370737332 ps
CPU time 121.21 seconds
Started Aug 11 06:11:44 PM PDT 24
Finished Aug 11 06:13:45 PM PDT 24
Peak memory 198728 kb
Host smart-a9c208db-5fca-4351-a464-74a9945b374d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147885214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.147885214
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.2237270011
Short name T398
Test name
Test status
Simulation time 46193154620 ps
CPU time 894.33 seconds
Started Aug 11 06:11:43 PM PDT 24
Finished Aug 11 06:26:38 PM PDT 24
Peak memory 207344 kb
Host smart-dfaf9bf9-f788-46f5-86e9-629b1877c45b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2237270011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.2237270011
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1431398843
Short name T646
Test name
Test status
Simulation time 15548312 ps
CPU time 0.56 seconds
Started Aug 11 06:12:29 PM PDT 24
Finished Aug 11 06:12:29 PM PDT 24
Peak memory 194476 kb
Host smart-bb33c774-5388-449a-9bce-0386463caec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431398843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1431398843
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2191064660
Short name T710
Test name
Test status
Simulation time 28522418 ps
CPU time 0.61 seconds
Started Aug 11 06:12:30 PM PDT 24
Finished Aug 11 06:12:31 PM PDT 24
Peak memory 194184 kb
Host smart-d3213daf-a3cd-4cf7-97ab-8b0768fefce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191064660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2191064660
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1902659104
Short name T451
Test name
Test status
Simulation time 1050509020 ps
CPU time 7.7 seconds
Started Aug 11 06:12:40 PM PDT 24
Finished Aug 11 06:12:48 PM PDT 24
Peak memory 197720 kb
Host smart-cb39aa16-ef3c-42bf-80ca-7d4286c41eaf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902659104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1902659104
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.264167905
Short name T516
Test name
Test status
Simulation time 233332348 ps
CPU time 0.83 seconds
Started Aug 11 06:12:33 PM PDT 24
Finished Aug 11 06:12:34 PM PDT 24
Peak memory 196548 kb
Host smart-bdcb7da5-040c-4850-b242-47625d552ad7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264167905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.264167905
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.4138040125
Short name T337
Test name
Test status
Simulation time 36224404 ps
CPU time 1.03 seconds
Started Aug 11 06:12:26 PM PDT 24
Finished Aug 11 06:12:27 PM PDT 24
Peak memory 197412 kb
Host smart-5fa200bf-9f29-4a17-adbc-e31da219745c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138040125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.4138040125
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.78441638
Short name T272
Test name
Test status
Simulation time 175221099 ps
CPU time 2.04 seconds
Started Aug 11 06:12:22 PM PDT 24
Finished Aug 11 06:12:24 PM PDT 24
Peak memory 198740 kb
Host smart-00ef12be-9b2b-4f45-96d1-6f1ca40625ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78441638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.gpio_intr_with_filter_rand_intr_event.78441638
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3003855256
Short name T636
Test name
Test status
Simulation time 95243873 ps
CPU time 2.66 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:48 PM PDT 24
Peak memory 197776 kb
Host smart-c0c85816-909c-42a2-b1de-f6573dbba4fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003855256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3003855256
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2018862663
Short name T171
Test name
Test status
Simulation time 333863125 ps
CPU time 1.22 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 196376 kb
Host smart-3b9827ca-f8e6-4630-832e-c42ca9f1001b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018862663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2018862663
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.189137149
Short name T154
Test name
Test status
Simulation time 67915502 ps
CPU time 0.65 seconds
Started Aug 11 06:12:31 PM PDT 24
Finished Aug 11 06:12:32 PM PDT 24
Peak memory 194900 kb
Host smart-1355d617-e876-4a48-a6df-45b294471554
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189137149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.189137149
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.21188580
Short name T309
Test name
Test status
Simulation time 46477561 ps
CPU time 2.07 seconds
Started Aug 11 06:12:47 PM PDT 24
Finished Aug 11 06:12:49 PM PDT 24
Peak memory 198612 kb
Host smart-611591cc-001a-4202-825f-6b187a35f5db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21188580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand
om_long_reg_writes_reg_reads.21188580
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2912639127
Short name T315
Test name
Test status
Simulation time 51707929 ps
CPU time 1.37 seconds
Started Aug 11 06:12:27 PM PDT 24
Finished Aug 11 06:12:28 PM PDT 24
Peak memory 197364 kb
Host smart-a3fb2202-1ec7-4649-934d-4815ff56e286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912639127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2912639127
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1745776052
Short name T616
Test name
Test status
Simulation time 196179984 ps
CPU time 1.37 seconds
Started Aug 11 06:12:12 PM PDT 24
Finished Aug 11 06:12:14 PM PDT 24
Peak memory 195924 kb
Host smart-106b40dd-cd76-4101-99c6-96bba0d0d8cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745776052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1745776052
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.550932759
Short name T119
Test name
Test status
Simulation time 5449729918 ps
CPU time 19 seconds
Started Aug 11 06:12:26 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 198676 kb
Host smart-b7324c2a-22e5-4639-9c44-f955d3fcf09e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550932759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.550932759
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3516296375
Short name T468
Test name
Test status
Simulation time 11766030 ps
CPU time 0.55 seconds
Started Aug 11 06:12:15 PM PDT 24
Finished Aug 11 06:12:16 PM PDT 24
Peak memory 194512 kb
Host smart-2d16af1b-3272-48ce-9ee7-d1839a1d6cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516296375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3516296375
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.721788558
Short name T356
Test name
Test status
Simulation time 45779709 ps
CPU time 0.65 seconds
Started Aug 11 06:12:20 PM PDT 24
Finished Aug 11 06:12:21 PM PDT 24
Peak memory 195196 kb
Host smart-a038b52d-8d21-44f6-ab84-f18ae0720a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721788558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.721788558
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3661883548
Short name T296
Test name
Test status
Simulation time 556398780 ps
CPU time 4.12 seconds
Started Aug 11 06:12:17 PM PDT 24
Finished Aug 11 06:12:21 PM PDT 24
Peak memory 196404 kb
Host smart-134542d1-b99d-46ac-81fb-29995f79035f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661883548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3661883548
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2101650230
Short name T401
Test name
Test status
Simulation time 257696939 ps
CPU time 0.96 seconds
Started Aug 11 06:12:30 PM PDT 24
Finished Aug 11 06:12:31 PM PDT 24
Peak memory 197504 kb
Host smart-e4d045d7-f0ba-4709-9399-a0e38c3a5175
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101650230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2101650230
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3487262252
Short name T705
Test name
Test status
Simulation time 162185122 ps
CPU time 1.28 seconds
Started Aug 11 06:12:33 PM PDT 24
Finished Aug 11 06:12:35 PM PDT 24
Peak memory 197300 kb
Host smart-2eb62322-8d2a-48ef-bad9-d2cbc7ff6365
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487262252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3487262252
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2245127869
Short name T322
Test name
Test status
Simulation time 58240565 ps
CPU time 2.36 seconds
Started Aug 11 06:12:26 PM PDT 24
Finished Aug 11 06:12:28 PM PDT 24
Peak memory 198644 kb
Host smart-909e262a-0186-4a6c-a17c-341dbcd49be1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245127869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2245127869
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1045895427
Short name T711
Test name
Test status
Simulation time 99626655 ps
CPU time 2.85 seconds
Started Aug 11 06:12:28 PM PDT 24
Finished Aug 11 06:12:31 PM PDT 24
Peak memory 196400 kb
Host smart-0f4f7db5-3ce2-4bf3-a491-257ffd989df2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045895427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1045895427
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1828913103
Short name T374
Test name
Test status
Simulation time 78624466 ps
CPU time 0.73 seconds
Started Aug 11 06:12:19 PM PDT 24
Finished Aug 11 06:12:19 PM PDT 24
Peak memory 195924 kb
Host smart-0ca0d5a8-76b3-43a9-8256-08f68fd5d1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828913103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1828913103
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3323770950
Short name T212
Test name
Test status
Simulation time 64078282 ps
CPU time 1.16 seconds
Started Aug 11 06:12:31 PM PDT 24
Finished Aug 11 06:12:32 PM PDT 24
Peak memory 196352 kb
Host smart-7f909004-2fd5-455e-8b6a-1c6767dea84d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323770950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3323770950
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.462244842
Short name T332
Test name
Test status
Simulation time 89806046 ps
CPU time 4.11 seconds
Started Aug 11 06:12:23 PM PDT 24
Finished Aug 11 06:12:27 PM PDT 24
Peak memory 198564 kb
Host smart-76c19084-b8f9-4db3-b11e-193e8a2aeeeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462244842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.462244842
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3989798470
Short name T403
Test name
Test status
Simulation time 62759467 ps
CPU time 1.21 seconds
Started Aug 11 06:12:26 PM PDT 24
Finished Aug 11 06:12:28 PM PDT 24
Peak memory 196852 kb
Host smart-4e53d3f7-9dfe-405a-b7d4-e06a2f633482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989798470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3989798470
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1152891542
Short name T551
Test name
Test status
Simulation time 49025504 ps
CPU time 1.03 seconds
Started Aug 11 06:12:20 PM PDT 24
Finished Aug 11 06:12:22 PM PDT 24
Peak memory 196856 kb
Host smart-22b6c398-d67b-4565-a419-d9661bed56fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152891542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1152891542
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.751129620
Short name T425
Test name
Test status
Simulation time 21563161159 ps
CPU time 211.3 seconds
Started Aug 11 06:12:28 PM PDT 24
Finished Aug 11 06:15:59 PM PDT 24
Peak memory 198712 kb
Host smart-54094621-a11e-4f2a-abfa-099017632059
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751129620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.751129620
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.4266014655
Short name T707
Test name
Test status
Simulation time 92135603 ps
CPU time 0.86 seconds
Started Aug 11 06:12:22 PM PDT 24
Finished Aug 11 06:12:23 PM PDT 24
Peak memory 195944 kb
Host smart-46c8c36a-0599-46d6-8b3a-2beb614786ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266014655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.4266014655
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3083892829
Short name T331
Test name
Test status
Simulation time 340622058 ps
CPU time 11.03 seconds
Started Aug 11 06:12:16 PM PDT 24
Finished Aug 11 06:12:27 PM PDT 24
Peak memory 197216 kb
Host smart-4af62195-3d2a-4375-9ca9-0a6a2008b944
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083892829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3083892829
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2005236107
Short name T318
Test name
Test status
Simulation time 23613203 ps
CPU time 0.65 seconds
Started Aug 11 06:12:18 PM PDT 24
Finished Aug 11 06:12:19 PM PDT 24
Peak memory 195756 kb
Host smart-e37991e5-c710-491c-b3b3-e40c8dd6620a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005236107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2005236107
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3765133762
Short name T441
Test name
Test status
Simulation time 177751297 ps
CPU time 0.83 seconds
Started Aug 11 06:12:16 PM PDT 24
Finished Aug 11 06:12:17 PM PDT 24
Peak memory 196420 kb
Host smart-4b649c4c-8bdc-4c08-8221-31b153151465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765133762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3765133762
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1996086679
Short name T165
Test name
Test status
Simulation time 670199546 ps
CPU time 3.19 seconds
Started Aug 11 06:12:15 PM PDT 24
Finished Aug 11 06:12:18 PM PDT 24
Peak memory 198684 kb
Host smart-91959b98-0ff8-4661-8ffc-62d6a1994f56
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996086679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1996086679
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.354380047
Short name T158
Test name
Test status
Simulation time 65153056 ps
CPU time 1.91 seconds
Started Aug 11 06:12:18 PM PDT 24
Finished Aug 11 06:12:20 PM PDT 24
Peak memory 197836 kb
Host smart-ccf86974-6aa7-4bfa-9b1f-1c0ce72ee664
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354380047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
354380047
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.889879385
Short name T661
Test name
Test status
Simulation time 468233381 ps
CPU time 0.99 seconds
Started Aug 11 06:12:54 PM PDT 24
Finished Aug 11 06:12:55 PM PDT 24
Peak memory 196568 kb
Host smart-33a241a1-f97f-4df7-af2a-1d15020062ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889879385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.889879385
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1835769006
Short name T433
Test name
Test status
Simulation time 154907361 ps
CPU time 0.96 seconds
Started Aug 11 06:12:27 PM PDT 24
Finished Aug 11 06:12:28 PM PDT 24
Peak memory 197072 kb
Host smart-8a42af57-e836-4684-8ecd-e571caef2141
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835769006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1835769006
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1086058965
Short name T567
Test name
Test status
Simulation time 92996026 ps
CPU time 4.22 seconds
Started Aug 11 06:12:34 PM PDT 24
Finished Aug 11 06:12:39 PM PDT 24
Peak memory 198524 kb
Host smart-c4a379d9-a7b4-460d-b8d1-955715db4e20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086058965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1086058965
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.804044910
Short name T641
Test name
Test status
Simulation time 42529285 ps
CPU time 1.11 seconds
Started Aug 11 06:12:25 PM PDT 24
Finished Aug 11 06:12:27 PM PDT 24
Peak memory 196416 kb
Host smart-e4ff4416-08e1-4f57-abfa-164c2b360c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804044910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.804044910
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3115538045
Short name T373
Test name
Test status
Simulation time 73772514 ps
CPU time 0.88 seconds
Started Aug 11 06:12:21 PM PDT 24
Finished Aug 11 06:12:22 PM PDT 24
Peak memory 195740 kb
Host smart-74bf4218-9388-4067-aa35-2bf72c7ccd85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115538045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3115538045
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2494051323
Short name T323
Test name
Test status
Simulation time 31945740033 ps
CPU time 83.36 seconds
Started Aug 11 06:12:15 PM PDT 24
Finished Aug 11 06:13:39 PM PDT 24
Peak memory 198728 kb
Host smart-ccea554f-dd1d-4938-9061-cef7949514f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494051323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2494051323
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.894371610
Short name T77
Test name
Test status
Simulation time 38787427 ps
CPU time 0.59 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:42 PM PDT 24
Peak memory 195540 kb
Host smart-b362c95d-2830-42fd-9194-7156549aaa21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894371610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.894371610
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3560131131
Short name T698
Test name
Test status
Simulation time 72769004 ps
CPU time 0.75 seconds
Started Aug 11 06:12:31 PM PDT 24
Finished Aug 11 06:12:31 PM PDT 24
Peak memory 195828 kb
Host smart-735e744c-4aac-4bc9-945b-a0e277c51f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560131131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3560131131
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1653634837
Short name T578
Test name
Test status
Simulation time 6205478194 ps
CPU time 26.45 seconds
Started Aug 11 06:12:36 PM PDT 24
Finished Aug 11 06:13:02 PM PDT 24
Peak memory 197676 kb
Host smart-abaabff0-abee-42ca-93bc-586380477841
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653634837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1653634837
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1367455949
Short name T428
Test name
Test status
Simulation time 619329937 ps
CPU time 0.94 seconds
Started Aug 11 06:12:50 PM PDT 24
Finished Aug 11 06:12:51 PM PDT 24
Peak memory 198464 kb
Host smart-f8e54372-e190-4e16-b2df-24cb82202fcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367455949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1367455949
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.92973498
Short name T685
Test name
Test status
Simulation time 140136196 ps
CPU time 0.99 seconds
Started Aug 11 06:12:24 PM PDT 24
Finished Aug 11 06:12:25 PM PDT 24
Peak memory 197568 kb
Host smart-a13bb4b2-3496-4d32-b117-d8d4538e0a5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92973498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.92973498
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2923086113
Short name T73
Test name
Test status
Simulation time 248317157 ps
CPU time 1.85 seconds
Started Aug 11 06:12:29 PM PDT 24
Finished Aug 11 06:12:31 PM PDT 24
Peak memory 198604 kb
Host smart-16ab6716-7e27-4e19-b5c6-8be85410a9aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923086113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2923086113
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.444075592
Short name T580
Test name
Test status
Simulation time 58702621 ps
CPU time 1.47 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 197400 kb
Host smart-676c043f-48b0-4728-ba7e-26b5eb57ab57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444075592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
444075592
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.92759177
Short name T383
Test name
Test status
Simulation time 43312313 ps
CPU time 0.9 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:42 PM PDT 24
Peak memory 196364 kb
Host smart-d908b980-89d5-4f31-b8a2-98d9b094937f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92759177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.92759177
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2992851533
Short name T361
Test name
Test status
Simulation time 56182349 ps
CPU time 1.14 seconds
Started Aug 11 06:12:29 PM PDT 24
Finished Aug 11 06:12:30 PM PDT 24
Peak memory 197652 kb
Host smart-5d5d16e4-725e-4835-8ce0-0a8a5a845b35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992851533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2992851533
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1152679557
Short name T573
Test name
Test status
Simulation time 249966484 ps
CPU time 5.93 seconds
Started Aug 11 06:12:39 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 198596 kb
Host smart-08daf24f-a63a-4f47-afea-7dedda49ea4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152679557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1152679557
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2160071086
Short name T694
Test name
Test status
Simulation time 357047262 ps
CPU time 1.28 seconds
Started Aug 11 06:12:34 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 196144 kb
Host smart-7ec9141c-7857-4009-88d5-34ab3c427d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160071086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2160071086
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.135147546
Short name T118
Test name
Test status
Simulation time 83418543 ps
CPU time 1.37 seconds
Started Aug 11 06:12:44 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 197304 kb
Host smart-929de5bc-7703-4c54-bc9f-0fc01b47a9bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135147546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.135147546
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3736288550
Short name T463
Test name
Test status
Simulation time 47825818822 ps
CPU time 75.6 seconds
Started Aug 11 06:12:33 PM PDT 24
Finished Aug 11 06:13:49 PM PDT 24
Peak memory 192708 kb
Host smart-af54fa42-ea87-4172-863f-a01cb57afcfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736288550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3736288550
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2448237072
Short name T211
Test name
Test status
Simulation time 33136744 ps
CPU time 0.56 seconds
Started Aug 11 06:12:26 PM PDT 24
Finished Aug 11 06:12:27 PM PDT 24
Peak memory 194440 kb
Host smart-a6f6188c-df1b-4738-a26a-d3eb40d40266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448237072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2448237072
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1537015390
Short name T408
Test name
Test status
Simulation time 229951122 ps
CPU time 0.83 seconds
Started Aug 11 06:12:33 PM PDT 24
Finished Aug 11 06:12:34 PM PDT 24
Peak memory 196816 kb
Host smart-62288755-bd64-402d-aa10-1f2477b87a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537015390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1537015390
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3210952996
Short name T617
Test name
Test status
Simulation time 921197908 ps
CPU time 24.39 seconds
Started Aug 11 06:12:36 PM PDT 24
Finished Aug 11 06:13:01 PM PDT 24
Peak memory 196992 kb
Host smart-ba37865a-8cee-4ddf-8c4d-65073b283968
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210952996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3210952996
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1356552909
Short name T591
Test name
Test status
Simulation time 30141309 ps
CPU time 0.75 seconds
Started Aug 11 06:12:44 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 196288 kb
Host smart-4ab7ba6b-ab46-4365-80a4-d2d2320b5c30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356552909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1356552909
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2249936259
Short name T584
Test name
Test status
Simulation time 181163375 ps
CPU time 1.43 seconds
Started Aug 11 06:12:31 PM PDT 24
Finished Aug 11 06:12:33 PM PDT 24
Peak memory 198684 kb
Host smart-624fc6e9-3af6-46e9-be27-68d235b702df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249936259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2249936259
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.167651185
Short name T656
Test name
Test status
Simulation time 288847448 ps
CPU time 2.5 seconds
Started Aug 11 06:12:34 PM PDT 24
Finished Aug 11 06:12:37 PM PDT 24
Peak memory 198596 kb
Host smart-1910d401-7b14-415a-bdf6-44f7a4a4c7fb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167651185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.167651185
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3385078799
Short name T386
Test name
Test status
Simulation time 207343917 ps
CPU time 0.89 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:12:39 PM PDT 24
Peak memory 195044 kb
Host smart-fdfa381d-8559-4ed4-b8f5-20d93b7f3721
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385078799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3385078799
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3439536815
Short name T340
Test name
Test status
Simulation time 55121768 ps
CPU time 1.16 seconds
Started Aug 11 06:12:30 PM PDT 24
Finished Aug 11 06:12:31 PM PDT 24
Peak memory 197740 kb
Host smart-283a974f-8e39-4758-9651-b1a7591384d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439536815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3439536815
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.423467246
Short name T592
Test name
Test status
Simulation time 30421103 ps
CPU time 0.68 seconds
Started Aug 11 06:12:32 PM PDT 24
Finished Aug 11 06:12:33 PM PDT 24
Peak memory 194796 kb
Host smart-5fa8fd32-096f-4a72-bfcc-cbab8c57e094
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423467246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.423467246
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2403749020
Short name T633
Test name
Test status
Simulation time 824000099 ps
CPU time 4.81 seconds
Started Aug 11 06:12:35 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 198524 kb
Host smart-47cb2658-c106-47e3-9b81-1a25773d3fe1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403749020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2403749020
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3436948692
Short name T637
Test name
Test status
Simulation time 139380970 ps
CPU time 1.09 seconds
Started Aug 11 06:12:34 PM PDT 24
Finished Aug 11 06:12:35 PM PDT 24
Peak memory 196072 kb
Host smart-f7d460ed-65be-4517-9cda-abd28408e7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436948692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3436948692
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.104508566
Short name T456
Test name
Test status
Simulation time 94541233 ps
CPU time 1.4 seconds
Started Aug 11 06:12:33 PM PDT 24
Finished Aug 11 06:12:35 PM PDT 24
Peak memory 197396 kb
Host smart-76e82aa3-f66c-4e69-b596-c954b6ff1d11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104508566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.104508566
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3992825194
Short name T606
Test name
Test status
Simulation time 38128028192 ps
CPU time 198.37 seconds
Started Aug 11 06:12:32 PM PDT 24
Finished Aug 11 06:15:50 PM PDT 24
Peak memory 198748 kb
Host smart-bbb5a776-b303-4f95-bf86-9746e4681657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992825194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3992825194
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3793128915
Short name T662
Test name
Test status
Simulation time 36055474 ps
CPU time 0.54 seconds
Started Aug 11 06:12:30 PM PDT 24
Finished Aug 11 06:12:31 PM PDT 24
Peak memory 194516 kb
Host smart-c9ab67a3-2748-4fed-b431-5df93cf5ee71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793128915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3793128915
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1490432176
Short name T600
Test name
Test status
Simulation time 17638374 ps
CPU time 0.64 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:46 PM PDT 24
Peak memory 195076 kb
Host smart-18f87337-669c-4297-ab0c-73155a4b52dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490432176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1490432176
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.747889085
Short name T420
Test name
Test status
Simulation time 312360755 ps
CPU time 16.16 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:58 PM PDT 24
Peak memory 198588 kb
Host smart-9c6077e0-f3eb-4219-89bf-0c57aeb0b388
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747889085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.747889085
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.29992496
Short name T123
Test name
Test status
Simulation time 45282354 ps
CPU time 0.84 seconds
Started Aug 11 06:12:40 PM PDT 24
Finished Aug 11 06:12:41 PM PDT 24
Peak memory 196516 kb
Host smart-a55b7ead-67f6-4e5c-ba9b-9a2abf4fb97b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29992496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.29992496
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.619064662
Short name T64
Test name
Test status
Simulation time 1837565491 ps
CPU time 1.44 seconds
Started Aug 11 06:12:35 PM PDT 24
Finished Aug 11 06:12:37 PM PDT 24
Peak memory 197752 kb
Host smart-7bea4e3b-1191-433c-bd11-4812c8e323d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619064662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.619064662
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2230150266
Short name T36
Test name
Test status
Simulation time 83817719 ps
CPU time 3.55 seconds
Started Aug 11 06:12:35 PM PDT 24
Finished Aug 11 06:12:39 PM PDT 24
Peak memory 198656 kb
Host smart-6f1038a2-b932-410e-9ea7-884ef49b20b1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230150266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2230150266
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.4128267892
Short name T334
Test name
Test status
Simulation time 350004752 ps
CPU time 2.04 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 197388 kb
Host smart-ee344771-a179-4c9e-b1ab-815d6de3bc35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128267892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.4128267892
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.127502116
Short name T248
Test name
Test status
Simulation time 53362106 ps
CPU time 0.74 seconds
Started Aug 11 06:12:33 PM PDT 24
Finished Aug 11 06:12:34 PM PDT 24
Peak memory 195832 kb
Host smart-30fa9c7e-ad48-47e1-b5a1-13183516e825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127502116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.127502116
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2726501340
Short name T475
Test name
Test status
Simulation time 54693004 ps
CPU time 1.12 seconds
Started Aug 11 06:12:33 PM PDT 24
Finished Aug 11 06:12:34 PM PDT 24
Peak memory 196368 kb
Host smart-60898b79-5a60-4c77-938c-93d683a3edea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726501340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2726501340
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1651221125
Short name T282
Test name
Test status
Simulation time 289554615 ps
CPU time 4.23 seconds
Started Aug 11 06:12:31 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 198364 kb
Host smart-17aa1314-83c8-427b-8ca9-9d1681c706e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651221125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1651221125
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.619337404
Short name T245
Test name
Test status
Simulation time 89904913 ps
CPU time 0.93 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:42 PM PDT 24
Peak memory 197700 kb
Host smart-cfe5f162-c6af-4a8a-a6c3-b0e69f8757ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619337404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.619337404
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1202989343
Short name T203
Test name
Test status
Simulation time 49962250 ps
CPU time 1.06 seconds
Started Aug 11 06:12:39 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 196708 kb
Host smart-d42bf1b4-4775-43f9-b917-85ca83c9c63f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202989343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1202989343
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3363084847
Short name T676
Test name
Test status
Simulation time 58462197604 ps
CPU time 198.69 seconds
Started Aug 11 06:12:36 PM PDT 24
Finished Aug 11 06:15:55 PM PDT 24
Peak memory 198760 kb
Host smart-ceae091a-1ae8-4d20-b749-036af5f8b49e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363084847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3363084847
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1001599528
Short name T419
Test name
Test status
Simulation time 69296649 ps
CPU time 0.58 seconds
Started Aug 11 06:12:35 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 194448 kb
Host smart-f88912c6-fa94-427d-b8f1-671f5d09e83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001599528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1001599528
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3223997252
Short name T390
Test name
Test status
Simulation time 79500052 ps
CPU time 0.94 seconds
Started Aug 11 06:12:35 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 197244 kb
Host smart-b0904b0c-2f73-4a23-a9ff-6e95bc477904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223997252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3223997252
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3538464668
Short name T134
Test name
Test status
Simulation time 931739094 ps
CPU time 12.38 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:55 PM PDT 24
Peak memory 197348 kb
Host smart-d29e45a6-01e4-4739-8174-864f8f7c0323
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538464668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3538464668
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1232397419
Short name T546
Test name
Test status
Simulation time 185048464 ps
CPU time 0.84 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:46 PM PDT 24
Peak memory 197244 kb
Host smart-83397854-92c0-4e63-96d8-fee18996ec12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232397419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1232397419
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3033483914
Short name T238
Test name
Test status
Simulation time 93567639 ps
CPU time 1.3 seconds
Started Aug 11 06:12:40 PM PDT 24
Finished Aug 11 06:12:41 PM PDT 24
Peak memory 198656 kb
Host smart-b4f8f303-edae-4f44-adbd-2d0f068e293c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033483914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3033483914
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3052527296
Short name T317
Test name
Test status
Simulation time 276332826 ps
CPU time 1.82 seconds
Started Aug 11 06:12:30 PM PDT 24
Finished Aug 11 06:12:31 PM PDT 24
Peak memory 198504 kb
Host smart-dbc5f37a-17ef-4c0b-befe-de05ee239e65
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052527296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3052527296
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3348296579
Short name T253
Test name
Test status
Simulation time 72966645 ps
CPU time 2.21 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:12:41 PM PDT 24
Peak memory 197660 kb
Host smart-f122dfb2-61b5-49b9-bd4b-265bfd22bd2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348296579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3348296579
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1218739272
Short name T540
Test name
Test status
Simulation time 23293344 ps
CPU time 0.9 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 196332 kb
Host smart-7ab4298e-a6a4-4219-bb7f-33d663842f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218739272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1218739272
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2697529248
Short name T174
Test name
Test status
Simulation time 102876236 ps
CPU time 0.82 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 197124 kb
Host smart-889cbb1f-8c2b-40c1-be12-a371e6cf0a13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697529248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2697529248
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3959786594
Short name T553
Test name
Test status
Simulation time 406159348 ps
CPU time 3.29 seconds
Started Aug 11 06:12:25 PM PDT 24
Finished Aug 11 06:12:28 PM PDT 24
Peak memory 198576 kb
Host smart-d7b107e1-dd79-48ff-823b-e1b453e874b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959786594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3959786594
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2709606411
Short name T615
Test name
Test status
Simulation time 520334037 ps
CPU time 1.03 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 196788 kb
Host smart-883d2a22-1ef3-4f5e-a7c7-afc373b168d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709606411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2709606411
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.134778066
Short name T137
Test name
Test status
Simulation time 67267230 ps
CPU time 1.06 seconds
Started Aug 11 06:12:48 PM PDT 24
Finished Aug 11 06:12:49 PM PDT 24
Peak memory 196296 kb
Host smart-b2ea39e3-0589-4438-ba48-2debaec37f03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134778066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.134778066
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.286993297
Short name T458
Test name
Test status
Simulation time 1774274269 ps
CPU time 24.42 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:13:05 PM PDT 24
Peak memory 198600 kb
Host smart-9207d427-7cf8-45d6-bcfa-69b5ff96b60e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286993297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.286993297
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2363711359
Short name T267
Test name
Test status
Simulation time 145817940 ps
CPU time 0.57 seconds
Started Aug 11 06:12:39 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 194688 kb
Host smart-1ab75898-6958-4fe7-b007-925624c36ab3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363711359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2363711359
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3503835404
Short name T706
Test name
Test status
Simulation time 79602379 ps
CPU time 0.79 seconds
Started Aug 11 06:12:52 PM PDT 24
Finished Aug 11 06:12:53 PM PDT 24
Peak memory 195708 kb
Host smart-af813e48-bada-4e4b-b2f6-2c4254f182d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503835404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3503835404
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2713751626
Short name T206
Test name
Test status
Simulation time 493244664 ps
CPU time 13.87 seconds
Started Aug 11 06:12:39 PM PDT 24
Finished Aug 11 06:12:53 PM PDT 24
Peak memory 196072 kb
Host smart-0ce2fda5-979a-4a27-9861-837f481906fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713751626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2713751626
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.704613324
Short name T455
Test name
Test status
Simulation time 86609591 ps
CPU time 1.02 seconds
Started Aug 11 06:12:37 PM PDT 24
Finished Aug 11 06:12:38 PM PDT 24
Peak memory 198348 kb
Host smart-0d855844-8ce1-43fb-8cf3-aa2a5b6be367
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704613324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.704613324
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1994609706
Short name T708
Test name
Test status
Simulation time 86336177 ps
CPU time 1 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 196464 kb
Host smart-efeb886e-60c9-4c54-9405-6d47d4033589
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994609706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1994609706
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.150489243
Short name T250
Test name
Test status
Simulation time 385055632 ps
CPU time 3.9 seconds
Started Aug 11 06:12:32 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 198532 kb
Host smart-063274cb-d785-46a5-aae6-79a43c43852c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150489243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.150489243
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1567301211
Short name T704
Test name
Test status
Simulation time 64781722 ps
CPU time 1.36 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 197372 kb
Host smart-f6556823-d7d4-47f5-a9a2-c0107984b028
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567301211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1567301211
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.827702106
Short name T712
Test name
Test status
Simulation time 33278809 ps
CPU time 0.71 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:42 PM PDT 24
Peak memory 194828 kb
Host smart-55af6fa7-3e35-4819-a6eb-7fc437137648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827702106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.827702106
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3495038776
Short name T193
Test name
Test status
Simulation time 54665334 ps
CPU time 1.08 seconds
Started Aug 11 06:12:54 PM PDT 24
Finished Aug 11 06:12:55 PM PDT 24
Peak memory 196532 kb
Host smart-26b6a700-cd0b-4fb7-9082-a7604f009973
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495038776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3495038776
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.4021555568
Short name T417
Test name
Test status
Simulation time 285162112 ps
CPU time 3.76 seconds
Started Aug 11 06:12:37 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 198600 kb
Host smart-2dbaeab9-b925-4170-aa9e-6f1346667287
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021555568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.4021555568
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.4066482957
Short name T66
Test name
Test status
Simulation time 81141707 ps
CPU time 0.98 seconds
Started Aug 11 06:12:47 PM PDT 24
Finished Aug 11 06:12:48 PM PDT 24
Peak memory 196972 kb
Host smart-2171a4e8-cec2-4508-94ec-e184a6f245f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066482957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.4066482957
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2238124974
Short name T555
Test name
Test status
Simulation time 62686728 ps
CPU time 1.18 seconds
Started Aug 11 06:12:35 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 197160 kb
Host smart-092d6cc9-0184-45d0-a350-99bd42a08f48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238124974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2238124974
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1344585029
Short name T302
Test name
Test status
Simulation time 14426559038 ps
CPU time 201.27 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:15:59 PM PDT 24
Peak memory 198752 kb
Host smart-bf65f367-c111-4222-a007-1c365d4dd43a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344585029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1344585029
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1966032352
Short name T70
Test name
Test status
Simulation time 504496814062 ps
CPU time 1239.39 seconds
Started Aug 11 06:12:37 PM PDT 24
Finished Aug 11 06:33:16 PM PDT 24
Peak memory 198804 kb
Host smart-bcbb742a-cdec-492c-b69f-c5b4b8c9b972
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1966032352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1966032352
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3166407706
Short name T47
Test name
Test status
Simulation time 15058667 ps
CPU time 0.55 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:12:53 PM PDT 24
Peak memory 195176 kb
Host smart-14820413-0242-4a37-9308-9d2b8f56f10f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166407706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3166407706
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1900990415
Short name T413
Test name
Test status
Simulation time 41579099 ps
CPU time 0.79 seconds
Started Aug 11 06:12:35 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 196640 kb
Host smart-0714dec0-2dcb-4edc-b716-4adf1ba54738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900990415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1900990415
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.956229893
Short name T297
Test name
Test status
Simulation time 530429741 ps
CPU time 7.97 seconds
Started Aug 11 06:12:47 PM PDT 24
Finished Aug 11 06:12:55 PM PDT 24
Peak memory 197476 kb
Host smart-084c73b0-35d0-41cd-974c-ed33fd9a5dcc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956229893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.956229893
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.342468604
Short name T138
Test name
Test status
Simulation time 763884663 ps
CPU time 0.88 seconds
Started Aug 11 06:13:13 PM PDT 24
Finished Aug 11 06:13:14 PM PDT 24
Peak memory 197696 kb
Host smart-6bf3483e-9c8c-4bf6-922f-ff8ac0569707
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342468604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.342468604
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.4117156220
Short name T655
Test name
Test status
Simulation time 99368733 ps
CPU time 1.04 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 197420 kb
Host smart-2ccbccac-4eaa-42be-84c6-197f0f43b338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117156220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.4117156220
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1701708327
Short name T595
Test name
Test status
Simulation time 68315253 ps
CPU time 1.43 seconds
Started Aug 11 06:12:44 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 195992 kb
Host smart-f81c11b9-f302-4c5d-b331-b2edd3c3adbd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701708327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1701708327
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2145194613
Short name T204
Test name
Test status
Simulation time 110503454 ps
CPU time 3.33 seconds
Started Aug 11 06:12:51 PM PDT 24
Finished Aug 11 06:12:54 PM PDT 24
Peak memory 197620 kb
Host smart-ea215c94-dbb6-4568-a88a-6b8c62c417c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145194613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2145194613
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3180326296
Short name T208
Test name
Test status
Simulation time 26575298 ps
CPU time 0.79 seconds
Started Aug 11 06:12:37 PM PDT 24
Finished Aug 11 06:12:38 PM PDT 24
Peak memory 196832 kb
Host smart-23ff45e2-f9ee-49de-9bf8-02eaa8e4041c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180326296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3180326296
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1482166845
Short name T133
Test name
Test status
Simulation time 242418659 ps
CPU time 1.13 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:12:39 PM PDT 24
Peak memory 196432 kb
Host smart-c97d07f6-85c2-42bd-85e1-e87d308d1807
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482166845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1482166845
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2023169673
Short name T10
Test name
Test status
Simulation time 248022762 ps
CPU time 3.31 seconds
Started Aug 11 06:12:34 PM PDT 24
Finished Aug 11 06:12:37 PM PDT 24
Peak memory 198500 kb
Host smart-5d763cd1-4327-4ba8-8049-00174adecf5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023169673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2023169673
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.171643654
Short name T254
Test name
Test status
Simulation time 145038371 ps
CPU time 1.25 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 197004 kb
Host smart-674d4f22-93a4-4285-a2c2-aa0514ff2f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171643654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.171643654
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.4027274
Short name T649
Test name
Test status
Simulation time 31913224 ps
CPU time 0.77 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 195788 kb
Host smart-a4d2245b-79f6-4dd7-a054-fd7712172cd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.4027274
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3392271343
Short name T67
Test name
Test status
Simulation time 20841108184 ps
CPU time 298.74 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:17:40 PM PDT 24
Peak memory 198892 kb
Host smart-ab552c83-316d-41d6-a76a-21122bca3065
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3392271343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3392271343
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1618054360
Short name T607
Test name
Test status
Simulation time 14324007 ps
CPU time 0.58 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:46 PM PDT 24
Peak memory 195200 kb
Host smart-0e23b002-72d1-452f-801d-7373ce18714d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618054360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1618054360
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2356466948
Short name T426
Test name
Test status
Simulation time 49128569 ps
CPU time 0.67 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:42 PM PDT 24
Peak memory 194720 kb
Host smart-01120b21-eb71-46b1-95b7-0ebab50c2138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356466948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2356466948
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1371333682
Short name T603
Test name
Test status
Simulation time 1092278257 ps
CPU time 9.02 seconds
Started Aug 11 06:12:35 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 196896 kb
Host smart-e6e636a5-82b5-496e-8523-8a769deab0ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371333682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1371333682
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1284214434
Short name T196
Test name
Test status
Simulation time 42297773 ps
CPU time 0.79 seconds
Started Aug 11 06:12:35 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 197124 kb
Host smart-064a785f-e05e-46ff-9dfe-11f0b04850ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284214434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1284214434
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.801281878
Short name T675
Test name
Test status
Simulation time 79374426 ps
CPU time 1.15 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 197160 kb
Host smart-fb9e4dfa-215d-4de8-a88f-b526b151e759
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801281878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.801281878
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3704566717
Short name T201
Test name
Test status
Simulation time 53677802 ps
CPU time 2.03 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 198744 kb
Host smart-b6ea2d25-d2fa-45e6-904f-c996e349241e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704566717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3704566717
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1113964079
Short name T141
Test name
Test status
Simulation time 158956904 ps
CPU time 3.57 seconds
Started Aug 11 06:12:36 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 197508 kb
Host smart-60b364cc-aa9a-4ef7-b2e0-ae1977ad83f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113964079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1113964079
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3433337720
Short name T507
Test name
Test status
Simulation time 125244462 ps
CPU time 0.91 seconds
Started Aug 11 06:12:33 PM PDT 24
Finished Aug 11 06:12:34 PM PDT 24
Peak memory 197240 kb
Host smart-45632642-381f-4652-921e-1f2993ae807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433337720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3433337720
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.99031692
Short name T522
Test name
Test status
Simulation time 49347553 ps
CPU time 1.02 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 196068 kb
Host smart-0b9189c5-3062-46d0-92fe-fce7944a6229
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99031692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup_
pulldown.99031692
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3963833050
Short name T504
Test name
Test status
Simulation time 344569806 ps
CPU time 5.65 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 198368 kb
Host smart-2cf983a8-2e23-45ba-aab0-6a00f683f462
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963833050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3963833050
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.5605138
Short name T702
Test name
Test status
Simulation time 117230931 ps
CPU time 0.93 seconds
Started Aug 11 06:12:46 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 196032 kb
Host smart-495706cc-0a76-4dee-a1d6-f8855ada329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5605138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.5605138
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1321706039
Short name T200
Test name
Test status
Simulation time 220602370 ps
CPU time 1.29 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 198588 kb
Host smart-a4237994-3a7d-4b75-bbc0-e8a38339f5d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321706039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1321706039
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.199030906
Short name T4
Test name
Test status
Simulation time 41897391477 ps
CPU time 214.45 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:16:18 PM PDT 24
Peak memory 198732 kb
Host smart-99f116ff-0fba-4416-9b5e-6964537c7f98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199030906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.199030906
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2352740997
Short name T375
Test name
Test status
Simulation time 14527370 ps
CPU time 0.56 seconds
Started Aug 11 06:11:45 PM PDT 24
Finished Aug 11 06:11:45 PM PDT 24
Peak memory 195156 kb
Host smart-d1540435-5d77-4856-b630-fc6fb541980c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352740997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2352740997
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1937163430
Short name T308
Test name
Test status
Simulation time 90761872 ps
CPU time 0.67 seconds
Started Aug 11 06:11:39 PM PDT 24
Finished Aug 11 06:11:45 PM PDT 24
Peak memory 194668 kb
Host smart-cefd1ade-c06b-42cf-8c9c-e78e384888ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937163430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1937163430
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2198588902
Short name T664
Test name
Test status
Simulation time 308364775 ps
CPU time 4.63 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:11:53 PM PDT 24
Peak memory 196232 kb
Host smart-e7a5c548-aa56-47e0-aafb-e107dd38dda8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198588902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2198588902
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.204225345
Short name T281
Test name
Test status
Simulation time 527530229 ps
CPU time 1.04 seconds
Started Aug 11 06:11:43 PM PDT 24
Finished Aug 11 06:11:44 PM PDT 24
Peak memory 197044 kb
Host smart-aaea16ea-ffa7-422f-82e1-a39b5b6e456d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204225345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.204225345
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1658894463
Short name T486
Test name
Test status
Simulation time 132113503 ps
CPU time 0.91 seconds
Started Aug 11 06:11:35 PM PDT 24
Finished Aug 11 06:11:36 PM PDT 24
Peak memory 196412 kb
Host smart-f23bded2-7d59-43fe-8103-ac4cb3394ae4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658894463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1658894463
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1070180069
Short name T713
Test name
Test status
Simulation time 153884486 ps
CPU time 1.7 seconds
Started Aug 11 06:11:58 PM PDT 24
Finished Aug 11 06:12:00 PM PDT 24
Peak memory 198748 kb
Host smart-8ece2b99-71fc-4253-ba95-557532a99bdc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070180069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1070180069
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.740935257
Short name T263
Test name
Test status
Simulation time 95400663 ps
CPU time 2.78 seconds
Started Aug 11 06:11:42 PM PDT 24
Finished Aug 11 06:11:45 PM PDT 24
Peak memory 198224 kb
Host smart-de98f590-ace4-4e32-89e4-feac04079407
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740935257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.740935257
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3337632592
Short name T218
Test name
Test status
Simulation time 56716884 ps
CPU time 0.8 seconds
Started Aug 11 06:11:45 PM PDT 24
Finished Aug 11 06:11:46 PM PDT 24
Peak memory 196000 kb
Host smart-793cc765-92c5-4d09-bf37-10c2325e4cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337632592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3337632592
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2483467015
Short name T700
Test name
Test status
Simulation time 202666036 ps
CPU time 1.24 seconds
Started Aug 11 06:11:45 PM PDT 24
Finished Aug 11 06:11:47 PM PDT 24
Peak memory 197636 kb
Host smart-b2c25c53-db64-41d3-bf08-543efc3c9b77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483467015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2483467015
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3511948866
Short name T409
Test name
Test status
Simulation time 340191149 ps
CPU time 5.66 seconds
Started Aug 11 06:11:44 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 198496 kb
Host smart-969de1e1-b4d1-4450-b71c-80ce161da6f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511948866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3511948866
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.855180591
Short name T46
Test name
Test status
Simulation time 236484224 ps
CPU time 0.88 seconds
Started Aug 11 06:11:43 PM PDT 24
Finished Aug 11 06:11:44 PM PDT 24
Peak memory 215300 kb
Host smart-78b31632-902d-46a5-89b0-61a1af0968c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855180591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.855180591
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2129493771
Short name T147
Test name
Test status
Simulation time 41794716 ps
CPU time 1.12 seconds
Started Aug 11 06:11:43 PM PDT 24
Finished Aug 11 06:11:44 PM PDT 24
Peak memory 197004 kb
Host smart-e6397428-c139-4be8-b4ad-7fb7897732b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129493771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2129493771
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2111249210
Short name T674
Test name
Test status
Simulation time 111644016 ps
CPU time 1.05 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:51 PM PDT 24
Peak memory 196236 kb
Host smart-9b5d75a8-99ff-4040-bfd9-9c8d76049799
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111249210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2111249210
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.4219396621
Short name T135
Test name
Test status
Simulation time 14239023356 ps
CPU time 212.11 seconds
Started Aug 11 06:11:44 PM PDT 24
Finished Aug 11 06:15:16 PM PDT 24
Peak memory 198756 kb
Host smart-57b3f7c9-346d-4daf-bdb8-ad57e4d9699a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219396621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.4219396621
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.810862960
Short name T112
Test name
Test status
Simulation time 28090528461 ps
CPU time 367.82 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:17:57 PM PDT 24
Peak memory 198872 kb
Host smart-21d0e239-0d6c-465b-8c8c-525ca452accc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=810862960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.810862960
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2310969239
Short name T289
Test name
Test status
Simulation time 106306309 ps
CPU time 0.53 seconds
Started Aug 11 06:12:36 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 193964 kb
Host smart-80568ad9-5d36-4a7f-b324-ba757809ffd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310969239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2310969239
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1331938301
Short name T693
Test name
Test status
Simulation time 66075597 ps
CPU time 0.74 seconds
Started Aug 11 06:13:06 PM PDT 24
Finished Aug 11 06:13:07 PM PDT 24
Peak memory 195860 kb
Host smart-066433ef-7323-4505-9605-90e48d1e40ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331938301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1331938301
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3757641749
Short name T353
Test name
Test status
Simulation time 1049513127 ps
CPU time 26.95 seconds
Started Aug 11 06:12:36 PM PDT 24
Finished Aug 11 06:13:03 PM PDT 24
Peak memory 197524 kb
Host smart-a1bb3ed7-9785-4f98-99bc-3cf1d0f57442
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757641749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3757641749
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.667400825
Short name T628
Test name
Test status
Simulation time 57054880 ps
CPU time 0.9 seconds
Started Aug 11 06:12:35 PM PDT 24
Finished Aug 11 06:12:36 PM PDT 24
Peak memory 197724 kb
Host smart-63fd0130-ab46-4360-832e-9a620e9b843b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667400825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.667400825
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.4156966749
Short name T619
Test name
Test status
Simulation time 59889005 ps
CPU time 1.11 seconds
Started Aug 11 06:12:36 PM PDT 24
Finished Aug 11 06:12:37 PM PDT 24
Peak memory 196332 kb
Host smart-8cc6ff3b-c574-4391-8f0c-d4c532d5ce45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156966749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.4156966749
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4037729010
Short name T406
Test name
Test status
Simulation time 252599530 ps
CPU time 2.62 seconds
Started Aug 11 06:12:35 PM PDT 24
Finished Aug 11 06:12:37 PM PDT 24
Peak memory 198736 kb
Host smart-4293674f-81a4-4528-bfb9-20ce23c281a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037729010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4037729010
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3616187304
Short name T634
Test name
Test status
Simulation time 1785927322 ps
CPU time 2.94 seconds
Started Aug 11 06:13:00 PM PDT 24
Finished Aug 11 06:13:03 PM PDT 24
Peak memory 198560 kb
Host smart-3f99a65e-a29a-417a-9abe-ec77f13f26cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616187304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3616187304
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3853400286
Short name T379
Test name
Test status
Simulation time 55405041 ps
CPU time 0.72 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:12:39 PM PDT 24
Peak memory 196624 kb
Host smart-851ac032-f825-4421-8e3f-b8e094ac7622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853400286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3853400286
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2082439778
Short name T139
Test name
Test status
Simulation time 352705367 ps
CPU time 1.16 seconds
Started Aug 11 06:12:36 PM PDT 24
Finished Aug 11 06:12:37 PM PDT 24
Peak memory 196408 kb
Host smart-37ab0ab1-16a1-465d-947d-7aef249ac63b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082439778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2082439778
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2112210086
Short name T487
Test name
Test status
Simulation time 1374165671 ps
CPU time 5.73 seconds
Started Aug 11 06:12:40 PM PDT 24
Finished Aug 11 06:12:46 PM PDT 24
Peak memory 198424 kb
Host smart-842f16eb-43c2-493c-a49f-6ded900dbc67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112210086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2112210086
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3758173931
Short name T295
Test name
Test status
Simulation time 123717712 ps
CPU time 1 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 196424 kb
Host smart-8bcf34a4-9930-4be0-b818-af228182d75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758173931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3758173931
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.160031714
Short name T246
Test name
Test status
Simulation time 122019471 ps
CPU time 1.02 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:46 PM PDT 24
Peak memory 196060 kb
Host smart-5adedf07-a660-4683-9632-082a149c196b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160031714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.160031714
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.4015634773
Short name T575
Test name
Test status
Simulation time 25423079034 ps
CPU time 185.53 seconds
Started Aug 11 06:12:51 PM PDT 24
Finished Aug 11 06:15:57 PM PDT 24
Peak memory 198708 kb
Host smart-5e523772-bc90-477a-b95a-a87e7ad54b35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015634773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.4015634773
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2164662764
Short name T49
Test name
Test status
Simulation time 52244263 ps
CPU time 0.58 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 195148 kb
Host smart-9aca763c-a9db-428c-aeeb-9087953b737d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164662764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2164662764
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1194634171
Short name T465
Test name
Test status
Simulation time 263143295 ps
CPU time 0.67 seconds
Started Aug 11 06:12:48 PM PDT 24
Finished Aug 11 06:12:49 PM PDT 24
Peak memory 195352 kb
Host smart-93423f23-da9e-4311-9c69-1d92394cafe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194634171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1194634171
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.879336664
Short name T310
Test name
Test status
Simulation time 3224564350 ps
CPU time 26.37 seconds
Started Aug 11 06:12:48 PM PDT 24
Finished Aug 11 06:13:15 PM PDT 24
Peak memory 196588 kb
Host smart-212325fa-2767-477c-9cf0-337bd81ab940
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879336664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.879336664
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2610240073
Short name T396
Test name
Test status
Simulation time 557471044 ps
CPU time 0.84 seconds
Started Aug 11 06:12:40 PM PDT 24
Finished Aug 11 06:12:41 PM PDT 24
Peak memory 195532 kb
Host smart-74ab2050-c7d1-4543-bff0-75f0488e7e22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610240073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2610240073
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2579554735
Short name T597
Test name
Test status
Simulation time 41615363 ps
CPU time 0.86 seconds
Started Aug 11 06:12:47 PM PDT 24
Finished Aug 11 06:12:48 PM PDT 24
Peak memory 197172 kb
Host smart-47703e5a-55f0-4ee4-9a65-95be60da879c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579554735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2579554735
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.39318439
Short name T19
Test name
Test status
Simulation time 37736931 ps
CPU time 1.59 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 198628 kb
Host smart-d64b96ca-e15e-4c10-8244-1594702c6daa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39318439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.gpio_intr_with_filter_rand_intr_event.39318439
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1897664557
Short name T512
Test name
Test status
Simulation time 94270508 ps
CPU time 1.04 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 196212 kb
Host smart-a6458a86-501f-4e62-93fe-73e3e9a5ad9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897664557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1897664557
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2149772308
Short name T533
Test name
Test status
Simulation time 29381501 ps
CPU time 0.74 seconds
Started Aug 11 06:12:51 PM PDT 24
Finished Aug 11 06:12:52 PM PDT 24
Peak memory 195976 kb
Host smart-2b1101d7-f24e-4165-a1d9-9f75d0b13b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149772308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2149772308
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.694236768
Short name T653
Test name
Test status
Simulation time 26048266 ps
CPU time 0.71 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 195964 kb
Host smart-ae93d20e-4e3f-4058-84a4-a3e84c3a2964
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694236768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.694236768
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.992080092
Short name T703
Test name
Test status
Simulation time 147346451 ps
CPU time 3.83 seconds
Started Aug 11 06:12:34 PM PDT 24
Finished Aug 11 06:12:38 PM PDT 24
Peak memory 198528 kb
Host smart-d66c3a2e-fb5f-4685-ae4f-6dc29e81c0bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992080092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.992080092
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.636241627
Short name T199
Test name
Test status
Simulation time 188681036 ps
CPU time 0.96 seconds
Started Aug 11 06:12:51 PM PDT 24
Finished Aug 11 06:12:52 PM PDT 24
Peak memory 196044 kb
Host smart-3a95eccf-c5d0-4f27-8e1d-943d5f38a899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636241627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.636241627
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2917451134
Short name T645
Test name
Test status
Simulation time 141930765 ps
CPU time 1.19 seconds
Started Aug 11 06:12:44 PM PDT 24
Finished Aug 11 06:12:46 PM PDT 24
Peak memory 198620 kb
Host smart-f8985bfe-eb19-4ccd-a0c8-9ee9ed7da007
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917451134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2917451134
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3758969840
Short name T582
Test name
Test status
Simulation time 5331112245 ps
CPU time 123.84 seconds
Started Aug 11 06:12:47 PM PDT 24
Finished Aug 11 06:14:50 PM PDT 24
Peak memory 198740 kb
Host smart-9f0adcdf-c5d8-429c-ba2f-11902b855a68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758969840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3758969840
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.524458138
Short name T515
Test name
Test status
Simulation time 202429439390 ps
CPU time 1049.43 seconds
Started Aug 11 06:12:44 PM PDT 24
Finished Aug 11 06:30:14 PM PDT 24
Peak memory 198848 kb
Host smart-db0eeddb-4b2d-4350-ae02-678a8a15add7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=524458138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.524458138
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3964639494
Short name T405
Test name
Test status
Simulation time 40578157 ps
CPU time 0.57 seconds
Started Aug 11 06:12:39 PM PDT 24
Finished Aug 11 06:12:39 PM PDT 24
Peak memory 194516 kb
Host smart-03621553-c088-49af-9b7e-629348c7ea9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964639494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3964639494
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.453927025
Short name T217
Test name
Test status
Simulation time 15271648 ps
CPU time 0.65 seconds
Started Aug 11 06:12:36 PM PDT 24
Finished Aug 11 06:12:37 PM PDT 24
Peak memory 194580 kb
Host smart-04481e1d-b353-4521-b459-3a6fa6f28630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453927025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.453927025
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.4160168483
Short name T543
Test name
Test status
Simulation time 125452717 ps
CPU time 6.75 seconds
Started Aug 11 06:12:37 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 197528 kb
Host smart-5bc35c03-3efe-4f5e-8779-ffd48124c34c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160168483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.4160168483
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3184242160
Short name T436
Test name
Test status
Simulation time 318452368 ps
CPU time 1 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 198360 kb
Host smart-faf68ba3-4da0-46ec-bf75-4f465e9e503e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184242160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3184242160
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.4045891042
Short name T571
Test name
Test status
Simulation time 103894363 ps
CPU time 0.88 seconds
Started Aug 11 06:12:33 PM PDT 24
Finished Aug 11 06:12:34 PM PDT 24
Peak memory 196304 kb
Host smart-0a44d2f2-7953-4447-8b15-d75c12b680eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045891042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.4045891042
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3319631923
Short name T690
Test name
Test status
Simulation time 22872982 ps
CPU time 1.12 seconds
Started Aug 11 06:12:34 PM PDT 24
Finished Aug 11 06:12:35 PM PDT 24
Peak memory 196616 kb
Host smart-0e64326b-a09e-46b8-a2c2-dd4408f38288
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319631923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3319631923
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3071616108
Short name T366
Test name
Test status
Simulation time 117818165 ps
CPU time 3.18 seconds
Started Aug 11 06:12:36 PM PDT 24
Finished Aug 11 06:12:39 PM PDT 24
Peak memory 196428 kb
Host smart-29a7380f-56fe-430b-a5f3-c873949e5c7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071616108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3071616108
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.747435474
Short name T393
Test name
Test status
Simulation time 15866458 ps
CPU time 0.69 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 195908 kb
Host smart-553343b3-be08-4ec7-8f06-08f3115a2083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747435474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.747435474
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3990012251
Short name T524
Test name
Test status
Simulation time 49364920 ps
CPU time 1.17 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 197248 kb
Host smart-0d6a0caf-1358-4de7-96c6-aa3ebe978ad6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990012251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3990012251
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.26841506
Short name T558
Test name
Test status
Simulation time 216675290 ps
CPU time 1.48 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 198504 kb
Host smart-c5b7ebe9-b40e-4122-ae96-10ba40e1f336
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26841506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand
om_long_reg_writes_reg_reads.26841506
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3106404249
Short name T320
Test name
Test status
Simulation time 65750099 ps
CPU time 0.99 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:42 PM PDT 24
Peak memory 196164 kb
Host smart-6b89ca9d-b5ae-4b1b-aadc-f96e997f20cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106404249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3106404249
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3786462592
Short name T150
Test name
Test status
Simulation time 158485757 ps
CPU time 1.04 seconds
Started Aug 11 06:12:39 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 196188 kb
Host smart-75091736-546c-40d9-ad9d-5f9e0a86def9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786462592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3786462592
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.136060115
Short name T290
Test name
Test status
Simulation time 4054398404 ps
CPU time 108.53 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:14:26 PM PDT 24
Peak memory 198808 kb
Host smart-aede4843-9c75-41a1-a7e0-36aa41b7bd20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136060115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.136060115
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2335003220
Short name T38
Test name
Test status
Simulation time 504188928314 ps
CPU time 1801.78 seconds
Started Aug 11 06:12:39 PM PDT 24
Finished Aug 11 06:42:41 PM PDT 24
Peak memory 207024 kb
Host smart-459de942-e305-4547-9284-0ce367be0807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2335003220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2335003220
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1866698741
Short name T232
Test name
Test status
Simulation time 23078487 ps
CPU time 0.55 seconds
Started Aug 11 06:12:44 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 195160 kb
Host smart-73767d4a-f484-4fb5-bd97-75ebe1b0506b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866698741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1866698741
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3497830652
Short name T25
Test name
Test status
Simulation time 125040489 ps
CPU time 0.84 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:12:54 PM PDT 24
Peak memory 197028 kb
Host smart-6cf6adbd-f8cc-46a1-a470-f46c22d9dfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497830652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3497830652
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3989000114
Short name T492
Test name
Test status
Simulation time 6871002298 ps
CPU time 24.32 seconds
Started Aug 11 06:12:44 PM PDT 24
Finished Aug 11 06:13:08 PM PDT 24
Peak memory 198328 kb
Host smart-b79f59d8-3f66-4239-ba74-4b2142fbf279
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989000114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3989000114
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2675475755
Short name T539
Test name
Test status
Simulation time 55984997 ps
CPU time 0.75 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:46 PM PDT 24
Peak memory 196388 kb
Host smart-3adbfd5f-3576-43f7-a079-ecf2c987fe08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675475755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2675475755
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1884130373
Short name T314
Test name
Test status
Simulation time 61815107 ps
CPU time 0.99 seconds
Started Aug 11 06:12:46 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 196588 kb
Host smart-6c22e236-b14f-4c71-bb01-de95f1e215f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884130373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1884130373
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1890895257
Short name T259
Test name
Test status
Simulation time 235834737 ps
CPU time 2.54 seconds
Started Aug 11 06:12:40 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 198396 kb
Host smart-1bc423ae-d253-4e5e-b4c9-0f21461ebe50
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890895257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1890895257
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.111712305
Short name T497
Test name
Test status
Simulation time 325910812 ps
CPU time 2.33 seconds
Started Aug 11 06:12:46 PM PDT 24
Finished Aug 11 06:12:48 PM PDT 24
Peak memory 198632 kb
Host smart-b62826c1-5697-494c-bd96-12c425938d55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111712305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
111712305
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.734846790
Short name T545
Test name
Test status
Simulation time 18296232 ps
CPU time 0.62 seconds
Started Aug 11 06:12:50 PM PDT 24
Finished Aug 11 06:12:50 PM PDT 24
Peak memory 195576 kb
Host smart-f0113e86-6988-4925-a59e-19ed5482251e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734846790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.734846790
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.636752256
Short name T344
Test name
Test status
Simulation time 464602968 ps
CPU time 1.18 seconds
Started Aug 11 06:12:47 PM PDT 24
Finished Aug 11 06:12:48 PM PDT 24
Peak memory 197096 kb
Host smart-2a752468-3d03-4993-8ef8-6a3af26034cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636752256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.636752256
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1671569436
Short name T363
Test name
Test status
Simulation time 286158133 ps
CPU time 1.37 seconds
Started Aug 11 06:12:51 PM PDT 24
Finished Aug 11 06:12:52 PM PDT 24
Peak memory 198332 kb
Host smart-3b9a40f8-69d6-4e01-bdc3-c8b5f02eeca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671569436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1671569436
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3671452513
Short name T464
Test name
Test status
Simulation time 158524224 ps
CPU time 1.33 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 197312 kb
Host smart-30e38d73-3d21-412a-ae6f-1d9644e28c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671452513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3671452513
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2401880695
Short name T298
Test name
Test status
Simulation time 46523746 ps
CPU time 1.18 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:42 PM PDT 24
Peak memory 196296 kb
Host smart-7e6a1c7e-c298-4b38-b701-a1bf493232d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401880695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2401880695
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.940308256
Short name T291
Test name
Test status
Simulation time 4022038490 ps
CPU time 106.41 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:14:39 PM PDT 24
Peak memory 198680 kb
Host smart-ba9384ae-7874-4835-81a4-734e49cd36b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940308256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.940308256
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2170814685
Short name T69
Test name
Test status
Simulation time 481099914208 ps
CPU time 1545.87 seconds
Started Aug 11 06:12:40 PM PDT 24
Finished Aug 11 06:38:26 PM PDT 24
Peak memory 199148 kb
Host smart-01c8cf1d-3941-4126-9aef-75e5fee9b831
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2170814685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2170814685
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3119375451
Short name T528
Test name
Test status
Simulation time 14215970 ps
CPU time 0.55 seconds
Started Aug 11 06:12:58 PM PDT 24
Finished Aug 11 06:12:58 PM PDT 24
Peak memory 195164 kb
Host smart-caf60067-273b-4336-a078-fc772ad149ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119375451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3119375451
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2121347314
Short name T624
Test name
Test status
Simulation time 95237044 ps
CPU time 0.81 seconds
Started Aug 11 06:12:39 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 195788 kb
Host smart-6fabf628-ae8a-45c9-aa1d-b774c34d99cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121347314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2121347314
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1594355325
Short name T228
Test name
Test status
Simulation time 65545086 ps
CPU time 3.72 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 196368 kb
Host smart-b8802af8-b58b-433d-aef1-79c7a288ee46
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594355325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1594355325
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3857275018
Short name T287
Test name
Test status
Simulation time 84522310 ps
CPU time 1.04 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 197228 kb
Host smart-9c1785b7-8477-4bf0-be48-e3285aa3b283
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857275018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3857275018
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2845166459
Short name T457
Test name
Test status
Simulation time 29625584 ps
CPU time 0.72 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 194940 kb
Host smart-722f8830-f04f-4397-91d5-0275315f3540
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845166459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2845166459
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2821143098
Short name T462
Test name
Test status
Simulation time 683806050 ps
CPU time 3.48 seconds
Started Aug 11 06:12:40 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 198492 kb
Host smart-ee8ef5a0-cea0-4412-becb-4bf83bf05a84
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821143098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2821143098
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.612279357
Short name T34
Test name
Test status
Simulation time 43426371 ps
CPU time 1.08 seconds
Started Aug 11 06:12:40 PM PDT 24
Finished Aug 11 06:12:41 PM PDT 24
Peak memory 196168 kb
Host smart-c9ca29be-8b19-4171-8bd2-75b952eac5de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612279357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
612279357
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.997601340
Short name T260
Test name
Test status
Simulation time 253254941 ps
CPU time 1.2 seconds
Started Aug 11 06:12:48 PM PDT 24
Finished Aug 11 06:12:49 PM PDT 24
Peak memory 197564 kb
Host smart-8a026438-4f29-4c60-8f08-83165c17d102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997601340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.997601340
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.968916734
Short name T23
Test name
Test status
Simulation time 24628222 ps
CPU time 0.64 seconds
Started Aug 11 06:12:46 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 195560 kb
Host smart-aa4660b3-fde3-46b1-957b-a4fba07c8e4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968916734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.968916734
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3810564408
Short name T197
Test name
Test status
Simulation time 65176751 ps
CPU time 2.86 seconds
Started Aug 11 06:12:39 PM PDT 24
Finished Aug 11 06:12:42 PM PDT 24
Peak memory 198576 kb
Host smart-9665ab25-d981-48f3-85c8-141338daac99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810564408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3810564408
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1360524157
Short name T503
Test name
Test status
Simulation time 312469492 ps
CPU time 1.2 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 196356 kb
Host smart-7c7a9d09-57fd-4559-8204-293128a13416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360524157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1360524157
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3832385621
Short name T30
Test name
Test status
Simulation time 143252054 ps
CPU time 1.1 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 196432 kb
Host smart-3301a4a0-9f34-4b60-a61b-e12a718e02d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832385621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3832385621
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.886528631
Short name T648
Test name
Test status
Simulation time 6748190147 ps
CPU time 176.18 seconds
Started Aug 11 06:12:37 PM PDT 24
Finished Aug 11 06:15:34 PM PDT 24
Peak memory 198716 kb
Host smart-3c3e6e33-e0c0-4df0-b9cc-b1fb52c61269
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886528631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.886528631
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2547590351
Short name T399
Test name
Test status
Simulation time 14337114 ps
CPU time 0.58 seconds
Started Aug 11 06:12:47 PM PDT 24
Finished Aug 11 06:12:48 PM PDT 24
Peak memory 194628 kb
Host smart-c1b25f57-d89f-41c4-8185-2dc241bb51fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547590351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2547590351
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.399936026
Short name T17
Test name
Test status
Simulation time 28594996 ps
CPU time 0.7 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:46 PM PDT 24
Peak memory 194960 kb
Host smart-1996e524-2efe-446a-866d-9885f2fe285d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399936026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.399936026
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.655565512
Short name T532
Test name
Test status
Simulation time 873167381 ps
CPU time 21.99 seconds
Started Aug 11 06:12:46 PM PDT 24
Finished Aug 11 06:13:08 PM PDT 24
Peak memory 197460 kb
Host smart-a8563c64-d711-43b4-aa11-f2a34da13050
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655565512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.655565512
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.1095725845
Short name T709
Test name
Test status
Simulation time 255337177 ps
CPU time 0.9 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 197544 kb
Host smart-fa7b590f-c35d-4f25-b36e-864fefbf2ff4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095725845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.1095725845
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3663745042
Short name T239
Test name
Test status
Simulation time 51201350 ps
CPU time 1.02 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:46 PM PDT 24
Peak memory 197284 kb
Host smart-b83938a9-07fc-4b11-9449-4d86162a1f1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663745042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3663745042
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2705168908
Short name T257
Test name
Test status
Simulation time 25709518 ps
CPU time 1.16 seconds
Started Aug 11 06:12:37 PM PDT 24
Finished Aug 11 06:12:38 PM PDT 24
Peak memory 198572 kb
Host smart-a43f0620-fcaf-43b8-b500-527e0708b4d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705168908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2705168908
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2443528048
Short name T59
Test name
Test status
Simulation time 131011162 ps
CPU time 2.74 seconds
Started Aug 11 06:12:50 PM PDT 24
Finished Aug 11 06:12:53 PM PDT 24
Peak memory 197788 kb
Host smart-b6a91553-8225-4dd1-a941-5c2ed6a0e77e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443528048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2443528048
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3998743367
Short name T265
Test name
Test status
Simulation time 21835611 ps
CPU time 0.74 seconds
Started Aug 11 06:12:42 PM PDT 24
Finished Aug 11 06:12:43 PM PDT 24
Peak memory 196764 kb
Host smart-0fa87f2e-a512-4e8c-82a6-8a41a2a91204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998743367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3998743367
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1053179166
Short name T564
Test name
Test status
Simulation time 57859861 ps
CPU time 1.07 seconds
Started Aug 11 06:12:58 PM PDT 24
Finished Aug 11 06:12:59 PM PDT 24
Peak memory 196524 kb
Host smart-160c180e-4ff8-4d9c-8872-0ec226acbb68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053179166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1053179166
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1981357312
Short name T244
Test name
Test status
Simulation time 5295783806 ps
CPU time 4.39 seconds
Started Aug 11 06:13:01 PM PDT 24
Finished Aug 11 06:13:05 PM PDT 24
Peak memory 198668 kb
Host smart-b690d26d-239a-42cc-b164-2d4c0884978d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981357312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1981357312
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2556847932
Short name T498
Test name
Test status
Simulation time 61938293 ps
CPU time 0.95 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:42 PM PDT 24
Peak memory 196968 kb
Host smart-b20a6585-e8bc-48ea-8329-c07bd76485f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556847932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2556847932
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.324517749
Short name T418
Test name
Test status
Simulation time 386499224 ps
CPU time 1.46 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 198568 kb
Host smart-982ef247-ddbd-4e16-8ac8-78b070fb50a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324517749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.324517749
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2046519887
Short name T635
Test name
Test status
Simulation time 4097788839 ps
CPU time 102.95 seconds
Started Aug 11 06:13:01 PM PDT 24
Finished Aug 11 06:14:44 PM PDT 24
Peak memory 198748 kb
Host smart-43cd9306-52a5-4325-ad7c-716d0e3e8c50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046519887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2046519887
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.583548731
Short name T277
Test name
Test status
Simulation time 52130370564 ps
CPU time 858.52 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:27:04 PM PDT 24
Peak memory 198888 kb
Host smart-01a1c73e-4a1e-4a21-85d0-056dc0411d32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=583548731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.583548731
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2122391874
Short name T446
Test name
Test status
Simulation time 34279886 ps
CPU time 0.57 seconds
Started Aug 11 06:12:44 PM PDT 24
Finished Aug 11 06:12:44 PM PDT 24
Peak memory 194532 kb
Host smart-6809b47c-02d8-4498-8814-0b1f5ee877ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122391874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2122391874
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.645026590
Short name T179
Test name
Test status
Simulation time 31042849 ps
CPU time 0.74 seconds
Started Aug 11 06:12:54 PM PDT 24
Finished Aug 11 06:12:55 PM PDT 24
Peak memory 195740 kb
Host smart-802d13d8-fa42-4d3d-be38-354c23eef966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645026590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.645026590
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2372322454
Short name T431
Test name
Test status
Simulation time 556925403 ps
CPU time 11.55 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:53 PM PDT 24
Peak memory 196080 kb
Host smart-883fd01a-20ab-4e5f-b82d-7222229d0673
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372322454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2372322454
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2885450204
Short name T131
Test name
Test status
Simulation time 174248723 ps
CPU time 0.86 seconds
Started Aug 11 06:12:48 PM PDT 24
Finished Aug 11 06:12:49 PM PDT 24
Peak memory 196364 kb
Host smart-4bbebb52-56d9-45ad-817b-a93d892cbc9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885450204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2885450204
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2514355990
Short name T494
Test name
Test status
Simulation time 362654528 ps
CPU time 1.34 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:12:39 PM PDT 24
Peak memory 196396 kb
Host smart-98fbaa56-d530-4260-8229-c018c182f348
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514355990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2514355990
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.105855352
Short name T60
Test name
Test status
Simulation time 77304802 ps
CPU time 2.5 seconds
Started Aug 11 06:13:05 PM PDT 24
Finished Aug 11 06:13:08 PM PDT 24
Peak memory 198780 kb
Host smart-7b7475b9-4f3f-40cd-815e-2a867df1b373
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105855352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.105855352
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3595286739
Short name T18
Test name
Test status
Simulation time 502454070 ps
CPU time 2.53 seconds
Started Aug 11 06:12:47 PM PDT 24
Finished Aug 11 06:12:50 PM PDT 24
Peak memory 196388 kb
Host smart-e6b56665-2188-4ed4-9493-8d849ac584d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595286739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3595286739
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.4209350548
Short name T172
Test name
Test status
Simulation time 39704495 ps
CPU time 1.01 seconds
Started Aug 11 06:12:44 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 196584 kb
Host smart-6eef923f-5a6f-4b8e-8407-496a58a577b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209350548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.4209350548
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2880832137
Short name T240
Test name
Test status
Simulation time 159746478 ps
CPU time 1.1 seconds
Started Aug 11 06:12:39 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 197364 kb
Host smart-37900967-a843-4626-949f-6598e88a3baf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880832137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2880832137
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1336130981
Short name T460
Test name
Test status
Simulation time 1004573005 ps
CPU time 6.89 seconds
Started Aug 11 06:12:50 PM PDT 24
Finished Aug 11 06:12:57 PM PDT 24
Peak memory 198788 kb
Host smart-6bf9b5b6-49b2-4e0b-be7b-9f84158cdfea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336130981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1336130981
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.117894077
Short name T168
Test name
Test status
Simulation time 76224086 ps
CPU time 1.27 seconds
Started Aug 11 06:12:38 PM PDT 24
Finished Aug 11 06:12:40 PM PDT 24
Peak memory 197236 kb
Host smart-3bc22039-67b0-4a67-9696-858de9661431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117894077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.117894077
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3841038250
Short name T581
Test name
Test status
Simulation time 154286246 ps
CPU time 0.96 seconds
Started Aug 11 06:13:01 PM PDT 24
Finished Aug 11 06:13:02 PM PDT 24
Peak memory 196508 kb
Host smart-7ad637c4-088d-4487-9fa3-d0335fd7f1b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841038250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3841038250
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.710012748
Short name T569
Test name
Test status
Simulation time 8111388563 ps
CPU time 221.34 seconds
Started Aug 11 06:13:00 PM PDT 24
Finished Aug 11 06:16:42 PM PDT 24
Peak memory 198772 kb
Host smart-2d7bb460-5b16-45e0-80be-4e03a1e8a4d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710012748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.710012748
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3372576766
Short name T614
Test name
Test status
Simulation time 13061563 ps
CPU time 0.58 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:12:54 PM PDT 24
Peak memory 194344 kb
Host smart-2ab77f88-cd4f-4564-af6f-0c794a2da22d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372576766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3372576766
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4065973318
Short name T588
Test name
Test status
Simulation time 31714036 ps
CPU time 0.79 seconds
Started Aug 11 06:12:44 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 195712 kb
Host smart-74f1ed5f-a12f-41cd-85c2-193b5fa78c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065973318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4065973318
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1723518538
Short name T369
Test name
Test status
Simulation time 81719826 ps
CPU time 4.84 seconds
Started Aug 11 06:12:43 PM PDT 24
Finished Aug 11 06:12:48 PM PDT 24
Peak memory 196616 kb
Host smart-31f96c94-2079-4e1e-8510-7cc650ef9f55
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723518538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1723518538
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3427226602
Short name T235
Test name
Test status
Simulation time 47209066 ps
CPU time 0.84 seconds
Started Aug 11 06:12:54 PM PDT 24
Finished Aug 11 06:12:55 PM PDT 24
Peak memory 197212 kb
Host smart-10f515f7-63f4-4934-8975-799eb09082d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427226602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3427226602
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3094425317
Short name T630
Test name
Test status
Simulation time 75775023 ps
CPU time 0.82 seconds
Started Aug 11 06:12:49 PM PDT 24
Finished Aug 11 06:12:50 PM PDT 24
Peak memory 197024 kb
Host smart-d2bb1e54-f79b-4600-8426-67fe2051b823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094425317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3094425317
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2585976138
Short name T566
Test name
Test status
Simulation time 334802382 ps
CPU time 2.24 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:48 PM PDT 24
Peak memory 198592 kb
Host smart-41439955-cc9c-4e83-a430-2af8b616e8a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585976138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2585976138
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.506487144
Short name T658
Test name
Test status
Simulation time 195968115 ps
CPU time 1.88 seconds
Started Aug 11 06:13:03 PM PDT 24
Finished Aug 11 06:13:05 PM PDT 24
Peak memory 197048 kb
Host smart-b6638b3c-9b6f-4ace-bb98-adcbde2fe7f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506487144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
506487144
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1737475676
Short name T178
Test name
Test status
Simulation time 238067457 ps
CPU time 0.93 seconds
Started Aug 11 06:12:54 PM PDT 24
Finished Aug 11 06:12:55 PM PDT 24
Peak memory 196548 kb
Host smart-ad3b67df-be29-4d98-a548-0c3a6cd77449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737475676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1737475676
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2698229540
Short name T241
Test name
Test status
Simulation time 44261372 ps
CPU time 1.13 seconds
Started Aug 11 06:12:44 PM PDT 24
Finished Aug 11 06:12:45 PM PDT 24
Peak memory 196624 kb
Host smart-6bc7b041-6b2a-44bd-afa5-16bc35f6d34e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698229540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2698229540
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2503922271
Short name T324
Test name
Test status
Simulation time 471987180 ps
CPU time 5.15 seconds
Started Aug 11 06:12:41 PM PDT 24
Finished Aug 11 06:12:46 PM PDT 24
Peak memory 198616 kb
Host smart-2094c1ca-13af-44d8-8168-94d4cc5124ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503922271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2503922271
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.73559737
Short name T339
Test name
Test status
Simulation time 63007842 ps
CPU time 1.15 seconds
Started Aug 11 06:12:47 PM PDT 24
Finished Aug 11 06:12:48 PM PDT 24
Peak memory 196360 kb
Host smart-8502ecde-0cff-4d76-a812-e889259b2f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73559737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.73559737
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3666395998
Short name T527
Test name
Test status
Simulation time 151867951 ps
CPU time 1 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:12:54 PM PDT 24
Peak memory 196324 kb
Host smart-a4c629e7-a822-4ef6-97b6-5b08c39ab77d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666395998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3666395998
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3063787398
Short name T355
Test name
Test status
Simulation time 8124003692 ps
CPU time 56.43 seconds
Started Aug 11 06:13:07 PM PDT 24
Finished Aug 11 06:14:03 PM PDT 24
Peak memory 198748 kb
Host smart-b67f18cf-10a3-4640-a11d-83e2a587b7e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063787398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3063787398
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2824745584
Short name T496
Test name
Test status
Simulation time 150985437821 ps
CPU time 1194.56 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:32:39 PM PDT 24
Peak memory 198876 kb
Host smart-f34e33a4-f2eb-4e15-9e1f-569d66c31b6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2824745584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2824745584
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.674088620
Short name T427
Test name
Test status
Simulation time 28477442 ps
CPU time 0.62 seconds
Started Aug 11 06:12:48 PM PDT 24
Finished Aug 11 06:12:48 PM PDT 24
Peak memory 194696 kb
Host smart-b01987fb-5fe0-44c3-a9db-15a12218e6b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674088620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.674088620
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.540005530
Short name T467
Test name
Test status
Simulation time 124550471 ps
CPU time 0.76 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:12:53 PM PDT 24
Peak memory 195852 kb
Host smart-013ad2a3-e103-432c-9f84-941a499edd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540005530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.540005530
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1091290133
Short name T188
Test name
Test status
Simulation time 752413058 ps
CPU time 25.01 seconds
Started Aug 11 06:12:56 PM PDT 24
Finished Aug 11 06:13:21 PM PDT 24
Peak memory 198576 kb
Host smart-891f45f0-b65f-41c2-964e-44c5f73f770a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091290133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1091290133
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2687016961
Short name T470
Test name
Test status
Simulation time 171820734 ps
CPU time 1.04 seconds
Started Aug 11 06:12:45 PM PDT 24
Finished Aug 11 06:12:46 PM PDT 24
Peak memory 197040 kb
Host smart-f9e1be3e-9954-4b61-a015-de97b9cca5f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687016961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2687016961
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1631335709
Short name T198
Test name
Test status
Simulation time 279450366 ps
CPU time 1.15 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:12:55 PM PDT 24
Peak memory 196736 kb
Host smart-b380b797-16d0-40c1-aabc-39f0a53374a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631335709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1631335709
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.286055705
Short name T343
Test name
Test status
Simulation time 80736866 ps
CPU time 1 seconds
Started Aug 11 06:12:48 PM PDT 24
Finished Aug 11 06:12:49 PM PDT 24
Peak memory 197716 kb
Host smart-88baac9f-ad10-4def-a876-ecb33caee6ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286055705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.286055705
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2675017107
Short name T327
Test name
Test status
Simulation time 156407624 ps
CPU time 1.58 seconds
Started Aug 11 06:12:56 PM PDT 24
Finished Aug 11 06:12:58 PM PDT 24
Peak memory 196744 kb
Host smart-2e2d3b0a-a0d6-4a27-974c-5b9fa720af64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675017107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2675017107
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.477167038
Short name T182
Test name
Test status
Simulation time 205153028 ps
CPU time 1.22 seconds
Started Aug 11 06:13:12 PM PDT 24
Finished Aug 11 06:13:13 PM PDT 24
Peak memory 197656 kb
Host smart-ca87db88-e35e-43bb-aeed-802899dcf8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477167038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.477167038
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2553177069
Short name T213
Test name
Test status
Simulation time 45038455 ps
CPU time 0.66 seconds
Started Aug 11 06:13:01 PM PDT 24
Finished Aug 11 06:13:02 PM PDT 24
Peak memory 195504 kb
Host smart-d35f75d6-9f1e-432d-888f-ab3c89baf22f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553177069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2553177069
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.63498618
Short name T560
Test name
Test status
Simulation time 88461965 ps
CPU time 1.64 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:12:55 PM PDT 24
Peak memory 198604 kb
Host smart-658742b9-2bf0-4e4b-a7b8-cbc354222e5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63498618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand
om_long_reg_writes_reg_reads.63498618
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1766998747
Short name T391
Test name
Test status
Simulation time 409993036 ps
CPU time 1.36 seconds
Started Aug 11 06:12:50 PM PDT 24
Finished Aug 11 06:12:52 PM PDT 24
Peak memory 196068 kb
Host smart-fca89b2d-3a99-4544-9407-6c85283ea968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766998747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1766998747
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3005087972
Short name T594
Test name
Test status
Simulation time 68498663 ps
CPU time 1.01 seconds
Started Aug 11 06:12:51 PM PDT 24
Finished Aug 11 06:12:52 PM PDT 24
Peak memory 197008 kb
Host smart-b8783717-cfd1-4bb2-b5fd-25a029f9b5ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005087972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3005087972
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3299399323
Short name T517
Test name
Test status
Simulation time 5077391348 ps
CPU time 128.01 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:15:01 PM PDT 24
Peak memory 198804 kb
Host smart-64c4fee4-021c-403c-9f64-ba3c57583996
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299399323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3299399323
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1706768412
Short name T388
Test name
Test status
Simulation time 89777917 ps
CPU time 0.59 seconds
Started Aug 11 06:12:56 PM PDT 24
Finished Aug 11 06:12:56 PM PDT 24
Peak memory 194536 kb
Host smart-b5f99b53-ab6c-4299-9c56-1e85a9157806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706768412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1706768412
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2045696930
Short name T226
Test name
Test status
Simulation time 37041502 ps
CPU time 0.92 seconds
Started Aug 11 06:12:48 PM PDT 24
Finished Aug 11 06:12:49 PM PDT 24
Peak memory 196824 kb
Host smart-3fb2e6f0-991a-46bf-940e-b89f520eadf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045696930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2045696930
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2413771003
Short name T638
Test name
Test status
Simulation time 69090375 ps
CPU time 3.29 seconds
Started Aug 11 06:13:11 PM PDT 24
Finished Aug 11 06:13:15 PM PDT 24
Peak memory 196316 kb
Host smart-be9733a4-399b-4d70-a56d-8d4e72037295
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413771003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2413771003
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.412387947
Short name T234
Test name
Test status
Simulation time 114538393 ps
CPU time 0.96 seconds
Started Aug 11 06:13:12 PM PDT 24
Finished Aug 11 06:13:13 PM PDT 24
Peak memory 198336 kb
Host smart-caaf60a7-c4c2-4ef7-9162-c0a074173826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412387947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.412387947
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.35411544
Short name T164
Test name
Test status
Simulation time 35158574 ps
CPU time 1.08 seconds
Started Aug 11 06:12:55 PM PDT 24
Finished Aug 11 06:12:56 PM PDT 24
Peak memory 197060 kb
Host smart-10c856d7-c9ee-45ae-acf8-0e334bcb4bd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35411544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.35411544
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.601930928
Short name T683
Test name
Test status
Simulation time 552976466 ps
CPU time 2.49 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:12:56 PM PDT 24
Peak memory 198476 kb
Host smart-f12f6e6c-b718-430d-95fa-e925252eb553
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601930928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.601930928
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3169853123
Short name T156
Test name
Test status
Simulation time 2389049034 ps
CPU time 2.88 seconds
Started Aug 11 06:12:49 PM PDT 24
Finished Aug 11 06:12:52 PM PDT 24
Peak memory 197964 kb
Host smart-a41cf18d-7752-4de8-a995-5808dffcf5d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169853123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3169853123
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1759067710
Short name T650
Test name
Test status
Simulation time 62059773 ps
CPU time 1.15 seconds
Started Aug 11 06:12:55 PM PDT 24
Finished Aug 11 06:12:56 PM PDT 24
Peak memory 196400 kb
Host smart-34b4cb57-e309-4843-a79a-5fec4812469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759067710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1759067710
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2147074522
Short name T195
Test name
Test status
Simulation time 94578879 ps
CPU time 0.81 seconds
Started Aug 11 06:12:46 PM PDT 24
Finished Aug 11 06:12:47 PM PDT 24
Peak memory 196064 kb
Host smart-30054bbc-fa5a-44a5-b469-e3b4be738359
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147074522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2147074522
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1097905566
Short name T380
Test name
Test status
Simulation time 123723335 ps
CPU time 1.58 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:12:55 PM PDT 24
Peak memory 198556 kb
Host smart-bd118378-9663-418b-acd8-c9f983466879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097905566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1097905566
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3025811923
Short name T663
Test name
Test status
Simulation time 67296495 ps
CPU time 1.23 seconds
Started Aug 11 06:13:00 PM PDT 24
Finished Aug 11 06:13:01 PM PDT 24
Peak memory 197160 kb
Host smart-56acc08d-c1b2-4d31-b7c3-d20cb7408dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025811923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3025811923
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1810128341
Short name T501
Test name
Test status
Simulation time 38657573 ps
CPU time 1.08 seconds
Started Aug 11 06:12:58 PM PDT 24
Finished Aug 11 06:12:59 PM PDT 24
Peak memory 197040 kb
Host smart-9f922ba8-3bb3-4ff0-a1ed-ffb39b47a18f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810128341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1810128341
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.402803766
Short name T469
Test name
Test status
Simulation time 36916456172 ps
CPU time 157.82 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:15:31 PM PDT 24
Peak memory 198808 kb
Host smart-1b48eff7-1aa1-4206-b005-30d604971bc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402803766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.402803766
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2737688708
Short name T385
Test name
Test status
Simulation time 53661485799 ps
CPU time 434.03 seconds
Started Aug 11 06:12:55 PM PDT 24
Finished Aug 11 06:20:09 PM PDT 24
Peak memory 198928 kb
Host smart-ed2b2902-5d8a-4f57-a2bd-bec430cdca5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2737688708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2737688708
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1262598954
Short name T279
Test name
Test status
Simulation time 15364169 ps
CPU time 0.57 seconds
Started Aug 11 06:11:51 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 194680 kb
Host smart-05483013-b50d-48ca-bb00-6aa79903bd12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262598954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1262598954
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1207692073
Short name T306
Test name
Test status
Simulation time 93655895 ps
CPU time 0.76 seconds
Started Aug 11 06:11:50 PM PDT 24
Finished Aug 11 06:11:51 PM PDT 24
Peak memory 195884 kb
Host smart-20791e61-2078-441e-b397-4634bba8a99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207692073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1207692073
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2275537738
Short name T382
Test name
Test status
Simulation time 1789725843 ps
CPU time 14.46 seconds
Started Aug 11 06:11:53 PM PDT 24
Finished Aug 11 06:12:07 PM PDT 24
Peak memory 197672 kb
Host smart-9b85ffbc-32fb-44ee-8d5d-dffec6211fce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275537738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2275537738
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.4260313799
Short name T644
Test name
Test status
Simulation time 455478485 ps
CPU time 1.13 seconds
Started Aug 11 06:11:44 PM PDT 24
Finished Aug 11 06:11:45 PM PDT 24
Peak memory 198600 kb
Host smart-d1aae70e-d0d2-4232-aeba-3aef23c963a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260313799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.4260313799
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2032631136
Short name T256
Test name
Test status
Simulation time 236371160 ps
CPU time 1.21 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:11:49 PM PDT 24
Peak memory 196852 kb
Host smart-117deaf3-6f0e-41e3-9080-fcd41785434c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032631136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2032631136
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.4156013586
Short name T215
Test name
Test status
Simulation time 53385967 ps
CPU time 0.94 seconds
Started Aug 11 06:11:43 PM PDT 24
Finished Aug 11 06:11:44 PM PDT 24
Peak memory 196836 kb
Host smart-8d7ea83d-784a-4941-850e-bed362bdc291
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156013586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.4156013586
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.690176713
Short name T74
Test name
Test status
Simulation time 85982076 ps
CPU time 1.83 seconds
Started Aug 11 06:11:40 PM PDT 24
Finished Aug 11 06:11:42 PM PDT 24
Peak memory 197380 kb
Host smart-c7b65ca7-2c1e-4167-94e0-f94daa6cfc2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690176713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.690176713
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3951739326
Short name T421
Test name
Test status
Simulation time 143219596 ps
CPU time 1.38 seconds
Started Aug 11 06:11:44 PM PDT 24
Finished Aug 11 06:11:46 PM PDT 24
Peak memory 198580 kb
Host smart-0c2d8aa1-4fbc-4cab-981f-005191d38510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951739326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3951739326
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2625956115
Short name T459
Test name
Test status
Simulation time 32823239 ps
CPU time 0.68 seconds
Started Aug 11 06:11:44 PM PDT 24
Finished Aug 11 06:11:45 PM PDT 24
Peak memory 195940 kb
Host smart-66178e72-6c08-4828-b212-4fa5aa9477c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625956115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2625956115
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2134051252
Short name T599
Test name
Test status
Simulation time 590514013 ps
CPU time 4.54 seconds
Started Aug 11 06:11:43 PM PDT 24
Finished Aug 11 06:11:47 PM PDT 24
Peak memory 198604 kb
Host smart-074da63e-0c60-4080-b56e-1450cf073e3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134051252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2134051252
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.347253902
Short name T44
Test name
Test status
Simulation time 337655820 ps
CPU time 0.94 seconds
Started Aug 11 06:11:50 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 215588 kb
Host smart-1fd20a35-d576-4313-81d6-232c6d6cb411
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347253902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.347253902
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3268439103
Short name T251
Test name
Test status
Simulation time 75576822 ps
CPU time 1.08 seconds
Started Aug 11 06:11:46 PM PDT 24
Finished Aug 11 06:11:47 PM PDT 24
Peak memory 196876 kb
Host smart-b0078a6e-7449-4bf6-80cc-c4065b217d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268439103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3268439103
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3093163352
Short name T652
Test name
Test status
Simulation time 37742353 ps
CPU time 1.12 seconds
Started Aug 11 06:11:51 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 197220 kb
Host smart-27ceda1d-23f8-4951-ad9e-9f17db8e488b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093163352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3093163352
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3019073517
Short name T180
Test name
Test status
Simulation time 1048962941 ps
CPU time 25.41 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:12:13 PM PDT 24
Peak memory 198548 kb
Host smart-c6db647b-52d6-4b27-ba7b-fe8a9b5996f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019073517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3019073517
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3039178340
Short name T632
Test name
Test status
Simulation time 13422106 ps
CPU time 0.61 seconds
Started Aug 11 06:13:18 PM PDT 24
Finished Aug 11 06:13:19 PM PDT 24
Peak memory 194492 kb
Host smart-45ba8a12-a4e3-4317-8dc0-19cb7fced367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039178340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3039178340
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1897257792
Short name T159
Test name
Test status
Simulation time 48735899 ps
CPU time 0.88 seconds
Started Aug 11 06:13:12 PM PDT 24
Finished Aug 11 06:13:13 PM PDT 24
Peak memory 197016 kb
Host smart-e803b9a9-d285-4c94-abe0-69e35f333912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897257792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1897257792
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2704395071
Short name T229
Test name
Test status
Simulation time 2671109572 ps
CPU time 23.59 seconds
Started Aug 11 06:12:54 PM PDT 24
Finished Aug 11 06:13:17 PM PDT 24
Peak memory 198260 kb
Host smart-c92193f3-ebd6-467a-91da-6ed862150e54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704395071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2704395071
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.593675902
Short name T368
Test name
Test status
Simulation time 34761742 ps
CPU time 0.64 seconds
Started Aug 11 06:12:52 PM PDT 24
Finished Aug 11 06:12:53 PM PDT 24
Peak memory 194944 kb
Host smart-9539a3e8-f0a7-403d-bc57-864810327771
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593675902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.593675902
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3066466650
Short name T381
Test name
Test status
Simulation time 74233096 ps
CPU time 1.14 seconds
Started Aug 11 06:12:56 PM PDT 24
Finished Aug 11 06:12:58 PM PDT 24
Peak memory 197372 kb
Host smart-35eb05a6-91c5-41a9-8f40-3ed9539e0324
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066466650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3066466650
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3571043551
Short name T15
Test name
Test status
Simulation time 312112750 ps
CPU time 2.97 seconds
Started Aug 11 06:12:55 PM PDT 24
Finished Aug 11 06:12:58 PM PDT 24
Peak memory 198640 kb
Host smart-f2cdf9dc-e20e-4970-8d6d-eb609fa89915
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571043551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3571043551
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.600636398
Short name T525
Test name
Test status
Simulation time 495365125 ps
CPU time 2.96 seconds
Started Aug 11 06:12:52 PM PDT 24
Finished Aug 11 06:12:55 PM PDT 24
Peak memory 197076 kb
Host smart-1820fa7f-6c6c-410a-bd99-45f19c973b6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600636398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
600636398
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1527033036
Short name T424
Test name
Test status
Simulation time 34745319 ps
CPU time 0.85 seconds
Started Aug 11 06:12:52 PM PDT 24
Finished Aug 11 06:12:53 PM PDT 24
Peak memory 197160 kb
Host smart-1d98a510-e92c-437a-b62c-b573ea485774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527033036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1527033036
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1317109564
Short name T618
Test name
Test status
Simulation time 87930212 ps
CPU time 0.74 seconds
Started Aug 11 06:13:02 PM PDT 24
Finished Aug 11 06:13:02 PM PDT 24
Peak memory 196032 kb
Host smart-582f269b-5a51-48ac-b082-9c9f9fbaa33b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317109564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1317109564
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.151784555
Short name T258
Test name
Test status
Simulation time 3268654818 ps
CPU time 3.34 seconds
Started Aug 11 06:13:08 PM PDT 24
Finished Aug 11 06:13:12 PM PDT 24
Peak memory 198700 kb
Host smart-93ece41c-76ff-4e00-a7d9-7909a3089773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151784555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.151784555
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2131117344
Short name T219
Test name
Test status
Simulation time 141438356 ps
CPU time 0.77 seconds
Started Aug 11 06:12:56 PM PDT 24
Finished Aug 11 06:12:56 PM PDT 24
Peak memory 195668 kb
Host smart-eb00c045-e291-4ddd-b79d-582232617d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131117344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2131117344
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3136225371
Short name T531
Test name
Test status
Simulation time 212855168 ps
CPU time 1.05 seconds
Started Aug 11 06:13:07 PM PDT 24
Finished Aug 11 06:13:08 PM PDT 24
Peak memory 197076 kb
Host smart-1b9d1010-9cb1-4c2a-8cc7-b950727ce1b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136225371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3136225371
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3111423566
Short name T601
Test name
Test status
Simulation time 47554405520 ps
CPU time 149.46 seconds
Started Aug 11 06:13:07 PM PDT 24
Finished Aug 11 06:15:37 PM PDT 24
Peak memory 198740 kb
Host smart-44106ff3-17fa-485d-be33-dff4871d31dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111423566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3111423566
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.662394283
Short name T511
Test name
Test status
Simulation time 77657905402 ps
CPU time 1428.44 seconds
Started Aug 11 06:12:53 PM PDT 24
Finished Aug 11 06:36:41 PM PDT 24
Peak memory 198864 kb
Host smart-6ab3b584-d914-419d-82ed-834cc0c30c95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=662394283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.662394283
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.210217606
Short name T622
Test name
Test status
Simulation time 14882954 ps
CPU time 0.58 seconds
Started Aug 11 06:13:19 PM PDT 24
Finished Aug 11 06:13:20 PM PDT 24
Peak memory 194428 kb
Host smart-a814f9d0-0a3c-4712-8dfc-aeb2c578af11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210217606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.210217606
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2227375831
Short name T347
Test name
Test status
Simulation time 103628489 ps
CPU time 0.71 seconds
Started Aug 11 06:13:04 PM PDT 24
Finished Aug 11 06:13:05 PM PDT 24
Peak memory 196448 kb
Host smart-78be70a5-dbec-4759-8bee-b12adf415d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227375831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2227375831
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2356690295
Short name T122
Test name
Test status
Simulation time 510852989 ps
CPU time 27.35 seconds
Started Aug 11 06:13:07 PM PDT 24
Finished Aug 11 06:13:35 PM PDT 24
Peak memory 196112 kb
Host smart-71e4d19e-0858-4e55-8b99-3d5d2a9486a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356690295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2356690295
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.600554584
Short name T466
Test name
Test status
Simulation time 33566108 ps
CPU time 0.61 seconds
Started Aug 11 06:12:58 PM PDT 24
Finished Aug 11 06:12:59 PM PDT 24
Peak memory 194692 kb
Host smart-6157cb3a-e632-45f2-92a1-13f8c7d36bb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600554584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.600554584
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2563856385
Short name T167
Test name
Test status
Simulation time 100812614 ps
CPU time 0.83 seconds
Started Aug 11 06:13:15 PM PDT 24
Finished Aug 11 06:13:16 PM PDT 24
Peak memory 197632 kb
Host smart-e7d786b1-c1c4-413a-a173-144a8244600c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563856385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2563856385
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1576616163
Short name T247
Test name
Test status
Simulation time 93063422 ps
CPU time 1.91 seconds
Started Aug 11 06:13:12 PM PDT 24
Finished Aug 11 06:13:14 PM PDT 24
Peak memory 198672 kb
Host smart-b7c74cbd-25d6-407f-81f8-2541d9b50d4f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576616163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1576616163
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2643817882
Short name T500
Test name
Test status
Simulation time 40534599 ps
CPU time 1.1 seconds
Started Aug 11 06:12:55 PM PDT 24
Finished Aug 11 06:12:56 PM PDT 24
Peak memory 196020 kb
Host smart-f3292d99-f23d-4937-a085-754159e6113c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643817882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2643817882
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1386290176
Short name T352
Test name
Test status
Simulation time 575793174 ps
CPU time 0.91 seconds
Started Aug 11 06:12:52 PM PDT 24
Finished Aug 11 06:12:53 PM PDT 24
Peak memory 196512 kb
Host smart-cde07454-2aa4-4969-b442-bea647fac46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386290176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1386290176
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3502888631
Short name T691
Test name
Test status
Simulation time 96536883 ps
CPU time 1.07 seconds
Started Aug 11 06:12:57 PM PDT 24
Finished Aug 11 06:12:58 PM PDT 24
Peak memory 196652 kb
Host smart-d1c223cd-218c-4c38-8b78-25e43f67be49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502888631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3502888631
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.331720006
Short name T9
Test name
Test status
Simulation time 3309214294 ps
CPU time 4.97 seconds
Started Aug 11 06:12:56 PM PDT 24
Finished Aug 11 06:13:01 PM PDT 24
Peak memory 198692 kb
Host smart-57f641f1-e60a-44a2-b656-fc66fde7ee86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331720006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.331720006
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1510448258
Short name T261
Test name
Test status
Simulation time 350304604 ps
CPU time 1.05 seconds
Started Aug 11 06:13:08 PM PDT 24
Finished Aug 11 06:13:10 PM PDT 24
Peak memory 196076 kb
Host smart-9c2cae34-5b67-4f2e-87f0-dbe77f2d8b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510448258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1510448258
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2261855995
Short name T329
Test name
Test status
Simulation time 658601276 ps
CPU time 1.03 seconds
Started Aug 11 06:12:57 PM PDT 24
Finished Aug 11 06:12:58 PM PDT 24
Peak memory 197100 kb
Host smart-d579353c-ecb9-4a7d-8c75-3a0ccb3eadaf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261855995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2261855995
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3516015014
Short name T474
Test name
Test status
Simulation time 13177905090 ps
CPU time 163.54 seconds
Started Aug 11 06:13:20 PM PDT 24
Finished Aug 11 06:16:04 PM PDT 24
Peak memory 198756 kb
Host smart-2ed8583e-967b-42d0-839c-9409e122bebe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516015014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3516015014
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1974795812
Short name T194
Test name
Test status
Simulation time 12209726 ps
CPU time 0.57 seconds
Started Aug 11 06:13:00 PM PDT 24
Finished Aug 11 06:13:00 PM PDT 24
Peak memory 194524 kb
Host smart-739b6e83-1329-40d8-885f-3d9cff276cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974795812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1974795812
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.333459260
Short name T142
Test name
Test status
Simulation time 121833807 ps
CPU time 0.71 seconds
Started Aug 11 06:12:59 PM PDT 24
Finished Aug 11 06:13:00 PM PDT 24
Peak memory 194768 kb
Host smart-c6b8638f-daad-4f3c-ae6e-6929f6640610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333459260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.333459260
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2592763750
Short name T611
Test name
Test status
Simulation time 267560032 ps
CPU time 13.65 seconds
Started Aug 11 06:13:06 PM PDT 24
Finished Aug 11 06:13:20 PM PDT 24
Peak memory 196080 kb
Host smart-752a7f62-25b4-4888-80ae-340b13375ad8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592763750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2592763750
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.720483897
Short name T407
Test name
Test status
Simulation time 56611628 ps
CPU time 0.71 seconds
Started Aug 11 06:12:59 PM PDT 24
Finished Aug 11 06:13:00 PM PDT 24
Peak memory 195064 kb
Host smart-6fb940f8-be08-46d5-9c1a-1d968d571f41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720483897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.720483897
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3054248830
Short name T596
Test name
Test status
Simulation time 98532614 ps
CPU time 1.39 seconds
Started Aug 11 06:12:58 PM PDT 24
Finished Aug 11 06:12:59 PM PDT 24
Peak memory 197216 kb
Host smart-cb85bf36-1a50-4a95-aff2-2db922fd243a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054248830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3054248830
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2080244659
Short name T577
Test name
Test status
Simulation time 456007644 ps
CPU time 2.87 seconds
Started Aug 11 06:12:57 PM PDT 24
Finished Aug 11 06:13:00 PM PDT 24
Peak memory 197064 kb
Host smart-941f8df4-97b4-4556-b444-c4b0e9c6896e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080244659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2080244659
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.57232338
Short name T192
Test name
Test status
Simulation time 129976862 ps
CPU time 2.71 seconds
Started Aug 11 06:13:13 PM PDT 24
Finished Aug 11 06:13:16 PM PDT 24
Peak memory 198688 kb
Host smart-bd4a7a60-72b9-4e16-961f-5faa3a9ee48e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57232338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.57232338
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2457214309
Short name T629
Test name
Test status
Simulation time 420053005 ps
CPU time 1.04 seconds
Started Aug 11 06:13:01 PM PDT 24
Finished Aug 11 06:13:02 PM PDT 24
Peak memory 196644 kb
Host smart-4ace4372-8942-4dbf-b3f1-a9a5a45b9090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457214309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2457214309
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3143216190
Short name T177
Test name
Test status
Simulation time 75062528 ps
CPU time 0.74 seconds
Started Aug 11 06:12:56 PM PDT 24
Finished Aug 11 06:12:57 PM PDT 24
Peak memory 196004 kb
Host smart-5bb625b1-bff1-4b60-85d7-bd9a8f1a5911
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143216190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3143216190
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3421691837
Short name T7
Test name
Test status
Simulation time 5667320838 ps
CPU time 6.37 seconds
Started Aug 11 06:12:59 PM PDT 24
Finished Aug 11 06:13:05 PM PDT 24
Peak memory 198632 kb
Host smart-50ed027a-04f9-4811-9ef1-48da65a5fbba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421691837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3421691837
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2988983911
Short name T76
Test name
Test status
Simulation time 40115199 ps
CPU time 0.77 seconds
Started Aug 11 06:13:23 PM PDT 24
Finished Aug 11 06:13:24 PM PDT 24
Peak memory 195676 kb
Host smart-3fb18968-90e1-4a15-b857-acc32ef50584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988983911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2988983911
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.225940004
Short name T404
Test name
Test status
Simulation time 285271333 ps
CPU time 1.13 seconds
Started Aug 11 06:13:07 PM PDT 24
Finished Aug 11 06:13:08 PM PDT 24
Peak memory 196220 kb
Host smart-12f97466-c61c-4901-8041-498c36b2c344
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225940004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.225940004
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2472818529
Short name T576
Test name
Test status
Simulation time 44711800204 ps
CPU time 108.7 seconds
Started Aug 11 06:12:59 PM PDT 24
Finished Aug 11 06:14:48 PM PDT 24
Peak memory 198656 kb
Host smart-cbc194be-db94-47be-ae5b-81c10c9b7c41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472818529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2472818529
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1548453182
Short name T442
Test name
Test status
Simulation time 37112421 ps
CPU time 0.59 seconds
Started Aug 11 06:13:04 PM PDT 24
Finished Aug 11 06:13:04 PM PDT 24
Peak memory 195172 kb
Host smart-de694db9-d924-44a9-8014-8a7a20fcd50a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548453182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1548453182
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2156041947
Short name T84
Test name
Test status
Simulation time 126089833 ps
CPU time 0.83 seconds
Started Aug 11 06:13:15 PM PDT 24
Finished Aug 11 06:13:16 PM PDT 24
Peak memory 196412 kb
Host smart-577f8c74-3d28-456e-9a6f-45d7c24161a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156041947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2156041947
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2651769776
Short name T187
Test name
Test status
Simulation time 696109999 ps
CPU time 15.54 seconds
Started Aug 11 06:13:20 PM PDT 24
Finished Aug 11 06:13:35 PM PDT 24
Peak memory 197524 kb
Host smart-c83d7f56-f774-4900-baa2-efab1e2c8048
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651769776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2651769776
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2378159810
Short name T365
Test name
Test status
Simulation time 48984066 ps
CPU time 0.69 seconds
Started Aug 11 06:13:24 PM PDT 24
Finished Aug 11 06:13:25 PM PDT 24
Peak memory 195324 kb
Host smart-4fdb5e8f-da53-468c-82f3-608f57c5b0b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378159810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2378159810
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.484655914
Short name T453
Test name
Test status
Simulation time 289654602 ps
CPU time 1.21 seconds
Started Aug 11 06:13:04 PM PDT 24
Finished Aug 11 06:13:05 PM PDT 24
Peak memory 196888 kb
Host smart-bbefa8fa-5b67-4e28-b056-bd6edf5f6c79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484655914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.484655914
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1612392472
Short name T81
Test name
Test status
Simulation time 152946644 ps
CPU time 1.65 seconds
Started Aug 11 06:13:10 PM PDT 24
Finished Aug 11 06:13:12 PM PDT 24
Peak memory 198600 kb
Host smart-886bc081-5134-42bb-b58a-9b61c749f044
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612392472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1612392472
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3254821592
Short name T461
Test name
Test status
Simulation time 61566327 ps
CPU time 1.97 seconds
Started Aug 11 06:13:04 PM PDT 24
Finished Aug 11 06:13:06 PM PDT 24
Peak memory 197748 kb
Host smart-40e268b4-2056-4730-a6e0-79978bbc440c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254821592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3254821592
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2493613118
Short name T485
Test name
Test status
Simulation time 48218119 ps
CPU time 0.83 seconds
Started Aug 11 06:12:55 PM PDT 24
Finished Aug 11 06:12:56 PM PDT 24
Peak memory 196008 kb
Host smart-c215fe0f-1a5a-439b-94f4-5995607d6add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493613118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2493613118
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3978175852
Short name T264
Test name
Test status
Simulation time 45943952 ps
CPU time 1.15 seconds
Started Aug 11 06:13:08 PM PDT 24
Finished Aug 11 06:13:09 PM PDT 24
Peak memory 196620 kb
Host smart-0507e978-464a-486d-84ac-012c0c7fb85c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978175852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3978175852
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.595885040
Short name T370
Test name
Test status
Simulation time 167991312 ps
CPU time 2.78 seconds
Started Aug 11 06:13:05 PM PDT 24
Finished Aug 11 06:13:08 PM PDT 24
Peak memory 198600 kb
Host smart-9cb4323d-0d2c-4419-9475-aa1794307f27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595885040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.595885040
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.936066805
Short name T189
Test name
Test status
Simulation time 151024258 ps
CPU time 1.5 seconds
Started Aug 11 06:12:59 PM PDT 24
Finished Aug 11 06:13:01 PM PDT 24
Peak memory 197428 kb
Host smart-36a7a19f-4717-4279-a23c-5f51899289d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936066805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.936066805
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1500223853
Short name T130
Test name
Test status
Simulation time 40205505 ps
CPU time 1.14 seconds
Started Aug 11 06:13:12 PM PDT 24
Finished Aug 11 06:13:14 PM PDT 24
Peak memory 196316 kb
Host smart-187c70d3-8721-44c2-a68a-87a1e03d1812
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500223853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1500223853
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3563924305
Short name T483
Test name
Test status
Simulation time 12650311559 ps
CPU time 66.01 seconds
Started Aug 11 06:13:03 PM PDT 24
Finished Aug 11 06:14:09 PM PDT 24
Peak memory 198704 kb
Host smart-e6d57ff8-81cf-4764-8f43-e6554392c5b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563924305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3563924305
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.601810980
Short name T37
Test name
Test status
Simulation time 490797526381 ps
CPU time 2068.33 seconds
Started Aug 11 06:13:21 PM PDT 24
Finished Aug 11 06:47:50 PM PDT 24
Peak memory 198840 kb
Host smart-64398c97-ebe8-4220-b52b-6dc0595db756
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=601810980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.601810980
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2447956098
Short name T523
Test name
Test status
Simulation time 70965178 ps
CPU time 0.6 seconds
Started Aug 11 06:13:22 PM PDT 24
Finished Aug 11 06:13:23 PM PDT 24
Peak memory 195404 kb
Host smart-52062375-0ff6-44fd-a7c6-c230eef75634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447956098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2447956098
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.832252346
Short name T550
Test name
Test status
Simulation time 61909650 ps
CPU time 0.92 seconds
Started Aug 11 06:13:05 PM PDT 24
Finished Aug 11 06:13:06 PM PDT 24
Peak memory 196244 kb
Host smart-71a75fe3-2e09-4bed-946f-9d8406d99ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832252346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.832252346
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.693600767
Short name T11
Test name
Test status
Simulation time 432071319 ps
CPU time 6.73 seconds
Started Aug 11 06:13:04 PM PDT 24
Finished Aug 11 06:13:11 PM PDT 24
Peak memory 197280 kb
Host smart-2ff8a22e-10ef-4d5a-9602-5c8806a6ef50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693600767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.693600767
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1169444527
Short name T120
Test name
Test status
Simulation time 36124858 ps
CPU time 0.75 seconds
Started Aug 11 06:13:20 PM PDT 24
Finished Aug 11 06:13:20 PM PDT 24
Peak memory 196016 kb
Host smart-cd43d7af-376c-41f0-92b5-04c2219f8156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169444527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1169444527
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3566088158
Short name T175
Test name
Test status
Simulation time 132397493 ps
CPU time 0.91 seconds
Started Aug 11 06:13:18 PM PDT 24
Finished Aug 11 06:13:19 PM PDT 24
Peak memory 198064 kb
Host smart-c1e808eb-6e6f-4f32-be01-c610c442ea38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566088158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3566088158
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1753060967
Short name T24
Test name
Test status
Simulation time 88924069 ps
CPU time 3.61 seconds
Started Aug 11 06:13:18 PM PDT 24
Finished Aug 11 06:13:22 PM PDT 24
Peak memory 198572 kb
Host smart-bf208964-771f-4977-a3ea-ed79d525b8b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753060967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1753060967
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.510155195
Short name T586
Test name
Test status
Simulation time 105226221 ps
CPU time 3.06 seconds
Started Aug 11 06:13:02 PM PDT 24
Finished Aug 11 06:13:05 PM PDT 24
Peak memory 197644 kb
Host smart-af3a901a-056f-4cbc-a8e3-464679a352fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510155195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
510155195
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1659970514
Short name T688
Test name
Test status
Simulation time 117514550 ps
CPU time 1.28 seconds
Started Aug 11 06:13:18 PM PDT 24
Finished Aug 11 06:13:20 PM PDT 24
Peak memory 198464 kb
Host smart-9f8231d3-0f1e-4336-8315-7cc1d5b56294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659970514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1659970514
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3239353451
Short name T268
Test name
Test status
Simulation time 41890452 ps
CPU time 0.66 seconds
Started Aug 11 06:13:04 PM PDT 24
Finished Aug 11 06:13:05 PM PDT 24
Peak memory 194768 kb
Host smart-20e080a5-9ae6-412d-a8c2-83a942ec55ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239353451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3239353451
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.4113049979
Short name T160
Test name
Test status
Simulation time 298574711 ps
CPU time 4.68 seconds
Started Aug 11 06:13:04 PM PDT 24
Finished Aug 11 06:13:09 PM PDT 24
Peak memory 198792 kb
Host smart-1c370a2b-6076-4099-ac84-f9141dbb87ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113049979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.4113049979
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3307980581
Short name T191
Test name
Test status
Simulation time 276140077 ps
CPU time 1.18 seconds
Started Aug 11 06:13:16 PM PDT 24
Finished Aug 11 06:13:18 PM PDT 24
Peak memory 196808 kb
Host smart-ceb9d3b4-ebdf-42d0-be34-949dd44de107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307980581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3307980581
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.938190750
Short name T155
Test name
Test status
Simulation time 68728781 ps
CPU time 1.27 seconds
Started Aug 11 06:13:06 PM PDT 24
Finished Aug 11 06:13:07 PM PDT 24
Peak memory 197560 kb
Host smart-9dd8c6bf-85db-4c6a-9ad2-b62cd91aef04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938190750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.938190750
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2905155511
Short name T608
Test name
Test status
Simulation time 12253959939 ps
CPU time 169.47 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:16:26 PM PDT 24
Peak memory 198732 kb
Host smart-73d452b2-94af-473e-9e26-9c4b16755ab7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905155511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2905155511
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.468391475
Short name T422
Test name
Test status
Simulation time 19728669 ps
CPU time 0.57 seconds
Started Aug 11 06:13:19 PM PDT 24
Finished Aug 11 06:13:20 PM PDT 24
Peak memory 195428 kb
Host smart-7e94fb68-9830-4064-8c5e-000dcaf237a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468391475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.468391475
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1018117369
Short name T255
Test name
Test status
Simulation time 102922390 ps
CPU time 0.68 seconds
Started Aug 11 06:13:19 PM PDT 24
Finished Aug 11 06:13:20 PM PDT 24
Peak memory 195244 kb
Host smart-100cc300-91f0-4971-aa13-6ba0592053f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018117369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1018117369
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.376179192
Short name T526
Test name
Test status
Simulation time 91154553 ps
CPU time 4.39 seconds
Started Aug 11 06:13:21 PM PDT 24
Finished Aug 11 06:13:26 PM PDT 24
Peak memory 197228 kb
Host smart-fffbf446-a2b5-4989-9760-dd26fb740c03
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376179192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.376179192
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.179716960
Short name T266
Test name
Test status
Simulation time 64185027 ps
CPU time 0.93 seconds
Started Aug 11 06:13:22 PM PDT 24
Finished Aug 11 06:13:23 PM PDT 24
Peak memory 198208 kb
Host smart-f1853a6b-180d-4fc0-ba9d-9da050433fed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179716960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.179716960
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.219345780
Short name T430
Test name
Test status
Simulation time 205089114 ps
CPU time 0.86 seconds
Started Aug 11 06:13:13 PM PDT 24
Finished Aug 11 06:13:14 PM PDT 24
Peak memory 197312 kb
Host smart-adfdcffd-80f9-434f-aa2c-841c352c5db0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219345780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.219345780
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.39477055
Short name T61
Test name
Test status
Simulation time 83054176 ps
CPU time 1.81 seconds
Started Aug 11 06:13:27 PM PDT 24
Finished Aug 11 06:13:29 PM PDT 24
Peak memory 198712 kb
Host smart-b2dce4ba-5415-4a47-9b36-0a92b2694ac4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39477055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.gpio_intr_with_filter_rand_intr_event.39477055
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2151326632
Short name T684
Test name
Test status
Simulation time 61874916 ps
CPU time 1.89 seconds
Started Aug 11 06:13:05 PM PDT 24
Finished Aug 11 06:13:07 PM PDT 24
Peak memory 197328 kb
Host smart-33e3f327-73f4-4316-8d6d-e5cc800b7784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151326632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2151326632
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.4290773942
Short name T202
Test name
Test status
Simulation time 97971818 ps
CPU time 1.26 seconds
Started Aug 11 06:13:17 PM PDT 24
Finished Aug 11 06:13:19 PM PDT 24
Peak memory 198584 kb
Host smart-584368f0-70ee-4394-bd3b-5e1d39ae57f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290773942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.4290773942
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1662170858
Short name T128
Test name
Test status
Simulation time 58681449 ps
CPU time 1.1 seconds
Started Aug 11 06:13:14 PM PDT 24
Finished Aug 11 06:13:15 PM PDT 24
Peak memory 196388 kb
Host smart-221e4330-c666-4cf8-84ac-e0fc73e10345
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662170858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1662170858
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2647505304
Short name T667
Test name
Test status
Simulation time 897465832 ps
CPU time 2.2 seconds
Started Aug 11 06:13:07 PM PDT 24
Finished Aug 11 06:13:09 PM PDT 24
Peak memory 198548 kb
Host smart-cd2c4ac4-b032-49a7-9f82-88d758f48d27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647505304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2647505304
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1535669982
Short name T349
Test name
Test status
Simulation time 125596135 ps
CPU time 1.2 seconds
Started Aug 11 06:13:07 PM PDT 24
Finished Aug 11 06:13:08 PM PDT 24
Peak memory 196400 kb
Host smart-3473c6e7-f643-4f1a-a3b3-1933b98d2e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535669982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1535669982
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.459194000
Short name T660
Test name
Test status
Simulation time 34733295 ps
CPU time 0.89 seconds
Started Aug 11 06:13:15 PM PDT 24
Finished Aug 11 06:13:16 PM PDT 24
Peak memory 196328 kb
Host smart-f4472e74-44a9-4c72-968b-10a963dac974
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459194000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.459194000
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1998410838
Short name T471
Test name
Test status
Simulation time 52356516851 ps
CPU time 151.17 seconds
Started Aug 11 06:13:20 PM PDT 24
Finished Aug 11 06:15:51 PM PDT 24
Peak memory 198696 kb
Host smart-2e3dec5b-1dc7-43b1-91d0-1756686b92d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998410838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1998410838
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.149067997
Short name T495
Test name
Test status
Simulation time 41344283246 ps
CPU time 1242.75 seconds
Started Aug 11 06:13:21 PM PDT 24
Finished Aug 11 06:34:04 PM PDT 24
Peak memory 198924 kb
Host smart-424b650c-3fd9-4ff4-81dc-0df2a32f58da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=149067997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.149067997
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2148676494
Short name T78
Test name
Test status
Simulation time 12250605 ps
CPU time 0.58 seconds
Started Aug 11 06:13:09 PM PDT 24
Finished Aug 11 06:13:10 PM PDT 24
Peak memory 195180 kb
Host smart-4d5eb6fd-5fd1-4c7d-acc9-e3e6be9a79b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148676494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2148676494
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1245047077
Short name T270
Test name
Test status
Simulation time 35937530 ps
CPU time 0.79 seconds
Started Aug 11 06:13:11 PM PDT 24
Finished Aug 11 06:13:11 PM PDT 24
Peak memory 195908 kb
Host smart-6ac43f7a-a9c2-46f5-b7a5-53c71b03be88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245047077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1245047077
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3592366550
Short name T269
Test name
Test status
Simulation time 1135870233 ps
CPU time 17.56 seconds
Started Aug 11 06:13:08 PM PDT 24
Finished Aug 11 06:13:26 PM PDT 24
Peak memory 196104 kb
Host smart-fb1b0087-27e5-46fc-b88b-5733bb5eb3ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592366550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3592366550
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2315586203
Short name T299
Test name
Test status
Simulation time 308864078 ps
CPU time 0.99 seconds
Started Aug 11 06:13:09 PM PDT 24
Finished Aug 11 06:13:11 PM PDT 24
Peak memory 197224 kb
Host smart-d1a0942c-017c-43c3-813f-a4c64f916a10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315586203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2315586203
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1167529122
Short name T321
Test name
Test status
Simulation time 61972840 ps
CPU time 1.31 seconds
Started Aug 11 06:13:11 PM PDT 24
Finished Aug 11 06:13:12 PM PDT 24
Peak memory 197572 kb
Host smart-d2f415dc-4d9f-4f80-87f4-5d991bd84c1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167529122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1167529122
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3324390436
Short name T561
Test name
Test status
Simulation time 225378844 ps
CPU time 2.21 seconds
Started Aug 11 06:13:34 PM PDT 24
Finished Aug 11 06:13:36 PM PDT 24
Peak memory 198556 kb
Host smart-6a1ef777-2a31-413a-bb9e-61d3bf404001
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324390436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3324390436
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1278985284
Short name T508
Test name
Test status
Simulation time 42385184 ps
CPU time 1.41 seconds
Started Aug 11 06:13:21 PM PDT 24
Finished Aug 11 06:13:23 PM PDT 24
Peak memory 196252 kb
Host smart-1c3aa2f9-dc55-4a60-8fc5-d4deba197d28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278985284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1278985284
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2736173460
Short name T534
Test name
Test status
Simulation time 272596715 ps
CPU time 0.84 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:13:37 PM PDT 24
Peak memory 196968 kb
Host smart-e530ec4e-c74e-475b-98c8-8ebb39a4f6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736173460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2736173460
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2211948872
Short name T625
Test name
Test status
Simulation time 31267542 ps
CPU time 0.75 seconds
Started Aug 11 06:13:19 PM PDT 24
Finished Aug 11 06:13:20 PM PDT 24
Peak memory 196072 kb
Host smart-5bb9bdd5-df85-4718-9fe8-6ae9b249c7c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211948872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2211948872
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4252281902
Short name T669
Test name
Test status
Simulation time 1523540909 ps
CPU time 1.9 seconds
Started Aug 11 06:13:11 PM PDT 24
Finished Aug 11 06:13:13 PM PDT 24
Peak memory 198552 kb
Host smart-db5e7d18-cf47-4e6e-a302-5c6dfd6ccbc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252281902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4252281902
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1926510944
Short name T593
Test name
Test status
Simulation time 153792773 ps
CPU time 1.07 seconds
Started Aug 11 06:13:10 PM PDT 24
Finished Aug 11 06:13:11 PM PDT 24
Peak memory 196304 kb
Host smart-f65dc90f-f708-4256-a9d8-63d00e6f853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926510944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1926510944
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3635253472
Short name T657
Test name
Test status
Simulation time 72463618 ps
CPU time 0.89 seconds
Started Aug 11 06:13:15 PM PDT 24
Finished Aug 11 06:13:16 PM PDT 24
Peak memory 196372 kb
Host smart-688f2cf4-b9cc-419e-b748-6b041ac934b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635253472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3635253472
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1094957800
Short name T2
Test name
Test status
Simulation time 54742448631 ps
CPU time 144.83 seconds
Started Aug 11 06:13:21 PM PDT 24
Finished Aug 11 06:15:46 PM PDT 24
Peak memory 198728 kb
Host smart-266282a0-4f0d-46b0-b99f-19fefe439645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094957800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1094957800
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3096919971
Short name T562
Test name
Test status
Simulation time 201227598890 ps
CPU time 987.92 seconds
Started Aug 11 06:13:20 PM PDT 24
Finished Aug 11 06:29:48 PM PDT 24
Peak memory 198820 kb
Host smart-78809fa6-69ff-402b-98a3-2d92243ec99d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3096919971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3096919971
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1155214092
Short name T570
Test name
Test status
Simulation time 35820402 ps
CPU time 0.57 seconds
Started Aug 11 06:13:28 PM PDT 24
Finished Aug 11 06:13:29 PM PDT 24
Peak memory 195188 kb
Host smart-aabbd66e-d320-4456-8c98-575374a9cbeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155214092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1155214092
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.601145092
Short name T384
Test name
Test status
Simulation time 119505762 ps
CPU time 0.64 seconds
Started Aug 11 06:13:25 PM PDT 24
Finished Aug 11 06:13:26 PM PDT 24
Peak memory 194604 kb
Host smart-28ebfe1b-46d8-4c7b-b3b3-7f695c000cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601145092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.601145092
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2746577116
Short name T186
Test name
Test status
Simulation time 1024720146 ps
CPU time 14.72 seconds
Started Aug 11 06:13:16 PM PDT 24
Finished Aug 11 06:13:31 PM PDT 24
Peak memory 196120 kb
Host smart-ff347a46-d146-4ab5-a7ee-9dae2ad28375
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746577116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2746577116
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.109396152
Short name T173
Test name
Test status
Simulation time 190602350 ps
CPU time 0.82 seconds
Started Aug 11 06:13:22 PM PDT 24
Finished Aug 11 06:13:23 PM PDT 24
Peak memory 196984 kb
Host smart-fa2dee54-6ae1-4efe-9043-6990bbfe3171
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109396152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.109396152
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1243549200
Short name T479
Test name
Test status
Simulation time 95769936 ps
CPU time 0.79 seconds
Started Aug 11 06:13:21 PM PDT 24
Finished Aug 11 06:13:22 PM PDT 24
Peak memory 196784 kb
Host smart-3e539870-7630-462f-96b7-ed9f1f4f7842
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243549200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1243549200
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2744234194
Short name T659
Test name
Test status
Simulation time 88135553 ps
CPU time 1.16 seconds
Started Aug 11 06:13:24 PM PDT 24
Finished Aug 11 06:13:26 PM PDT 24
Peak memory 197804 kb
Host smart-847b0e0e-6ca4-45e4-b2f6-fb34a7af8c26
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744234194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2744234194
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2946714459
Short name T473
Test name
Test status
Simulation time 631748068 ps
CPU time 2.26 seconds
Started Aug 11 06:13:20 PM PDT 24
Finished Aug 11 06:13:23 PM PDT 24
Peak memory 197736 kb
Host smart-1295be06-3381-4177-bbb9-64c1f44fc60e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946714459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2946714459
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1439855074
Short name T613
Test name
Test status
Simulation time 28413781 ps
CPU time 0.81 seconds
Started Aug 11 06:13:12 PM PDT 24
Finished Aug 11 06:13:13 PM PDT 24
Peak memory 196632 kb
Host smart-4dbd0211-89ed-4864-9faf-cac40ee86fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439855074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1439855074
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1899882682
Short name T415
Test name
Test status
Simulation time 89216546 ps
CPU time 1.14 seconds
Started Aug 11 06:13:08 PM PDT 24
Finished Aug 11 06:13:09 PM PDT 24
Peak memory 197296 kb
Host smart-25f0036e-40c4-4efa-8e72-de2495cd546f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899882682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1899882682
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1559742593
Short name T5
Test name
Test status
Simulation time 197590294 ps
CPU time 2.65 seconds
Started Aug 11 06:13:17 PM PDT 24
Finished Aug 11 06:13:20 PM PDT 24
Peak memory 198600 kb
Host smart-8cce500a-1d9e-4714-a434-1f32b2cf724c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559742593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1559742593
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1737099020
Short name T449
Test name
Test status
Simulation time 93637083 ps
CPU time 1.44 seconds
Started Aug 11 06:13:11 PM PDT 24
Finished Aug 11 06:13:12 PM PDT 24
Peak memory 198500 kb
Host smart-e1be1af7-2b12-4f6a-8e1f-fa280a574cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737099020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1737099020
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.70792862
Short name T230
Test name
Test status
Simulation time 110241393 ps
CPU time 1.11 seconds
Started Aug 11 06:13:22 PM PDT 24
Finished Aug 11 06:13:23 PM PDT 24
Peak memory 196812 kb
Host smart-bcf80ca7-e3bb-4f77-837f-16db8d39d07d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70792862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.70792862
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1785152112
Short name T681
Test name
Test status
Simulation time 36950609361 ps
CPU time 158.63 seconds
Started Aug 11 06:13:20 PM PDT 24
Finished Aug 11 06:15:59 PM PDT 24
Peak memory 198760 kb
Host smart-90a95a9b-254e-4db6-bcc7-c269ad41148e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785152112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1785152112
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1484991650
Short name T472
Test name
Test status
Simulation time 12747546 ps
CPU time 0.59 seconds
Started Aug 11 06:13:24 PM PDT 24
Finished Aug 11 06:13:25 PM PDT 24
Peak memory 194436 kb
Host smart-856d86bb-4016-455f-b3b6-a6ba82326c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484991650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1484991650
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1341702041
Short name T292
Test name
Test status
Simulation time 136054272 ps
CPU time 0.71 seconds
Started Aug 11 06:13:23 PM PDT 24
Finished Aug 11 06:13:24 PM PDT 24
Peak memory 195384 kb
Host smart-0eaf5511-6396-4909-b8a6-21ad3a54f66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341702041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1341702041
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1347201347
Short name T80
Test name
Test status
Simulation time 10845740634 ps
CPU time 27.71 seconds
Started Aug 11 06:13:26 PM PDT 24
Finished Aug 11 06:13:54 PM PDT 24
Peak memory 197972 kb
Host smart-888a7e7a-ec8c-46cd-9d20-e668a5d44b53
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347201347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1347201347
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.633303904
Short name T547
Test name
Test status
Simulation time 128391737 ps
CPU time 0.97 seconds
Started Aug 11 06:13:29 PM PDT 24
Finished Aug 11 06:13:30 PM PDT 24
Peak memory 197772 kb
Host smart-fdacfda8-7745-4126-a55c-95cc6be2f76d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633303904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.633303904
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3466732956
Short name T117
Test name
Test status
Simulation time 456505568 ps
CPU time 1.26 seconds
Started Aug 11 06:13:15 PM PDT 24
Finished Aug 11 06:13:17 PM PDT 24
Peak memory 196372 kb
Host smart-531bd0f4-aa32-4147-ad86-08b7fb8dfbdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466732956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3466732956
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3080875088
Short name T556
Test name
Test status
Simulation time 169872968 ps
CPU time 3.38 seconds
Started Aug 11 06:13:40 PM PDT 24
Finished Aug 11 06:13:44 PM PDT 24
Peak memory 197044 kb
Host smart-69c2c203-f6ec-4c8b-82ea-498d8a2d39bf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080875088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3080875088
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2797016430
Short name T686
Test name
Test status
Simulation time 174113810 ps
CPU time 3.18 seconds
Started Aug 11 06:13:26 PM PDT 24
Finished Aug 11 06:13:29 PM PDT 24
Peak memory 197892 kb
Host smart-46f4d302-6b40-433e-bb11-fea1d54722f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797016430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2797016430
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1354334444
Short name T493
Test name
Test status
Simulation time 65955883 ps
CPU time 1.29 seconds
Started Aug 11 06:13:28 PM PDT 24
Finished Aug 11 06:13:29 PM PDT 24
Peak memory 197532 kb
Host smart-1a614bf4-ce34-4bb6-b6d3-6c4eaa491989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354334444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1354334444
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.419752667
Short name T411
Test name
Test status
Simulation time 60932865 ps
CPU time 1.08 seconds
Started Aug 11 06:13:31 PM PDT 24
Finished Aug 11 06:13:33 PM PDT 24
Peak memory 196460 kb
Host smart-a51a9e69-2950-4aca-b01f-efd621640c2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419752667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.419752667
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2070324980
Short name T31
Test name
Test status
Simulation time 373736787 ps
CPU time 2.32 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:13:32 PM PDT 24
Peak memory 198600 kb
Host smart-bd269007-5dde-48ca-a12e-d59ebca568af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070324980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2070324980
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.182642205
Short name T221
Test name
Test status
Simulation time 35310108 ps
CPU time 1.08 seconds
Started Aug 11 06:13:18 PM PDT 24
Finished Aug 11 06:13:19 PM PDT 24
Peak memory 197032 kb
Host smart-448eb475-c326-47a5-ada0-ac6b019adc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182642205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.182642205
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2164107586
Short name T62
Test name
Test status
Simulation time 68178373 ps
CPU time 1.08 seconds
Started Aug 11 06:13:23 PM PDT 24
Finished Aug 11 06:13:24 PM PDT 24
Peak memory 196352 kb
Host smart-cb8f185c-bc18-4619-8b09-62c656394477
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164107586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2164107586
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.136350746
Short name T1
Test name
Test status
Simulation time 5015317620 ps
CPU time 29.68 seconds
Started Aug 11 06:13:32 PM PDT 24
Finished Aug 11 06:14:02 PM PDT 24
Peak memory 198748 kb
Host smart-ea6128d4-0814-4bc3-b640-185e8991ffa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136350746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.136350746
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2123282988
Short name T111
Test name
Test status
Simulation time 549989737561 ps
CPU time 1556.82 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:39:27 PM PDT 24
Peak memory 198912 kb
Host smart-4182ac92-a4fc-46c9-ae4e-9415a9b27406
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2123282988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2123282988
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3144723105
Short name T548
Test name
Test status
Simulation time 20643799 ps
CPU time 0.59 seconds
Started Aug 11 06:13:23 PM PDT 24
Finished Aug 11 06:13:24 PM PDT 24
Peak memory 194432 kb
Host smart-1c865af7-3180-4a4b-8674-6406ca5cbcd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144723105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3144723105
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3381643223
Short name T311
Test name
Test status
Simulation time 42262284 ps
CPU time 0.59 seconds
Started Aug 11 06:13:20 PM PDT 24
Finished Aug 11 06:13:21 PM PDT 24
Peak memory 194508 kb
Host smart-5eb3209b-82a3-4321-86a7-203bc47ed4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381643223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3381643223
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.285334257
Short name T579
Test name
Test status
Simulation time 614180613 ps
CPU time 20.52 seconds
Started Aug 11 06:13:26 PM PDT 24
Finished Aug 11 06:13:47 PM PDT 24
Peak memory 197476 kb
Host smart-db29a67f-3836-4cd2-9730-a757d5c07da5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285334257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.285334257
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2035536483
Short name T358
Test name
Test status
Simulation time 63163480 ps
CPU time 0.69 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:13:31 PM PDT 24
Peak memory 195040 kb
Host smart-c4ec4f0d-79b6-41f7-9fce-b919a5845a38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035536483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2035536483
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1461900968
Short name T452
Test name
Test status
Simulation time 268697815 ps
CPU time 1.22 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:13:35 PM PDT 24
Peak memory 196388 kb
Host smart-e2049dc4-1026-42d4-b552-1847cdcc73a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461900968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1461900968
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3922493265
Short name T651
Test name
Test status
Simulation time 31608859 ps
CPU time 1.37 seconds
Started Aug 11 06:13:30 PM PDT 24
Finished Aug 11 06:13:32 PM PDT 24
Peak memory 198608 kb
Host smart-f516dbd0-36bb-4f52-b2ce-9e85c72dcb83
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922493265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3922493265
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2774804081
Short name T153
Test name
Test status
Simulation time 844421645 ps
CPU time 2.19 seconds
Started Aug 11 06:13:27 PM PDT 24
Finished Aug 11 06:13:29 PM PDT 24
Peak memory 196452 kb
Host smart-ddf1a78f-71fc-41e2-8081-ee9db9283d00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774804081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2774804081
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1301429996
Short name T559
Test name
Test status
Simulation time 77957591 ps
CPU time 1.03 seconds
Started Aug 11 06:13:36 PM PDT 24
Finished Aug 11 06:13:38 PM PDT 24
Peak memory 197244 kb
Host smart-c47ede03-adfb-43c9-820a-4597ed9ec94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301429996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1301429996
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3453086778
Short name T414
Test name
Test status
Simulation time 517354288 ps
CPU time 1.27 seconds
Started Aug 11 06:13:37 PM PDT 24
Finished Aug 11 06:13:38 PM PDT 24
Peak memory 197608 kb
Host smart-0b30ea07-7a62-4095-a959-d280296d922c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453086778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3453086778
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.4020994680
Short name T437
Test name
Test status
Simulation time 336816786 ps
CPU time 3.59 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:13:37 PM PDT 24
Peak memory 198512 kb
Host smart-02f8438d-86ff-453a-9201-485eb8bf1508
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020994680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.4020994680
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3229840702
Short name T536
Test name
Test status
Simulation time 138987386 ps
CPU time 1.09 seconds
Started Aug 11 06:13:21 PM PDT 24
Finished Aug 11 06:13:22 PM PDT 24
Peak memory 196108 kb
Host smart-10c92384-1fc3-4f40-9afe-f331d598c526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229840702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3229840702
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1438173709
Short name T362
Test name
Test status
Simulation time 106221849 ps
CPU time 0.92 seconds
Started Aug 11 06:13:28 PM PDT 24
Finished Aug 11 06:13:30 PM PDT 24
Peak memory 196752 kb
Host smart-90510c88-f56f-4d7d-baab-edf715b6697e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438173709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1438173709
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1630036581
Short name T319
Test name
Test status
Simulation time 11417593111 ps
CPU time 78.72 seconds
Started Aug 11 06:13:21 PM PDT 24
Finished Aug 11 06:14:40 PM PDT 24
Peak memory 198752 kb
Host smart-c6eea813-a93b-48b2-a12e-ac8650004fc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630036581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1630036581
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.4215862091
Short name T39
Test name
Test status
Simulation time 45075580174 ps
CPU time 1170.56 seconds
Started Aug 11 06:13:33 PM PDT 24
Finished Aug 11 06:33:04 PM PDT 24
Peak memory 198952 kb
Host smart-e88d3b83-914a-4bb8-9b71-910b2841a9fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4215862091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.4215862091
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1937177797
Short name T538
Test name
Test status
Simulation time 12872620 ps
CPU time 0.63 seconds
Started Aug 11 06:12:02 PM PDT 24
Finished Aug 11 06:12:02 PM PDT 24
Peak memory 193652 kb
Host smart-16d69edf-68d3-40ad-8618-9dabcd1c7a41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937177797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1937177797
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3904294769
Short name T544
Test name
Test status
Simulation time 33612649 ps
CPU time 0.77 seconds
Started Aug 11 06:11:53 PM PDT 24
Finished Aug 11 06:11:54 PM PDT 24
Peak memory 195660 kb
Host smart-37083f2b-66a6-44ae-bdd5-3ff21aeb395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904294769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3904294769
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2314381532
Short name T478
Test name
Test status
Simulation time 285755411 ps
CPU time 8.07 seconds
Started Aug 11 06:11:46 PM PDT 24
Finished Aug 11 06:11:54 PM PDT 24
Peak memory 197736 kb
Host smart-7587fbdf-7888-46c1-bef1-cdd06a690ee2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314381532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2314381532
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3517664135
Short name T518
Test name
Test status
Simulation time 95274369 ps
CPU time 0.77 seconds
Started Aug 11 06:11:50 PM PDT 24
Finished Aug 11 06:11:51 PM PDT 24
Peak memory 197176 kb
Host smart-6a1cea35-d678-40a9-bb16-da9f0ef5c6d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517664135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3517664135
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3393417764
Short name T132
Test name
Test status
Simulation time 64000780 ps
CPU time 0.89 seconds
Started Aug 11 06:11:35 PM PDT 24
Finished Aug 11 06:11:36 PM PDT 24
Peak memory 196436 kb
Host smart-4be148cf-b265-4da7-8346-f75a63d53b78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393417764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3393417764
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2385348490
Short name T372
Test name
Test status
Simulation time 57331494 ps
CPU time 1.24 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 198732 kb
Host smart-b3454587-1654-46c3-a058-df42ae038c33
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385348490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2385348490
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2594764611
Short name T689
Test name
Test status
Simulation time 120499884 ps
CPU time 2.72 seconds
Started Aug 11 06:11:43 PM PDT 24
Finished Aug 11 06:11:46 PM PDT 24
Peak memory 197864 kb
Host smart-780e053d-b9ba-41aa-87e8-938c58319c1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594764611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2594764611
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.356434809
Short name T364
Test name
Test status
Simulation time 120077613 ps
CPU time 1.07 seconds
Started Aug 11 06:11:45 PM PDT 24
Finished Aug 11 06:11:46 PM PDT 24
Peak memory 196396 kb
Host smart-2dca7984-cba1-47ad-ad37-c0f81a3706f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356434809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.356434809
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.4216109592
Short name T273
Test name
Test status
Simulation time 49754249 ps
CPU time 1.04 seconds
Started Aug 11 06:11:56 PM PDT 24
Finished Aug 11 06:11:57 PM PDT 24
Peak memory 196588 kb
Host smart-7e7f0cb1-9eeb-44d1-b828-a2e0be5beaf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216109592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.4216109592
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2094603931
Short name T359
Test name
Test status
Simulation time 385202147 ps
CPU time 4.01 seconds
Started Aug 11 06:11:52 PM PDT 24
Finished Aug 11 06:11:57 PM PDT 24
Peak memory 198600 kb
Host smart-646d2900-9c8a-4d7e-8dcd-ba4a5f4a4251
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094603931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2094603931
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3128073718
Short name T338
Test name
Test status
Simulation time 48172191 ps
CPU time 1.05 seconds
Started Aug 11 06:11:40 PM PDT 24
Finished Aug 11 06:11:41 PM PDT 24
Peak memory 197088 kb
Host smart-7d0971cd-1fa9-4218-bbaf-30ef74be9668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128073718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3128073718
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1002155312
Short name T140
Test name
Test status
Simulation time 108331461 ps
CPU time 0.8 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:11:49 PM PDT 24
Peak memory 196492 kb
Host smart-0db64bc7-1e54-4b3c-9ab9-d4277bf1b762
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002155312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1002155312
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.154259143
Short name T32
Test name
Test status
Simulation time 63655496213 ps
CPU time 232.63 seconds
Started Aug 11 06:11:47 PM PDT 24
Finished Aug 11 06:15:40 PM PDT 24
Peak memory 198740 kb
Host smart-9a6dd8be-aa87-40fa-bb1a-65c6e290a234
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154259143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.154259143
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2593812240
Short name T610
Test name
Test status
Simulation time 35453240 ps
CPU time 0.59 seconds
Started Aug 11 06:11:51 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 195172 kb
Host smart-1ac5cd4b-1b4f-4116-b9b1-57739b6ef28d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593812240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2593812240
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.780547726
Short name T423
Test name
Test status
Simulation time 60006060 ps
CPU time 0.59 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 194368 kb
Host smart-26d517b3-2ad7-4d81-bb73-fdf316f12726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780547726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.780547726
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3989869542
Short name T149
Test name
Test status
Simulation time 443095638 ps
CPU time 6.15 seconds
Started Aug 11 06:11:45 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 196732 kb
Host smart-573ccf04-46ba-44bf-9427-c34618633c96
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989869542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3989869542
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2853444416
Short name T22
Test name
Test status
Simulation time 336561734 ps
CPU time 0.87 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:11:49 PM PDT 24
Peak memory 197456 kb
Host smart-8db30f8a-352e-43b0-9317-3b0330707652
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853444416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2853444416
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3657186355
Short name T170
Test name
Test status
Simulation time 51557046 ps
CPU time 1.22 seconds
Started Aug 11 06:11:53 PM PDT 24
Finished Aug 11 06:11:55 PM PDT 24
Peak memory 197696 kb
Host smart-736d40f7-24ae-419b-af00-8fff83dfc736
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657186355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3657186355
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2966613298
Short name T565
Test name
Test status
Simulation time 283367782 ps
CPU time 1.57 seconds
Started Aug 11 06:11:46 PM PDT 24
Finished Aug 11 06:11:48 PM PDT 24
Peak memory 197212 kb
Host smart-3e8dac37-a36b-4d61-9ef3-ba82a076ba05
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966613298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2966613298
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3350435493
Short name T609
Test name
Test status
Simulation time 331702573 ps
CPU time 1.99 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:11:59 PM PDT 24
Peak memory 196768 kb
Host smart-9a4ebda0-e62e-4a99-a472-ddb8ccd5af01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350435493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3350435493
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3274659431
Short name T568
Test name
Test status
Simulation time 59794362 ps
CPU time 1.28 seconds
Started Aug 11 06:11:45 PM PDT 24
Finished Aug 11 06:11:47 PM PDT 24
Peak memory 197540 kb
Host smart-14b1ca3e-6f85-4714-8256-123f73869d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274659431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3274659431
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.4124249166
Short name T82
Test name
Test status
Simulation time 24848860 ps
CPU time 1.01 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:11:49 PM PDT 24
Peak memory 196428 kb
Host smart-b229e6d3-106e-4f75-9d1f-60bd19c832af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124249166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.4124249166
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.806653365
Short name T692
Test name
Test status
Simulation time 774956917 ps
CPU time 2.4 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 198588 kb
Host smart-a2d66616-09a1-4c67-8fa6-28948fc9af33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806653365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.806653365
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.187228402
Short name T537
Test name
Test status
Simulation time 176753730 ps
CPU time 1.08 seconds
Started Aug 11 06:11:52 PM PDT 24
Finished Aug 11 06:11:53 PM PDT 24
Peak memory 196096 kb
Host smart-c9217182-00d8-473a-aeb6-328bad4a925c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187228402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.187228402
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1265144983
Short name T301
Test name
Test status
Simulation time 104899002 ps
CPU time 1.39 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:11:59 PM PDT 24
Peak memory 197292 kb
Host smart-bc9759a4-d677-4367-a49d-188fe332b489
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265144983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1265144983
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1658472863
Short name T304
Test name
Test status
Simulation time 51286071872 ps
CPU time 133.84 seconds
Started Aug 11 06:11:47 PM PDT 24
Finished Aug 11 06:14:01 PM PDT 24
Peak memory 198796 kb
Host smart-385f0b70-cf29-4846-a944-0b8f5d9e4a3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658472863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1658472863
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3620853362
Short name T71
Test name
Test status
Simulation time 1113577314975 ps
CPU time 1759.9 seconds
Started Aug 11 06:11:52 PM PDT 24
Finished Aug 11 06:41:12 PM PDT 24
Peak memory 207104 kb
Host smart-c7e2b852-dc0f-44ca-a980-8aa5f6c71cae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3620853362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3620853362
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3831503208
Short name T695
Test name
Test status
Simulation time 21749194 ps
CPU time 0.56 seconds
Started Aug 11 06:11:53 PM PDT 24
Finished Aug 11 06:11:54 PM PDT 24
Peak memory 194436 kb
Host smart-03ec7e2e-1fad-408a-919d-2f3a3effb138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831503208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3831503208
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3814615338
Short name T275
Test name
Test status
Simulation time 80418144 ps
CPU time 0.65 seconds
Started Aug 11 06:11:47 PM PDT 24
Finished Aug 11 06:11:48 PM PDT 24
Peak memory 194560 kb
Host smart-61ab6a93-3ea4-4ca9-bd25-e72a8b6406f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814615338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3814615338
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3364770684
Short name T639
Test name
Test status
Simulation time 2139101685 ps
CPU time 6.57 seconds
Started Aug 11 06:11:41 PM PDT 24
Finished Aug 11 06:11:48 PM PDT 24
Peak memory 197348 kb
Host smart-dc85ff29-b5fb-496e-b8d8-699aa180565b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364770684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3364770684
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1044926542
Short name T357
Test name
Test status
Simulation time 57359385 ps
CPU time 0.86 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 197104 kb
Host smart-cc917c14-3b22-4e1e-99cf-db714afd7678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044926542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1044926542
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.942970524
Short name T640
Test name
Test status
Simulation time 331048672 ps
CPU time 1.31 seconds
Started Aug 11 06:11:44 PM PDT 24
Finished Aug 11 06:11:46 PM PDT 24
Peak memory 196368 kb
Host smart-d8e5286b-bff3-4d15-989d-9daf9a6afc85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942970524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.942970524
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3280615942
Short name T205
Test name
Test status
Simulation time 210593871 ps
CPU time 2.16 seconds
Started Aug 11 06:11:42 PM PDT 24
Finished Aug 11 06:11:45 PM PDT 24
Peak memory 198664 kb
Host smart-1fd58d9b-f955-4e6b-a6dd-b06ad6e81b13
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280615942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3280615942
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3456710455
Short name T271
Test name
Test status
Simulation time 101292990 ps
CPU time 1.76 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:11:59 PM PDT 24
Peak memory 196356 kb
Host smart-ac74fc1b-3353-4c78-bc9f-0d30d68b8939
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456710455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3456710455
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1028499134
Short name T395
Test name
Test status
Simulation time 100996087 ps
CPU time 1.03 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:55 PM PDT 24
Peak memory 196368 kb
Host smart-a03dce89-77a0-40dd-b0b2-bfe5de303fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028499134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1028499134
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2059324760
Short name T678
Test name
Test status
Simulation time 27082515 ps
CPU time 1.01 seconds
Started Aug 11 06:11:50 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 197168 kb
Host smart-33438cc5-8e71-471e-a0b0-e3729fd06b9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059324760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2059324760
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2336292532
Short name T682
Test name
Test status
Simulation time 141630910 ps
CPU time 4.67 seconds
Started Aug 11 06:11:47 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 198416 kb
Host smart-47cade95-27c5-4a65-8631-6cc95c22ac82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336292532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2336292532
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3306895948
Short name T216
Test name
Test status
Simulation time 133173101 ps
CPU time 1.15 seconds
Started Aug 11 06:11:55 PM PDT 24
Finished Aug 11 06:11:56 PM PDT 24
Peak memory 196084 kb
Host smart-c5964132-327e-4c78-93bf-677f8c1f73eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306895948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3306895948
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3205239319
Short name T227
Test name
Test status
Simulation time 266076129 ps
CPU time 1.01 seconds
Started Aug 11 06:11:52 PM PDT 24
Finished Aug 11 06:11:53 PM PDT 24
Peak memory 196116 kb
Host smart-7e0cf043-68af-42f4-86c8-50cdd7c9bf33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205239319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3205239319
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3098856929
Short name T482
Test name
Test status
Simulation time 5222994724 ps
CPU time 136.78 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:14:05 PM PDT 24
Peak memory 198704 kb
Host smart-4a3fd32d-923e-4238-bff7-89c3022df349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098856929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3098856929
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.529802382
Short name T378
Test name
Test status
Simulation time 40932661 ps
CPU time 0.57 seconds
Started Aug 11 06:11:50 PM PDT 24
Finished Aug 11 06:11:51 PM PDT 24
Peak memory 195144 kb
Host smart-69a24d06-492e-4f5c-bf66-ea3f8eac49e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529802382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.529802382
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3827163382
Short name T476
Test name
Test status
Simulation time 94216207 ps
CPU time 0.64 seconds
Started Aug 11 06:11:45 PM PDT 24
Finished Aug 11 06:11:45 PM PDT 24
Peak memory 195284 kb
Host smart-3d7c6568-0a47-41d1-b2df-33868d5e5ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827163382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3827163382
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.87147489
Short name T673
Test name
Test status
Simulation time 230955062 ps
CPU time 5.05 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:11:53 PM PDT 24
Peak memory 196160 kb
Host smart-30fedd03-c09d-4f9a-8ece-62a11b896120
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87147489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress.87147489
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3104763584
Short name T157
Test name
Test status
Simulation time 649579674 ps
CPU time 0.87 seconds
Started Aug 11 06:11:40 PM PDT 24
Finished Aug 11 06:11:42 PM PDT 24
Peak memory 197612 kb
Host smart-f5ccca57-a0b3-41a5-9721-9738f0f35cdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104763584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3104763584
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2365077275
Short name T680
Test name
Test status
Simulation time 20279692 ps
CPU time 0.75 seconds
Started Aug 11 06:11:51 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 196592 kb
Host smart-5bfb1034-7cfb-4a64-bae8-f17076b033f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365077275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2365077275
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2257512553
Short name T623
Test name
Test status
Simulation time 122092277 ps
CPU time 2.61 seconds
Started Aug 11 06:11:41 PM PDT 24
Finished Aug 11 06:11:44 PM PDT 24
Peak memory 198684 kb
Host smart-50b98db9-4568-4428-be56-3bbe7f7e9dd4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257512553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2257512553
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2282201471
Short name T670
Test name
Test status
Simulation time 52413383 ps
CPU time 1.68 seconds
Started Aug 11 06:11:51 PM PDT 24
Finished Aug 11 06:11:53 PM PDT 24
Peak memory 197376 kb
Host smart-bdfe9b86-e488-472c-9238-1292638649e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282201471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2282201471
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3584471557
Short name T502
Test name
Test status
Simulation time 36452407 ps
CPU time 0.89 seconds
Started Aug 11 06:11:53 PM PDT 24
Finished Aug 11 06:11:54 PM PDT 24
Peak memory 196336 kb
Host smart-2099da93-d905-440b-8fbe-d99ecb4efa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584471557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3584471557
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3148398214
Short name T367
Test name
Test status
Simulation time 28523667 ps
CPU time 0.68 seconds
Started Aug 11 06:11:42 PM PDT 24
Finished Aug 11 06:11:43 PM PDT 24
Peak memory 196672 kb
Host smart-bc66dadd-adf6-4374-ae2b-afadfd6f0b03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148398214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3148398214
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3617585962
Short name T307
Test name
Test status
Simulation time 3172983476 ps
CPU time 6.67 seconds
Started Aug 11 06:11:46 PM PDT 24
Finished Aug 11 06:11:53 PM PDT 24
Peak memory 198720 kb
Host smart-1534d6fc-3ba9-4791-b392-7e431ea1ba31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617585962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3617585962
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3451777559
Short name T231
Test name
Test status
Simulation time 55367787 ps
CPU time 0.86 seconds
Started Aug 11 06:11:51 PM PDT 24
Finished Aug 11 06:11:52 PM PDT 24
Peak memory 195796 kb
Host smart-31e28bc9-19ee-4d4a-be1b-cc324412d32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451777559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3451777559
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1509872737
Short name T387
Test name
Test status
Simulation time 40307475 ps
CPU time 1.03 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 195804 kb
Host smart-9452cfd7-0d70-4673-b456-e32a6e52c40e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509872737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1509872737
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.704943733
Short name T3
Test name
Test status
Simulation time 144487384861 ps
CPU time 149.95 seconds
Started Aug 11 06:12:00 PM PDT 24
Finished Aug 11 06:14:30 PM PDT 24
Peak memory 198720 kb
Host smart-d53fc1c9-3526-454f-92b6-0a5d4ef76986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704943733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.704943733
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.4138650285
Short name T72
Test name
Test status
Simulation time 107052775340 ps
CPU time 391.81 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:18:20 PM PDT 24
Peak memory 198904 kb
Host smart-0408ff67-0960-4abc-9e6d-8c52001357d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4138650285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.4138650285
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3897699694
Short name T443
Test name
Test status
Simulation time 26984039 ps
CPU time 0.58 seconds
Started Aug 11 06:11:47 PM PDT 24
Finished Aug 11 06:11:48 PM PDT 24
Peak memory 196216 kb
Host smart-641738b1-7439-4ba9-8b39-6c6c15597baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897699694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3897699694
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1346231222
Short name T303
Test name
Test status
Simulation time 22394507 ps
CPU time 0.74 seconds
Started Aug 11 06:12:10 PM PDT 24
Finished Aug 11 06:12:16 PM PDT 24
Peak memory 194748 kb
Host smart-d38259e6-82d7-4a70-a20d-1bd6f95d2d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346231222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1346231222
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2315572536
Short name T416
Test name
Test status
Simulation time 1494392644 ps
CPU time 21.06 seconds
Started Aug 11 06:11:53 PM PDT 24
Finished Aug 11 06:12:15 PM PDT 24
Peak memory 197480 kb
Host smart-79e45e67-9df7-4dcf-b72a-4efc1331afc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315572536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2315572536
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1935651981
Short name T535
Test name
Test status
Simulation time 49931583 ps
CPU time 0.79 seconds
Started Aug 11 06:12:01 PM PDT 24
Finished Aug 11 06:12:02 PM PDT 24
Peak memory 196484 kb
Host smart-91d323a9-8a79-49aa-bbe8-c30c22973b66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935651981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1935651981
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3537200844
Short name T654
Test name
Test status
Simulation time 57705379 ps
CPU time 0.95 seconds
Started Aug 11 06:11:57 PM PDT 24
Finished Aug 11 06:11:58 PM PDT 24
Peak memory 196584 kb
Host smart-15c10b55-bf28-4e6c-b564-be62d64e5d88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537200844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3537200844
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3253975104
Short name T75
Test name
Test status
Simulation time 64790114 ps
CPU time 2.49 seconds
Started Aug 11 06:11:45 PM PDT 24
Finished Aug 11 06:11:47 PM PDT 24
Peak memory 198676 kb
Host smart-6567ad23-2eb9-4791-8b8e-56a90ef8e109
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253975104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3253975104
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2529383664
Short name T394
Test name
Test status
Simulation time 393908315 ps
CPU time 2.73 seconds
Started Aug 11 06:11:59 PM PDT 24
Finished Aug 11 06:12:02 PM PDT 24
Peak memory 197808 kb
Host smart-0cb64b48-896a-4349-bddf-92f500b83829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529383664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2529383664
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1359479947
Short name T454
Test name
Test status
Simulation time 196860604 ps
CPU time 1.21 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 197544 kb
Host smart-269c6ce2-3a8e-4539-b874-f5d182387f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359479947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1359479947
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1056007335
Short name T589
Test name
Test status
Simulation time 57819674 ps
CPU time 0.87 seconds
Started Aug 11 06:11:48 PM PDT 24
Finished Aug 11 06:11:49 PM PDT 24
Peak memory 197972 kb
Host smart-19f089a4-6e78-425f-9b84-1df4d288a9ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056007335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1056007335
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3554039125
Short name T602
Test name
Test status
Simulation time 2432606156 ps
CPU time 4.15 seconds
Started Aug 11 06:11:55 PM PDT 24
Finished Aug 11 06:11:59 PM PDT 24
Peak memory 198704 kb
Host smart-2eedd070-a320-4c44-9508-c3cb492c5510
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554039125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3554039125
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1077253007
Short name T184
Test name
Test status
Simulation time 59542730 ps
CPU time 1.1 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:11:50 PM PDT 24
Peak memory 197124 kb
Host smart-4ef75bfb-7094-4ba6-a7c5-1e836ba93a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077253007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1077253007
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1304947218
Short name T542
Test name
Test status
Simulation time 85551118 ps
CPU time 1.1 seconds
Started Aug 11 06:11:55 PM PDT 24
Finished Aug 11 06:11:57 PM PDT 24
Peak memory 196256 kb
Host smart-0ea6cc0a-b9be-495d-b436-642f640d0ebe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304947218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1304947218
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1979773569
Short name T519
Test name
Test status
Simulation time 34458948884 ps
CPU time 105.18 seconds
Started Aug 11 06:11:49 PM PDT 24
Finished Aug 11 06:13:34 PM PDT 24
Peak memory 198776 kb
Host smart-84737461-0e2b-4bd8-a22d-279c2438438c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979773569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1979773569
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2399831045
Short name T346
Test name
Test status
Simulation time 111755436027 ps
CPU time 815.22 seconds
Started Aug 11 06:11:58 PM PDT 24
Finished Aug 11 06:25:34 PM PDT 24
Peak memory 198924 kb
Host smart-aa886123-84d7-4ee6-ae23-8838842d64bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2399831045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2399831045
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.359454991
Short name T865
Test name
Test status
Simulation time 239421936 ps
CPU time 1.1 seconds
Started Aug 11 07:00:32 PM PDT 24
Finished Aug 11 07:00:33 PM PDT 24
Peak memory 196452 kb
Host smart-c4053257-e367-4503-928b-2dc05bcb0f47
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=359454991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.359454991
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.302943577
Short name T869
Test name
Test status
Simulation time 260352989 ps
CPU time 1.11 seconds
Started Aug 11 07:00:37 PM PDT 24
Finished Aug 11 07:00:39 PM PDT 24
Peak memory 196688 kb
Host smart-728e339d-4e73-4d8a-a9b3-5795cb1a6e64
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302943577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.302943577
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3807626356
Short name T913
Test name
Test status
Simulation time 53703115 ps
CPU time 1.38 seconds
Started Aug 11 07:00:28 PM PDT 24
Finished Aug 11 07:00:30 PM PDT 24
Peak memory 196700 kb
Host smart-d9a98a8b-a329-4b96-a20f-367bf35332d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3807626356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3807626356
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3907102876
Short name T896
Test name
Test status
Simulation time 70401943 ps
CPU time 1.03 seconds
Started Aug 11 07:00:30 PM PDT 24
Finished Aug 11 07:00:31 PM PDT 24
Peak memory 196760 kb
Host smart-f269b13c-c6c6-4e64-856d-f2bd663ae36d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907102876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3907102876
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3779925712
Short name T927
Test name
Test status
Simulation time 55776837 ps
CPU time 1.12 seconds
Started Aug 11 07:00:40 PM PDT 24
Finished Aug 11 07:00:41 PM PDT 24
Peak memory 196704 kb
Host smart-60b99d5c-d32d-4b0f-a1b6-95d9ddf2d58c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3779925712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3779925712
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4159026254
Short name T938
Test name
Test status
Simulation time 346934551 ps
CPU time 1.32 seconds
Started Aug 11 07:00:42 PM PDT 24
Finished Aug 11 07:00:43 PM PDT 24
Peak memory 196776 kb
Host smart-907fce89-63d9-497d-acb2-c91a3b77c8fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159026254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4159026254
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.596473910
Short name T923
Test name
Test status
Simulation time 104168572 ps
CPU time 1.08 seconds
Started Aug 11 07:00:42 PM PDT 24
Finished Aug 11 07:00:43 PM PDT 24
Peak memory 195840 kb
Host smart-0421a605-9c88-43c6-b2d5-7724c0fddba5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=596473910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.596473910
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3109759000
Short name T846
Test name
Test status
Simulation time 96143211 ps
CPU time 0.73 seconds
Started Aug 11 07:00:42 PM PDT 24
Finished Aug 11 07:00:43 PM PDT 24
Peak memory 196060 kb
Host smart-31e9a66b-0e49-43a1-825c-0b24b670b05c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109759000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3109759000
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.514549155
Short name T864
Test name
Test status
Simulation time 243983987 ps
CPU time 1.13 seconds
Started Aug 11 07:00:42 PM PDT 24
Finished Aug 11 07:00:43 PM PDT 24
Peak memory 196848 kb
Host smart-c144b0e9-2935-4c1c-8e73-ca211718b8db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=514549155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.514549155
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3913132187
Short name T930
Test name
Test status
Simulation time 29813257 ps
CPU time 0.8 seconds
Started Aug 11 07:00:41 PM PDT 24
Finished Aug 11 07:00:42 PM PDT 24
Peak memory 195452 kb
Host smart-05ce8693-1896-4530-ab44-913b75eefe9b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913132187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3913132187
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.220863308
Short name T872
Test name
Test status
Simulation time 45632128 ps
CPU time 1.12 seconds
Started Aug 11 07:00:42 PM PDT 24
Finished Aug 11 07:00:43 PM PDT 24
Peak memory 196492 kb
Host smart-204f033f-7868-49ba-9f23-6ff7bcce4c15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=220863308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.220863308
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2454440560
Short name T901
Test name
Test status
Simulation time 74508298 ps
CPU time 1.12 seconds
Started Aug 11 07:00:42 PM PDT 24
Finished Aug 11 07:00:43 PM PDT 24
Peak memory 195724 kb
Host smart-1886e847-6ed3-42aa-b807-500bdfdbef76
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454440560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2454440560
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.881491667
Short name T920
Test name
Test status
Simulation time 34381007 ps
CPU time 0.96 seconds
Started Aug 11 07:00:42 PM PDT 24
Finished Aug 11 07:00:43 PM PDT 24
Peak memory 196504 kb
Host smart-400b2692-2333-474d-ac57-6bc0a0823a86
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=881491667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.881491667
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1236405099
Short name T851
Test name
Test status
Simulation time 51245200 ps
CPU time 1.01 seconds
Started Aug 11 07:00:42 PM PDT 24
Finished Aug 11 07:00:43 PM PDT 24
Peak memory 197820 kb
Host smart-123c6297-6af9-4e6a-b0b4-2f023ccec2e1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236405099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1236405099
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2479688995
Short name T881
Test name
Test status
Simulation time 74920849 ps
CPU time 0.95 seconds
Started Aug 11 07:00:43 PM PDT 24
Finished Aug 11 07:00:44 PM PDT 24
Peak memory 197832 kb
Host smart-4733afcb-2cd3-4c14-b573-cd04b30f13b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2479688995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2479688995
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.61792267
Short name T862
Test name
Test status
Simulation time 37148710 ps
CPU time 0.86 seconds
Started Aug 11 07:00:43 PM PDT 24
Finished Aug 11 07:00:44 PM PDT 24
Peak memory 195380 kb
Host smart-f65648ab-413b-448e-923c-3ca9949dd79e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61792267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.61792267
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2793000060
Short name T917
Test name
Test status
Simulation time 337550253 ps
CPU time 1 seconds
Started Aug 11 07:00:47 PM PDT 24
Finished Aug 11 07:00:48 PM PDT 24
Peak memory 196704 kb
Host smart-6261277e-0025-4cd1-9ae3-cfa59280129e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2793000060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2793000060
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3368736580
Short name T888
Test name
Test status
Simulation time 124465712 ps
CPU time 0.81 seconds
Started Aug 11 07:00:47 PM PDT 24
Finished Aug 11 07:00:48 PM PDT 24
Peak memory 196068 kb
Host smart-1ca26532-897a-4619-8df8-c50ce8bdf82b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368736580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3368736580
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2635720867
Short name T922
Test name
Test status
Simulation time 1811849333 ps
CPU time 1.39 seconds
Started Aug 11 07:00:48 PM PDT 24
Finished Aug 11 07:00:50 PM PDT 24
Peak memory 196844 kb
Host smart-fd1d26d7-3eee-4932-be85-313a327c9015
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2635720867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2635720867
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1908307995
Short name T847
Test name
Test status
Simulation time 51192553 ps
CPU time 1.38 seconds
Started Aug 11 07:00:48 PM PDT 24
Finished Aug 11 07:00:50 PM PDT 24
Peak memory 197916 kb
Host smart-ae5a4d53-f30e-4038-8726-29cf189c06a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908307995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1908307995
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3825621407
Short name T878
Test name
Test status
Simulation time 57018802 ps
CPU time 1.01 seconds
Started Aug 11 07:00:49 PM PDT 24
Finished Aug 11 07:00:50 PM PDT 24
Peak memory 195840 kb
Host smart-ac7894ea-9e7b-46a7-bf45-78b4b5a40346
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3825621407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3825621407
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2204571624
Short name T880
Test name
Test status
Simulation time 124307630 ps
CPU time 1.31 seconds
Started Aug 11 07:00:46 PM PDT 24
Finished Aug 11 07:00:48 PM PDT 24
Peak memory 198244 kb
Host smart-b468de03-3158-4a0e-a545-ccae037cced3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204571624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2204571624
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.463387051
Short name T874
Test name
Test status
Simulation time 375847813 ps
CPU time 1.42 seconds
Started Aug 11 07:00:46 PM PDT 24
Finished Aug 11 07:00:48 PM PDT 24
Peak memory 198052 kb
Host smart-a27d9b63-3cf6-4b58-a9ca-88ebd4d37eeb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=463387051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.463387051
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2566295741
Short name T902
Test name
Test status
Simulation time 83018122 ps
CPU time 1.01 seconds
Started Aug 11 07:00:47 PM PDT 24
Finished Aug 11 07:00:48 PM PDT 24
Peak memory 198048 kb
Host smart-c638e1b3-1bef-4201-bd1a-83abcc549ed6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566295741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2566295741
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4160693128
Short name T856
Test name
Test status
Simulation time 215109071 ps
CPU time 1.19 seconds
Started Aug 11 07:00:33 PM PDT 24
Finished Aug 11 07:00:34 PM PDT 24
Peak memory 195948 kb
Host smart-c08b6346-333e-42f8-9f82-ba49495c9784
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4160693128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.4160693128
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2602913773
Short name T909
Test name
Test status
Simulation time 130031993 ps
CPU time 1.02 seconds
Started Aug 11 07:00:29 PM PDT 24
Finished Aug 11 07:00:30 PM PDT 24
Peak memory 196668 kb
Host smart-1ce505e2-1561-4a93-8760-75b553a59c67
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602913773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2602913773
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.919646049
Short name T894
Test name
Test status
Simulation time 87098055 ps
CPU time 0.8 seconds
Started Aug 11 07:00:47 PM PDT 24
Finished Aug 11 07:00:48 PM PDT 24
Peak memory 196044 kb
Host smart-0719187d-acec-4b21-a88c-5c2eb73f5876
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=919646049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.919646049
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1976284217
Short name T903
Test name
Test status
Simulation time 617333407 ps
CPU time 0.89 seconds
Started Aug 11 07:00:47 PM PDT 24
Finished Aug 11 07:00:48 PM PDT 24
Peak memory 196492 kb
Host smart-f4362308-2de4-4564-a840-6cdfd0a8fabd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976284217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1976284217
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.311484864
Short name T852
Test name
Test status
Simulation time 37318428 ps
CPU time 1.26 seconds
Started Aug 11 07:00:48 PM PDT 24
Finished Aug 11 07:00:49 PM PDT 24
Peak memory 197644 kb
Host smart-84a6258a-8e05-4951-82a2-0c13f78cdb21
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=311484864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.311484864
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2294834294
Short name T914
Test name
Test status
Simulation time 76632468 ps
CPU time 1.23 seconds
Started Aug 11 07:00:48 PM PDT 24
Finished Aug 11 07:00:49 PM PDT 24
Peak memory 196972 kb
Host smart-c64fb273-9a22-440b-935f-6c3f51601524
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294834294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2294834294
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2088542011
Short name T850
Test name
Test status
Simulation time 169062583 ps
CPU time 1.35 seconds
Started Aug 11 07:00:49 PM PDT 24
Finished Aug 11 07:00:50 PM PDT 24
Peak memory 198060 kb
Host smart-6ca0812b-3975-4ab6-832f-12fbbf656a5f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2088542011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2088542011
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3515871928
Short name T912
Test name
Test status
Simulation time 79181348 ps
CPU time 1.23 seconds
Started Aug 11 07:00:48 PM PDT 24
Finished Aug 11 07:00:49 PM PDT 24
Peak memory 196592 kb
Host smart-41a82bf7-63d3-493d-9e06-062f1b0c3b8b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515871928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3515871928
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3123574477
Short name T886
Test name
Test status
Simulation time 191939933 ps
CPU time 1.42 seconds
Started Aug 11 07:00:49 PM PDT 24
Finished Aug 11 07:00:50 PM PDT 24
Peak memory 198100 kb
Host smart-af792de6-2644-4a9f-bfb0-2df53e63f861
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3123574477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3123574477
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.945644907
Short name T882
Test name
Test status
Simulation time 33027232 ps
CPU time 0.85 seconds
Started Aug 11 07:00:46 PM PDT 24
Finished Aug 11 07:00:47 PM PDT 24
Peak memory 195428 kb
Host smart-73ed3bbc-0752-4e67-ad15-c9d7421b12a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945644907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.945644907
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.764299069
Short name T915
Test name
Test status
Simulation time 74795328 ps
CPU time 1.28 seconds
Started Aug 11 07:00:55 PM PDT 24
Finished Aug 11 07:00:56 PM PDT 24
Peak memory 196624 kb
Host smart-c8c80835-bb4b-4507-a6a2-bfc99854fde6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=764299069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.764299069
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3821739124
Short name T939
Test name
Test status
Simulation time 33492369 ps
CPU time 0.99 seconds
Started Aug 11 07:00:52 PM PDT 24
Finished Aug 11 07:00:53 PM PDT 24
Peak memory 195804 kb
Host smart-e98d5325-5b37-4768-b16c-144a478b4f5a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821739124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3821739124
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2149329424
Short name T906
Test name
Test status
Simulation time 174304032 ps
CPU time 1.31 seconds
Started Aug 11 07:00:53 PM PDT 24
Finished Aug 11 07:00:54 PM PDT 24
Peak memory 197044 kb
Host smart-61850383-eb63-4676-a88a-16c095af9ef9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2149329424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2149329424
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2314357215
Short name T904
Test name
Test status
Simulation time 96818390 ps
CPU time 1.04 seconds
Started Aug 11 07:00:54 PM PDT 24
Finished Aug 11 07:00:55 PM PDT 24
Peak memory 196536 kb
Host smart-85480907-c204-4b06-8e4b-2f529f0ebc2f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314357215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2314357215
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3596136910
Short name T871
Test name
Test status
Simulation time 93025685 ps
CPU time 0.86 seconds
Started Aug 11 07:00:52 PM PDT 24
Finished Aug 11 07:00:53 PM PDT 24
Peak memory 195388 kb
Host smart-3d56aba3-4f42-4812-94c7-86642f2a258c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3596136910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3596136910
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1763499969
Short name T860
Test name
Test status
Simulation time 267353378 ps
CPU time 1.3 seconds
Started Aug 11 07:00:54 PM PDT 24
Finished Aug 11 07:00:55 PM PDT 24
Peak memory 196916 kb
Host smart-3096d548-657c-4404-a8df-f49646557e8b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763499969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1763499969
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3023382564
Short name T879
Test name
Test status
Simulation time 106913471 ps
CPU time 1.05 seconds
Started Aug 11 07:00:53 PM PDT 24
Finished Aug 11 07:00:54 PM PDT 24
Peak memory 198044 kb
Host smart-be0b2cd8-3cc9-41dc-8556-20fb8145c091
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3023382564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3023382564
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3732544281
Short name T857
Test name
Test status
Simulation time 40641403 ps
CPU time 1.15 seconds
Started Aug 11 07:00:57 PM PDT 24
Finished Aug 11 07:00:58 PM PDT 24
Peak memory 195940 kb
Host smart-c1d1c819-3ba5-4666-a854-42cafb4524ad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732544281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3732544281
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2232998088
Short name T926
Test name
Test status
Simulation time 89500074 ps
CPU time 0.89 seconds
Started Aug 11 07:00:52 PM PDT 24
Finished Aug 11 07:00:53 PM PDT 24
Peak memory 197116 kb
Host smart-e71098de-e8cd-460e-bfe9-98aa8659f72c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2232998088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2232998088
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3745081197
Short name T858
Test name
Test status
Simulation time 43866520 ps
CPU time 1.09 seconds
Started Aug 11 07:00:53 PM PDT 24
Finished Aug 11 07:00:54 PM PDT 24
Peak memory 196576 kb
Host smart-98abe057-1d3d-4ae6-b2b1-30c2e2a0e92b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745081197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3745081197
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3928065646
Short name T940
Test name
Test status
Simulation time 65590242 ps
CPU time 1.29 seconds
Started Aug 11 07:00:54 PM PDT 24
Finished Aug 11 07:00:55 PM PDT 24
Peak memory 197088 kb
Host smart-a4721fb3-92ff-4c49-9f2e-690830fe4ebe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3928065646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3928065646
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1992837924
Short name T854
Test name
Test status
Simulation time 170176817 ps
CPU time 0.96 seconds
Started Aug 11 07:00:53 PM PDT 24
Finished Aug 11 07:00:54 PM PDT 24
Peak memory 197320 kb
Host smart-3e31db60-317a-48a7-a958-9595ae5b741b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992837924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1992837924
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3628211566
Short name T863
Test name
Test status
Simulation time 180248931 ps
CPU time 1.03 seconds
Started Aug 11 07:00:30 PM PDT 24
Finished Aug 11 07:00:31 PM PDT 24
Peak memory 195780 kb
Host smart-7ac6f928-6acf-4a46-9a7b-2a6524a1ead5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3628211566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3628211566
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.291375494
Short name T889
Test name
Test status
Simulation time 43456817 ps
CPU time 1.15 seconds
Started Aug 11 07:00:29 PM PDT 24
Finished Aug 11 07:00:30 PM PDT 24
Peak memory 196660 kb
Host smart-9d2abd10-3384-45f4-a696-ffb2af9e1bd7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291375494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.291375494
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4267306350
Short name T907
Test name
Test status
Simulation time 149243283 ps
CPU time 1.12 seconds
Started Aug 11 07:00:55 PM PDT 24
Finished Aug 11 07:00:56 PM PDT 24
Peak memory 195964 kb
Host smart-fd37e5d1-cf8f-40f4-9b4e-340c159afbfa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4267306350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.4267306350
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3601102660
Short name T899
Test name
Test status
Simulation time 71110490 ps
CPU time 1.17 seconds
Started Aug 11 07:00:53 PM PDT 24
Finished Aug 11 07:00:54 PM PDT 24
Peak memory 196652 kb
Host smart-98508073-69a5-4594-a8e5-870c0eedfee1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601102660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3601102660
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1652970158
Short name T861
Test name
Test status
Simulation time 37137723 ps
CPU time 1.07 seconds
Started Aug 11 07:00:54 PM PDT 24
Finished Aug 11 07:00:55 PM PDT 24
Peak memory 195644 kb
Host smart-749460eb-9dc2-4621-866a-cf2490a0409a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1652970158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1652970158
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1378982981
Short name T935
Test name
Test status
Simulation time 31052991 ps
CPU time 0.87 seconds
Started Aug 11 07:00:53 PM PDT 24
Finished Aug 11 07:00:54 PM PDT 24
Peak memory 196228 kb
Host smart-b0db657a-e840-4234-a464-53e7a45ed70e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378982981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1378982981
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2980301900
Short name T924
Test name
Test status
Simulation time 37426161 ps
CPU time 0.75 seconds
Started Aug 11 07:00:55 PM PDT 24
Finished Aug 11 07:00:56 PM PDT 24
Peak memory 194980 kb
Host smart-686021d1-0caf-4791-9fba-7500f7ac22a7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2980301900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2980301900
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.348907060
Short name T928
Test name
Test status
Simulation time 25578619 ps
CPU time 0.85 seconds
Started Aug 11 07:00:59 PM PDT 24
Finished Aug 11 07:01:00 PM PDT 24
Peak memory 195608 kb
Host smart-e0b34070-6669-4f44-9404-9407358f12c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348907060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.348907060
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1968533415
Short name T933
Test name
Test status
Simulation time 290153459 ps
CPU time 1.02 seconds
Started Aug 11 07:01:00 PM PDT 24
Finished Aug 11 07:01:01 PM PDT 24
Peak memory 196516 kb
Host smart-3591359e-e6d1-44b4-8275-6ca99f482207
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1968533415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1968533415
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1060010262
Short name T883
Test name
Test status
Simulation time 31433168 ps
CPU time 1.11 seconds
Started Aug 11 07:01:00 PM PDT 24
Finished Aug 11 07:01:01 PM PDT 24
Peak memory 196528 kb
Host smart-847f7f2a-0b80-47a2-b40b-32dddac98c3f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060010262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1060010262
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3262356973
Short name T887
Test name
Test status
Simulation time 80653952 ps
CPU time 0.87 seconds
Started Aug 11 07:00:59 PM PDT 24
Finished Aug 11 07:01:00 PM PDT 24
Peak memory 195476 kb
Host smart-3fa9d4a1-7d27-4c88-9101-e42b5022eaba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3262356973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3262356973
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1420735827
Short name T843
Test name
Test status
Simulation time 107616701 ps
CPU time 0.97 seconds
Started Aug 11 07:00:58 PM PDT 24
Finished Aug 11 07:00:59 PM PDT 24
Peak memory 195624 kb
Host smart-0a068470-5e30-4daa-8abb-8061b7071aae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420735827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1420735827
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.668636017
Short name T849
Test name
Test status
Simulation time 117024700 ps
CPU time 0.97 seconds
Started Aug 11 07:01:00 PM PDT 24
Finished Aug 11 07:01:01 PM PDT 24
Peak memory 196652 kb
Host smart-75235a96-e78a-43fb-9524-9660d1bd609c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=668636017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.668636017
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3849351903
Short name T897
Test name
Test status
Simulation time 46234085 ps
CPU time 1.05 seconds
Started Aug 11 07:00:59 PM PDT 24
Finished Aug 11 07:01:00 PM PDT 24
Peak memory 197628 kb
Host smart-aa40bf8a-1833-4498-877b-831258cec874
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849351903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3849351903
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3379656158
Short name T845
Test name
Test status
Simulation time 234032278 ps
CPU time 1.14 seconds
Started Aug 11 07:01:00 PM PDT 24
Finished Aug 11 07:01:01 PM PDT 24
Peak memory 196672 kb
Host smart-a42ed580-9e25-442b-9da0-a5c010664e17
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3379656158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3379656158
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2489724149
Short name T929
Test name
Test status
Simulation time 183655927 ps
CPU time 1.23 seconds
Started Aug 11 07:00:59 PM PDT 24
Finished Aug 11 07:01:00 PM PDT 24
Peak memory 196624 kb
Host smart-231c4457-e6f0-4d37-a60e-a475cffd7eda
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489724149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2489724149
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.954187885
Short name T890
Test name
Test status
Simulation time 22298925 ps
CPU time 0.77 seconds
Started Aug 11 07:00:59 PM PDT 24
Finished Aug 11 07:00:59 PM PDT 24
Peak memory 196144 kb
Host smart-3a697027-30a9-4aed-af0a-79cac8b86ccd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=954187885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.954187885
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4187483116
Short name T911
Test name
Test status
Simulation time 148334257 ps
CPU time 1.44 seconds
Started Aug 11 07:00:59 PM PDT 24
Finished Aug 11 07:01:01 PM PDT 24
Peak memory 196692 kb
Host smart-472a1f85-8dab-4287-9560-7ec2c3bfb8fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187483116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4187483116
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3855111682
Short name T891
Test name
Test status
Simulation time 434450189 ps
CPU time 1.15 seconds
Started Aug 11 07:01:04 PM PDT 24
Finished Aug 11 07:01:06 PM PDT 24
Peak memory 198136 kb
Host smart-6c1316da-90da-4b50-9f41-f49fdbc65fa9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3855111682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3855111682
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3477042005
Short name T932
Test name
Test status
Simulation time 52001667 ps
CPU time 1.1 seconds
Started Aug 11 07:01:04 PM PDT 24
Finished Aug 11 07:01:05 PM PDT 24
Peak memory 196556 kb
Host smart-3bd24e9a-a9f9-4ae0-a274-4368f13f0c03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477042005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3477042005
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1886580040
Short name T873
Test name
Test status
Simulation time 613313032 ps
CPU time 1.21 seconds
Started Aug 11 07:01:06 PM PDT 24
Finished Aug 11 07:01:08 PM PDT 24
Peak memory 196556 kb
Host smart-05fc1e23-b81a-4c78-852d-5ae232ae8c8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1886580040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1886580040
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1625785691
Short name T921
Test name
Test status
Simulation time 294072261 ps
CPU time 1.08 seconds
Started Aug 11 07:01:08 PM PDT 24
Finished Aug 11 07:01:09 PM PDT 24
Peak memory 196636 kb
Host smart-fffc9ce0-833a-4a39-a5b3-315811e5232e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625785691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1625785691
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2979282810
Short name T916
Test name
Test status
Simulation time 166737458 ps
CPU time 0.85 seconds
Started Aug 11 07:00:34 PM PDT 24
Finished Aug 11 07:00:35 PM PDT 24
Peak memory 196216 kb
Host smart-75761551-7994-4839-a265-40853c948b46
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2979282810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2979282810
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.248621783
Short name T918
Test name
Test status
Simulation time 329152285 ps
CPU time 1.26 seconds
Started Aug 11 07:00:39 PM PDT 24
Finished Aug 11 07:00:41 PM PDT 24
Peak memory 196688 kb
Host smart-5dda3645-ff96-4d50-a425-31cdbd8562de
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248621783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.248621783
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3088259422
Short name T925
Test name
Test status
Simulation time 214598881 ps
CPU time 1.01 seconds
Started Aug 11 07:01:05 PM PDT 24
Finished Aug 11 07:01:06 PM PDT 24
Peak memory 196632 kb
Host smart-2ab97f58-cf34-4a01-baac-73e51cb7afbb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3088259422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3088259422
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2863717134
Short name T908
Test name
Test status
Simulation time 49323288 ps
CPU time 1.11 seconds
Started Aug 11 07:01:09 PM PDT 24
Finished Aug 11 07:01:10 PM PDT 24
Peak memory 196652 kb
Host smart-ce7d2a0f-6462-45ab-8978-49c37a1883df
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863717134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2863717134
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1037083339
Short name T875
Test name
Test status
Simulation time 52404723 ps
CPU time 0.85 seconds
Started Aug 11 07:01:05 PM PDT 24
Finished Aug 11 07:01:06 PM PDT 24
Peak memory 195380 kb
Host smart-fb21c5bc-05d1-4697-b2b4-0615f4efe2e0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1037083339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1037083339
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3636949583
Short name T844
Test name
Test status
Simulation time 521534420 ps
CPU time 1.06 seconds
Started Aug 11 07:01:04 PM PDT 24
Finished Aug 11 07:01:06 PM PDT 24
Peak memory 196448 kb
Host smart-29b017ec-81bb-4092-bc2d-bf7ad36e527a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636949583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3636949583
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3722486495
Short name T866
Test name
Test status
Simulation time 68764840 ps
CPU time 1.12 seconds
Started Aug 11 07:01:04 PM PDT 24
Finished Aug 11 07:01:06 PM PDT 24
Peak memory 198060 kb
Host smart-abc3f946-62c6-4892-ade6-93106bbe7838
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3722486495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3722486495
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4269070295
Short name T934
Test name
Test status
Simulation time 50035605 ps
CPU time 1.19 seconds
Started Aug 11 07:01:05 PM PDT 24
Finished Aug 11 07:01:06 PM PDT 24
Peak memory 197016 kb
Host smart-b0bda997-23fe-4ee5-93cc-f75e71e83f6d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269070295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4269070295
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1887953589
Short name T876
Test name
Test status
Simulation time 74677616 ps
CPU time 1.41 seconds
Started Aug 11 07:01:04 PM PDT 24
Finished Aug 11 07:01:06 PM PDT 24
Peak memory 196836 kb
Host smart-5126beb5-2f98-4cd1-ae3c-dc36b2f26727
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1887953589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1887953589
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2362129700
Short name T867
Test name
Test status
Simulation time 62158430 ps
CPU time 1.01 seconds
Started Aug 11 07:01:06 PM PDT 24
Finished Aug 11 07:01:07 PM PDT 24
Peak memory 195656 kb
Host smart-2498a16a-48ec-4755-ba59-2b122ba093c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362129700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2362129700
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3383498707
Short name T910
Test name
Test status
Simulation time 43262455 ps
CPU time 0.78 seconds
Started Aug 11 07:01:05 PM PDT 24
Finished Aug 11 07:01:06 PM PDT 24
Peak memory 195392 kb
Host smart-fadbcc96-3017-43d2-9bfb-387c5cd97683
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3383498707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3383498707
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1198813417
Short name T936
Test name
Test status
Simulation time 254909453 ps
CPU time 1.19 seconds
Started Aug 11 07:01:05 PM PDT 24
Finished Aug 11 07:01:07 PM PDT 24
Peak memory 198056 kb
Host smart-f8f40a8c-102e-43a2-aaf9-579557072689
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198813417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1198813417
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1458495914
Short name T892
Test name
Test status
Simulation time 24155279 ps
CPU time 0.9 seconds
Started Aug 11 07:01:04 PM PDT 24
Finished Aug 11 07:01:05 PM PDT 24
Peak memory 197308 kb
Host smart-c09e7cc8-e5f4-4fc6-8b61-49d2fc96e3e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1458495914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1458495914
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2694804022
Short name T848
Test name
Test status
Simulation time 1526518811 ps
CPU time 1.46 seconds
Started Aug 11 07:01:08 PM PDT 24
Finished Aug 11 07:01:09 PM PDT 24
Peak memory 197412 kb
Host smart-62dd2449-8e44-4863-b193-87411c5ffa81
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694804022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2694804022
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.863699789
Short name T853
Test name
Test status
Simulation time 690900456 ps
CPU time 1.28 seconds
Started Aug 11 07:01:09 PM PDT 24
Finished Aug 11 07:01:11 PM PDT 24
Peak memory 197076 kb
Host smart-28eb7eb4-0b62-4fff-b66f-544c5c0acc20
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=863699789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.863699789
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1842829957
Short name T931
Test name
Test status
Simulation time 98356258 ps
CPU time 0.93 seconds
Started Aug 11 07:01:08 PM PDT 24
Finished Aug 11 07:01:09 PM PDT 24
Peak memory 196352 kb
Host smart-e7ace698-161a-4d93-a1dd-85ce1cd5870c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842829957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1842829957
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3613865321
Short name T855
Test name
Test status
Simulation time 297639255 ps
CPU time 1.3 seconds
Started Aug 11 07:01:05 PM PDT 24
Finished Aug 11 07:01:06 PM PDT 24
Peak memory 196792 kb
Host smart-d585e8ce-ba81-4374-89d7-0cf2106b6150
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3613865321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3613865321
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3333279754
Short name T937
Test name
Test status
Simulation time 96492216 ps
CPU time 1.31 seconds
Started Aug 11 07:01:04 PM PDT 24
Finished Aug 11 07:01:06 PM PDT 24
Peak memory 197984 kb
Host smart-0f9c517e-91d1-4d86-a373-51db0d26b961
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333279754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3333279754
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1656684980
Short name T893
Test name
Test status
Simulation time 292709776 ps
CPU time 1.24 seconds
Started Aug 11 07:01:05 PM PDT 24
Finished Aug 11 07:01:07 PM PDT 24
Peak memory 198016 kb
Host smart-042a2815-4050-4bc3-946e-1dcdc2406704
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1656684980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1656684980
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2535205817
Short name T870
Test name
Test status
Simulation time 78423560 ps
CPU time 1.5 seconds
Started Aug 11 07:01:19 PM PDT 24
Finished Aug 11 07:01:21 PM PDT 24
Peak memory 196908 kb
Host smart-f7fde7de-d587-4417-a222-89af3d5e638c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535205817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2535205817
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2227084121
Short name T900
Test name
Test status
Simulation time 751173342 ps
CPU time 1.13 seconds
Started Aug 11 07:01:14 PM PDT 24
Finished Aug 11 07:01:15 PM PDT 24
Peak memory 196760 kb
Host smart-38b54a5e-6d88-45ca-ab43-0c8d21a19903
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2227084121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2227084121
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3125154312
Short name T898
Test name
Test status
Simulation time 29760570 ps
CPU time 0.74 seconds
Started Aug 11 07:01:11 PM PDT 24
Finished Aug 11 07:01:12 PM PDT 24
Peak memory 195372 kb
Host smart-2973ed2d-f463-48b1-86f9-715b6f1e8de4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125154312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3125154312
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2566738531
Short name T884
Test name
Test status
Simulation time 84558792 ps
CPU time 0.74 seconds
Started Aug 11 07:00:36 PM PDT 24
Finished Aug 11 07:00:36 PM PDT 24
Peak memory 195396 kb
Host smart-c534f707-46f9-4f22-bfba-23ff7f5d5517
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2566738531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2566738531
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.250089009
Short name T877
Test name
Test status
Simulation time 63788206 ps
CPU time 1.26 seconds
Started Aug 11 07:00:36 PM PDT 24
Finished Aug 11 07:00:37 PM PDT 24
Peak memory 196632 kb
Host smart-c4cb5b3a-edf3-45f5-bf10-00ac798a9688
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250089009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.250089009
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.89171344
Short name T905
Test name
Test status
Simulation time 248350068 ps
CPU time 1.17 seconds
Started Aug 11 07:00:35 PM PDT 24
Finished Aug 11 07:00:36 PM PDT 24
Peak memory 196776 kb
Host smart-8f5a7562-d759-4ce5-a4a0-6e96ba76900d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=89171344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.89171344
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2358216582
Short name T885
Test name
Test status
Simulation time 177895727 ps
CPU time 1.38 seconds
Started Aug 11 07:00:34 PM PDT 24
Finished Aug 11 07:00:36 PM PDT 24
Peak memory 196904 kb
Host smart-26d6c551-3606-43bb-8bc3-dc69fcd43112
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358216582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2358216582
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.995431124
Short name T942
Test name
Test status
Simulation time 45106489 ps
CPU time 0.99 seconds
Started Aug 11 07:00:35 PM PDT 24
Finished Aug 11 07:00:37 PM PDT 24
Peak memory 197884 kb
Host smart-af1947d9-4f2e-4c54-a3d1-0e4acf3f96f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=995431124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.995431124
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.845401881
Short name T859
Test name
Test status
Simulation time 40945147 ps
CPU time 1.11 seconds
Started Aug 11 07:00:59 PM PDT 24
Finished Aug 11 07:01:00 PM PDT 24
Peak memory 195820 kb
Host smart-730f2b1d-e0b1-4024-8532-d7f554ef8495
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845401881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.845401881
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.4073598518
Short name T919
Test name
Test status
Simulation time 28781137 ps
CPU time 0.9 seconds
Started Aug 11 07:00:39 PM PDT 24
Finished Aug 11 07:00:40 PM PDT 24
Peak memory 195276 kb
Host smart-77c1f86e-9d02-4fb0-9ae4-00f5f3e3f08b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4073598518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.4073598518
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4038786809
Short name T895
Test name
Test status
Simulation time 327064487 ps
CPU time 1.48 seconds
Started Aug 11 07:00:35 PM PDT 24
Finished Aug 11 07:00:37 PM PDT 24
Peak memory 198016 kb
Host smart-41e159a5-fdf4-47b9-befc-7128f1b552b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038786809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4038786809
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.415036842
Short name T868
Test name
Test status
Simulation time 220456861 ps
CPU time 1.15 seconds
Started Aug 11 07:00:40 PM PDT 24
Finished Aug 11 07:00:42 PM PDT 24
Peak memory 196636 kb
Host smart-f7185595-0f68-493f-a4de-fcdd5686a8c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=415036842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.415036842
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.159398075
Short name T941
Test name
Test status
Simulation time 35946940 ps
CPU time 0.96 seconds
Started Aug 11 07:00:39 PM PDT 24
Finished Aug 11 07:00:40 PM PDT 24
Peak memory 197992 kb
Host smart-5fd7b0ee-128b-4d3f-96fe-c43a740dc083
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159398075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.159398075
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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