Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1704044	1			T29	1		T30	1		T31	67
all_pins[1]	1704044	1			T29	1		T30	1		T31	67
all_pins[2]	1704044	1			T29	1		T30	1		T31	67
all_pins[3]	1704044	1			T29	1		T30	1		T31	67
all_pins[4]	1704044	1			T29	1		T30	1		T31	67
all_pins[5]	1704044	1			T29	1		T30	1		T31	67
all_pins[6]	1704044	1			T29	1		T30	1		T31	67
all_pins[7]	1704044	1			T29	1		T30	1		T31	67
all_pins[8]	1704044	1			T29	1		T30	1		T31	67
all_pins[9]	1704044	1			T29	1		T30	1		T31	67
all_pins[10]	1704044	1			T29	1		T30	1		T31	67
all_pins[11]	1704044	1			T29	1		T30	1		T31	67
all_pins[12]	1704044	1			T29	1		T30	1		T31	67
all_pins[13]	1704044	1			T29	1		T30	1		T31	67
all_pins[14]	1704044	1			T29	1		T30	1		T31	67
all_pins[15]	1704044	1			T29	1		T30	1		T31	67
all_pins[16]	1704044	1			T29	1		T30	1		T31	67
all_pins[17]	1704044	1			T29	1		T30	1		T31	67
all_pins[18]	1704044	1			T29	1		T30	1		T31	67
all_pins[19]	1704044	1			T29	1		T30	1		T31	67
all_pins[20]	1704044	1			T29	1		T30	1		T31	67
all_pins[21]	1704044	1			T29	1		T30	1		T31	67
all_pins[22]	1704044	1			T29	1		T30	1		T31	67
all_pins[23]	1704044	1			T29	1		T30	1		T31	67
all_pins[24]	1704044	1			T29	1		T30	1		T31	67
all_pins[25]	1704044	1			T29	1		T30	1		T31	67
all_pins[26]	1704044	1			T29	1		T30	1		T31	67
all_pins[27]	1704044	1			T29	1		T30	1		T31	67
all_pins[28]	1704044	1			T29	1		T30	1		T31	67
all_pins[29]	1704044	1			T29	1		T30	1		T31	67
all_pins[30]	1704044	1			T29	1		T30	1		T31	67
all_pins[31]	1704044	1			T29	1		T30	1		T31	67

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	33905843	1			T29	32		T30	32		T31	1099
values[0x1]	20623565	1			T31	1045		T1	183		T11	1635
transitions[0x0=>0x1]	12348361	1			T31	517		T1	143		T11	1039
transitions[0x1=>0x0]	12348220	1			T31	517		T1	143		T11	1039

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1062477	1			T29	1		T30	1		T31	40
all_pins[0]	values[0x1]	641567	1			T31	27		T11	78		T12	15
all_pins[0]	transitions[0x0=>0x1]	394870	1			T31	10		T11	57		T12	7
all_pins[0]	transitions[0x1=>0x0]	398161	1			T31	18		T1	15		T11	14
all_pins[1]	values[0x0]	1060609	1			T29	1		T30	1		T31	39
all_pins[1]	values[0x1]	643435	1			T31	28		T1	8		T11	37
all_pins[1]	transitions[0x0=>0x1]	385812	1			T31	15		T1	8		T11	33
all_pins[1]	transitions[0x1=>0x0]	383944	1			T31	14		T11	74		T12	10
all_pins[2]	values[0x0]	1057700	1			T29	1		T30	1		T31	35
all_pins[2]	values[0x1]	646344	1			T31	32		T11	62		T12	5
all_pins[2]	transitions[0x0=>0x1]	387851	1			T31	16		T11	43		T12	4
all_pins[2]	transitions[0x1=>0x0]	384942	1			T31	12		T1	8		T11	18
all_pins[3]	values[0x0]	1061919	1			T29	1		T30	1		T31	30
all_pins[3]	values[0x1]	642125	1			T31	37		T1	6		T11	61
all_pins[3]	transitions[0x0=>0x1]	383345	1			T31	18		T1	6		T11	36
all_pins[3]	transitions[0x1=>0x0]	387564	1			T31	13		T11	37		T12	5
all_pins[4]	values[0x0]	1056567	1			T29	1		T30	1		T31	32
all_pins[4]	values[0x1]	647477	1			T31	35		T1	7		T11	37
all_pins[4]	transitions[0x0=>0x1]	389486	1			T31	14		T1	5		T11	23
all_pins[4]	transitions[0x1=>0x0]	384134	1			T31	16		T1	4		T11	47
all_pins[5]	values[0x0]	1059357	1			T29	1		T30	1		T31	33
all_pins[5]	values[0x1]	644687	1			T31	34		T1	1		T11	40
all_pins[5]	transitions[0x0=>0x1]	385457	1			T31	15		T1	1		T11	26
all_pins[5]	transitions[0x1=>0x0]	388247	1			T31	16		T1	7		T11	23
all_pins[6]	values[0x0]	1056708	1			T29	1		T30	1		T31	27
all_pins[6]	values[0x1]	647336	1			T31	40		T1	2		T11	48
all_pins[6]	transitions[0x0=>0x1]	386908	1			T31	21		T1	2		T11	35
all_pins[6]	transitions[0x1=>0x0]	384259	1			T31	15		T1	1		T11	27
all_pins[7]	values[0x0]	1056033	1			T29	1		T30	1		T31	43
all_pins[7]	values[0x1]	648011	1			T31	24		T1	3		T11	74
all_pins[7]	transitions[0x0=>0x1]	387684	1			T31	8		T1	1		T11	48
all_pins[7]	transitions[0x1=>0x0]	387009	1			T31	24		T11	22		T12	19
all_pins[8]	values[0x0]	1059545	1			T29	1		T30	1		T31	34
all_pins[8]	values[0x1]	644499	1			T31	33		T1	1		T11	38
all_pins[8]	transitions[0x0=>0x1]	383848	1			T31	16		T1	1		T11	18
all_pins[8]	transitions[0x1=>0x0]	387360	1			T31	7		T1	3		T11	54
all_pins[9]	values[0x0]	1061350	1			T29	1		T30	1		T31	34
all_pins[9]	values[0x1]	642694	1			T31	33		T1	4		T11	59
all_pins[9]	transitions[0x0=>0x1]	383907	1			T31	17		T1	3		T11	49
all_pins[9]	transitions[0x1=>0x0]	385712	1			T31	17		T11	28		T15	24
all_pins[10]	values[0x0]	1061760	1			T29	1		T30	1		T31	40
all_pins[10]	values[0x1]	642284	1			T31	27		T1	10		T11	55
all_pins[10]	transitions[0x0=>0x1]	385321	1			T31	17		T1	8		T11	38
all_pins[10]	transitions[0x1=>0x0]	385731	1			T31	23		T1	2		T11	42
all_pins[11]	values[0x0]	1059553	1			T29	1		T30	1		T31	31
all_pins[11]	values[0x1]	644491	1			T31	36		T1	1		T11	48
all_pins[11]	transitions[0x0=>0x1]	386048	1			T31	22		T11	29		T12	6
all_pins[11]	transitions[0x1=>0x0]	383841	1			T31	13		T1	9		T11	36
all_pins[12]	values[0x0]	1059732	1			T29	1		T30	1		T31	25
all_pins[12]	values[0x1]	644312	1			T31	42		T1	13		T11	42
all_pins[12]	transitions[0x0=>0x1]	384520	1			T31	20		T1	13		T11	29
all_pins[12]	transitions[0x1=>0x0]	384699	1			T31	14		T1	1		T11	35
all_pins[13]	values[0x0]	1057540	1			T29	1		T30	1		T31	40
all_pins[13]	values[0x1]	646504	1			T31	27		T1	7		T11	49
all_pins[13]	transitions[0x0=>0x1]	387355	1			T31	14		T1	1		T11	30
all_pins[13]	transitions[0x1=>0x0]	385163	1			T31	29		T1	7		T11	23
all_pins[14]	values[0x0]	1059417	1			T29	1		T30	1		T31	36
all_pins[14]	values[0x1]	644627	1			T31	31		T11	63		T12	9
all_pins[14]	transitions[0x0=>0x1]	385956	1			T31	20		T11	38		T12	7
all_pins[14]	transitions[0x1=>0x0]	387833	1			T31	16		T1	7		T11	24
all_pins[15]	values[0x0]	1062533	1			T29	1		T30	1		T31	35
all_pins[15]	values[0x1]	641511	1			T31	32		T1	6		T11	63
all_pins[15]	transitions[0x0=>0x1]	384623	1			T31	17		T1	6		T11	38
all_pins[15]	transitions[0x1=>0x0]	387739	1			T31	16		T11	38		T12	3
all_pins[16]	values[0x0]	1064385	1			T29	1		T30	1		T31	26
all_pins[16]	values[0x1]	639659	1			T31	41		T1	6		T11	39
all_pins[16]	transitions[0x0=>0x1]	385266	1			T31	18		T1	4		T11	27
all_pins[16]	transitions[0x1=>0x0]	387118	1			T31	9		T1	4		T11	51
all_pins[17]	values[0x0]	1056565	1			T29	1		T30	1		T31	37
all_pins[17]	values[0x1]	647479	1			T31	30		T1	8		T11	38
all_pins[17]	transitions[0x0=>0x1]	389537	1			T31	9		T1	8		T11	29
all_pins[17]	transitions[0x1=>0x0]	381717	1			T31	20		T1	6		T11	30
all_pins[18]	values[0x0]	1062354	1			T29	1		T30	1		T31	36
all_pins[18]	values[0x1]	641690	1			T31	31		T1	1		T11	63
all_pins[18]	transitions[0x0=>0x1]	382557	1			T31	16		T11	48		T12	8
all_pins[18]	transitions[0x1=>0x0]	388346	1			T31	15		T1	7		T11	23
all_pins[19]	values[0x0]	1058814	1			T29	1		T30	1		T31	31
all_pins[19]	values[0x1]	645230	1			T31	36		T1	4		T11	42
all_pins[19]	transitions[0x0=>0x1]	387399	1			T31	21		T1	3		T11	20
all_pins[19]	transitions[0x1=>0x0]	383859	1			T31	16		T11	41		T12	17
all_pins[20]	values[0x0]	1064463	1			T29	1		T30	1		T31	29
all_pins[20]	values[0x1]	639581	1			T31	38		T1	9		T11	60
all_pins[20]	transitions[0x0=>0x1]	382233	1			T31	16		T1	9		T11	35
all_pins[20]	transitions[0x1=>0x0]	387882	1			T31	14		T1	4		T11	17
all_pins[21]	values[0x0]	1058703	1			T29	1		T30	1		T31	30
all_pins[21]	values[0x1]	645341	1			T31	37		T1	14		T11	55
all_pins[21]	transitions[0x0=>0x1]	387177	1			T31	12		T1	7		T11	27
all_pins[21]	transitions[0x1=>0x0]	381417	1			T31	13		T1	2		T11	32
all_pins[22]	values[0x0]	1060615	1			T29	1		T30	1		T31	36
all_pins[22]	values[0x1]	643429	1			T31	31		T1	4		T11	45
all_pins[22]	transitions[0x0=>0x1]	383934	1			T31	9		T1	4		T11	22
all_pins[22]	transitions[0x1=>0x0]	385846	1			T31	15		T1	14		T11	32
all_pins[23]	values[0x0]	1061577	1			T29	1		T30	1		T31	33
all_pins[23]	values[0x1]	642467	1			T31	34		T1	6		T11	49
all_pins[23]	transitions[0x0=>0x1]	383542	1			T31	15		T1	6		T11	30
all_pins[23]	transitions[0x1=>0x0]	384504	1			T31	12		T1	4		T11	26
all_pins[24]	values[0x0]	1056443	1			T29	1		T30	1		T31	37
all_pins[24]	values[0x1]	647601	1			T31	30		T11	62		T12	23
all_pins[24]	transitions[0x0=>0x1]	388019	1			T31	14		T11	46		T12	8
all_pins[24]	transitions[0x1=>0x0]	382885	1			T31	18		T1	6		T11	33
all_pins[25]	values[0x0]	1059517	1			T29	1		T30	1		T31	31
all_pins[25]	values[0x1]	644527	1			T31	36		T1	3		T11	54
all_pins[25]	transitions[0x0=>0x1]	384292	1			T31	21		T1	3		T11	20
all_pins[25]	transitions[0x1=>0x0]	387366	1			T31	15		T11	28		T12	19
all_pins[26]	values[0x0]	1058690	1			T29	1		T30	1		T31	34
all_pins[26]	values[0x1]	645354	1			T31	33		T1	9		T11	33
all_pins[26]	transitions[0x0=>0x1]	385339	1			T31	18		T1	9		T11	20
all_pins[26]	transitions[0x1=>0x0]	384512	1			T31	21		T1	3		T11	41
all_pins[27]	values[0x0]	1055364	1			T29	1		T30	1		T31	35
all_pins[27]	values[0x1]	648680	1			T31	32		T1	15		T11	61
all_pins[27]	transitions[0x0=>0x1]	387206	1			T31	15		T1	12		T11	39
all_pins[27]	transitions[0x1=>0x0]	383880	1			T31	16		T1	6		T11	11
all_pins[28]	values[0x0]	1059910	1			T29	1		T30	1		T31	39
all_pins[28]	values[0x1]	644134	1			T31	28		T1	11		T11	52
all_pins[28]	transitions[0x0=>0x1]	382723	1			T31	11		T1	4		T11	25
all_pins[28]	transitions[0x1=>0x0]	387269	1			T31	15		T1	8		T11	34
all_pins[29]	values[0x0]	1057632	1			T29	1		T30	1		T31	38
all_pins[29]	values[0x1]	646412	1			T31	29		T1	7		T11	28
all_pins[29]	transitions[0x0=>0x1]	386120	1			T31	18		T1	4		T11	15
all_pins[29]	transitions[0x1=>0x0]	383842	1			T31	17		T1	8		T11	39
all_pins[30]	values[0x0]	1058966	1			T29	1		T30	1		T31	41
all_pins[30]	values[0x1]	645078	1			T31	26		T1	2		T11	65
all_pins[30]	transitions[0x0=>0x1]	383507	1			T31	18		T1	2		T11	47
all_pins[30]	transitions[0x1=>0x0]	384841	1			T31	21		T1	7		T11	10
all_pins[31]	values[0x0]	1059045	1			T29	1		T30	1		T31	32
all_pins[31]	values[0x1]	644999	1			T31	35		T1	15		T11	35
all_pins[31]	transitions[0x0=>0x1]	386519	1			T31	26		T1	13		T11	19
all_pins[31]	transitions[0x1=>0x0]	386598	1			T31	17		T11	49		T12	22