Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6850126	1			T29	354		T30	259		T31	33631
all_values[1]	6850126	1			T29	354		T30	259		T31	33631
all_values[2]	6850126	1			T29	354		T30	259		T31	33631
all_values[3]	6850126	1			T29	354		T30	259		T31	33631
all_values[4]	6850126	1			T29	354		T30	259		T31	33631
all_values[5]	6850126	1			T29	354		T30	259		T31	33631
all_values[6]	6850126	1			T29	354		T30	259		T31	33631
all_values[7]	6850126	1			T29	354		T30	259		T31	33631
all_values[8]	6850126	1			T29	354		T30	259		T31	33631
all_values[9]	6850126	1			T29	354		T30	259		T31	33631
all_values[10]	6850126	1			T29	354		T30	259		T31	33631
all_values[11]	6850126	1			T29	354		T30	259		T31	33631
all_values[12]	6850126	1			T29	354		T30	259		T31	33631
all_values[13]	6850126	1			T29	354		T30	259		T31	33631
all_values[14]	6850126	1			T29	354		T30	259		T31	33631
all_values[15]	6850126	1			T29	354		T30	259		T31	33631
all_values[16]	6850126	1			T29	354		T30	259		T31	33631
all_values[17]	6850126	1			T29	354		T30	259		T31	33631
all_values[18]	6850126	1			T29	354		T30	259		T31	33631
all_values[19]	6850126	1			T29	354		T30	259		T31	33631
all_values[20]	6850126	1			T29	354		T30	259		T31	33631
all_values[21]	6850126	1			T29	354		T30	259		T31	33631
all_values[22]	6850126	1			T29	354		T30	259		T31	33631
all_values[23]	6850126	1			T29	354		T30	259		T31	33631
all_values[24]	6850126	1			T29	354		T30	259		T31	33631
all_values[25]	6850126	1			T29	354		T30	259		T31	33631
all_values[26]	6850126	1			T29	354		T30	259		T31	33631
all_values[27]	6850126	1			T29	354		T30	259		T31	33631
all_values[28]	6850126	1			T29	354		T30	259		T31	33631
all_values[29]	6850126	1			T29	354		T30	259		T31	33631
all_values[30]	6850126	1			T29	354		T30	259		T31	33631
all_values[31]	6850126	1			T29	354		T30	259		T31	33631

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144703153

1

T29

11328

T30

8288

T31

107619

auto[1]

74500879

1

T1

604

T11

3625

T12

883

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84831250

1

T29

11328

T30

8288

T31

107619

auto[1]

134372782

1

T1

668

T11

5689

T12

1418

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

217172609

1

T29

11328

T30

8288

T31

107619

auto[1]

2031423

1

T1

90

T12

182

T16

51800

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2419575	1			T29	354		T30	259		T31	33631
all_values[0]	auto[0]	auto[0]	auto[1]	2086657	1			T1	6		T11	66		T12	31
all_values[0]	auto[0]	auto[1]	auto[0]	235237	1			T1	31		T11	15		T12	10
all_values[0]	auto[0]	auto[1]	auto[1]	2045172	1			T11	125		T12	14		T15	49
all_values[0]	auto[1]	auto[0]	auto[1]	31703	1			T1	1		T12	4		T16	741
all_values[0]	auto[1]	auto[1]	auto[1]	31782	1			T12	1		T16	869		T17	270
all_values[1]	auto[0]	auto[0]	auto[0]	2418276	1			T29	354		T30	259		T31	33631
all_values[1]	auto[0]	auto[0]	auto[1]	2081977	1			T1	15		T11	124		T12	33
all_values[1]	auto[0]	auto[1]	auto[0]	231558	1			T11	1		T12	10		T15	17
all_values[1]	auto[0]	auto[1]	auto[1]	2055155	1			T1	9		T11	72		T12	6
all_values[1]	auto[1]	auto[0]	auto[1]	32009	1			T1	1		T12	4		T16	855
all_values[1]	auto[1]	auto[1]	auto[1]	31151	1			T12	2		T16	790		T17	238
all_values[2]	auto[0]	auto[0]	auto[0]	2417176	1			T29	354		T30	259		T31	33631
all_values[2]	auto[0]	auto[0]	auto[1]	2067691	1			T1	20		T11	57		T12	21
all_values[2]	auto[0]	auto[1]	auto[0]	234752	1			T1	7		T11	28		T12	14
all_values[2]	auto[0]	auto[1]	auto[1]	2067044	1			T11	107		T12	5		T15	100
all_values[2]	auto[1]	auto[0]	auto[1]	32009	1			T1	3		T12	6		T16	863
all_values[2]	auto[1]	auto[1]	auto[1]	31454	1			T12	1		T16	813		T17	240
all_values[3]	auto[0]	auto[0]	auto[0]	2414302	1			T29	354		T30	259		T31	33631
all_values[3]	auto[0]	auto[0]	auto[1]	2080112	1			T1	6		T11	59		T12	34
all_values[3]	auto[0]	auto[1]	auto[0]	231454	1			T1	8		T11	25		T12	10
all_values[3]	auto[0]	auto[1]	auto[1]	2060688	1			T1	6		T11	128		T15	78
all_values[3]	auto[1]	auto[0]	auto[1]	31858	1			T12	4		T16	798		T17	248
all_values[3]	auto[1]	auto[1]	auto[1]	31712	1			T1	3		T16	825		T17	277
all_values[4]	auto[0]	auto[0]	auto[0]	2419199	1			T29	354		T30	259		T31	33631
all_values[4]	auto[0]	auto[0]	auto[1]	2071434	1			T1	12		T11	121		T12	34
all_values[4]	auto[0]	auto[1]	auto[0]	231914	1			T1	10		T11	7		T12	15
all_values[4]	auto[0]	auto[1]	auto[1]	2064131	1			T1	8		T11	69		T12	7
all_values[4]	auto[1]	auto[0]	auto[1]	31921	1			T1	1		T12	8		T16	869
all_values[4]	auto[1]	auto[1]	auto[1]	31527	1			T1	1		T12	1		T16	842
all_values[5]	auto[0]	auto[0]	auto[0]	2414173	1			T29	354		T30	259		T31	33631
all_values[5]	auto[0]	auto[0]	auto[1]	2069892	1			T1	10		T11	108		T12	30
all_values[5]	auto[0]	auto[1]	auto[0]	237729	1			T1	13		T11	29		T12	4
all_values[5]	auto[0]	auto[1]	auto[1]	2065182	1			T11	77		T12	21		T15	89
all_values[5]	auto[1]	auto[0]	auto[1]	31476	1			T1	3		T12	6		T16	786
all_values[5]	auto[1]	auto[1]	auto[1]	31674	1			T1	1		T12	1		T16	814
all_values[6]	auto[0]	auto[0]	auto[0]	2419780	1			T29	354		T30	259		T31	33631
all_values[6]	auto[0]	auto[0]	auto[1]	2062166	1			T1	6		T11	73		T12	7
all_values[6]	auto[0]	auto[1]	auto[0]	234985	1			T1	11		T11	43		T12	21
all_values[6]	auto[0]	auto[1]	auto[1]	2069591	1			T1	3		T11	85		T12	24
all_values[6]	auto[1]	auto[0]	auto[1]	32248	1			T1	3		T12	2		T16	810
all_values[6]	auto[1]	auto[1]	auto[1]	31356	1			T12	4		T16	818		T17	276
all_values[7]	auto[0]	auto[0]	auto[0]	2414332	1			T29	354		T30	259		T31	33631
all_values[7]	auto[0]	auto[0]	auto[1]	2063788	1			T1	6		T11	64		T12	32
all_values[7]	auto[0]	auto[1]	auto[0]	232443	1			T1	16		T11	18		T12	17
all_values[7]	auto[0]	auto[1]	auto[1]	2076332	1			T1	3		T11	125		T12	5
all_values[7]	auto[1]	auto[0]	auto[1]	31771	1			T1	2		T12	4		T16	844
all_values[7]	auto[1]	auto[1]	auto[1]	31460	1			T1	1		T12	3		T16	756
all_values[8]	auto[0]	auto[0]	auto[0]	2416975	1			T29	354		T30	259		T31	33631
all_values[8]	auto[0]	auto[0]	auto[1]	2072636	1			T1	11		T11	93		T12	38
all_values[8]	auto[0]	auto[1]	auto[0]	231268	1			T1	3		T11	23		T12	18
all_values[8]	auto[0]	auto[1]	auto[1]	2065680	1			T11	71		T15	55		T16	52867
all_values[8]	auto[1]	auto[0]	auto[1]	32037	1			T1	2		T12	4		T16	734
all_values[8]	auto[1]	auto[1]	auto[1]	31530	1			T1	1		T16	863		T17	274
all_values[9]	auto[0]	auto[0]	auto[0]	2423140	1			T29	354		T30	259		T31	33631
all_values[9]	auto[0]	auto[0]	auto[1]	2085031	1			T1	11		T11	76		T12	19
all_values[9]	auto[0]	auto[1]	auto[0]	234357	1			T1	15		T11	20		T12	13
all_values[9]	auto[0]	auto[1]	auto[1]	2044110	1			T1	3		T11	110		T12	6
all_values[9]	auto[1]	auto[0]	auto[1]	31698	1			T1	2		T12	6		T16	784
all_values[9]	auto[1]	auto[1]	auto[1]	31790	1			T1	2		T12	1		T16	812
all_values[10]	auto[0]	auto[0]	auto[0]	2417506	1			T29	354		T30	259		T31	33631
all_values[10]	auto[0]	auto[0]	auto[1]	2078936	1			T1	12		T11	87		T12	31
all_values[10]	auto[0]	auto[1]	auto[0]	235689	1			T1	16		T11	19		T12	11
all_values[10]	auto[0]	auto[1]	auto[1]	2054490	1			T1	14		T11	87		T12	10
all_values[10]	auto[1]	auto[0]	auto[1]	32193	1			T1	2		T12	5		T16	809
all_values[10]	auto[1]	auto[1]	auto[1]	31312	1			T1	1		T16	769		T17	256
all_values[11]	auto[0]	auto[0]	auto[0]	2416284	1			T29	354		T30	259		T31	33631
all_values[11]	auto[0]	auto[0]	auto[1]	2070398	1			T1	11		T11	59		T12	34
all_values[11]	auto[0]	auto[1]	auto[0]	230575	1			T1	31		T11	37		T12	13
all_values[11]	auto[0]	auto[1]	auto[1]	2069235	1			T11	101		T12	8		T15	51
all_values[11]	auto[1]	auto[0]	auto[1]	31902	1			T12	4		T16	786		T17	279
all_values[11]	auto[1]	auto[1]	auto[1]	31732	1			T1	1		T12	3		T16	840
all_values[12]	auto[0]	auto[0]	auto[0]	2418717	1			T29	354		T30	259		T31	33631
all_values[12]	auto[0]	auto[0]	auto[1]	2076943	1			T1	14		T11	71		T12	24
all_values[12]	auto[0]	auto[1]	auto[0]	235698	1			T11	18		T12	13		T15	12
all_values[12]	auto[0]	auto[1]	auto[1]	2055375	1			T1	17		T11	80		T12	19
all_values[12]	auto[1]	auto[0]	auto[1]	31914	1			T1	3		T12	2		T16	801
all_values[12]	auto[1]	auto[1]	auto[1]	31479	1			T12	1		T16	801		T17	278
all_values[13]	auto[0]	auto[0]	auto[0]	2418593	1			T29	354		T30	259		T31	33631
all_values[13]	auto[0]	auto[0]	auto[1]	2060628	1			T1	10		T11	84		T12	27
all_values[13]	auto[0]	auto[1]	auto[0]	237546	1			T1	28		T11	27		T12	6
all_values[13]	auto[0]	auto[1]	auto[1]	2069978	1			T1	7		T11	96		T12	18
all_values[13]	auto[1]	auto[0]	auto[1]	32096	1			T1	2		T12	4		T16	795
all_values[13]	auto[1]	auto[1]	auto[1]	31285	1			T1	1		T12	2		T16	786
all_values[14]	auto[0]	auto[0]	auto[0]	2411331	1			T29	354		T30	259		T31	33631
all_values[14]	auto[0]	auto[0]	auto[1]	2073902	1			T1	10		T11	44		T12	20
all_values[14]	auto[0]	auto[1]	auto[0]	238420	1			T1	8		T11	42		T12	28
all_values[14]	auto[0]	auto[1]	auto[1]	2062915	1			T11	117		T12	7		T15	94
all_values[14]	auto[1]	auto[0]	auto[1]	32180	1			T1	3		T12	5		T16	836
all_values[14]	auto[1]	auto[1]	auto[1]	31378	1			T12	2		T16	775		T17	298
all_values[15]	auto[0]	auto[0]	auto[0]	2415561	1			T29	354		T30	259		T31	33631
all_values[15]	auto[0]	auto[0]	auto[1]	2082450	1			T1	4		T11	103		T12	5
all_values[15]	auto[0]	auto[1]	auto[0]	231526	1			T1	13		T11	6		T12	12
all_values[15]	auto[0]	auto[1]	auto[1]	2057129	1			T1	7		T11	103		T12	31
all_values[15]	auto[1]	auto[0]	auto[1]	32348	1			T1	2		T12	3		T16	832
all_values[15]	auto[1]	auto[1]	auto[1]	31112	1			T1	1		T12	2		T16	814
all_values[16]	auto[0]	auto[0]	auto[0]	2418398	1			T29	354		T30	259		T31	33631
all_values[16]	auto[0]	auto[0]	auto[1]	2082561	1			T1	19		T11	101		T12	20
all_values[16]	auto[0]	auto[1]	auto[0]	235450	1			T1	4		T11	33		T12	7
all_values[16]	auto[0]	auto[1]	auto[1]	2050207	1			T1	7		T11	63		T12	15
all_values[16]	auto[1]	auto[0]	auto[1]	31875	1			T1	3		T12	4		T16	777
all_values[16]	auto[1]	auto[1]	auto[1]	31635	1			T16	833		T17	270		T35	101
all_values[17]	auto[0]	auto[0]	auto[0]	2414257	1			T29	354		T30	259		T31	33631
all_values[17]	auto[0]	auto[0]	auto[1]	2063751	1			T1	8		T11	138		T12	31
all_values[17]	auto[0]	auto[1]	auto[0]	234765	1			T1	4		T11	10		T12	9
all_values[17]	auto[0]	auto[1]	auto[1]	2073926	1			T1	11		T11	54		T12	18
all_values[17]	auto[1]	auto[0]	auto[1]	31868	1			T1	2		T12	4		T16	766
all_values[17]	auto[1]	auto[1]	auto[1]	31559	1			T1	2		T16	852		T17	266
all_values[18]	auto[0]	auto[0]	auto[0]	2414951	1			T29	354		T30	259		T31	33631
all_values[18]	auto[0]	auto[0]	auto[1]	2078126	1			T1	14		T11	42		T12	15
all_values[18]	auto[0]	auto[1]	auto[0]	231977	1			T1	13		T11	29		T12	32
all_values[18]	auto[0]	auto[1]	auto[1]	2061294	1			T11	124		T12	17		T15	41
all_values[18]	auto[1]	auto[0]	auto[1]	32496	1			T1	1		T12	3		T16	836
all_values[18]	auto[1]	auto[1]	auto[1]	31282	1			T1	1		T12	3		T16	816
all_values[19]	auto[0]	auto[0]	auto[0]	2413741	1			T29	354		T30	259		T31	33631
all_values[19]	auto[0]	auto[0]	auto[1]	2073775	1			T1	7		T11	114		T12	40
all_values[19]	auto[0]	auto[1]	auto[0]	234169	1			T1	11		T11	16		T12	3
all_values[19]	auto[0]	auto[1]	auto[1]	2064707	1			T1	1		T11	73		T12	2
all_values[19]	auto[1]	auto[0]	auto[1]	32009	1			T1	2		T12	3		T16	817
all_values[19]	auto[1]	auto[1]	auto[1]	31725	1			T1	2		T16	770		T17	271
all_values[20]	auto[0]	auto[0]	auto[0]	2418324	1			T29	354		T30	259		T31	33631
all_values[20]	auto[0]	auto[0]	auto[1]	2080910	1			T1	22		T11	71		T12	37
all_values[20]	auto[0]	auto[1]	auto[0]	232799	1			T1	6		T11	28		T12	12
all_values[20]	auto[0]	auto[1]	auto[1]	2054894	1			T1	10		T11	105		T12	5
all_values[20]	auto[1]	auto[0]	auto[1]	31883	1			T1	3		T12	5		T16	820
all_values[20]	auto[1]	auto[1]	auto[1]	31316	1			T1	1		T12	1		T16	756
all_values[21]	auto[0]	auto[0]	auto[0]	2412698	1			T29	354		T30	259		T31	33631
all_values[21]	auto[0]	auto[0]	auto[1]	2075943	1			T1	4		T11	90		T12	29
all_values[21]	auto[0]	auto[1]	auto[0]	234451	1			T1	11		T11	15		T12	13
all_values[21]	auto[0]	auto[1]	auto[1]	2063609	1			T1	19		T11	99		T12	19
all_values[21]	auto[1]	auto[0]	auto[1]	31767	1			T12	5		T16	846		T17	226
all_values[21]	auto[1]	auto[1]	auto[1]	31658	1			T1	2		T12	1		T16	776
all_values[22]	auto[0]	auto[0]	auto[0]	2416137	1			T29	354		T30	259		T31	33631
all_values[22]	auto[0]	auto[0]	auto[1]	2076867	1			T1	23		T11	82		T12	16
all_values[22]	auto[0]	auto[1]	auto[0]	235126	1			T1	7		T11	29		T12	32
all_values[22]	auto[0]	auto[1]	auto[1]	2058584	1			T1	4		T11	88		T12	10
all_values[22]	auto[1]	auto[0]	auto[1]	32153	1			T1	1		T12	2		T16	855
all_values[22]	auto[1]	auto[1]	auto[1]	31259	1			T12	3		T16	761		T17	287
all_values[23]	auto[0]	auto[0]	auto[0]	2416125	1			T29	354		T30	259		T31	33631
all_values[23]	auto[0]	auto[0]	auto[1]	2085830	1			T1	13		T11	73		T12	10
all_values[23]	auto[0]	auto[1]	auto[0]	233415	1			T11	12		T12	21		T15	17
all_values[23]	auto[0]	auto[1]	auto[1]	2051221	1			T1	8		T11	95		T12	26
all_values[23]	auto[1]	auto[0]	auto[1]	31947	1			T1	4		T12	4		T16	831
all_values[23]	auto[1]	auto[1]	auto[1]	31588	1			T12	3		T16	787		T17	263
all_values[24]	auto[0]	auto[0]	auto[0]	2413466	1			T29	354		T30	259		T31	33631
all_values[24]	auto[0]	auto[0]	auto[1]	2067390	1			T1	2		T11	71		T12	29
all_values[24]	auto[0]	auto[1]	auto[0]	235128	1			T1	4		T11	15		T12	7
all_values[24]	auto[0]	auto[1]	auto[1]	2070510	1			T11	110		T12	24		T15	63
all_values[24]	auto[1]	auto[0]	auto[1]	32204	1			T1	4		T12	5		T16	827
all_values[24]	auto[1]	auto[1]	auto[1]	31428	1			T12	2		T16	794		T17	254
all_values[25]	auto[0]	auto[0]	auto[0]	2415446	1			T29	354		T30	259		T31	33631
all_values[25]	auto[0]	auto[0]	auto[1]	2073746	1			T1	20		T11	100		T12	28
all_values[25]	auto[0]	auto[1]	auto[0]	229071	1			T1	17		T11	10		T12	16
all_values[25]	auto[0]	auto[1]	auto[1]	2068642	1			T1	2		T11	97		T12	6
all_values[25]	auto[1]	auto[0]	auto[1]	31535	1			T1	1		T12	3		T16	709
all_values[25]	auto[1]	auto[1]	auto[1]	31686	1			T12	1		T16	880		T17	285
all_values[26]	auto[0]	auto[0]	auto[0]	2417431	1			T29	354		T30	259		T31	33631
all_values[26]	auto[0]	auto[0]	auto[1]	2069074	1			T1	19		T11	102		T12	41
all_values[26]	auto[0]	auto[1]	auto[0]	240706	1			T1	7		T11	28		T15	9
all_values[26]	auto[0]	auto[1]	auto[1]	2059390	1			T1	10		T11	51		T15	49
all_values[26]	auto[1]	auto[0]	auto[1]	32115	1			T1	3		T12	4		T16	837
all_values[26]	auto[1]	auto[1]	auto[1]	31410	1			T1	2		T16	830		T17	250
all_values[27]	auto[0]	auto[0]	auto[0]	2413707	1			T29	354		T30	259		T31	33631
all_values[27]	auto[0]	auto[0]	auto[1]	2060268	1			T1	12		T11	62		T12	31
all_values[27]	auto[0]	auto[1]	auto[0]	231819	1			T1	18		T11	35		T12	13
all_values[27]	auto[0]	auto[1]	auto[1]	2080815	1			T1	13		T11	108		T12	6
all_values[27]	auto[1]	auto[0]	auto[1]	31899	1			T1	1		T12	8		T16	826
all_values[27]	auto[1]	auto[1]	auto[1]	31618	1			T1	2		T12	1		T16	815
all_values[28]	auto[0]	auto[0]	auto[0]	2420339	1			T29	354		T30	259		T31	33631
all_values[28]	auto[0]	auto[0]	auto[1]	2084146	1			T1	19		T11	113		T12	39
all_values[28]	auto[0]	auto[1]	auto[0]	233085	1			T1	8		T11	15		T12	9
all_values[28]	auto[0]	auto[1]	auto[1]	2048742	1			T1	16		T11	86		T15	50
all_values[28]	auto[1]	auto[0]	auto[1]	32086	1			T1	1		T12	5		T16	780
all_values[28]	auto[1]	auto[1]	auto[1]	31728	1			T1	1		T12	1		T16	791
all_values[29]	auto[0]	auto[0]	auto[0]	2417617	1			T29	354		T30	259		T31	33631
all_values[29]	auto[0]	auto[0]	auto[1]	2069918	1			T1	3		T11	101		T12	17
all_values[29]	auto[0]	auto[1]	auto[0]	236393	1			T1	18		T11	24		T12	16
all_values[29]	auto[0]	auto[1]	auto[1]	2062616	1			T1	9		T11	56		T12	22
all_values[29]	auto[1]	auto[0]	auto[1]	31855	1			T1	1		T12	3		T16	856
all_values[29]	auto[1]	auto[1]	auto[1]	31727	1			T1	1		T12	1		T16	814
all_values[30]	auto[0]	auto[0]	auto[0]	2416677	1			T29	354		T30	259		T31	33631
all_values[30]	auto[0]	auto[0]	auto[1]	2057515	1			T1	5		T11	76		T12	10
all_values[30]	auto[0]	auto[1]	auto[0]	241344	1			T1	16		T11	10		T12	18
all_values[30]	auto[0]	auto[1]	auto[1]	2071173	1			T1	4		T11	113		T12	33
all_values[30]	auto[1]	auto[0]	auto[1]	31931	1			T1	2		T12	3		T16	763
all_values[30]	auto[1]	auto[1]	auto[1]	31486	1			T12	4		T16	840		T17	263
all_values[31]	auto[0]	auto[0]	auto[0]	2418263	1			T29	354		T30	259		T31	33631
all_values[31]	auto[0]	auto[0]	auto[1]	2062942	1			T1	15		T11	117		T12	30
all_values[31]	auto[0]	auto[1]	auto[0]	233904	1			T1	11		T11	11		T12	20
all_values[31]	auto[0]	auto[1]	auto[1]	2071419	1			T1	18		T11	72		T12	9
all_values[31]	auto[1]	auto[0]	auto[1]	32267	1			T1	1		T12	3		T16	806
all_values[31]	auto[1]	auto[1]	auto[1]	31331	1			T1	3		T12	2		T16	803

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal