Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[1]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[2]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[3]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[4]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[5]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[6]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[7]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[8]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[9]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[10]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[11]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[12]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[13]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[14]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[15]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[16]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[17]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[18]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[19]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[20]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[21]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[22]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[23]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[24]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[25]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[26]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[27]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[28]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[29]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[30]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[31]	6802354	1			T29	685		T30	327		T31	33631

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115424599

1

T29

17110

T30

6375

T31

539421

auto[1]

102250729

1

T29

4810

T30

4089

T31

536771

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

180527315

1

T29

16307

T30

8405

T31

107619

auto[1]

37148013

1

T29

5613

T30

2059

T32

5108

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169625576

1

T29

11398

T30

8296

T31

107619

auto[1]

48049752

1

T29

10522

T30

2168

T32

5102

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2451082	1			T29	239		T30	135		T31	16815
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2267166	1			T29	63		T30	95		T31	16816
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	583330	1			T29	174		T30	26		T32	78
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	562366	1			T29	123		T30	41		T32	98
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	360061	1			T29	18		T34	17		T1	6
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	578349	1			T29	68		T30	30		T32	82
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2468282	1			T29	258		T30	137		T31	16790
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2253013	1			T29	45		T30	87		T31	16841
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	587670	1			T29	107		T30	28		T32	68
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	557808	1			T29	195		T30	46		T32	78
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	360113	1			T29	30		T34	11		T1	18
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	575468	1			T29	50		T30	29		T32	85
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2459189	1			T29	251		T30	120		T31	18648
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2254070	1			T29	41		T30	100		T31	14983
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	585737	1			T29	145		T30	20		T32	69
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	563330	1			T29	162		T30	47		T32	68
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	361797	1			T29	23		T34	17		T1	18
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	578231	1			T29	63		T30	40		T32	88
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2458224	1			T29	265		T30	143		T31	17564
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2257862	1			T29	44		T30	84		T31	16067
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	583890	1			T29	102		T30	28		T32	96
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	560578	1			T29	142		T30	44		T32	84
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	362724	1			T29	24		T34	16		T1	15
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	579076	1			T29	108		T30	28		T32	56
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2463333	1			T29	252		T30	140		T31	16625
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2249218	1			T29	40		T30	84		T31	17006
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	582751	1			T29	115		T30	36		T32	102
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	564392	1			T29	173		T30	34		T32	74
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	363613	1			T29	14		T34	7		T1	10
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	579047	1			T29	91		T30	33		T32	78
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2461251	1			T29	188		T30	142		T31	15656
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2258416	1			T29	22		T30	98		T31	17975
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	583325	1			T29	37		T30	31		T32	60
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	563565	1			T29	294		T30	26		T32	115
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	359854	1			T29	43		T34	20		T1	26
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	575943	1			T29	101		T30	30		T32	80
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2453816	1			T29	199		T30	115		T31	17064
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2263759	1			T29	37		T30	105		T31	16567
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	584910	1			T29	116		T30	56		T32	91
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	562130	1			T29	218		T30	19		T32	82
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	362357	1			T29	38		T34	21		T12	4
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	575382	1			T29	77		T30	32		T32	66
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2463856	1			T29	188		T30	150		T31	16292
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2255799	1			T29	21		T30	84		T31	17339
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	585541	1			T29	103		T30	22		T32	61
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	559647	1			T29	248		T30	29		T32	104
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	361108	1			T29	32		T34	11		T1	8
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	576403	1			T29	93		T30	42		T32	100
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2457144	1			T29	221		T30	136		T31	17260
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2254914	1			T29	43		T30	76		T31	16371
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	582757	1			T29	78		T30	48		T32	82
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	561425	1			T29	223		T30	26		T32	58
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	364357	1			T29	33		T34	12		T1	5
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	581757	1			T29	87		T30	41		T32	102
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2464031	1			T29	233		T30	130		T31	17769
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2253773	1			T29	35		T30	100		T31	15862
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	584959	1			T29	52		T30	38		T32	77
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	561259	1			T29	267		T30	28		T32	96
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	361786	1			T29	27		T34	13		T12	11
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	576546	1			T29	71		T30	31		T32	76
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2452321	1			T29	273		T30	144		T31	16198
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2263815	1			T29	36		T30	80		T31	17433
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	583055	1			T29	78		T30	36		T32	92
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	563930	1			T29	214		T30	38		T32	72
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	360218	1			T29	38		T34	16		T1	3
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	579015	1			T29	46		T30	29		T32	68
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2462145	1			T29	193		T30	146		T31	16536
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2258751	1			T29	40		T30	96		T31	17095
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	584181	1			T29	143		T30	37		T32	119
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	561825	1			T29	191		T30	20		T32	58
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	360952	1			T29	24		T34	16		T1	7
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	574500	1			T29	94		T30	28		T32	90
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2462117	1			T29	219		T30	142		T31	16958
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2253628	1			T29	45		T30	82		T31	16673
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	586514	1			T29	103		T30	44		T32	51
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	557752	1			T29	234		T30	42		T32	98
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	361948	1			T29	30		T34	11		T1	5
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	580395	1			T29	54		T30	17		T32	94
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2465734	1			T29	277		T30	142		T31	17261
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2252553	1			T29	45		T30	101		T31	16370
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	585704	1			T29	111		T30	24		T32	72
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	562349	1			T29	170		T30	36		T32	90
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	360200	1			T29	33		T34	18		T1	12
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	575814	1			T29	49		T30	24		T32	85
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2461393	1			T29	231		T30	123		T31	17924
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2254187	1			T29	37		T30	97		T31	15707
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	587499	1			T29	59		T30	32		T32	81
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	561675	1			T29	238		T30	39		T32	96
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	361785	1			T29	30		T34	26		T1	9
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	575815	1			T29	90		T30	36		T32	52
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2458946	1			T29	186		T30	130		T31	15428
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2254612	1			T29	37		T30	101		T31	18203
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	584727	1			T29	86		T30	28		T32	80
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	563821	1			T29	243		T30	32		T32	79
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	362818	1			T29	28		T34	17		T1	6
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	577430	1			T29	105		T30	36		T32	84
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2454517	1			T29	192		T30	112		T31	16418
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2261843	1			T29	33		T30	106		T31	17213
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	581835	1			T29	80		T30	18		T32	76
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	564704	1			T29	243		T30	64		T32	78
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	363575	1			T29	44		T34	9		T1	10
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	575880	1			T29	93		T30	27		T32	93
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2472975	1			T29	245		T30	129		T31	17543
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2245718	1			T29	43		T30	99		T31	16088
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	582866	1			T29	95		T30	35		T32	60
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	561806	1			T29	214		T30	34		T32	90
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	362103	1			T29	24		T34	21		T1	11
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	576886	1			T29	64		T30	30		T32	77
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2462403	1			T29	178		T30	138		T31	17099
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2254712	1			T29	33		T30	94		T31	16532
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	583742	1			T29	79		T30	36		T32	68
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	559727	1			T29	279		T30	34		T32	98
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	363611	1			T29	46		T34	22		T1	10
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	578159	1			T29	70		T30	25		T32	57
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2468283	1			T29	205		T30	140		T31	17133
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2251685	1			T29	24		T30	98		T31	16498
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	580985	1			T29	75		T30	25		T32	98
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	563975	1			T29	218		T30	36		T32	69
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	362506	1			T29	41		T34	24		T1	8
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	574920	1			T29	122		T30	28		T32	78
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2458875	1			T29	207		T30	121		T31	16902
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2260601	1			T29	42		T30	105		T31	16729
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	581311	1			T29	148		T30	34		T32	86
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	561726	1			T29	179		T30	32		T32	73
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	363784	1			T29	42		T34	16		T1	9
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	576057	1			T29	67		T30	35		T32	66
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2463762	1			T29	239		T30	127		T31	17419
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2253435	1			T29	37		T30	90		T31	16212
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	584818	1			T29	90		T30	42		T32	60
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	560898	1			T29	220		T30	22		T32	63
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	362508	1			T29	26		T34	17		T1	8
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	576933	1			T29	73		T30	46		T32	96
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2458589	1			T29	222		T30	141		T31	16897
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2259449	1			T29	49		T30	89		T31	16734
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	581878	1			T29	109		T30	46		T32	114
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	561937	1			T29	141		T30	24		T32	58
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	362134	1			T29	29		T34	9		T1	18
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	578367	1			T29	135		T30	27		T32	78
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2464549	1			T29	239		T30	109		T31	18792
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2245195	1			T29	35		T30	107		T31	14839
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	580659	1			T29	44		T30	24		T32	93
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	568099	1			T29	256		T30	46		T32	64
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	363991	1			T29	36		T34	16		T1	7
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	579861	1			T29	75		T30	41		T32	92
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2460538	1			T29	149		T30	123		T31	15462
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2260671	1			T29	16		T30	104		T31	18169
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	581284	1			T29	81		T30	36		T32	88
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	561302	1			T29	292		T30	28		T32	75
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	360279	1			T29	41		T34	9		T1	14
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	578280	1			T29	106		T30	36		T32	56
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2455358	1			T29	240		T30	145		T31	15776
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2259583	1			T29	32		T30	85		T31	17855
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	582263	1			T29	70		T30	30		T32	82
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	566732	1			T29	225		T30	33		T32	58
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	363106	1			T29	37		T34	4		T1	15
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	575312	1			T29	81		T30	34		T32	74
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2469899	1			T29	208		T30	131		T31	16214
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2246811	1			T29	37		T30	99		T31	17417
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	581138	1			T29	107		T30	26		T32	54
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	563226	1			T29	219		T30	32		T32	116
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	364650	1			T29	34		T34	9		T1	12
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	576630	1			T29	80		T30	39		T32	75
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2452286	1			T29	227		T30	117		T31	16691
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2264728	1			T29	31		T30	107		T31	16940
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	582733	1			T29	126		T30	31		T32	82
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	565030	1			T29	185		T30	50		T32	78
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	363662	1			T29	37		T34	36		T1	11
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	573915	1			T29	79		T30	22		T32	78
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2462982	1			T29	261		T30	134		T31	16831
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2259669	1			T29	41		T30	87		T31	16800
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	586753	1			T29	53		T30	34		T32	99
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	558250	1			T29	246		T30	26		T32	78
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	360351	1			T29	23		T34	12		T1	18
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	574349	1			T29	61		T30	46		T32	82
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2469860	1			T29	175		T30	134		T31	16001
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2249419	1			T29	39		T30	96		T31	17630
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	584291	1			T29	69		T30	22		T32	77
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	560690	1			T29	305		T30	32		T32	84
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	360686	1			T29	46		T34	19		T1	4
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	577408	1			T29	51		T30	43		T32	88
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2455487	1			T29	220		T30	144		T31	16039
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2259702	1			T29	33		T30	95		T31	17592
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	584642	1			T29	81		T30	20		T32	80
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	563880	1			T29	216		T30	28		T32	79
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	361893	1			T29	26		T34	10		T1	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	576750	1			T29	109		T30	40		T32	60
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2454747	1			T29	271		T30	136		T31	17416
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2258114	1			T29	54		T30	104		T31	16215
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	582983	1			T29	121		T30	12		T32	92
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	566060	1			T29	149		T30	46		T32	71
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	362046	1			T29	27		T34	22		T1	6
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	578404	1			T29	63		T30	29		T32	84

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal