Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[1]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[2]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[3]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[4]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[5]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[6]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[7]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[8]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[9]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[10]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[11]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[12]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[13]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[14]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[15]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[16]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[17]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[18]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[19]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[20]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[21]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[22]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[23]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[24]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[25]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[26]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[27]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[28]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[29]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[30]	6802354	1			T29	685		T30	327		T31	33631
bins_for_gpio_bits[31]	6802354	1			T29	685		T30	327		T31	33631

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115424599

1

T29

17110

T30

6375

T31

539421

auto[1]

102250729

1

T29

4810

T30

4089

T31

536771

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115415489

1

T29

17110

T30

6361

T31

539421

auto[1]

102259839

1

T29

4810

T30

4103

T31

536771

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3491634	1			T29	526		T30	194		T31	16815
bins_for_gpio_bits[0]	auto[0]	auto[1]	104854	1			T29	10		T30	8		T32	20
bins_for_gpio_bits[0]	auto[1]	auto[0]	105144	1			T29	10		T30	8		T32	20
bins_for_gpio_bits[0]	auto[1]	auto[1]	3100722	1			T29	139		T30	117		T31	16816
bins_for_gpio_bits[1]	auto[0]	auto[0]	3508852	1			T29	549		T30	203		T31	16790
bins_for_gpio_bits[1]	auto[0]	auto[1]	104612	1			T29	11		T30	7		T32	20
bins_for_gpio_bits[1]	auto[1]	auto[0]	104908	1			T29	11		T30	8		T32	21
bins_for_gpio_bits[1]	auto[1]	auto[1]	3083982	1			T29	114		T30	109		T31	16841
bins_for_gpio_bits[2]	auto[0]	auto[0]	3503029	1			T29	546		T30	176		T31	18648
bins_for_gpio_bits[2]	auto[0]	auto[1]	104918	1			T29	12		T30	11		T32	19
bins_for_gpio_bits[2]	auto[1]	auto[0]	105227	1			T29	12		T30	11		T32	19
bins_for_gpio_bits[2]	auto[1]	auto[1]	3089180	1			T29	115		T30	129		T31	14983
bins_for_gpio_bits[3]	auto[0]	auto[0]	3497965	1			T29	491		T30	205		T31	17564
bins_for_gpio_bits[3]	auto[0]	auto[1]	104474	1			T29	18		T30	10		T32	17
bins_for_gpio_bits[3]	auto[1]	auto[0]	104727	1			T29	18		T30	10		T32	17
bins_for_gpio_bits[3]	auto[1]	auto[1]	3095188	1			T29	158		T30	102		T31	16067
bins_for_gpio_bits[4]	auto[0]	auto[0]	3505381	1			T29	527		T30	199		T31	16625
bins_for_gpio_bits[4]	auto[0]	auto[1]	104834	1			T29	13		T30	10		T32	23
bins_for_gpio_bits[4]	auto[1]	auto[0]	105095	1			T29	13		T30	11		T32	23
bins_for_gpio_bits[4]	auto[1]	auto[1]	3087044	1			T29	132		T30	107		T31	17006
bins_for_gpio_bits[5]	auto[0]	auto[0]	3503208	1			T29	503		T30	189		T31	15656
bins_for_gpio_bits[5]	auto[0]	auto[1]	104654	1			T29	16		T30	10		T32	17
bins_for_gpio_bits[5]	auto[1]	auto[0]	104933	1			T29	16		T30	10		T32	17
bins_for_gpio_bits[5]	auto[1]	auto[1]	3089559	1			T29	150		T30	118		T31	17975
bins_for_gpio_bits[6]	auto[0]	auto[0]	3495830	1			T29	517		T30	180		T31	17064
bins_for_gpio_bits[6]	auto[0]	auto[1]	104726	1			T29	16		T30	10		T32	17
bins_for_gpio_bits[6]	auto[1]	auto[0]	105026	1			T29	16		T30	10		T32	17
bins_for_gpio_bits[6]	auto[1]	auto[1]	3096772	1			T29	136		T30	127		T31	16567
bins_for_gpio_bits[7]	auto[0]	auto[0]	3504014	1			T29	522		T30	194		T31	16292
bins_for_gpio_bits[7]	auto[0]	auto[1]	104730	1			T29	17		T30	7		T32	20
bins_for_gpio_bits[7]	auto[1]	auto[0]	105030	1			T29	17		T30	7		T32	20
bins_for_gpio_bits[7]	auto[1]	auto[1]	3088580	1			T29	129		T30	119		T31	17339
bins_for_gpio_bits[8]	auto[0]	auto[0]	3496070	1			T29	506		T30	200		T31	17260
bins_for_gpio_bits[8]	auto[0]	auto[1]	104934	1			T29	16		T30	9		T32	22
bins_for_gpio_bits[8]	auto[1]	auto[0]	105256	1			T29	16		T30	10		T32	22
bins_for_gpio_bits[8]	auto[1]	auto[1]	3096094	1			T29	147		T30	108		T31	16371
bins_for_gpio_bits[9]	auto[0]	auto[0]	3505203	1			T29	535		T30	188		T31	17769
bins_for_gpio_bits[9]	auto[0]	auto[1]	104723	1			T29	17		T30	7		T32	22
bins_for_gpio_bits[9]	auto[1]	auto[0]	105046	1			T29	17		T30	8		T32	22
bins_for_gpio_bits[9]	auto[1]	auto[1]	3087382	1			T29	116		T30	124		T31	15862
bins_for_gpio_bits[10]	auto[0]	auto[0]	3494163	1			T29	555		T30	210		T31	16198
bins_for_gpio_bits[10]	auto[0]	auto[1]	104857	1			T29	10		T30	7		T32	19
bins_for_gpio_bits[10]	auto[1]	auto[0]	105143	1			T29	10		T30	8		T32	19
bins_for_gpio_bits[10]	auto[1]	auto[1]	3098191	1			T29	110		T30	102		T31	17433
bins_for_gpio_bits[11]	auto[0]	auto[0]	3503452	1			T29	509		T30	193		T31	16536
bins_for_gpio_bits[11]	auto[0]	auto[1]	104388	1			T29	18		T30	10		T32	23
bins_for_gpio_bits[11]	auto[1]	auto[0]	104699	1			T29	18		T30	10		T32	23
bins_for_gpio_bits[11]	auto[1]	auto[1]	3089815	1			T29	140		T30	114		T31	17095
bins_for_gpio_bits[12]	auto[0]	auto[0]	3500962	1			T29	541		T30	222		T31	16958
bins_for_gpio_bits[12]	auto[0]	auto[1]	105121	1			T29	15		T30	5		T32	22
bins_for_gpio_bits[12]	auto[1]	auto[0]	105421	1			T29	15		T30	6		T32	22
bins_for_gpio_bits[12]	auto[1]	auto[1]	3090850	1			T29	114		T30	94		T31	16673
bins_for_gpio_bits[13]	auto[0]	auto[0]	3508610	1			T29	546		T30	196		T31	17261
bins_for_gpio_bits[13]	auto[0]	auto[1]	104869	1			T29	12		T30	6		T32	24
bins_for_gpio_bits[13]	auto[1]	auto[0]	105177	1			T29	12		T30	6		T32	25
bins_for_gpio_bits[13]	auto[1]	auto[1]	3083698	1			T29	115		T30	119		T31	16370
bins_for_gpio_bits[14]	auto[0]	auto[0]	3505438	1			T29	510		T30	186		T31	17924
bins_for_gpio_bits[14]	auto[0]	auto[1]	104848	1			T29	18		T30	8		T32	17
bins_for_gpio_bits[14]	auto[1]	auto[0]	105129	1			T29	18		T30	8		T32	17
bins_for_gpio_bits[14]	auto[1]	auto[1]	3086939	1			T29	139		T30	125		T31	15707
bins_for_gpio_bits[15]	auto[0]	auto[0]	3502362	1			T29	498		T30	181		T31	15428
bins_for_gpio_bits[15]	auto[0]	auto[1]	104866	1			T29	17		T30	9		T32	20
bins_for_gpio_bits[15]	auto[1]	auto[0]	105132	1			T29	17		T30	9		T32	20
bins_for_gpio_bits[15]	auto[1]	auto[1]	3089994	1			T29	153		T30	128		T31	18203
bins_for_gpio_bits[16]	auto[0]	auto[0]	3495802	1			T29	504		T30	184		T31	16418
bins_for_gpio_bits[16]	auto[0]	auto[1]	104979	1			T29	11		T30	9		T32	24
bins_for_gpio_bits[16]	auto[1]	auto[0]	105254	1			T29	11		T30	10		T32	25
bins_for_gpio_bits[16]	auto[1]	auto[1]	3096319	1			T29	159		T30	124		T31	17213
bins_for_gpio_bits[17]	auto[0]	auto[0]	3512039	1			T29	544		T30	189		T31	17543
bins_for_gpio_bits[17]	auto[0]	auto[1]	105325	1			T29	10		T30	9		T32	19
bins_for_gpio_bits[17]	auto[1]	auto[0]	105608	1			T29	10		T30	9		T32	20
bins_for_gpio_bits[17]	auto[1]	auto[1]	3079382	1			T29	121		T30	120		T31	16088
bins_for_gpio_bits[18]	auto[0]	auto[0]	3500685	1			T29	523		T30	201		T31	17099
bins_for_gpio_bits[18]	auto[0]	auto[1]	104895	1			T29	13		T30	6		T32	17
bins_for_gpio_bits[18]	auto[1]	auto[0]	105187	1			T29	13		T30	7		T32	18
bins_for_gpio_bits[18]	auto[1]	auto[1]	3091587	1			T29	136		T30	113		T31	16532
bins_for_gpio_bits[19]	auto[0]	auto[0]	3508167	1			T29	479		T30	193		T31	17133
bins_for_gpio_bits[19]	auto[0]	auto[1]	104805	1			T29	19		T30	8		T32	16
bins_for_gpio_bits[19]	auto[1]	auto[0]	105076	1			T29	19		T30	8		T32	16
bins_for_gpio_bits[19]	auto[1]	auto[1]	3084306	1			T29	168		T30	118		T31	16498
bins_for_gpio_bits[20]	auto[0]	auto[0]	3496695	1			T29	521		T30	177		T31	16902
bins_for_gpio_bits[20]	auto[0]	auto[1]	104918	1			T29	13		T30	9		T32	19
bins_for_gpio_bits[20]	auto[1]	auto[0]	105217	1			T29	13		T30	10		T32	19
bins_for_gpio_bits[20]	auto[1]	auto[1]	3095524	1			T29	138		T30	131		T31	16729
bins_for_gpio_bits[21]	auto[0]	auto[0]	3504277	1			T29	538		T30	184		T31	17419
bins_for_gpio_bits[21]	auto[0]	auto[1]	104921	1			T29	11		T30	7		T32	16
bins_for_gpio_bits[21]	auto[1]	auto[0]	105201	1			T29	11		T30	7		T32	16
bins_for_gpio_bits[21]	auto[1]	auto[1]	3087955	1			T29	125		T30	129		T31	16212
bins_for_gpio_bits[22]	auto[0]	auto[0]	3496827	1			T29	455		T30	200		T31	16897
bins_for_gpio_bits[22]	auto[0]	auto[1]	105339	1			T29	17		T30	10		T32	23
bins_for_gpio_bits[22]	auto[1]	auto[0]	105577	1			T29	17		T30	11		T32	23
bins_for_gpio_bits[22]	auto[1]	auto[1]	3094611	1			T29	196		T30	106		T31	16734
bins_for_gpio_bits[23]	auto[0]	auto[0]	3508093	1			T29	523		T30	169		T31	18792
bins_for_gpio_bits[23]	auto[0]	auto[1]	104945	1			T29	16		T30	9		T32	20
bins_for_gpio_bits[23]	auto[1]	auto[0]	105214	1			T29	16		T30	10		T32	20
bins_for_gpio_bits[23]	auto[1]	auto[1]	3084102	1			T29	130		T30	139		T31	14839
bins_for_gpio_bits[24]	auto[0]	auto[0]	3498041	1			T29	504		T30	179		T31	15462
bins_for_gpio_bits[24]	auto[0]	auto[1]	104834	1			T29	18		T30	8		T32	15
bins_for_gpio_bits[24]	auto[1]	auto[0]	105083	1			T29	18		T30	8		T32	15
bins_for_gpio_bits[24]	auto[1]	auto[1]	3094396	1			T29	145		T30	132		T31	18169
bins_for_gpio_bits[25]	auto[0]	auto[0]	3499369	1			T29	520		T30	199		T31	15776
bins_for_gpio_bits[25]	auto[0]	auto[1]	104647	1			T29	15		T30	9		T32	21
bins_for_gpio_bits[25]	auto[1]	auto[0]	104984	1			T29	15		T30	9		T32	21
bins_for_gpio_bits[25]	auto[1]	auto[1]	3093354	1			T29	135		T30	110		T31	17855
bins_for_gpio_bits[26]	auto[0]	auto[0]	3509271	1			T29	520		T30	178		T31	16214
bins_for_gpio_bits[26]	auto[0]	auto[1]	104681	1			T29	14		T30	10		T32	20
bins_for_gpio_bits[26]	auto[1]	auto[0]	104992	1			T29	14		T30	11		T32	21
bins_for_gpio_bits[26]	auto[1]	auto[1]	3083410	1			T29	137		T30	128		T31	17417
bins_for_gpio_bits[27]	auto[0]	auto[0]	3495040	1			T29	525		T30	189		T31	16691
bins_for_gpio_bits[27]	auto[0]	auto[1]	104731	1			T29	13		T30	9		T32	22
bins_for_gpio_bits[27]	auto[1]	auto[0]	105009	1			T29	13		T30	9		T32	22
bins_for_gpio_bits[27]	auto[1]	auto[1]	3097574	1			T29	134		T30	120		T31	16940
bins_for_gpio_bits[28]	auto[0]	auto[0]	3502797	1			T29	550		T30	186		T31	16831
bins_for_gpio_bits[28]	auto[0]	auto[1]	104955	1			T29	10		T30	8		T32	23
bins_for_gpio_bits[28]	auto[1]	auto[0]	105188	1			T29	10		T30	8		T32	23
bins_for_gpio_bits[28]	auto[1]	auto[1]	3089414	1			T29	115		T30	125		T31	16800
bins_for_gpio_bits[29]	auto[0]	auto[0]	3509346	1			T29	539		T30	180		T31	16001
bins_for_gpio_bits[29]	auto[0]	auto[1]	105190	1			T29	10		T30	7		T32	21
bins_for_gpio_bits[29]	auto[1]	auto[0]	105495	1			T29	10		T30	8		T32	21
bins_for_gpio_bits[29]	auto[1]	auto[1]	3082323	1			T29	126		T30	132		T31	17630
bins_for_gpio_bits[30]	auto[0]	auto[0]	3499090	1			T29	498		T30	184		T31	16039
bins_for_gpio_bits[30]	auto[0]	auto[1]	104652	1			T29	19		T30	8		T32	14
bins_for_gpio_bits[30]	auto[1]	auto[0]	104919	1			T29	19		T30	8		T32	14
bins_for_gpio_bits[30]	auto[1]	auto[1]	3093693	1			T29	149		T30	127		T31	17592
bins_for_gpio_bits[31]	auto[0]	auto[0]	3498312	1			T29	528		T30	188		T31	17416
bins_for_gpio_bits[31]	auto[0]	auto[1]	105240	1			T29	13		T30	5		T32	20
bins_for_gpio_bits[31]	auto[1]	auto[0]	105478	1			T29	13		T30	6		T32	20
bins_for_gpio_bits[31]	auto[1]	auto[1]	3093324	1			T29	131		T30	128		T31	16215