Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4537935 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2312191 |
1 |
|
|
T1 |
31 |
|
T11 |
140 |
|
T12 |
25 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6555901 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
294225 |
1 |
|
|
T11 |
8 |
|
T15 |
4 |
|
T16 |
7161 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4532874 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2317252 |
1 |
|
|
T1 |
9 |
|
T11 |
117 |
|
T12 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1018746 |
1 |
|
|
T1 |
9 |
|
T11 |
41 |
|
T12 |
22 |
| auto[1] |
auto[0] |
auto[1] |
148485 |
1 |
|
|
T11 |
4 |
|
T15 |
2 |
|
T16 |
3347 |
| auto[1] |
auto[1] |
auto[0] |
1004281 |
1 |
|
|
T11 |
68 |
|
T15 |
28 |
|
T16 |
26252 |
| auto[1] |
auto[1] |
auto[1] |
145740 |
1 |
|
|
T11 |
4 |
|
T15 |
2 |
|
T16 |
3814 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4532262 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2317864 |
1 |
|
|
T1 |
9 |
|
T11 |
73 |
|
T12 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6554311 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
295815 |
1 |
|
|
T1 |
1 |
|
T11 |
9 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4523930 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2326196 |
1 |
|
|
T1 |
13 |
|
T11 |
128 |
|
T12 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1029734 |
1 |
|
|
T1 |
12 |
|
T11 |
75 |
|
T12 |
21 |
| auto[1] |
auto[0] |
auto[1] |
150089 |
1 |
|
|
T1 |
1 |
|
T11 |
7 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1000647 |
1 |
|
|
T11 |
44 |
|
T15 |
33 |
|
T16 |
25702 |
| auto[1] |
auto[1] |
auto[1] |
145726 |
1 |
|
|
T11 |
2 |
|
T15 |
3 |
|
T16 |
3879 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4528635 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2321491 |
1 |
|
|
T1 |
31 |
|
T11 |
106 |
|
T12 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6556020 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
294106 |
1 |
|
|
T11 |
11 |
|
T15 |
8 |
|
T16 |
7342 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4526922 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2323204 |
1 |
|
|
T1 |
17 |
|
T11 |
136 |
|
T12 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1022917 |
1 |
|
|
T1 |
17 |
|
T11 |
76 |
|
T12 |
30 |
| auto[1] |
auto[0] |
auto[1] |
148630 |
1 |
|
|
T11 |
4 |
|
T15 |
1 |
|
T16 |
3748 |
| auto[1] |
auto[1] |
auto[0] |
1006181 |
1 |
|
|
T11 |
49 |
|
T15 |
60 |
|
T16 |
24637 |
| auto[1] |
auto[1] |
auto[1] |
145476 |
1 |
|
|
T11 |
7 |
|
T15 |
7 |
|
T16 |
3594 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4518584 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2331542 |
1 |
|
|
T1 |
32 |
|
T11 |
138 |
|
T12 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6553822 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
296304 |
1 |
|
|
T1 |
1 |
|
T11 |
6 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4515578 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2334548 |
1 |
|
|
T1 |
4 |
|
T11 |
117 |
|
T12 |
50 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1023147 |
1 |
|
|
T1 |
3 |
|
T11 |
43 |
|
T12 |
41 |
| auto[1] |
auto[0] |
auto[1] |
148965 |
1 |
|
|
T1 |
1 |
|
T11 |
3 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1015097 |
1 |
|
|
T11 |
68 |
|
T12 |
8 |
|
T15 |
26 |
| auto[1] |
auto[1] |
auto[1] |
147339 |
1 |
|
|
T11 |
3 |
|
T15 |
5 |
|
T16 |
3620 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4527574 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2322552 |
1 |
|
|
T1 |
17 |
|
T11 |
98 |
|
T12 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6554701 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
295425 |
1 |
|
|
T11 |
4 |
|
T15 |
4 |
|
T16 |
7483 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4524230 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2325896 |
1 |
|
|
T1 |
17 |
|
T11 |
87 |
|
T12 |
46 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1018694 |
1 |
|
|
T1 |
13 |
|
T11 |
42 |
|
T12 |
31 |
| auto[1] |
auto[0] |
auto[1] |
148049 |
1 |
|
|
T11 |
3 |
|
T16 |
3589 |
|
T17 |
853 |
| auto[1] |
auto[1] |
auto[0] |
1011777 |
1 |
|
|
T1 |
4 |
|
T11 |
41 |
|
T12 |
15 |
| auto[1] |
auto[1] |
auto[1] |
147376 |
1 |
|
|
T11 |
1 |
|
T15 |
4 |
|
T16 |
3894 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4511317 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2338809 |
1 |
|
|
T1 |
36 |
|
T11 |
123 |
|
T12 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6556111 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
294015 |
1 |
|
|
T1 |
1 |
|
T11 |
7 |
|
T15 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4528024 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2322102 |
1 |
|
|
T1 |
4 |
|
T11 |
76 |
|
T12 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1010987 |
1 |
|
|
T1 |
3 |
|
T11 |
21 |
|
T12 |
19 |
| auto[1] |
auto[0] |
auto[1] |
146082 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T15 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1017100 |
1 |
|
|
T11 |
48 |
|
T12 |
6 |
|
T15 |
58 |
| auto[1] |
auto[1] |
auto[1] |
147933 |
1 |
|
|
T11 |
6 |
|
T15 |
2 |
|
T16 |
3769 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4517413 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2332713 |
1 |
|
|
T1 |
8 |
|
T11 |
159 |
|
T12 |
37 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6554827 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
295299 |
1 |
|
|
T11 |
9 |
|
T15 |
5 |
|
T16 |
7107 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4520503 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2329623 |
1 |
|
|
T1 |
9 |
|
T11 |
128 |
|
T12 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1018075 |
1 |
|
|
T1 |
9 |
|
T11 |
23 |
|
T12 |
25 |
| auto[1] |
auto[0] |
auto[1] |
147912 |
1 |
|
|
T11 |
3 |
|
T15 |
2 |
|
T16 |
3586 |
| auto[1] |
auto[1] |
auto[0] |
1016249 |
1 |
|
|
T11 |
96 |
|
T12 |
13 |
|
T15 |
42 |
| auto[1] |
auto[1] |
auto[1] |
147387 |
1 |
|
|
T11 |
6 |
|
T15 |
3 |
|
T16 |
3521 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4530359 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2319767 |
1 |
|
|
T1 |
21 |
|
T11 |
109 |
|
T12 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6553704 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
296422 |
1 |
|
|
T11 |
10 |
|
T12 |
1 |
|
T15 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4518429 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2331697 |
1 |
|
|
T1 |
13 |
|
T11 |
129 |
|
T12 |
37 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1019395 |
1 |
|
|
T1 |
9 |
|
T11 |
70 |
|
T12 |
17 |
| auto[1] |
auto[0] |
auto[1] |
148482 |
1 |
|
|
T11 |
6 |
|
T12 |
1 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1015880 |
1 |
|
|
T1 |
4 |
|
T11 |
49 |
|
T12 |
19 |
| auto[1] |
auto[1] |
auto[1] |
147940 |
1 |
|
|
T11 |
4 |
|
T15 |
5 |
|
T16 |
3595 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4532834 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2317292 |
1 |
|
|
T1 |
11 |
|
T11 |
96 |
|
T12 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6555347 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
294779 |
1 |
|
|
T11 |
8 |
|
T12 |
1 |
|
T15 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4526357 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2323769 |
1 |
|
|
T1 |
13 |
|
T11 |
94 |
|
T12 |
22 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1023217 |
1 |
|
|
T1 |
13 |
|
T11 |
45 |
|
T12 |
16 |
| auto[1] |
auto[0] |
auto[1] |
148803 |
1 |
|
|
T11 |
3 |
|
T12 |
1 |
|
T15 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1005773 |
1 |
|
|
T11 |
41 |
|
T12 |
5 |
|
T15 |
23 |
| auto[1] |
auto[1] |
auto[1] |
145976 |
1 |
|
|
T11 |
5 |
|
T16 |
3550 |
|
T17 |
936 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4509876 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2340250 |
1 |
|
|
T1 |
17 |
|
T11 |
64 |
|
T12 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6554184 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
295942 |
1 |
|
|
T1 |
1 |
|
T11 |
10 |
|
T15 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4522656 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2327470 |
1 |
|
|
T1 |
13 |
|
T11 |
131 |
|
T12 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1012893 |
1 |
|
|
T1 |
9 |
|
T11 |
84 |
|
T12 |
10 |
| auto[1] |
auto[0] |
auto[1] |
147181 |
1 |
|
|
T11 |
8 |
|
T15 |
2 |
|
T16 |
3747 |
| auto[1] |
auto[1] |
auto[0] |
1018635 |
1 |
|
|
T1 |
3 |
|
T11 |
37 |
|
T12 |
14 |
| auto[1] |
auto[1] |
auto[1] |
148761 |
1 |
|
|
T1 |
1 |
|
T11 |
2 |
|
T16 |
3773 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4525573 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2324553 |
1 |
|
|
T1 |
14 |
|
T11 |
153 |
|
T12 |
52 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6557225 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
292901 |
1 |
|
|
T11 |
4 |
|
T15 |
1 |
|
T16 |
7226 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4533160 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2316966 |
1 |
|
|
T1 |
9 |
|
T11 |
67 |
|
T12 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1021016 |
1 |
|
|
T1 |
9 |
|
T11 |
20 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
147834 |
1 |
|
|
T11 |
3 |
|
T15 |
1 |
|
T16 |
3661 |
| auto[1] |
auto[1] |
auto[0] |
1003049 |
1 |
|
|
T11 |
43 |
|
T12 |
17 |
|
T15 |
16 |
| auto[1] |
auto[1] |
auto[1] |
145067 |
1 |
|
|
T11 |
1 |
|
T16 |
3565 |
|
T17 |
948 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4519525 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2330601 |
1 |
|
|
T1 |
14 |
|
T11 |
89 |
|
T12 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6555261 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
294865 |
1 |
|
|
T11 |
6 |
|
T12 |
1 |
|
T15 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4528832 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2321294 |
1 |
|
|
T1 |
17 |
|
T11 |
86 |
|
T12 |
37 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1011484 |
1 |
|
|
T1 |
17 |
|
T11 |
56 |
|
T12 |
36 |
| auto[1] |
auto[0] |
auto[1] |
147091 |
1 |
|
|
T11 |
4 |
|
T12 |
1 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1014945 |
1 |
|
|
T11 |
24 |
|
T15 |
68 |
|
T16 |
25912 |
| auto[1] |
auto[1] |
auto[1] |
147774 |
1 |
|
|
T11 |
2 |
|
T15 |
5 |
|
T16 |
3872 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4516876 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2333250 |
1 |
|
|
T1 |
7 |
|
T11 |
135 |
|
T12 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6556467 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
293659 |
1 |
|
|
T11 |
7 |
|
T15 |
5 |
|
T16 |
7213 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4538298 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2311828 |
1 |
|
|
T1 |
8 |
|
T11 |
98 |
|
T12 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1007299 |
1 |
|
|
T1 |
8 |
|
T11 |
26 |
|
T12 |
35 |
| auto[1] |
auto[0] |
auto[1] |
146359 |
1 |
|
|
T11 |
2 |
|
T15 |
1 |
|
T16 |
3745 |
| auto[1] |
auto[1] |
auto[0] |
1010870 |
1 |
|
|
T11 |
65 |
|
T12 |
5 |
|
T15 |
51 |
| auto[1] |
auto[1] |
auto[1] |
147300 |
1 |
|
|
T11 |
5 |
|
T15 |
4 |
|
T16 |
3468 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4531117 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2319009 |
1 |
|
|
T1 |
17 |
|
T11 |
133 |
|
T12 |
18 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6554950 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
295176 |
1 |
|
|
T11 |
10 |
|
T15 |
4 |
|
T16 |
6889 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4526447 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2323679 |
1 |
|
|
T1 |
8 |
|
T11 |
108 |
|
T12 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1020561 |
1 |
|
|
T1 |
8 |
|
T11 |
41 |
|
T12 |
20 |
| auto[1] |
auto[0] |
auto[1] |
148850 |
1 |
|
|
T11 |
2 |
|
T15 |
1 |
|
T16 |
3278 |
| auto[1] |
auto[1] |
auto[0] |
1007942 |
1 |
|
|
T11 |
57 |
|
T12 |
5 |
|
T15 |
32 |
| auto[1] |
auto[1] |
auto[1] |
146326 |
1 |
|
|
T11 |
8 |
|
T15 |
3 |
|
T16 |
3611 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4520408 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2329718 |
1 |
|
|
T1 |
32 |
|
T11 |
114 |
|
T12 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6555326 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
294800 |
1 |
|
|
T11 |
9 |
|
T12 |
1 |
|
T15 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4524467 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2325659 |
1 |
|
|
T1 |
4 |
|
T11 |
104 |
|
T12 |
50 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1013625 |
1 |
|
|
T11 |
42 |
|
T12 |
29 |
|
T15 |
19 |
| auto[1] |
auto[0] |
auto[1] |
146862 |
1 |
|
|
T11 |
6 |
|
T12 |
1 |
|
T16 |
3568 |
| auto[1] |
auto[1] |
auto[0] |
1017234 |
1 |
|
|
T1 |
4 |
|
T11 |
53 |
|
T12 |
20 |
| auto[1] |
auto[1] |
auto[1] |
147938 |
1 |
|
|
T11 |
3 |
|
T15 |
4 |
|
T16 |
3478 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4525157 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2324969 |
1 |
|
|
T1 |
11 |
|
T11 |
117 |
|
T12 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6555399 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
294727 |
1 |
|
|
T11 |
5 |
|
T15 |
8 |
|
T16 |
7563 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4532134 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2317992 |
1 |
|
|
T1 |
17 |
|
T11 |
115 |
|
T12 |
49 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1015991 |
1 |
|
|
T1 |
17 |
|
T11 |
62 |
|
T12 |
29 |
| auto[1] |
auto[0] |
auto[1] |
147260 |
1 |
|
|
T11 |
4 |
|
T15 |
3 |
|
T16 |
3911 |
| auto[1] |
auto[1] |
auto[0] |
1007274 |
1 |
|
|
T11 |
48 |
|
T12 |
20 |
|
T15 |
42 |
| auto[1] |
auto[1] |
auto[1] |
147467 |
1 |
|
|
T11 |
1 |
|
T15 |
5 |
|
T16 |
3652 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4533902 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2316224 |
1 |
|
|
T1 |
8 |
|
T11 |
107 |
|
T12 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6557114 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
293012 |
1 |
|
|
T11 |
12 |
|
T12 |
1 |
|
T15 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4530118 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2320008 |
1 |
|
|
T1 |
8 |
|
T11 |
162 |
|
T12 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1020613 |
1 |
|
|
T1 |
8 |
|
T11 |
78 |
|
T12 |
9 |
| auto[1] |
auto[0] |
auto[1] |
147691 |
1 |
|
|
T11 |
4 |
|
T15 |
10 |
|
T16 |
3631 |
| auto[1] |
auto[1] |
auto[0] |
1006383 |
1 |
|
|
T11 |
72 |
|
T12 |
21 |
|
T15 |
38 |
| auto[1] |
auto[1] |
auto[1] |
145321 |
1 |
|
|
T11 |
8 |
|
T12 |
1 |
|
T15 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4513060 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2337066 |
1 |
|
|
T1 |
4 |
|
T11 |
125 |
|
T12 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6557238 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
292888 |
1 |
|
|
T11 |
12 |
|
T15 |
7 |
|
T16 |
7648 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4538518 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2311608 |
1 |
|
|
T1 |
13 |
|
T11 |
115 |
|
T12 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1011974 |
1 |
|
|
T1 |
13 |
|
T11 |
48 |
|
T12 |
17 |
| auto[1] |
auto[0] |
auto[1] |
146632 |
1 |
|
|
T11 |
3 |
|
T15 |
2 |
|
T16 |
3830 |
| auto[1] |
auto[1] |
auto[0] |
1006746 |
1 |
|
|
T11 |
55 |
|
T12 |
18 |
|
T15 |
31 |
| auto[1] |
auto[1] |
auto[1] |
146256 |
1 |
|
|
T11 |
9 |
|
T15 |
5 |
|
T16 |
3818 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4520727 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2329399 |
1 |
|
|
T1 |
19 |
|
T11 |
107 |
|
T12 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6553689 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
296437 |
1 |
|
|
T11 |
9 |
|
T12 |
1 |
|
T15 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4520390 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2329736 |
1 |
|
|
T1 |
17 |
|
T11 |
119 |
|
T12 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1015000 |
1 |
|
|
T1 |
13 |
|
T11 |
62 |
|
T12 |
28 |
| auto[1] |
auto[0] |
auto[1] |
148483 |
1 |
|
|
T11 |
4 |
|
T15 |
2 |
|
T16 |
3672 |
| auto[1] |
auto[1] |
auto[0] |
1018299 |
1 |
|
|
T1 |
4 |
|
T11 |
48 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
147954 |
1 |
|
|
T11 |
5 |
|
T12 |
1 |
|
T15 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4518620 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2331506 |
1 |
|
|
T1 |
19 |
|
T11 |
79 |
|
T15 |
58 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6554756 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
295370 |
1 |
|
|
T11 |
10 |
|
T15 |
3 |
|
T16 |
7225 |