Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4528635 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2321491 |
1 |
|
|
T1 |
31 |
|
T11 |
106 |
|
T12 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5755840 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
1094286 |
1 |
|
|
T1 |
10 |
|
T11 |
38 |
|
T12 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4533724 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2316402 |
1 |
|
|
T1 |
13 |
|
T11 |
81 |
|
T12 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
618927 |
1 |
|
|
T1 |
3 |
|
T11 |
23 |
|
T12 |
9 |
| auto[1] |
auto[0] |
auto[1] |
551120 |
1 |
|
|
T1 |
3 |
|
T11 |
24 |
|
T12 |
21 |
| auto[1] |
auto[1] |
auto[0] |
603189 |
1 |
|
|
T11 |
20 |
|
T15 |
6 |
|
T16 |
18140 |
| auto[1] |
auto[1] |
auto[1] |
543166 |
1 |
|
|
T1 |
7 |
|
T11 |
14 |
|
T12 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |