Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4530359 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2319767 |
1 |
|
|
T1 |
21 |
|
T11 |
109 |
|
T12 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5748589 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
1101537 |
1 |
|
|
T1 |
10 |
|
T11 |
97 |
|
T12 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4514594 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2335532 |
1 |
|
|
T1 |
13 |
|
T11 |
162 |
|
T12 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
619685 |
1 |
|
|
T11 |
39 |
|
T12 |
5 |
|
T15 |
16 |
| auto[1] |
auto[0] |
auto[1] |
554240 |
1 |
|
|
T1 |
3 |
|
T11 |
61 |
|
T15 |
26 |
| auto[1] |
auto[1] |
auto[0] |
614310 |
1 |
|
|
T1 |
3 |
|
T11 |
26 |
|
T12 |
12 |
| auto[1] |
auto[1] |
auto[1] |
547297 |
1 |
|
|
T1 |
7 |
|
T11 |
36 |
|
T12 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |