Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4525157 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2324969 |
1 |
|
|
T1 |
11 |
|
T11 |
117 |
|
T12 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5747829 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
1102297 |
1 |
|
|
T1 |
15 |
|
T11 |
62 |
|
T12 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4514048 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2336078 |
1 |
|
|
T1 |
22 |
|
T11 |
115 |
|
T12 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
623725 |
1 |
|
|
T1 |
1 |
|
T11 |
33 |
|
T12 |
8 |
| auto[1] |
auto[0] |
auto[1] |
552164 |
1 |
|
|
T1 |
11 |
|
T11 |
22 |
|
T12 |
10 |
| auto[1] |
auto[1] |
auto[0] |
610056 |
1 |
|
|
T1 |
6 |
|
T11 |
20 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
550133 |
1 |
|
|
T1 |
4 |
|
T11 |
40 |
|
T12 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |