Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4513060 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2337066 |
1 |
|
|
T1 |
4 |
|
T11 |
125 |
|
T12 |
33 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5753265 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
1096861 |
1 |
|
|
T11 |
71 |
|
T12 |
33 |
|
T15 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4526271 |
1 |
|
|
T29 |
354 |
|
T30 |
259 |
|
T31 |
33631 |
| auto[1] |
2323855 |
1 |
|
|
T1 |
12 |
|
T11 |
120 |
|
T12 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
606648 |
1 |
|
|
T1 |
12 |
|
T11 |
23 |
|
T15 |
27 |
| auto[1] |
auto[0] |
auto[1] |
544108 |
1 |
|
|
T11 |
29 |
|
T12 |
20 |
|
T15 |
13 |
| auto[1] |
auto[1] |
auto[0] |
620346 |
1 |
|
|
T11 |
26 |
|
T12 |
6 |
|
T15 |
29 |
| auto[1] |
auto[1] |
auto[1] |
552753 |
1 |
|
|
T11 |
42 |
|
T12 |
13 |
|
T15 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |