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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 940
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T763 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1194236277 Aug 12 05:13:14 PM PDT 24 Aug 12 05:13:16 PM PDT 24 778061802 ps
T764 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3013043050 Aug 12 05:13:31 PM PDT 24 Aug 12 05:13:31 PM PDT 24 194767733 ps
T765 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2173221443 Aug 12 05:13:02 PM PDT 24 Aug 12 05:13:06 PM PDT 24 1338540019 ps
T766 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.982288615 Aug 12 05:13:22 PM PDT 24 Aug 12 05:13:23 PM PDT 24 29230365 ps
T99 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.290858684 Aug 12 05:13:22 PM PDT 24 Aug 12 05:13:23 PM PDT 24 36903543 ps
T83 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1636197324 Aug 12 05:13:12 PM PDT 24 Aug 12 05:13:13 PM PDT 24 15533612 ps
T767 /workspace/coverage/cover_reg_top/38.gpio_intr_test.3845685426 Aug 12 05:13:28 PM PDT 24 Aug 12 05:13:29 PM PDT 24 18648592 ps
T768 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3491539749 Aug 12 05:13:12 PM PDT 24 Aug 12 05:13:13 PM PDT 24 16636586 ps
T769 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1225615300 Aug 12 05:13:18 PM PDT 24 Aug 12 05:13:18 PM PDT 24 31841709 ps
T770 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1379667947 Aug 12 05:13:12 PM PDT 24 Aug 12 05:13:12 PM PDT 24 15281910 ps
T84 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1813296309 Aug 12 05:13:22 PM PDT 24 Aug 12 05:13:23 PM PDT 24 52431947 ps
T771 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2219136837 Aug 12 05:13:28 PM PDT 24 Aug 12 05:13:29 PM PDT 24 21496009 ps
T772 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3234998641 Aug 12 05:13:04 PM PDT 24 Aug 12 05:13:05 PM PDT 24 51381051 ps
T773 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3980102086 Aug 12 05:13:19 PM PDT 24 Aug 12 05:13:20 PM PDT 24 92144735 ps
T85 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.60129760 Aug 12 05:13:23 PM PDT 24 Aug 12 05:13:24 PM PDT 24 23142650 ps
T774 /workspace/coverage/cover_reg_top/32.gpio_intr_test.869080789 Aug 12 05:13:28 PM PDT 24 Aug 12 05:13:29 PM PDT 24 25424134 ps
T775 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2621201443 Aug 12 05:13:23 PM PDT 24 Aug 12 05:13:24 PM PDT 24 47204343 ps
T86 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2191148396 Aug 12 05:13:12 PM PDT 24 Aug 12 05:13:13 PM PDT 24 39176572 ps
T776 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.798891487 Aug 12 05:13:12 PM PDT 24 Aug 12 05:13:15 PM PDT 24 214316068 ps
T777 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4193400201 Aug 12 05:13:22 PM PDT 24 Aug 12 05:13:22 PM PDT 24 64533971 ps
T778 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.75598329 Aug 12 05:13:20 PM PDT 24 Aug 12 05:13:21 PM PDT 24 93174476 ps
T779 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4123953875 Aug 12 05:13:04 PM PDT 24 Aug 12 05:13:05 PM PDT 24 169376204 ps
T780 /workspace/coverage/cover_reg_top/11.gpio_intr_test.105794064 Aug 12 05:13:24 PM PDT 24 Aug 12 05:13:24 PM PDT 24 11724407 ps
T89 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3793933753 Aug 12 05:13:03 PM PDT 24 Aug 12 05:13:06 PM PDT 24 319254213 ps
T87 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3902911593 Aug 12 05:13:04 PM PDT 24 Aug 12 05:13:05 PM PDT 24 58986459 ps
T781 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2566784290 Aug 12 05:13:19 PM PDT 24 Aug 12 05:13:20 PM PDT 24 13805527 ps
T782 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.711902591 Aug 12 05:13:01 PM PDT 24 Aug 12 05:13:01 PM PDT 24 14258691 ps
T783 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3256311142 Aug 12 05:13:26 PM PDT 24 Aug 12 05:13:27 PM PDT 24 63013677 ps
T784 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3469555464 Aug 12 05:13:12 PM PDT 24 Aug 12 05:13:13 PM PDT 24 13384671 ps
T785 /workspace/coverage/cover_reg_top/47.gpio_intr_test.3650556055 Aug 12 05:13:26 PM PDT 24 Aug 12 05:13:27 PM PDT 24 14330251 ps
T786 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2144395202 Aug 12 05:13:07 PM PDT 24 Aug 12 05:13:07 PM PDT 24 55484056 ps
T787 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1500321700 Aug 12 05:13:22 PM PDT 24 Aug 12 05:13:22 PM PDT 24 16605120 ps
T788 /workspace/coverage/cover_reg_top/27.gpio_intr_test.884291725 Aug 12 05:13:26 PM PDT 24 Aug 12 05:13:27 PM PDT 24 15226811 ps
T789 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.469486403 Aug 12 05:13:24 PM PDT 24 Aug 12 05:13:25 PM PDT 24 19902383 ps
T790 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2696171001 Aug 12 05:13:02 PM PDT 24 Aug 12 05:13:03 PM PDT 24 14397466 ps
T88 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3580101134 Aug 12 05:13:12 PM PDT 24 Aug 12 05:13:13 PM PDT 24 12776461 ps
T791 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.4181149615 Aug 12 05:13:18 PM PDT 24 Aug 12 05:13:19 PM PDT 24 368512849 ps
T792 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.4055000999 Aug 12 05:13:21 PM PDT 24 Aug 12 05:13:23 PM PDT 24 169233888 ps
T793 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3526779306 Aug 12 05:13:03 PM PDT 24 Aug 12 05:13:04 PM PDT 24 136582697 ps
T794 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3852251445 Aug 12 05:13:28 PM PDT 24 Aug 12 05:13:29 PM PDT 24 33604814 ps
T795 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1942102123 Aug 12 05:13:04 PM PDT 24 Aug 12 05:13:06 PM PDT 24 48871943 ps
T90 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3434432459 Aug 12 05:13:21 PM PDT 24 Aug 12 05:13:22 PM PDT 24 12213241 ps
T796 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3488339712 Aug 12 05:13:03 PM PDT 24 Aug 12 05:13:05 PM PDT 24 38438009 ps
T797 /workspace/coverage/cover_reg_top/21.gpio_intr_test.3644979318 Aug 12 05:13:25 PM PDT 24 Aug 12 05:13:26 PM PDT 24 58475454 ps
T91 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.4046436645 Aug 12 05:13:14 PM PDT 24 Aug 12 05:13:15 PM PDT 24 19297671 ps
T798 /workspace/coverage/cover_reg_top/2.gpio_intr_test.599286341 Aug 12 05:13:05 PM PDT 24 Aug 12 05:13:06 PM PDT 24 12483094 ps
T92 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.844648133 Aug 12 05:13:03 PM PDT 24 Aug 12 05:13:04 PM PDT 24 114800800 ps
T799 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1634519320 Aug 12 05:13:23 PM PDT 24 Aug 12 05:13:24 PM PDT 24 12165035 ps
T800 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2045603115 Aug 12 05:13:26 PM PDT 24 Aug 12 05:13:27 PM PDT 24 57472806 ps
T801 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2906161424 Aug 12 05:13:12 PM PDT 24 Aug 12 05:13:14 PM PDT 24 479532730 ps
T802 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1963757741 Aug 12 05:13:28 PM PDT 24 Aug 12 05:13:29 PM PDT 24 32282672 ps
T803 /workspace/coverage/cover_reg_top/3.gpio_intr_test.4191328568 Aug 12 05:13:06 PM PDT 24 Aug 12 05:13:07 PM PDT 24 19544086 ps
T804 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1690120653 Aug 12 05:13:11 PM PDT 24 Aug 12 05:13:12 PM PDT 24 214469650 ps
T805 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4037056455 Aug 12 05:13:24 PM PDT 24 Aug 12 05:13:25 PM PDT 24 17138540 ps
T806 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2069132930 Aug 12 05:13:25 PM PDT 24 Aug 12 05:13:26 PM PDT 24 26681817 ps
T807 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3758743428 Aug 12 05:13:22 PM PDT 24 Aug 12 05:13:23 PM PDT 24 67750210 ps
T808 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1061759527 Aug 12 05:13:13 PM PDT 24 Aug 12 05:13:14 PM PDT 24 15479433 ps
T809 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1665265115 Aug 12 05:13:27 PM PDT 24 Aug 12 05:13:28 PM PDT 24 14030996 ps
T810 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.656352111 Aug 12 05:13:14 PM PDT 24 Aug 12 05:13:14 PM PDT 24 20812141 ps
T811 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.869064722 Aug 12 05:13:27 PM PDT 24 Aug 12 05:13:28 PM PDT 24 26628096 ps
T812 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2268850714 Aug 12 05:13:25 PM PDT 24 Aug 12 05:13:26 PM PDT 24 16403875 ps
T813 /workspace/coverage/cover_reg_top/48.gpio_intr_test.281095208 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:41 PM PDT 24 51105243 ps
T814 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3871014962 Aug 12 05:13:12 PM PDT 24 Aug 12 05:13:15 PM PDT 24 324387252 ps
T815 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2466559128 Aug 12 05:13:12 PM PDT 24 Aug 12 05:13:13 PM PDT 24 14328871 ps
T816 /workspace/coverage/cover_reg_top/19.gpio_intr_test.2103915871 Aug 12 05:13:27 PM PDT 24 Aug 12 05:13:28 PM PDT 24 15115488 ps
T817 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2181416455 Aug 12 05:13:19 PM PDT 24 Aug 12 05:13:21 PM PDT 24 346790476 ps
T818 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2330083113 Aug 12 05:13:24 PM PDT 24 Aug 12 05:13:26 PM PDT 24 35090274 ps
T819 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3266216157 Aug 12 05:13:22 PM PDT 24 Aug 12 05:13:23 PM PDT 24 530894935 ps
T820 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3861428384 Aug 12 05:13:21 PM PDT 24 Aug 12 05:13:21 PM PDT 24 24271280 ps
T821 /workspace/coverage/cover_reg_top/0.gpio_intr_test.13075158 Aug 12 05:13:05 PM PDT 24 Aug 12 05:13:06 PM PDT 24 129164860 ps
T822 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1948731507 Aug 12 05:13:11 PM PDT 24 Aug 12 05:13:12 PM PDT 24 261953293 ps
T823 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3436705848 Aug 12 05:13:21 PM PDT 24 Aug 12 05:13:22 PM PDT 24 25964913 ps
T93 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2075433905 Aug 12 05:13:04 PM PDT 24 Aug 12 05:13:05 PM PDT 24 63605194 ps
T824 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1379034949 Aug 12 05:13:13 PM PDT 24 Aug 12 05:13:14 PM PDT 24 33607495 ps
T825 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2828392217 Aug 12 05:13:04 PM PDT 24 Aug 12 05:13:06 PM PDT 24 189035012 ps
T826 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.159870696 Aug 12 05:13:04 PM PDT 24 Aug 12 05:13:05 PM PDT 24 78833526 ps
T827 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2720721956 Aug 12 05:13:13 PM PDT 24 Aug 12 05:13:14 PM PDT 24 346840194 ps
T828 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2236232992 Aug 12 05:13:04 PM PDT 24 Aug 12 05:13:05 PM PDT 24 14148965 ps
T829 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1185558156 Aug 12 05:13:27 PM PDT 24 Aug 12 05:13:27 PM PDT 24 71081733 ps
T830 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3176702554 Aug 12 05:13:06 PM PDT 24 Aug 12 05:13:07 PM PDT 24 63463391 ps
T831 /workspace/coverage/cover_reg_top/40.gpio_intr_test.880290524 Aug 12 05:13:28 PM PDT 24 Aug 12 05:13:29 PM PDT 24 18292468 ps
T832 /workspace/coverage/cover_reg_top/8.gpio_intr_test.471682299 Aug 12 05:13:14 PM PDT 24 Aug 12 05:13:15 PM PDT 24 16248817 ps
T833 /workspace/coverage/cover_reg_top/34.gpio_intr_test.387394407 Aug 12 05:13:25 PM PDT 24 Aug 12 05:13:26 PM PDT 24 26406516 ps
T834 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2785825112 Aug 12 05:13:03 PM PDT 24 Aug 12 05:13:04 PM PDT 24 59149358 ps
T835 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1066322995 Aug 12 05:13:22 PM PDT 24 Aug 12 05:13:23 PM PDT 24 55972357 ps
T836 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1686771226 Aug 12 05:13:14 PM PDT 24 Aug 12 05:13:15 PM PDT 24 76143686 ps
T837 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2977767761 Aug 12 05:13:12 PM PDT 24 Aug 12 05:13:14 PM PDT 24 47149358 ps
T838 /workspace/coverage/cover_reg_top/37.gpio_intr_test.736940964 Aug 12 05:13:28 PM PDT 24 Aug 12 05:13:29 PM PDT 24 27128813 ps
T839 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2749847446 Aug 12 05:13:20 PM PDT 24 Aug 12 05:13:21 PM PDT 24 154739447 ps
T840 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2631228206 Aug 12 05:13:11 PM PDT 24 Aug 12 05:13:12 PM PDT 24 24554675 ps
T841 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1406986482 Aug 12 05:13:38 PM PDT 24 Aug 12 05:13:39 PM PDT 24 93449978 ps
T842 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2623790465 Aug 12 05:13:44 PM PDT 24 Aug 12 05:13:46 PM PDT 24 66145900 ps
T843 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3908835214 Aug 12 05:13:47 PM PDT 24 Aug 12 05:13:48 PM PDT 24 57520932 ps
T844 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2689199607 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:42 PM PDT 24 112322198 ps
T845 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1801858601 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:44 PM PDT 24 70480192 ps
T846 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.441586774 Aug 12 05:13:40 PM PDT 24 Aug 12 05:13:41 PM PDT 24 54224010 ps
T847 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1341328283 Aug 12 05:13:47 PM PDT 24 Aug 12 05:13:48 PM PDT 24 30560808 ps
T848 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.17292739 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 46829138 ps
T849 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.428639376 Aug 12 05:13:40 PM PDT 24 Aug 12 05:13:42 PM PDT 24 64269694 ps
T850 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3772960784 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 63616305 ps
T851 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.477029396 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:42 PM PDT 24 56155302 ps
T852 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.275465310 Aug 12 05:13:44 PM PDT 24 Aug 12 05:13:45 PM PDT 24 66820475 ps
T853 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2693303831 Aug 12 05:13:47 PM PDT 24 Aug 12 05:13:49 PM PDT 24 106161777 ps
T854 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.857836931 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:43 PM PDT 24 1619947551 ps
T855 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3268929628 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:44 PM PDT 24 343312084 ps
T856 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2375578088 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:43 PM PDT 24 42746669 ps
T857 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2498937412 Aug 12 05:13:37 PM PDT 24 Aug 12 05:13:38 PM PDT 24 103378727 ps
T858 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2891493171 Aug 12 05:13:44 PM PDT 24 Aug 12 05:13:46 PM PDT 24 83865931 ps
T859 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3076996758 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:45 PM PDT 24 290644743 ps
T860 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1222034423 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:43 PM PDT 24 98334645 ps
T861 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4241289326 Aug 12 05:13:40 PM PDT 24 Aug 12 05:13:42 PM PDT 24 135478435 ps
T862 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.768094969 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:43 PM PDT 24 228507908 ps
T863 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1520692396 Aug 12 05:13:44 PM PDT 24 Aug 12 05:13:45 PM PDT 24 31544051 ps
T864 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2418253055 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:44 PM PDT 24 53749707 ps
T865 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1356492324 Aug 12 05:13:45 PM PDT 24 Aug 12 05:13:46 PM PDT 24 241766476 ps
T866 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.382527136 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:44 PM PDT 24 26491131 ps
T867 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2465162159 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 52477754 ps
T868 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2975374152 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:42 PM PDT 24 153801872 ps
T869 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3453194825 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:44 PM PDT 24 210632746 ps
T870 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1642760765 Aug 12 05:13:38 PM PDT 24 Aug 12 05:13:40 PM PDT 24 125155021 ps
T871 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.921954850 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 93606102 ps
T872 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2980396340 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 240884889 ps
T873 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.801135317 Aug 12 05:13:40 PM PDT 24 Aug 12 05:13:42 PM PDT 24 955016460 ps
T874 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2684037794 Aug 12 05:13:48 PM PDT 24 Aug 12 05:13:49 PM PDT 24 143859895 ps
T875 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3772144090 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:45 PM PDT 24 35192581 ps
T876 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2860471481 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:43 PM PDT 24 158892222 ps
T877 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2598321162 Aug 12 05:13:51 PM PDT 24 Aug 12 05:13:52 PM PDT 24 49554250 ps
T878 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3809291456 Aug 12 05:13:39 PM PDT 24 Aug 12 05:13:40 PM PDT 24 145540042 ps
T879 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3858415816 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 78734142 ps
T880 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.273358260 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 159483402 ps
T881 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2052096130 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:44 PM PDT 24 144006346 ps
T882 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2998780857 Aug 12 05:13:50 PM PDT 24 Aug 12 05:13:50 PM PDT 24 91856954 ps
T883 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3305087950 Aug 12 05:13:51 PM PDT 24 Aug 12 05:13:52 PM PDT 24 25405460 ps
T884 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3860345664 Aug 12 05:13:40 PM PDT 24 Aug 12 05:13:42 PM PDT 24 39205426 ps
T885 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4250042366 Aug 12 05:13:47 PM PDT 24 Aug 12 05:13:48 PM PDT 24 36385448 ps
T886 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4278919814 Aug 12 05:13:40 PM PDT 24 Aug 12 05:13:41 PM PDT 24 44964471 ps
T887 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3306983777 Aug 12 05:13:38 PM PDT 24 Aug 12 05:13:40 PM PDT 24 157951897 ps
T888 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1391884265 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 59090042 ps
T889 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.56055924 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:42 PM PDT 24 61756727 ps
T890 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1230963262 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:43 PM PDT 24 62142360 ps
T891 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2802134002 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 175488397 ps
T892 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2357045382 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 95544026 ps
T893 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1335102362 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:43 PM PDT 24 88104305 ps
T894 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3271412384 Aug 12 05:13:39 PM PDT 24 Aug 12 05:13:40 PM PDT 24 145269670 ps
T895 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1193374927 Aug 12 05:13:44 PM PDT 24 Aug 12 05:13:45 PM PDT 24 197028760 ps
T896 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4243165617 Aug 12 05:13:50 PM PDT 24 Aug 12 05:13:52 PM PDT 24 107144895 ps
T897 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2628699773 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:44 PM PDT 24 54834219 ps
T898 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3930304855 Aug 12 05:13:40 PM PDT 24 Aug 12 05:13:41 PM PDT 24 144069457 ps
T899 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.79201302 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:42 PM PDT 24 152368788 ps
T900 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4017182597 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:44 PM PDT 24 679831478 ps
T901 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.735762378 Aug 12 05:13:46 PM PDT 24 Aug 12 05:13:48 PM PDT 24 78713017 ps
T902 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.713424310 Aug 12 05:13:47 PM PDT 24 Aug 12 05:13:48 PM PDT 24 47805564 ps
T903 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2178652729 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:44 PM PDT 24 57331659 ps
T904 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1686616642 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:44 PM PDT 24 47190363 ps
T905 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2247081598 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:44 PM PDT 24 106565592 ps
T906 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1849531666 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:42 PM PDT 24 59805886 ps
T907 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2094660425 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 56378890 ps
T908 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3464630631 Aug 12 05:13:44 PM PDT 24 Aug 12 05:13:45 PM PDT 24 76229617 ps
T909 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.397935178 Aug 12 05:13:39 PM PDT 24 Aug 12 05:13:40 PM PDT 24 42765240 ps
T910 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.794288882 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:44 PM PDT 24 275215499 ps
T911 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.692583856 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 29267411 ps
T912 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4265740728 Aug 12 05:13:38 PM PDT 24 Aug 12 05:13:40 PM PDT 24 90695623 ps
T913 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.127700791 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:44 PM PDT 24 120768294 ps
T914 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3447005098 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:45 PM PDT 24 38535929 ps
T915 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.192461092 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:43 PM PDT 24 80419234 ps
T916 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1118653805 Aug 12 05:13:39 PM PDT 24 Aug 12 05:13:40 PM PDT 24 105625575 ps
T917 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.337640327 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:44 PM PDT 24 46017705 ps
T918 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.73643242 Aug 12 05:13:44 PM PDT 24 Aug 12 05:13:45 PM PDT 24 42388253 ps
T919 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3324137084 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:43 PM PDT 24 45055742 ps
T920 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2185985467 Aug 12 05:13:50 PM PDT 24 Aug 12 05:13:52 PM PDT 24 67023515 ps
T921 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1021984517 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:44 PM PDT 24 231183649 ps
T922 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.538104442 Aug 12 05:13:45 PM PDT 24 Aug 12 05:13:46 PM PDT 24 214851024 ps
T923 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2584822270 Aug 12 05:13:40 PM PDT 24 Aug 12 05:13:41 PM PDT 24 68921098 ps
T924 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2780703216 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:45 PM PDT 24 121391772 ps
T925 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1957832681 Aug 12 05:13:40 PM PDT 24 Aug 12 05:13:41 PM PDT 24 513067746 ps
T926 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1532688445 Aug 12 05:13:47 PM PDT 24 Aug 12 05:13:48 PM PDT 24 118357348 ps
T927 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1814088070 Aug 12 05:13:41 PM PDT 24 Aug 12 05:13:42 PM PDT 24 50452264 ps
T928 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1134381961 Aug 12 05:13:49 PM PDT 24 Aug 12 05:13:50 PM PDT 24 89277708 ps
T929 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1579304692 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 77912257 ps
T930 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.624898471 Aug 12 05:13:44 PM PDT 24 Aug 12 05:13:46 PM PDT 24 277614079 ps
T931 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2010266249 Aug 12 05:13:46 PM PDT 24 Aug 12 05:13:47 PM PDT 24 43798195 ps
T932 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4044358573 Aug 12 05:13:44 PM PDT 24 Aug 12 05:13:46 PM PDT 24 31985635 ps
T933 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.65373429 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:44 PM PDT 24 40798850 ps
T934 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3650043198 Aug 12 05:13:43 PM PDT 24 Aug 12 05:13:44 PM PDT 24 147460812 ps
T935 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.4202651658 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:44 PM PDT 24 291870881 ps
T936 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3496121263 Aug 12 05:13:40 PM PDT 24 Aug 12 05:13:42 PM PDT 24 151807142 ps
T937 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2787209204 Aug 12 05:13:42 PM PDT 24 Aug 12 05:13:43 PM PDT 24 105416151 ps
T938 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1310370522 Aug 12 05:13:47 PM PDT 24 Aug 12 05:13:48 PM PDT 24 64201956 ps
T939 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.594450009 Aug 12 05:13:47 PM PDT 24 Aug 12 05:13:48 PM PDT 24 56726264 ps
T940 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3142669036 Aug 12 05:13:49 PM PDT 24 Aug 12 05:13:50 PM PDT 24 116600263 ps

Test location /workspace/coverage/default/26.gpio_full_random.591712659
Short name T12
Test name
Test status
Simulation time 201208790 ps
CPU time 0.83 seconds
Started Aug 12 05:14:47 PM PDT 24
Finished Aug 12 05:14:48 PM PDT 24
Peak memory 196596 kb
Host smart-1204378a-2aac-49ca-9d21-1c9888212dd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591712659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.591712659
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2537339151
Short name T101
Test name
Test status
Simulation time 692560052 ps
CPU time 3.51 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:23 PM PDT 24
Peak memory 198028 kb
Host smart-0b147af3-49f1-463e-bbd2-b69c5bc8d3cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537339151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2537339151
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.27607938
Short name T17
Test name
Test status
Simulation time 6265896553 ps
CPU time 77.3 seconds
Started Aug 12 05:14:16 PM PDT 24
Finished Aug 12 05:15:33 PM PDT 24
Peak memory 198388 kb
Host smart-075846cf-19e1-48c6-bc49-c1ed0a2dc984
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=27607938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.27607938
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1710429900
Short name T40
Test name
Test status
Simulation time 69970624 ps
CPU time 0.86 seconds
Started Aug 12 05:13:51 PM PDT 24
Finished Aug 12 05:13:52 PM PDT 24
Peak memory 213908 kb
Host smart-b32fdf25-7153-448d-b90b-2fbbae2329f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710429900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1710429900
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1129328676
Short name T75
Test name
Test status
Simulation time 25308646 ps
CPU time 0.67 seconds
Started Aug 12 05:13:02 PM PDT 24
Finished Aug 12 05:13:03 PM PDT 24
Peak memory 194840 kb
Host smart-db7020fa-6c6c-4807-a9fc-0008ee71818f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129328676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1129328676
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2122976593
Short name T2
Test name
Test status
Simulation time 120004164648 ps
CPU time 77.16 seconds
Started Aug 12 05:14:47 PM PDT 24
Finished Aug 12 05:16:04 PM PDT 24
Peak memory 198328 kb
Host smart-675b2855-782f-4020-9319-fe0fc47b86bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122976593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2122976593
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3400335882
Short name T13
Test name
Test status
Simulation time 16046066 ps
CPU time 0.58 seconds
Started Aug 12 05:15:22 PM PDT 24
Finished Aug 12 05:15:23 PM PDT 24
Peak memory 194212 kb
Host smart-be77946d-ec94-492d-b432-c10a007a1a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400335882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3400335882
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3669698917
Short name T39
Test name
Test status
Simulation time 535743188 ps
CPU time 1.19 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 198528 kb
Host smart-204fe232-2099-430b-8d66-cf0cfe9fa587
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669698917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3669698917
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3266216157
Short name T819
Test name
Test status
Simulation time 530894935 ps
CPU time 1.39 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 198464 kb
Host smart-056e0b5d-013e-47fa-a259-7ec1be509977
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266216157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3266216157
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.918782361
Short name T72
Test name
Test status
Simulation time 42332693 ps
CPU time 0.66 seconds
Started Aug 12 05:13:15 PM PDT 24
Finished Aug 12 05:13:16 PM PDT 24
Peak memory 194864 kb
Host smart-dd2e2fbd-9363-4eef-ba43-27afa373b1af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918782361 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.918782361
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3424051151
Short name T15
Test name
Test status
Simulation time 53964273 ps
CPU time 0.91 seconds
Started Aug 12 05:13:53 PM PDT 24
Finished Aug 12 05:13:54 PM PDT 24
Peak memory 197436 kb
Host smart-7a492686-07b8-46dd-b351-759898c10fb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424051151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3424051151
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2471740952
Short name T37
Test name
Test status
Simulation time 310895384 ps
CPU time 1.2 seconds
Started Aug 12 05:13:20 PM PDT 24
Finished Aug 12 05:13:21 PM PDT 24
Peak memory 198484 kb
Host smart-5545da80-11e3-494d-b7b6-9cf631687178
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471740952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2471740952
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2075433905
Short name T93
Test name
Test status
Simulation time 63605194 ps
CPU time 0.88 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 197216 kb
Host smart-d010556e-083c-463a-ae97-95dc885fd755
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075433905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2075433905
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2173221443
Short name T765
Test name
Test status
Simulation time 1338540019 ps
CPU time 3.38 seconds
Started Aug 12 05:13:02 PM PDT 24
Finished Aug 12 05:13:06 PM PDT 24
Peak memory 197584 kb
Host smart-21ec59d8-e654-41e7-a093-189e5bd59d66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173221443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2173221443
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2144395202
Short name T786
Test name
Test status
Simulation time 55484056 ps
CPU time 0.63 seconds
Started Aug 12 05:13:07 PM PDT 24
Finished Aug 12 05:13:07 PM PDT 24
Peak memory 195820 kb
Host smart-ad03b122-7b2c-48a2-b0e9-402fb899d788
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144395202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2144395202
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2710435490
Short name T738
Test name
Test status
Simulation time 16218212 ps
CPU time 0.69 seconds
Started Aug 12 05:13:14 PM PDT 24
Finished Aug 12 05:13:15 PM PDT 24
Peak memory 197860 kb
Host smart-79e75880-b85d-4cfd-aaa7-c9752da9e9c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710435490 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2710435490
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.362807848
Short name T97
Test name
Test status
Simulation time 10687511 ps
CPU time 0.64 seconds
Started Aug 12 05:12:56 PM PDT 24
Finished Aug 12 05:12:57 PM PDT 24
Peak memory 195036 kb
Host smart-ce881388-8caf-4077-b6d2-92d2f85e39b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362807848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.362807848
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.13075158
Short name T821
Test name
Test status
Simulation time 129164860 ps
CPU time 0.6 seconds
Started Aug 12 05:13:05 PM PDT 24
Finished Aug 12 05:13:06 PM PDT 24
Peak memory 194120 kb
Host smart-eb547a90-c658-4150-be35-fa8673e0dfb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13075158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.13075158
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3234998641
Short name T772
Test name
Test status
Simulation time 51381051 ps
CPU time 0.78 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 196488 kb
Host smart-953e3ffe-eec0-4e8a-96d2-7fd8a0d04d2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234998641 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3234998641
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.159870696
Short name T826
Test name
Test status
Simulation time 78833526 ps
CPU time 1.16 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 198328 kb
Host smart-43ef5458-bdb2-445c-9a2e-a6665f0e91c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159870696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.159870696
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3488339712
Short name T796
Test name
Test status
Simulation time 38438009 ps
CPU time 0.88 seconds
Started Aug 12 05:13:03 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 198324 kb
Host smart-52520fcd-ec06-443a-be15-6ac8687f5f09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488339712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3488339712
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3176702554
Short name T830
Test name
Test status
Simulation time 63463391 ps
CPU time 0.67 seconds
Started Aug 12 05:13:06 PM PDT 24
Finished Aug 12 05:13:07 PM PDT 24
Peak memory 194948 kb
Host smart-3786425f-8fe8-414e-915e-26e56f509884
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176702554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3176702554
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2208301361
Short name T757
Test name
Test status
Simulation time 94426081 ps
CPU time 1.48 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:06 PM PDT 24
Peak memory 196940 kb
Host smart-4f18a095-fd86-42a9-b1e9-dd7e46953cc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208301361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2208301361
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.844648133
Short name T92
Test name
Test status
Simulation time 114800800 ps
CPU time 0.69 seconds
Started Aug 12 05:13:03 PM PDT 24
Finished Aug 12 05:13:04 PM PDT 24
Peak memory 195380 kb
Host smart-ee75729f-3b98-4dc2-ae92-8b595ae3fdd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844648133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.844648133
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4123953875
Short name T779
Test name
Test status
Simulation time 169376204 ps
CPU time 1.05 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 198276 kb
Host smart-5b217f6e-5300-4e2e-a9fc-bdb8373c627b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123953875 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4123953875
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3526779306
Short name T793
Test name
Test status
Simulation time 136582697 ps
CPU time 0.62 seconds
Started Aug 12 05:13:03 PM PDT 24
Finished Aug 12 05:13:04 PM PDT 24
Peak memory 194088 kb
Host smart-b7caa903-86a9-4887-9128-0954e0d47702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526779306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3526779306
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3574152715
Short name T79
Test name
Test status
Simulation time 20284444 ps
CPU time 0.88 seconds
Started Aug 12 05:13:02 PM PDT 24
Finished Aug 12 05:13:03 PM PDT 24
Peak memory 197452 kb
Host smart-8e335ae5-4fc4-48c1-b5ca-fa8e1012d0ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574152715 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3574152715
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2558450455
Short name T737
Test name
Test status
Simulation time 161088676 ps
CPU time 3.31 seconds
Started Aug 12 05:13:06 PM PDT 24
Finished Aug 12 05:13:09 PM PDT 24
Peak memory 198356 kb
Host smart-ca581f1a-5090-4206-b942-946eeaedb206
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558450455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2558450455
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3013204345
Short name T48
Test name
Test status
Simulation time 416037225 ps
CPU time 1.56 seconds
Started Aug 12 05:13:03 PM PDT 24
Finished Aug 12 05:13:04 PM PDT 24
Peak memory 198468 kb
Host smart-59647d61-f0f4-465d-a932-4bb60bdc1718
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013204345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3013204345
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.656352111
Short name T810
Test name
Test status
Simulation time 20812141 ps
CPU time 0.71 seconds
Started Aug 12 05:13:14 PM PDT 24
Finished Aug 12 05:13:14 PM PDT 24
Peak memory 197624 kb
Host smart-44b930aa-5e34-4d9e-a064-c24288a5b3ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656352111 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.656352111
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2191148396
Short name T86
Test name
Test status
Simulation time 39176572 ps
CPU time 0.59 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 194680 kb
Host smart-b64817da-e9a4-447e-a40d-0668d65e5ade
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191148396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2191148396
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1500321700
Short name T787
Test name
Test status
Simulation time 16605120 ps
CPU time 0.64 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:22 PM PDT 24
Peak memory 194152 kb
Host smart-0b3564d1-cab7-4cf4-b897-db13eae5938c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500321700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1500321700
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1590541128
Short name T731
Test name
Test status
Simulation time 636191295 ps
CPU time 2.87 seconds
Started Aug 12 05:13:20 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 198412 kb
Host smart-283f8f98-0464-469c-8ae0-7f6478b04d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590541128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1590541128
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.75598329
Short name T778
Test name
Test status
Simulation time 93174476 ps
CPU time 0.88 seconds
Started Aug 12 05:13:20 PM PDT 24
Finished Aug 12 05:13:21 PM PDT 24
Peak memory 198156 kb
Host smart-51912e4c-5b7c-470b-b857-bebb5e4b58a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75598329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.gpio_tl_intg_err.75598329
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2593512286
Short name T726
Test name
Test status
Simulation time 28035231 ps
CPU time 1.26 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 198600 kb
Host smart-a34f9971-c841-4f50-a6ae-9b1172c30ae4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593512286 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2593512286
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2566784290
Short name T781
Test name
Test status
Simulation time 13805527 ps
CPU time 0.59 seconds
Started Aug 12 05:13:19 PM PDT 24
Finished Aug 12 05:13:20 PM PDT 24
Peak memory 193764 kb
Host smart-a7eb5353-ab61-4d10-829c-2174fbaa3bce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566784290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2566784290
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.105794064
Short name T780
Test name
Test status
Simulation time 11724407 ps
CPU time 0.64 seconds
Started Aug 12 05:13:24 PM PDT 24
Finished Aug 12 05:13:24 PM PDT 24
Peak memory 194848 kb
Host smart-2aed0007-3068-4494-8a8e-4d2781ebc7cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105794064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.105794064
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2360156916
Short name T78
Test name
Test status
Simulation time 29657519 ps
CPU time 0.77 seconds
Started Aug 12 05:13:21 PM PDT 24
Finished Aug 12 05:13:22 PM PDT 24
Peak memory 196360 kb
Host smart-8c36946b-0506-4f9a-aae9-69bbad2362de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360156916 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2360156916
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.958347514
Short name T716
Test name
Test status
Simulation time 201637182 ps
CPU time 1.3 seconds
Started Aug 12 05:13:24 PM PDT 24
Finished Aug 12 05:13:25 PM PDT 24
Peak memory 198448 kb
Host smart-5bbb6e17-6c0b-47c7-9d81-0f0c3da69160
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958347514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.958347514
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.171251316
Short name T51
Test name
Test status
Simulation time 155987511 ps
CPU time 1.43 seconds
Started Aug 12 05:13:19 PM PDT 24
Finished Aug 12 05:13:21 PM PDT 24
Peak memory 198484 kb
Host smart-18ed9416-5e9a-469c-953e-119f8f9021f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171251316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.171251316
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.4181149615
Short name T791
Test name
Test status
Simulation time 368512849 ps
CPU time 1.03 seconds
Started Aug 12 05:13:18 PM PDT 24
Finished Aug 12 05:13:19 PM PDT 24
Peak memory 198340 kb
Host smart-9f4ecf92-0dea-48a9-926b-f884b5ab16c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181149615 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.4181149615
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2597508084
Short name T756
Test name
Test status
Simulation time 17869558 ps
CPU time 0.62 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 195692 kb
Host smart-46683c1f-b954-4809-bc7c-464b2be8862e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597508084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2597508084
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3954353511
Short name T735
Test name
Test status
Simulation time 34089567 ps
CPU time 0.63 seconds
Started Aug 12 05:13:19 PM PDT 24
Finished Aug 12 05:13:20 PM PDT 24
Peak memory 194228 kb
Host smart-86febbe6-a788-4da9-9f81-3c5d26eac671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954353511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3954353511
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3861428384
Short name T820
Test name
Test status
Simulation time 24271280 ps
CPU time 0.74 seconds
Started Aug 12 05:13:21 PM PDT 24
Finished Aug 12 05:13:21 PM PDT 24
Peak memory 196372 kb
Host smart-91993532-fb18-4e8d-841d-7b813e7d9fbc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861428384 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3861428384
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.4055000999
Short name T792
Test name
Test status
Simulation time 169233888 ps
CPU time 2.35 seconds
Started Aug 12 05:13:21 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 198556 kb
Host smart-551b88b2-bb47-4c78-8c4d-e3d41bab9a12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055000999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.4055000999
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1876573169
Short name T50
Test name
Test status
Simulation time 257989975 ps
CPU time 1.36 seconds
Started Aug 12 05:13:26 PM PDT 24
Finished Aug 12 05:13:28 PM PDT 24
Peak memory 198428 kb
Host smart-9eebff3f-9cb1-4d2b-937b-caaf777912f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876573169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1876573169
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2330083113
Short name T818
Test name
Test status
Simulation time 35090274 ps
CPU time 1.75 seconds
Started Aug 12 05:13:24 PM PDT 24
Finished Aug 12 05:13:26 PM PDT 24
Peak memory 198532 kb
Host smart-eda5b6e4-86eb-4db9-84dc-aad4a45ebab1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330083113 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2330083113
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1634519320
Short name T799
Test name
Test status
Simulation time 12165035 ps
CPU time 0.59 seconds
Started Aug 12 05:13:23 PM PDT 24
Finished Aug 12 05:13:24 PM PDT 24
Peak memory 193672 kb
Host smart-4deb7d43-1a40-49bf-9be0-3f6a7dd0f35f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634519320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1634519320
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2621201443
Short name T775
Test name
Test status
Simulation time 47204343 ps
CPU time 0.62 seconds
Started Aug 12 05:13:23 PM PDT 24
Finished Aug 12 05:13:24 PM PDT 24
Peak memory 194236 kb
Host smart-7b5d2f7c-10fd-475e-9bfb-44bda9c887b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621201443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2621201443
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3436705848
Short name T823
Test name
Test status
Simulation time 25964913 ps
CPU time 0.8 seconds
Started Aug 12 05:13:21 PM PDT 24
Finished Aug 12 05:13:22 PM PDT 24
Peak memory 197416 kb
Host smart-a6ec630f-def6-4cb4-a7ba-82bb32d3ce8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436705848 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3436705848
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4038716008
Short name T718
Test name
Test status
Simulation time 77863438 ps
CPU time 1.53 seconds
Started Aug 12 05:13:19 PM PDT 24
Finished Aug 12 05:13:21 PM PDT 24
Peak memory 198508 kb
Host smart-0321d9f7-73d0-4e85-bb6f-ad5341780e10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038716008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.4038716008
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.985791157
Short name T38
Test name
Test status
Simulation time 79881623 ps
CPU time 0.89 seconds
Started Aug 12 05:13:23 PM PDT 24
Finished Aug 12 05:13:24 PM PDT 24
Peak memory 198284 kb
Host smart-aa6abf47-f7a5-4986-a367-950bf8513dea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985791157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.985791157
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2749847446
Short name T839
Test name
Test status
Simulation time 154739447 ps
CPU time 0.79 seconds
Started Aug 12 05:13:20 PM PDT 24
Finished Aug 12 05:13:21 PM PDT 24
Peak memory 198280 kb
Host smart-a6d38b4d-bb38-47d2-9f9e-a31b8148bb6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749847446 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2749847446
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3434432459
Short name T90
Test name
Test status
Simulation time 12213241 ps
CPU time 0.61 seconds
Started Aug 12 05:13:21 PM PDT 24
Finished Aug 12 05:13:22 PM PDT 24
Peak memory 195248 kb
Host smart-09cfc483-86e5-4d32-81b3-34f70ab2d5f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434432459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3434432459
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1066322995
Short name T835
Test name
Test status
Simulation time 55972357 ps
CPU time 0.61 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 194048 kb
Host smart-818d2fa8-e8dc-4016-9d9a-dc7a84b7b0a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066322995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1066322995
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2969572768
Short name T95
Test name
Test status
Simulation time 93436564 ps
CPU time 0.77 seconds
Started Aug 12 05:13:20 PM PDT 24
Finished Aug 12 05:13:21 PM PDT 24
Peak memory 196516 kb
Host smart-9671f35e-018e-4dc2-815e-0b996ba83541
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969572768 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2969572768
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2181416455
Short name T817
Test name
Test status
Simulation time 346790476 ps
CPU time 1.99 seconds
Started Aug 12 05:13:19 PM PDT 24
Finished Aug 12 05:13:21 PM PDT 24
Peak memory 198508 kb
Host smart-85e025ed-021e-4aad-a841-a5752547e006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181416455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2181416455
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1776644470
Short name T751
Test name
Test status
Simulation time 29876332 ps
CPU time 1.41 seconds
Started Aug 12 05:13:20 PM PDT 24
Finished Aug 12 05:13:21 PM PDT 24
Peak memory 198520 kb
Host smart-7d53b8ff-2bef-4bb2-8dce-236bdc4cb0ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776644470 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1776644470
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1426006839
Short name T82
Test name
Test status
Simulation time 13921644 ps
CPU time 0.6 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 195440 kb
Host smart-52252b2f-0e92-4d16-bc06-b678475db351
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426006839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1426006839
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2045603115
Short name T800
Test name
Test status
Simulation time 57472806 ps
CPU time 0.61 seconds
Started Aug 12 05:13:26 PM PDT 24
Finished Aug 12 05:13:27 PM PDT 24
Peak memory 194200 kb
Host smart-24b517c7-d2df-4cba-88c3-7c2e5d457baa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045603115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2045603115
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1870347419
Short name T755
Test name
Test status
Simulation time 16229911 ps
CPU time 0.64 seconds
Started Aug 12 05:13:21 PM PDT 24
Finished Aug 12 05:13:22 PM PDT 24
Peak memory 195428 kb
Host smart-23952e76-2e83-434b-aea9-9a48bb8c0d09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870347419 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1870347419
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2369760058
Short name T754
Test name
Test status
Simulation time 570173817 ps
CPU time 2.72 seconds
Started Aug 12 05:13:21 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 198464 kb
Host smart-f23644f4-ef63-4d45-8d3d-7ed36a0416e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369760058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2369760058
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3758743428
Short name T807
Test name
Test status
Simulation time 67750210 ps
CPU time 0.9 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 198264 kb
Host smart-adc74590-f3bd-4291-9dad-625da289f0f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758743428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3758743428
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3980102086
Short name T773
Test name
Test status
Simulation time 92144735 ps
CPU time 0.72 seconds
Started Aug 12 05:13:19 PM PDT 24
Finished Aug 12 05:13:20 PM PDT 24
Peak memory 198348 kb
Host smart-640256ee-595b-411b-89e0-fb37a181a87c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980102086 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3980102086
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1813296309
Short name T84
Test name
Test status
Simulation time 52431947 ps
CPU time 0.63 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 195212 kb
Host smart-079ae1a2-d6ec-4615-bd3a-f583a08dacc5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813296309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1813296309
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.929525220
Short name T720
Test name
Test status
Simulation time 14233339 ps
CPU time 0.63 seconds
Started Aug 12 05:13:19 PM PDT 24
Finished Aug 12 05:13:20 PM PDT 24
Peak memory 194264 kb
Host smart-6bc4f995-e990-49da-a060-020eb1f365f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929525220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.929525220
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.869064722
Short name T811
Test name
Test status
Simulation time 26628096 ps
CPU time 0.74 seconds
Started Aug 12 05:13:27 PM PDT 24
Finished Aug 12 05:13:28 PM PDT 24
Peak memory 196324 kb
Host smart-dba4318a-426e-4ceb-9f79-30216b73ba49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869064722 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.869064722
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.982288615
Short name T766
Test name
Test status
Simulation time 29230365 ps
CPU time 1.4 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 198612 kb
Host smart-9a13fc88-58ae-44df-a919-2723eba74eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982288615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.982288615
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4002881728
Short name T45
Test name
Test status
Simulation time 130687956 ps
CPU time 1.17 seconds
Started Aug 12 05:13:26 PM PDT 24
Finished Aug 12 05:13:28 PM PDT 24
Peak memory 198408 kb
Host smart-b17662b4-52c6-4a03-a14e-cef968de975c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002881728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.4002881728
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.732135233
Short name T723
Test name
Test status
Simulation time 21898543 ps
CPU time 0.99 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 198232 kb
Host smart-fdd7371a-5364-4e67-8f42-9a9cf8c90ee2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732135233 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.732135233
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4193400201
Short name T777
Test name
Test status
Simulation time 64533971 ps
CPU time 0.63 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:22 PM PDT 24
Peak memory 194988 kb
Host smart-b03aec1c-0a5a-4e8f-8aa4-9f9046b04603
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193400201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.4193400201
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3908838805
Short name T734
Test name
Test status
Simulation time 107917991 ps
CPU time 0.59 seconds
Started Aug 12 05:13:21 PM PDT 24
Finished Aug 12 05:13:22 PM PDT 24
Peak memory 194740 kb
Host smart-e1cf3143-8e59-4c23-b48a-99085720c202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908838805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3908838805
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.469486403
Short name T789
Test name
Test status
Simulation time 19902383 ps
CPU time 0.86 seconds
Started Aug 12 05:13:24 PM PDT 24
Finished Aug 12 05:13:25 PM PDT 24
Peak memory 196788 kb
Host smart-57158d91-54e2-4040-9cf6-b1d048b6ebbf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469486403 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.469486403
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3256311142
Short name T783
Test name
Test status
Simulation time 63013677 ps
CPU time 1.56 seconds
Started Aug 12 05:13:26 PM PDT 24
Finished Aug 12 05:13:27 PM PDT 24
Peak memory 198416 kb
Host smart-1e49c9dd-5ae1-4777-955f-6fdf08b280b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256311142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3256311142
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3539515196
Short name T739
Test name
Test status
Simulation time 62420759 ps
CPU time 0.72 seconds
Started Aug 12 05:13:25 PM PDT 24
Finished Aug 12 05:13:26 PM PDT 24
Peak memory 191984 kb
Host smart-9d8119f7-b84b-4bf5-87ce-31053752a55c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539515196 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3539515196
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.60129760
Short name T85
Test name
Test status
Simulation time 23142650 ps
CPU time 0.59 seconds
Started Aug 12 05:13:23 PM PDT 24
Finished Aug 12 05:13:24 PM PDT 24
Peak memory 195116 kb
Host smart-45c9a583-d329-4a90-a62e-8f35a7560322
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60129760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_
csr_rw.60129760
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.435083242
Short name T746
Test name
Test status
Simulation time 15318456 ps
CPU time 0.63 seconds
Started Aug 12 05:13:21 PM PDT 24
Finished Aug 12 05:13:22 PM PDT 24
Peak memory 194208 kb
Host smart-7bc301ac-689b-46c8-9cb9-a798eb3ef2d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435083242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.435083242
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4037056455
Short name T805
Test name
Test status
Simulation time 17138540 ps
CPU time 0.75 seconds
Started Aug 12 05:13:24 PM PDT 24
Finished Aug 12 05:13:25 PM PDT 24
Peak memory 196512 kb
Host smart-43ce0fe5-60ff-44b6-886d-5e570180bdec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037056455 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.4037056455
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3146080644
Short name T750
Test name
Test status
Simulation time 29587509 ps
CPU time 1.5 seconds
Started Aug 12 05:13:18 PM PDT 24
Finished Aug 12 05:13:19 PM PDT 24
Peak memory 198524 kb
Host smart-752a002d-62fb-49e7-b968-32bd4381cb8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146080644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3146080644
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2931660651
Short name T47
Test name
Test status
Simulation time 92942769 ps
CPU time 0.85 seconds
Started Aug 12 05:13:27 PM PDT 24
Finished Aug 12 05:13:28 PM PDT 24
Peak memory 197516 kb
Host smart-6cf0c8a9-ccb3-4b09-aba0-9aba5e261f4f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931660651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2931660651
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1074810560
Short name T740
Test name
Test status
Simulation time 28021610 ps
CPU time 0.83 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 198336 kb
Host smart-ab1292bd-2f29-47af-b030-32a53ba1feb7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074810560 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1074810560
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2069132930
Short name T806
Test name
Test status
Simulation time 26681817 ps
CPU time 0.62 seconds
Started Aug 12 05:13:25 PM PDT 24
Finished Aug 12 05:13:26 PM PDT 24
Peak memory 195180 kb
Host smart-85f60038-854c-438b-a0c3-7fde63bf3eec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069132930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2069132930
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2103915871
Short name T816
Test name
Test status
Simulation time 15115488 ps
CPU time 0.62 seconds
Started Aug 12 05:13:27 PM PDT 24
Finished Aug 12 05:13:28 PM PDT 24
Peak memory 194164 kb
Host smart-682501bb-9a4d-4918-8f2a-f40e27fd80be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103915871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2103915871
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1151292968
Short name T70
Test name
Test status
Simulation time 33117768 ps
CPU time 0.83 seconds
Started Aug 12 05:13:18 PM PDT 24
Finished Aug 12 05:13:19 PM PDT 24
Peak memory 197336 kb
Host smart-2779d927-cc5e-49e0-a33d-6d9c06c469d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151292968 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1151292968
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1573580145
Short name T722
Test name
Test status
Simulation time 360670233 ps
CPU time 2.01 seconds
Started Aug 12 05:13:20 PM PDT 24
Finished Aug 12 05:13:22 PM PDT 24
Peak memory 198520 kb
Host smart-33ba7c3d-d336-40e1-9501-e1a5748c4e4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573580145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1573580145
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.290858684
Short name T99
Test name
Test status
Simulation time 36903543 ps
CPU time 0.85 seconds
Started Aug 12 05:13:22 PM PDT 24
Finished Aug 12 05:13:23 PM PDT 24
Peak memory 197384 kb
Host smart-81dcaf7c-b5f1-4e34-99cd-a1be2aa4b7f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290858684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.290858684
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1187190499
Short name T81
Test name
Test status
Simulation time 20621892 ps
CPU time 0.66 seconds
Started Aug 12 05:13:05 PM PDT 24
Finished Aug 12 05:13:06 PM PDT 24
Peak memory 194836 kb
Host smart-5567a875-b821-4d02-aa31-e4a38f470a5a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187190499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1187190499
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3793933753
Short name T89
Test name
Test status
Simulation time 319254213 ps
CPU time 2.95 seconds
Started Aug 12 05:13:03 PM PDT 24
Finished Aug 12 05:13:06 PM PDT 24
Peak memory 197228 kb
Host smart-8ee0ede0-c99b-4bbf-9cb3-eed97832a823
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793933753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3793933753
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.4046436645
Short name T91
Test name
Test status
Simulation time 19297671 ps
CPU time 0.61 seconds
Started Aug 12 05:13:14 PM PDT 24
Finished Aug 12 05:13:15 PM PDT 24
Peak memory 195396 kb
Host smart-dce18193-aa19-4887-8cbf-0f2363a96cd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046436645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.4046436645
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2785825112
Short name T834
Test name
Test status
Simulation time 59149358 ps
CPU time 1.09 seconds
Started Aug 12 05:13:03 PM PDT 24
Finished Aug 12 05:13:04 PM PDT 24
Peak memory 198624 kb
Host smart-7a7264ff-c6d6-4fe3-8289-d88a97c8456c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785825112 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2785825112
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2696171001
Short name T790
Test name
Test status
Simulation time 14397466 ps
CPU time 0.61 seconds
Started Aug 12 05:13:02 PM PDT 24
Finished Aug 12 05:13:03 PM PDT 24
Peak memory 194444 kb
Host smart-dcac9801-511c-4a85-a01c-e5b7641b9801
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696171001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2696171001
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.599286341
Short name T798
Test name
Test status
Simulation time 12483094 ps
CPU time 0.58 seconds
Started Aug 12 05:13:05 PM PDT 24
Finished Aug 12 05:13:06 PM PDT 24
Peak memory 194120 kb
Host smart-770bd810-1bc4-4548-8955-335ba8e887b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599286341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.599286341
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.248383578
Short name T94
Test name
Test status
Simulation time 17423423 ps
CPU time 0.79 seconds
Started Aug 12 05:13:05 PM PDT 24
Finished Aug 12 05:13:06 PM PDT 24
Peak memory 197388 kb
Host smart-c5d282a3-0991-4926-aceb-ac2f1ec4cc17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248383578 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.248383578
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1594368191
Short name T733
Test name
Test status
Simulation time 85150688 ps
CPU time 1.98 seconds
Started Aug 12 05:13:05 PM PDT 24
Finished Aug 12 05:13:07 PM PDT 24
Peak memory 198440 kb
Host smart-dbe4466e-8374-46e0-ae8f-ab06e19185e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594368191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1594368191
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2720721956
Short name T827
Test name
Test status
Simulation time 346840194 ps
CPU time 1.4 seconds
Started Aug 12 05:13:13 PM PDT 24
Finished Aug 12 05:13:14 PM PDT 24
Peak memory 198428 kb
Host smart-d4ace8c2-d06b-48e3-af0c-1ac5a8167631
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720721956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2720721956
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1963757741
Short name T802
Test name
Test status
Simulation time 32282672 ps
CPU time 0.62 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194212 kb
Host smart-446b96bf-d340-48b6-bcfe-c8ae5df7b2b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963757741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1963757741
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3644979318
Short name T797
Test name
Test status
Simulation time 58475454 ps
CPU time 0.64 seconds
Started Aug 12 05:13:25 PM PDT 24
Finished Aug 12 05:13:26 PM PDT 24
Peak memory 194212 kb
Host smart-81f619ff-acea-4326-8269-e3c2e8690be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644979318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3644979318
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1615822893
Short name T742
Test name
Test status
Simulation time 28971055 ps
CPU time 0.61 seconds
Started Aug 12 05:13:26 PM PDT 24
Finished Aug 12 05:13:27 PM PDT 24
Peak memory 194856 kb
Host smart-5f9a59a5-eae0-4094-ad3f-93619423d3a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615822893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1615822893
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1185558156
Short name T829
Test name
Test status
Simulation time 71081733 ps
CPU time 0.65 seconds
Started Aug 12 05:13:27 PM PDT 24
Finished Aug 12 05:13:27 PM PDT 24
Peak memory 194844 kb
Host smart-8fbd400a-72c5-43bc-a049-28bc99d23548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185558156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1185558156
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1134268207
Short name T743
Test name
Test status
Simulation time 39806677 ps
CPU time 0.59 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194144 kb
Host smart-cdf19d47-cd40-47b3-a8b4-e2c7a96b41f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134268207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1134268207
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3027518336
Short name T741
Test name
Test status
Simulation time 32961037 ps
CPU time 0.59 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194052 kb
Host smart-138497d9-063e-4d9a-a5dd-8fb003f9ed8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027518336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3027518336
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1665265115
Short name T809
Test name
Test status
Simulation time 14030996 ps
CPU time 0.62 seconds
Started Aug 12 05:13:27 PM PDT 24
Finished Aug 12 05:13:28 PM PDT 24
Peak memory 194872 kb
Host smart-592e937d-9600-4793-bd4e-c7dd3ffddf51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665265115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1665265115
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.884291725
Short name T788
Test name
Test status
Simulation time 15226811 ps
CPU time 0.62 seconds
Started Aug 12 05:13:26 PM PDT 24
Finished Aug 12 05:13:27 PM PDT 24
Peak memory 194144 kb
Host smart-5f5196bd-c606-494d-8046-4fc35b6e811b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884291725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.884291725
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1997782344
Short name T724
Test name
Test status
Simulation time 38023402 ps
CPU time 0.59 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194088 kb
Host smart-b4a74e2b-2b45-4903-8798-29fd15af229c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997782344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1997782344
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2219136837
Short name T771
Test name
Test status
Simulation time 21496009 ps
CPU time 0.6 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194844 kb
Host smart-e055953a-40cc-47ab-ad45-44bbbeda0132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219136837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2219136837
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3613503318
Short name T762
Test name
Test status
Simulation time 17326912 ps
CPU time 0.75 seconds
Started Aug 12 05:13:14 PM PDT 24
Finished Aug 12 05:13:15 PM PDT 24
Peak memory 196300 kb
Host smart-a9f3666c-9700-4954-b947-0faee014832c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613503318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3613503318
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2074977144
Short name T76
Test name
Test status
Simulation time 4975578101 ps
CPU time 3.31 seconds
Started Aug 12 05:13:02 PM PDT 24
Finished Aug 12 05:13:06 PM PDT 24
Peak memory 198520 kb
Host smart-acd12d4a-4629-4485-a93f-bd70a224bb11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074977144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2074977144
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3902911593
Short name T87
Test name
Test status
Simulation time 58986459 ps
CPU time 0.65 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 195964 kb
Host smart-67251efc-e9ff-4160-8d4f-ec61b5cf4867
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902911593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3902911593
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.433268721
Short name T745
Test name
Test status
Simulation time 42484702 ps
CPU time 1.86 seconds
Started Aug 12 05:13:14 PM PDT 24
Finished Aug 12 05:13:16 PM PDT 24
Peak memory 198540 kb
Host smart-4e4b42e8-3531-4929-b53b-bdaa37568e73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433268721 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.433268721
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.711902591
Short name T782
Test name
Test status
Simulation time 14258691 ps
CPU time 0.65 seconds
Started Aug 12 05:13:01 PM PDT 24
Finished Aug 12 05:13:01 PM PDT 24
Peak memory 195168 kb
Host smart-0e2c691d-0fec-411f-95a2-d7aa46c5aec9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711902591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.711902591
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.4191328568
Short name T803
Test name
Test status
Simulation time 19544086 ps
CPU time 0.64 seconds
Started Aug 12 05:13:06 PM PDT 24
Finished Aug 12 05:13:07 PM PDT 24
Peak memory 194124 kb
Host smart-0992da63-3b83-47a2-bb45-ee741347ac87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191328568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.4191328568
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.4191427309
Short name T74
Test name
Test status
Simulation time 15739537 ps
CPU time 0.68 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 195488 kb
Host smart-70edadc1-a26c-4cb4-95a8-e98c40263063
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191427309 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.4191427309
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2828392217
Short name T825
Test name
Test status
Simulation time 189035012 ps
CPU time 1.18 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:06 PM PDT 24
Peak memory 198284 kb
Host smart-f3840ee8-3dcd-41c5-a161-a91564196727
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828392217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2828392217
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1942102123
Short name T795
Test name
Test status
Simulation time 48871943 ps
CPU time 0.9 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:06 PM PDT 24
Peak memory 197548 kb
Host smart-13a32c85-7cb7-43a0-aa2b-07318c85a6d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942102123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1942102123
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.747366941
Short name T736
Test name
Test status
Simulation time 25718812 ps
CPU time 0.65 seconds
Started Aug 12 05:13:32 PM PDT 24
Finished Aug 12 05:13:33 PM PDT 24
Peak memory 194192 kb
Host smart-5b6f0d30-e3a2-4e1a-a69e-cc88facf23c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747366941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.747366941
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.4279297393
Short name T744
Test name
Test status
Simulation time 14174867 ps
CPU time 0.61 seconds
Started Aug 12 05:13:26 PM PDT 24
Finished Aug 12 05:13:27 PM PDT 24
Peak memory 194240 kb
Host smart-58f94ed8-c2d1-4ae8-a5f6-70e03fab76b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279297393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.4279297393
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.869080789
Short name T774
Test name
Test status
Simulation time 25424134 ps
CPU time 0.64 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194804 kb
Host smart-45c13352-4487-47e4-b831-eb57a046c394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869080789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.869080789
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3978771955
Short name T727
Test name
Test status
Simulation time 22548214 ps
CPU time 0.58 seconds
Started Aug 12 05:13:27 PM PDT 24
Finished Aug 12 05:13:28 PM PDT 24
Peak memory 194176 kb
Host smart-01376ea2-93ec-4302-80e8-f89ac13dc9cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978771955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3978771955
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.387394407
Short name T833
Test name
Test status
Simulation time 26406516 ps
CPU time 0.6 seconds
Started Aug 12 05:13:25 PM PDT 24
Finished Aug 12 05:13:26 PM PDT 24
Peak memory 194040 kb
Host smart-e982da77-dba6-4a8b-aa0f-a4cd65dcc7cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387394407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.387394407
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.4156247878
Short name T717
Test name
Test status
Simulation time 38608102 ps
CPU time 0.58 seconds
Started Aug 12 05:13:27 PM PDT 24
Finished Aug 12 05:13:28 PM PDT 24
Peak memory 194140 kb
Host smart-df5c9089-a25e-44c0-aa94-c0a4675cae93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156247878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.4156247878
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3013043050
Short name T764
Test name
Test status
Simulation time 194767733 ps
CPU time 0.61 seconds
Started Aug 12 05:13:31 PM PDT 24
Finished Aug 12 05:13:31 PM PDT 24
Peak memory 194152 kb
Host smart-c80ab112-3999-41ed-9226-d8e57080a62a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013043050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3013043050
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.736940964
Short name T838
Test name
Test status
Simulation time 27128813 ps
CPU time 0.6 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194132 kb
Host smart-bb17d3cb-7508-413a-8b8b-5c4fde140888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736940964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.736940964
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3845685426
Short name T767
Test name
Test status
Simulation time 18648592 ps
CPU time 0.64 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194192 kb
Host smart-3986d437-d13e-4b67-b0e5-3404802132cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845685426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3845685426
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2268850714
Short name T812
Test name
Test status
Simulation time 16403875 ps
CPU time 0.72 seconds
Started Aug 12 05:13:25 PM PDT 24
Finished Aug 12 05:13:26 PM PDT 24
Peak memory 194280 kb
Host smart-24a83910-0813-4aa9-9159-b25d3ee7c4bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268850714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2268850714
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.416545725
Short name T98
Test name
Test status
Simulation time 57586726 ps
CPU time 0.82 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 196228 kb
Host smart-069ddf7a-f888-4a13-b604-73982d25103e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416545725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.416545725
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2906161424
Short name T801
Test name
Test status
Simulation time 479532730 ps
CPU time 1.46 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:14 PM PDT 24
Peak memory 198376 kb
Host smart-76808388-d3e1-481d-bbf4-606795ff8a26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906161424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2906161424
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1248068577
Short name T80
Test name
Test status
Simulation time 15144405 ps
CPU time 0.63 seconds
Started Aug 12 05:13:14 PM PDT 24
Finished Aug 12 05:13:15 PM PDT 24
Peak memory 195172 kb
Host smart-c9daa0a7-5422-4837-ba0d-b7e9e9d866fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248068577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1248068577
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2079469504
Short name T752
Test name
Test status
Simulation time 32044746 ps
CPU time 0.86 seconds
Started Aug 12 05:13:02 PM PDT 24
Finished Aug 12 05:13:03 PM PDT 24
Peak memory 198312 kb
Host smart-b11b6baa-1027-4ae3-b892-99957f9944ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079469504 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2079469504
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2236232992
Short name T828
Test name
Test status
Simulation time 14148965 ps
CPU time 0.6 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 194976 kb
Host smart-1a310260-ca19-462d-8273-6c8a1c12bb85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236232992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2236232992
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1188440696
Short name T730
Test name
Test status
Simulation time 134099272 ps
CPU time 0.62 seconds
Started Aug 12 05:13:14 PM PDT 24
Finished Aug 12 05:13:15 PM PDT 24
Peak memory 194852 kb
Host smart-dc74cd28-7923-47be-9816-6bcd52df9688
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188440696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1188440696
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.331837754
Short name T96
Test name
Test status
Simulation time 94776548 ps
CPU time 0.74 seconds
Started Aug 12 05:13:04 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 197180 kb
Host smart-b0ec0afa-3c56-4345-b44e-8c0bba5d7eec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331837754 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.331837754
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1194236277
Short name T763
Test name
Test status
Simulation time 778061802 ps
CPU time 2.23 seconds
Started Aug 12 05:13:14 PM PDT 24
Finished Aug 12 05:13:16 PM PDT 24
Peak memory 198436 kb
Host smart-f2224a0e-f777-4eb3-980b-086f1d4e9b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194236277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1194236277
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1422847724
Short name T49
Test name
Test status
Simulation time 109327642 ps
CPU time 1.1 seconds
Started Aug 12 05:13:03 PM PDT 24
Finished Aug 12 05:13:05 PM PDT 24
Peak memory 198492 kb
Host smart-bfd95c7c-cc63-4f81-9b59-b31faad84259
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422847724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1422847724
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.880290524
Short name T831
Test name
Test status
Simulation time 18292468 ps
CPU time 0.59 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194116 kb
Host smart-f9dfb763-f347-43de-818a-4719166ca447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880290524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.880290524
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3852251445
Short name T794
Test name
Test status
Simulation time 33604814 ps
CPU time 0.59 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194004 kb
Host smart-90a003d2-03f2-4acb-8c3f-cc13ff90710d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852251445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3852251445
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2053450320
Short name T721
Test name
Test status
Simulation time 12602412 ps
CPU time 0.61 seconds
Started Aug 12 05:13:32 PM PDT 24
Finished Aug 12 05:13:33 PM PDT 24
Peak memory 194780 kb
Host smart-f31af172-7cd1-4759-bd8e-d023958019f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053450320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2053450320
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.4007854488
Short name T728
Test name
Test status
Simulation time 84269511 ps
CPU time 0.62 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:28 PM PDT 24
Peak memory 194820 kb
Host smart-62861573-526a-4399-8c7d-f5e3f7a0823e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007854488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4007854488
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3834410199
Short name T748
Test name
Test status
Simulation time 34885331 ps
CPU time 0.56 seconds
Started Aug 12 05:13:26 PM PDT 24
Finished Aug 12 05:13:27 PM PDT 24
Peak memory 194136 kb
Host smart-68d0374c-cc29-46cb-8914-e861dafc36f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834410199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3834410199
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.4286033064
Short name T753
Test name
Test status
Simulation time 34079513 ps
CPU time 0.59 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194760 kb
Host smart-4df44e82-8332-47d8-b8af-9d7a00be60af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286033064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.4286033064
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3759694859
Short name T725
Test name
Test status
Simulation time 12156687 ps
CPU time 0.6 seconds
Started Aug 12 05:13:28 PM PDT 24
Finished Aug 12 05:13:29 PM PDT 24
Peak memory 194232 kb
Host smart-b175088e-b9bf-4845-9c59-53ffc269d4a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759694859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3759694859
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3650556055
Short name T785
Test name
Test status
Simulation time 14330251 ps
CPU time 0.62 seconds
Started Aug 12 05:13:26 PM PDT 24
Finished Aug 12 05:13:27 PM PDT 24
Peak memory 194932 kb
Host smart-643e0197-8cf2-4b3e-bba7-7d38fa107694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650556055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3650556055
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.281095208
Short name T813
Test name
Test status
Simulation time 51105243 ps
CPU time 0.63 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:41 PM PDT 24
Peak memory 194180 kb
Host smart-1c58409b-fbf9-410e-89d0-ee56d690b446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281095208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.281095208
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3284218233
Short name T732
Test name
Test status
Simulation time 26107660 ps
CPU time 0.62 seconds
Started Aug 12 05:13:39 PM PDT 24
Finished Aug 12 05:13:40 PM PDT 24
Peak memory 194956 kb
Host smart-2a40f786-16fa-46fc-9011-6f7d4d58242c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284218233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3284218233
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3322488888
Short name T729
Test name
Test status
Simulation time 46995532 ps
CPU time 0.78 seconds
Started Aug 12 05:13:11 PM PDT 24
Finished Aug 12 05:13:12 PM PDT 24
Peak memory 198360 kb
Host smart-ba4fb200-6b46-462f-9e9c-7c6d809a4181
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322488888 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3322488888
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1636197324
Short name T83
Test name
Test status
Simulation time 15533612 ps
CPU time 0.62 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 195316 kb
Host smart-d797d84e-646e-437b-b30f-fed70a544ae6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636197324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1636197324
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2466559128
Short name T815
Test name
Test status
Simulation time 14328871 ps
CPU time 0.64 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 194240 kb
Host smart-0bee5926-ca6c-4086-a9aa-1c76b5aa8fca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466559128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2466559128
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1225615300
Short name T769
Test name
Test status
Simulation time 31841709 ps
CPU time 0.67 seconds
Started Aug 12 05:13:18 PM PDT 24
Finished Aug 12 05:13:18 PM PDT 24
Peak memory 194888 kb
Host smart-7ebbcb6c-ab39-42cc-b193-da20ae897193
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225615300 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1225615300
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3871014962
Short name T814
Test name
Test status
Simulation time 324387252 ps
CPU time 2.03 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:15 PM PDT 24
Peak memory 198424 kb
Host smart-a6841acb-d978-4f2e-9afb-eb7f972c7098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871014962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3871014962
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.392139699
Short name T760
Test name
Test status
Simulation time 140476774 ps
CPU time 1.18 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:14 PM PDT 24
Peak memory 198512 kb
Host smart-2055117e-04a4-4e3f-a4d6-bd50ef7e04bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392139699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.392139699
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2977767761
Short name T837
Test name
Test status
Simulation time 47149358 ps
CPU time 1.28 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:14 PM PDT 24
Peak memory 198572 kb
Host smart-e4af94f2-5504-409e-89e4-540c558dfa98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977767761 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2977767761
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3269452114
Short name T759
Test name
Test status
Simulation time 14123790 ps
CPU time 0.61 seconds
Started Aug 12 05:13:13 PM PDT 24
Finished Aug 12 05:13:14 PM PDT 24
Peak memory 195044 kb
Host smart-e7dbac70-2be3-4798-a613-47d3b7580466
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269452114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3269452114
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3469555464
Short name T784
Test name
Test status
Simulation time 13384671 ps
CPU time 0.57 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 194256 kb
Host smart-82aa3cde-a361-4d0f-8889-a72b0f4d4974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469555464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3469555464
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2634612766
Short name T71
Test name
Test status
Simulation time 223237308 ps
CPU time 0.84 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 196896 kb
Host smart-406a5103-76ff-4b15-9538-3f62a4e85211
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634612766 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2634612766
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1974542841
Short name T747
Test name
Test status
Simulation time 119473036 ps
CPU time 2.4 seconds
Started Aug 12 05:13:13 PM PDT 24
Finished Aug 12 05:13:16 PM PDT 24
Peak memory 198516 kb
Host smart-a27773fd-b8cc-4a8b-953f-3e427af46179
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974542841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1974542841
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.479700525
Short name T46
Test name
Test status
Simulation time 166370293 ps
CPU time 0.86 seconds
Started Aug 12 05:13:13 PM PDT 24
Finished Aug 12 05:13:14 PM PDT 24
Peak memory 197444 kb
Host smart-8967c580-5731-45a0-91a7-032d059e7627
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479700525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.479700525
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3512714268
Short name T758
Test name
Test status
Simulation time 169662104 ps
CPU time 1 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 198308 kb
Host smart-da693f62-a109-47e1-95f1-93424a4a746b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512714268 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3512714268
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3580101134
Short name T88
Test name
Test status
Simulation time 12776461 ps
CPU time 0.62 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 195212 kb
Host smart-3440d344-a1bf-4393-909a-9b92d6a3b88c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580101134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3580101134
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1061759527
Short name T808
Test name
Test status
Simulation time 15479433 ps
CPU time 0.63 seconds
Started Aug 12 05:13:13 PM PDT 24
Finished Aug 12 05:13:14 PM PDT 24
Peak memory 194212 kb
Host smart-4c98911f-20e6-449e-872c-b84323bbacdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061759527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1061759527
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1379034949
Short name T824
Test name
Test status
Simulation time 33607495 ps
CPU time 0.83 seconds
Started Aug 12 05:13:13 PM PDT 24
Finished Aug 12 05:13:14 PM PDT 24
Peak memory 197384 kb
Host smart-83cf4b6c-9c2d-4eac-a065-aa915a8921c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379034949 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1379034949
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1948731507
Short name T822
Test name
Test status
Simulation time 261953293 ps
CPU time 1.36 seconds
Started Aug 12 05:13:11 PM PDT 24
Finished Aug 12 05:13:12 PM PDT 24
Peak memory 198452 kb
Host smart-24639801-8af5-4115-a2c7-13e88af46a47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948731507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1948731507
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1686771226
Short name T836
Test name
Test status
Simulation time 76143686 ps
CPU time 1.16 seconds
Started Aug 12 05:13:14 PM PDT 24
Finished Aug 12 05:13:15 PM PDT 24
Peak memory 198500 kb
Host smart-0f694967-d84b-43dd-a273-1f2104b6b1f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686771226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1686771226
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3980664126
Short name T761
Test name
Test status
Simulation time 56563969 ps
CPU time 1.34 seconds
Started Aug 12 05:13:11 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 198556 kb
Host smart-646524ec-cc31-4bf0-8b72-238cd29cd9bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980664126 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3980664126
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3491539749
Short name T768
Test name
Test status
Simulation time 16636586 ps
CPU time 0.66 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 196016 kb
Host smart-43491c14-2fd5-45cd-96a1-c2c0a1b9b8cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491539749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3491539749
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.471682299
Short name T832
Test name
Test status
Simulation time 16248817 ps
CPU time 0.62 seconds
Started Aug 12 05:13:14 PM PDT 24
Finished Aug 12 05:13:15 PM PDT 24
Peak memory 194132 kb
Host smart-6828ef1d-9113-42f2-a770-1a0afbc719fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471682299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.471682299
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3970756987
Short name T73
Test name
Test status
Simulation time 29600397 ps
CPU time 0.76 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 196528 kb
Host smart-b8cae3da-0194-4531-b66d-0d917648e78f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970756987 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3970756987
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4220823953
Short name T749
Test name
Test status
Simulation time 93784803 ps
CPU time 1.2 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:13 PM PDT 24
Peak memory 198484 kb
Host smart-d796ef14-f4f8-4db0-8560-e5acd9c9a3cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220823953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.4220823953
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1690120653
Short name T804
Test name
Test status
Simulation time 214469650 ps
CPU time 1.37 seconds
Started Aug 12 05:13:11 PM PDT 24
Finished Aug 12 05:13:12 PM PDT 24
Peak memory 198468 kb
Host smart-303448d8-a38f-4070-8895-f8afd4ea8215
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690120653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1690120653
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1252363706
Short name T719
Test name
Test status
Simulation time 50352327 ps
CPU time 1.4 seconds
Started Aug 12 05:13:13 PM PDT 24
Finished Aug 12 05:13:15 PM PDT 24
Peak memory 198540 kb
Host smart-e43f9788-478a-46ac-bd95-b84f7f97bac2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252363706 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1252363706
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1379667947
Short name T770
Test name
Test status
Simulation time 15281910 ps
CPU time 0.72 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:12 PM PDT 24
Peak memory 195356 kb
Host smart-10c015a9-8bae-45db-94e9-5cf1ff7ba9d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379667947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1379667947
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2631228206
Short name T840
Test name
Test status
Simulation time 24554675 ps
CPU time 0.58 seconds
Started Aug 12 05:13:11 PM PDT 24
Finished Aug 12 05:13:12 PM PDT 24
Peak memory 194184 kb
Host smart-f773b1cd-e872-43da-a08b-c802d0c1dc5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631228206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2631228206
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3618939896
Short name T77
Test name
Test status
Simulation time 19214460 ps
CPU time 0.62 seconds
Started Aug 12 05:13:11 PM PDT 24
Finished Aug 12 05:13:12 PM PDT 24
Peak memory 195172 kb
Host smart-3da86d93-b029-471d-9028-c54e666ff236
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618939896 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3618939896
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.798891487
Short name T776
Test name
Test status
Simulation time 214316068 ps
CPU time 2.33 seconds
Started Aug 12 05:13:12 PM PDT 24
Finished Aug 12 05:13:15 PM PDT 24
Peak memory 198412 kb
Host smart-d228f423-f65c-434c-90fb-b70e8dbcca3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798891487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.798891487
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1419401706
Short name T234
Test name
Test status
Simulation time 71141888 ps
CPU time 0.57 seconds
Started Aug 12 05:13:51 PM PDT 24
Finished Aug 12 05:13:51 PM PDT 24
Peak memory 194716 kb
Host smart-71cf3409-ccbc-46f4-af90-1607661f98c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419401706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1419401706
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3275226039
Short name T382
Test name
Test status
Simulation time 325460708 ps
CPU time 0.81 seconds
Started Aug 12 05:13:51 PM PDT 24
Finished Aug 12 05:13:52 PM PDT 24
Peak memory 196096 kb
Host smart-e0868f75-f100-44c5-9b70-e34a66683e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275226039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3275226039
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3779830249
Short name T260
Test name
Test status
Simulation time 117438003 ps
CPU time 4.13 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:14:00 PM PDT 24
Peak memory 196764 kb
Host smart-286ea963-6341-4c99-986c-6a5dd4c89839
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779830249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3779830249
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1800607593
Short name T166
Test name
Test status
Simulation time 69614042 ps
CPU time 0.78 seconds
Started Aug 12 05:13:50 PM PDT 24
Finished Aug 12 05:13:51 PM PDT 24
Peak memory 195844 kb
Host smart-a9c79985-f0cd-4f0f-a87c-7c6427aad596
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800607593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1800607593
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1279462569
Short name T580
Test name
Test status
Simulation time 136068015 ps
CPU time 1.21 seconds
Started Aug 12 05:13:52 PM PDT 24
Finished Aug 12 05:13:53 PM PDT 24
Peak memory 197256 kb
Host smart-900b46d8-4c52-42ba-9315-a578e8e0ee7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279462569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1279462569
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3541210796
Short name T343
Test name
Test status
Simulation time 376401135 ps
CPU time 3.65 seconds
Started Aug 12 05:13:49 PM PDT 24
Finished Aug 12 05:13:53 PM PDT 24
Peak memory 198064 kb
Host smart-27350e29-bd70-4f37-94bd-0f7878e74408
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541210796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3541210796
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1031464060
Short name T696
Test name
Test status
Simulation time 104092688 ps
CPU time 2.05 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:13:58 PM PDT 24
Peak memory 196208 kb
Host smart-fc64ed71-0068-419f-be4d-86b4c8b319c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031464060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1031464060
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2465291322
Short name T25
Test name
Test status
Simulation time 185301205 ps
CPU time 1.02 seconds
Started Aug 12 05:13:49 PM PDT 24
Finished Aug 12 05:13:50 PM PDT 24
Peak memory 196036 kb
Host smart-49d7e6ea-0306-4d7f-b49c-31e4b0d49406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465291322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2465291322
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.421341278
Short name T606
Test name
Test status
Simulation time 362159076 ps
CPU time 1 seconds
Started Aug 12 05:13:49 PM PDT 24
Finished Aug 12 05:13:50 PM PDT 24
Peak memory 196044 kb
Host smart-73bd20ca-4a43-46c7-94b7-03dd0396e74c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421341278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.421341278
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2761760348
Short name T263
Test name
Test status
Simulation time 70813822 ps
CPU time 3.43 seconds
Started Aug 12 05:13:51 PM PDT 24
Finished Aug 12 05:13:55 PM PDT 24
Peak memory 198004 kb
Host smart-96c7931c-98e7-4539-814a-84977770e65c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761760348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2761760348
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.4149801889
Short name T443
Test name
Test status
Simulation time 96746445 ps
CPU time 0.95 seconds
Started Aug 12 05:13:51 PM PDT 24
Finished Aug 12 05:13:52 PM PDT 24
Peak memory 196280 kb
Host smart-5c34f234-e4cb-41b2-9e9f-9efe03056c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149801889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.4149801889
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3800154660
Short name T664
Test name
Test status
Simulation time 26583183 ps
CPU time 0.88 seconds
Started Aug 12 05:14:31 PM PDT 24
Finished Aug 12 05:14:32 PM PDT 24
Peak memory 196564 kb
Host smart-742b8fda-4232-4e53-a484-477be77fd75d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800154660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3800154660
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.4019915305
Short name T673
Test name
Test status
Simulation time 15975285012 ps
CPU time 175.99 seconds
Started Aug 12 05:13:53 PM PDT 24
Finished Aug 12 05:16:49 PM PDT 24
Peak memory 198220 kb
Host smart-bbf52396-096a-4917-9f46-6051f90d408b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019915305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.4019915305
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2070894609
Short name T675
Test name
Test status
Simulation time 16472365 ps
CPU time 0.6 seconds
Started Aug 12 05:13:52 PM PDT 24
Finished Aug 12 05:13:52 PM PDT 24
Peak memory 194756 kb
Host smart-38cafbcc-59ea-4c69-a68a-903fa162e4ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070894609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2070894609
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.53481500
Short name T295
Test name
Test status
Simulation time 79569112 ps
CPU time 0.66 seconds
Started Aug 12 05:13:50 PM PDT 24
Finished Aug 12 05:13:51 PM PDT 24
Peak memory 193992 kb
Host smart-23766022-7208-44cb-8776-4b48d0684f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53481500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.53481500
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2219611193
Short name T576
Test name
Test status
Simulation time 703315462 ps
CPU time 6.55 seconds
Started Aug 12 05:13:50 PM PDT 24
Finished Aug 12 05:13:57 PM PDT 24
Peak memory 198104 kb
Host smart-f01cd45f-7cd6-48db-8eed-226e685fe6b2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219611193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2219611193
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2200217496
Short name T525
Test name
Test status
Simulation time 86701115 ps
CPU time 1.1 seconds
Started Aug 12 05:13:47 PM PDT 24
Finished Aug 12 05:13:49 PM PDT 24
Peak memory 197960 kb
Host smart-c49582d2-1242-46ca-99c3-c84d2343b8d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200217496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2200217496
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.839320255
Short name T152
Test name
Test status
Simulation time 55331967 ps
CPU time 0.89 seconds
Started Aug 12 05:13:49 PM PDT 24
Finished Aug 12 05:13:50 PM PDT 24
Peak memory 196908 kb
Host smart-f51b2740-d19b-4382-98c8-687243c67a76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839320255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.839320255
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1702416840
Short name T630
Test name
Test status
Simulation time 151652497 ps
CPU time 3.12 seconds
Started Aug 12 05:13:55 PM PDT 24
Finished Aug 12 05:13:58 PM PDT 24
Peak memory 198172 kb
Host smart-be68dfc7-ccb9-4b52-8256-460bc6434190
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702416840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1702416840
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2811707959
Short name T446
Test name
Test status
Simulation time 78811755 ps
CPU time 1.67 seconds
Started Aug 12 05:13:52 PM PDT 24
Finished Aug 12 05:13:54 PM PDT 24
Peak memory 196036 kb
Host smart-87839fe7-7ea4-4186-9e2b-8a8c4f972be1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811707959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2811707959
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2575214814
Short name T24
Test name
Test status
Simulation time 44060371 ps
CPU time 1.05 seconds
Started Aug 12 05:13:51 PM PDT 24
Finished Aug 12 05:13:52 PM PDT 24
Peak memory 196804 kb
Host smart-a4d1cde6-b2c2-461e-af51-9daa7b817c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575214814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2575214814
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.846308120
Short name T671
Test name
Test status
Simulation time 421664476 ps
CPU time 0.99 seconds
Started Aug 12 05:13:49 PM PDT 24
Finished Aug 12 05:13:50 PM PDT 24
Peak memory 196648 kb
Host smart-360e4d61-b97e-4e72-8ed0-30c153c46772
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846308120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.846308120
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1330681550
Short name T6
Test name
Test status
Simulation time 501928135 ps
CPU time 1.34 seconds
Started Aug 12 05:13:59 PM PDT 24
Finished Aug 12 05:14:01 PM PDT 24
Peak memory 197944 kb
Host smart-0087de74-b5d4-4eb1-975a-b2bdcee0f09e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330681550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1330681550
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3756696989
Short name T53
Test name
Test status
Simulation time 720636043 ps
CPU time 0.77 seconds
Started Aug 12 05:13:52 PM PDT 24
Finished Aug 12 05:13:53 PM PDT 24
Peak memory 213880 kb
Host smart-df99d71a-5f46-47f5-8c51-e77f754834b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756696989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3756696989
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.4223495163
Short name T215
Test name
Test status
Simulation time 105964748 ps
CPU time 0.85 seconds
Started Aug 12 05:13:49 PM PDT 24
Finished Aug 12 05:13:50 PM PDT 24
Peak memory 196056 kb
Host smart-3497b517-61ed-48bc-9e5a-722cb7011b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223495163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.4223495163
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2214177804
Short name T700
Test name
Test status
Simulation time 77423379 ps
CPU time 1.4 seconds
Started Aug 12 05:13:51 PM PDT 24
Finished Aug 12 05:13:53 PM PDT 24
Peak memory 196652 kb
Host smart-2093ca5a-a81b-4e4e-8f9a-18d510aad5b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214177804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2214177804
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1185435485
Short name T233
Test name
Test status
Simulation time 88277010433 ps
CPU time 203.23 seconds
Started Aug 12 05:13:50 PM PDT 24
Finished Aug 12 05:17:14 PM PDT 24
Peak memory 198008 kb
Host smart-db5d1d02-82c2-4813-9e21-ab409c5743c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185435485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1185435485
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.1394076817
Short name T329
Test name
Test status
Simulation time 5937724825 ps
CPU time 19.71 seconds
Started Aug 12 05:13:53 PM PDT 24
Finished Aug 12 05:14:13 PM PDT 24
Peak memory 198388 kb
Host smart-c074ee3f-9de0-41cf-a5b9-b774c070b866
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1394076817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.1394076817
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1730716965
Short name T409
Test name
Test status
Simulation time 46345945 ps
CPU time 0.58 seconds
Started Aug 12 05:14:19 PM PDT 24
Finished Aug 12 05:14:20 PM PDT 24
Peak memory 194908 kb
Host smart-9e6d233e-262c-4e98-a8c0-c0366928983a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730716965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1730716965
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.91203810
Short name T629
Test name
Test status
Simulation time 37190616 ps
CPU time 0.71 seconds
Started Aug 12 05:14:11 PM PDT 24
Finished Aug 12 05:14:12 PM PDT 24
Peak memory 196036 kb
Host smart-d8d478d2-64af-469e-80cc-162b170785c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91203810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.91203810
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3645410320
Short name T161
Test name
Test status
Simulation time 542359707 ps
CPU time 26.33 seconds
Started Aug 12 05:14:14 PM PDT 24
Finished Aug 12 05:14:40 PM PDT 24
Peak memory 198020 kb
Host smart-2c7982df-24b3-4a0f-9350-cee4f6a73537
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645410320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3645410320
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2974762790
Short name T685
Test name
Test status
Simulation time 26786936 ps
CPU time 0.64 seconds
Started Aug 12 05:14:12 PM PDT 24
Finished Aug 12 05:14:13 PM PDT 24
Peak memory 194448 kb
Host smart-fedf6732-3f75-4dfd-9d34-cbf6a2ea921a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974762790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2974762790
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2221138069
Short name T361
Test name
Test status
Simulation time 111652707 ps
CPU time 0.8 seconds
Started Aug 12 05:14:13 PM PDT 24
Finished Aug 12 05:14:14 PM PDT 24
Peak memory 195552 kb
Host smart-9febd60c-cff3-469a-835e-399af5d58cea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221138069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2221138069
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1016127387
Short name T611
Test name
Test status
Simulation time 50403986 ps
CPU time 1.99 seconds
Started Aug 12 05:14:11 PM PDT 24
Finished Aug 12 05:14:13 PM PDT 24
Peak memory 198152 kb
Host smart-3a719d49-cd1a-446c-80e0-a42bb12bb553
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016127387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1016127387
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2003464578
Short name T320
Test name
Test status
Simulation time 166538303 ps
CPU time 3.28 seconds
Started Aug 12 05:14:12 PM PDT 24
Finished Aug 12 05:14:15 PM PDT 24
Peak memory 197404 kb
Host smart-dabcb496-a0a7-46cf-a91a-feb1c52cfe80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003464578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2003464578
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2384867017
Short name T433
Test name
Test status
Simulation time 19559848 ps
CPU time 0.69 seconds
Started Aug 12 05:14:05 PM PDT 24
Finished Aug 12 05:14:06 PM PDT 24
Peak memory 194320 kb
Host smart-aa127f53-c0ca-4083-9d20-644429c47384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384867017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2384867017
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3586555598
Short name T21
Test name
Test status
Simulation time 155849229 ps
CPU time 0.91 seconds
Started Aug 12 05:14:11 PM PDT 24
Finished Aug 12 05:14:12 PM PDT 24
Peak memory 196148 kb
Host smart-91ef16fe-2804-4fdb-b7b6-fb036395396f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586555598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3586555598
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3314232708
Short name T341
Test name
Test status
Simulation time 79140153 ps
CPU time 1.07 seconds
Started Aug 12 05:14:13 PM PDT 24
Finished Aug 12 05:14:14 PM PDT 24
Peak memory 196468 kb
Host smart-548654ca-554c-4a3f-bd5b-0a8bc13983bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314232708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3314232708
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.807966853
Short name T248
Test name
Test status
Simulation time 42510300 ps
CPU time 1.21 seconds
Started Aug 12 05:14:11 PM PDT 24
Finished Aug 12 05:14:13 PM PDT 24
Peak memory 196776 kb
Host smart-2d3b1323-2a67-454d-89ba-3d492ba43552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807966853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.807966853
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2023054559
Short name T562
Test name
Test status
Simulation time 26214923 ps
CPU time 0.83 seconds
Started Aug 12 05:14:12 PM PDT 24
Finished Aug 12 05:14:13 PM PDT 24
Peak memory 196080 kb
Host smart-1f9aa606-b58f-4c51-8b92-de23ce8d0818
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023054559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2023054559
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.554998021
Short name T435
Test name
Test status
Simulation time 3998155874 ps
CPU time 56.97 seconds
Started Aug 12 05:14:20 PM PDT 24
Finished Aug 12 05:15:17 PM PDT 24
Peak memory 198256 kb
Host smart-315c13b1-ef98-46ff-9363-031c45a3a966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554998021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.554998021
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3275454217
Short name T180
Test name
Test status
Simulation time 14273548 ps
CPU time 0.58 seconds
Started Aug 12 05:14:14 PM PDT 24
Finished Aug 12 05:14:15 PM PDT 24
Peak memory 193920 kb
Host smart-927f05b8-3c32-4c97-b350-72a0174addc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275454217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3275454217
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2930770054
Short name T265
Test name
Test status
Simulation time 25704493 ps
CPU time 0.61 seconds
Started Aug 12 05:14:21 PM PDT 24
Finished Aug 12 05:14:21 PM PDT 24
Peak memory 193880 kb
Host smart-f6da1b27-5a70-49aa-bfc1-5368a9fdfdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930770054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2930770054
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3969716059
Short name T158
Test name
Test status
Simulation time 735155453 ps
CPU time 25.28 seconds
Started Aug 12 05:14:03 PM PDT 24
Finished Aug 12 05:14:28 PM PDT 24
Peak memory 196864 kb
Host smart-3e2d2df7-c27d-404c-8cc8-c2f5acbc5754
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969716059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3969716059
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1723507025
Short name T105
Test name
Test status
Simulation time 84162793 ps
CPU time 1.03 seconds
Started Aug 12 05:14:04 PM PDT 24
Finished Aug 12 05:14:05 PM PDT 24
Peak memory 196696 kb
Host smart-e5ea3775-a935-407a-8c63-4236d32449ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723507025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1723507025
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2207674640
Short name T269
Test name
Test status
Simulation time 92849916 ps
CPU time 1.36 seconds
Started Aug 12 05:14:23 PM PDT 24
Finished Aug 12 05:14:24 PM PDT 24
Peak memory 198192 kb
Host smart-f51315c3-df0c-44aa-be5f-84b8acb2950e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207674640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2207674640
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.802541019
Short name T519
Test name
Test status
Simulation time 24695913 ps
CPU time 1.05 seconds
Started Aug 12 05:14:10 PM PDT 24
Finished Aug 12 05:14:11 PM PDT 24
Peak memory 198012 kb
Host smart-f87c5003-a83b-44d2-a794-1705108474a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802541019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.802541019
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1935771072
Short name T322
Test name
Test status
Simulation time 551280047 ps
CPU time 2.28 seconds
Started Aug 12 05:14:28 PM PDT 24
Finished Aug 12 05:14:31 PM PDT 24
Peak memory 197256 kb
Host smart-554864b5-81fb-4d6f-b605-0de3384495a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935771072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1935771072
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.4132937702
Short name T552
Test name
Test status
Simulation time 38408041 ps
CPU time 0.66 seconds
Started Aug 12 05:14:18 PM PDT 24
Finished Aug 12 05:14:19 PM PDT 24
Peak memory 194276 kb
Host smart-bfb962e2-7caf-4517-841d-bb340b47b01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132937702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.4132937702
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2682833076
Short name T694
Test name
Test status
Simulation time 68120216 ps
CPU time 0.64 seconds
Started Aug 12 05:14:04 PM PDT 24
Finished Aug 12 05:14:05 PM PDT 24
Peak memory 194292 kb
Host smart-48f5ad62-1fd2-4fde-b98f-54fc3487d288
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682833076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2682833076
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.316482424
Short name T615
Test name
Test status
Simulation time 206326899 ps
CPU time 2.57 seconds
Started Aug 12 05:14:11 PM PDT 24
Finished Aug 12 05:14:14 PM PDT 24
Peak memory 198004 kb
Host smart-ef4bff2f-4272-44f3-a9a4-e8152a9831c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316482424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.316482424
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2441190272
Short name T627
Test name
Test status
Simulation time 38535758 ps
CPU time 1.07 seconds
Started Aug 12 05:14:20 PM PDT 24
Finished Aug 12 05:14:21 PM PDT 24
Peak memory 196220 kb
Host smart-228b2917-6598-4193-b868-f8a34e03fa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441190272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2441190272
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.514091725
Short name T359
Test name
Test status
Simulation time 36193361 ps
CPU time 1.06 seconds
Started Aug 12 05:14:14 PM PDT 24
Finished Aug 12 05:14:15 PM PDT 24
Peak memory 195804 kb
Host smart-fabaa7bb-f32b-4380-bca9-f7ad459173d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514091725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.514091725
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1366935707
Short name T680
Test name
Test status
Simulation time 148918728755 ps
CPU time 195.21 seconds
Started Aug 12 05:14:16 PM PDT 24
Finished Aug 12 05:17:31 PM PDT 24
Peak memory 198224 kb
Host smart-63ddcabd-44e2-41e1-8337-a701b4d72a33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366935707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1366935707
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.4001650469
Short name T399
Test name
Test status
Simulation time 12686994 ps
CPU time 0.57 seconds
Started Aug 12 05:14:26 PM PDT 24
Finished Aug 12 05:14:26 PM PDT 24
Peak memory 194012 kb
Host smart-5021238c-72da-4bad-988c-23805f0fc73e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001650469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.4001650469
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.405808341
Short name T375
Test name
Test status
Simulation time 20789209 ps
CPU time 0.74 seconds
Started Aug 12 05:14:21 PM PDT 24
Finished Aug 12 05:14:22 PM PDT 24
Peak memory 195428 kb
Host smart-a8011c62-4e07-4546-81a1-d514529811d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405808341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.405808341
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2731344000
Short name T252
Test name
Test status
Simulation time 489770487 ps
CPU time 25.38 seconds
Started Aug 12 05:14:26 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 197028 kb
Host smart-28f84234-6ede-46d8-9de3-4aab0eb9bba3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731344000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2731344000
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.540583566
Short name T604
Test name
Test status
Simulation time 69809941 ps
CPU time 0.95 seconds
Started Aug 12 05:14:13 PM PDT 24
Finished Aug 12 05:14:14 PM PDT 24
Peak memory 197780 kb
Host smart-7717f91e-fa2f-4c02-a36c-268a0b6a4545
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540583566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.540583566
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1750265956
Short name T69
Test name
Test status
Simulation time 165496023 ps
CPU time 1.16 seconds
Started Aug 12 05:14:13 PM PDT 24
Finished Aug 12 05:14:14 PM PDT 24
Peak memory 198144 kb
Host smart-52891f4a-9cb4-4094-a52d-95f29f299aea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750265956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1750265956
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.4101800201
Short name T279
Test name
Test status
Simulation time 167119608 ps
CPU time 1.8 seconds
Started Aug 12 05:14:20 PM PDT 24
Finished Aug 12 05:14:22 PM PDT 24
Peak memory 197816 kb
Host smart-2c274a53-2c1a-493e-b587-35c53714265b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101800201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.4101800201
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1884182820
Short name T642
Test name
Test status
Simulation time 243396976 ps
CPU time 1.94 seconds
Started Aug 12 05:14:24 PM PDT 24
Finished Aug 12 05:14:26 PM PDT 24
Peak memory 198060 kb
Host smart-70df2751-7e94-4808-bf9b-c38feb181e3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884182820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1884182820
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3692975744
Short name T421
Test name
Test status
Simulation time 31354011 ps
CPU time 1.12 seconds
Started Aug 12 05:14:19 PM PDT 24
Finished Aug 12 05:14:20 PM PDT 24
Peak memory 196668 kb
Host smart-48cf0e2d-8954-43cd-92ae-3c0e23450bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692975744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3692975744
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1269294994
Short name T513
Test name
Test status
Simulation time 34587785 ps
CPU time 1.2 seconds
Started Aug 12 05:14:18 PM PDT 24
Finished Aug 12 05:14:20 PM PDT 24
Peak memory 195860 kb
Host smart-668ea380-a211-4c48-9742-80cf084167e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269294994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1269294994
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.499400408
Short name T188
Test name
Test status
Simulation time 612637823 ps
CPU time 4.99 seconds
Started Aug 12 05:14:15 PM PDT 24
Finished Aug 12 05:14:20 PM PDT 24
Peak memory 198132 kb
Host smart-b2f75115-151b-40b8-969c-dc0e130e6288
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499400408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.499400408
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1603886931
Short name T586
Test name
Test status
Simulation time 543713914 ps
CPU time 1.3 seconds
Started Aug 12 05:14:21 PM PDT 24
Finished Aug 12 05:14:23 PM PDT 24
Peak memory 195564 kb
Host smart-7518b9e5-7905-4753-badf-78affa6242f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603886931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1603886931
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2232801947
Short name T495
Test name
Test status
Simulation time 57066636 ps
CPU time 0.9 seconds
Started Aug 12 05:14:17 PM PDT 24
Finished Aug 12 05:14:18 PM PDT 24
Peak memory 195332 kb
Host smart-46c3b600-216d-4750-894d-d0ce4148e140
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232801947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2232801947
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2589656174
Short name T225
Test name
Test status
Simulation time 13550315344 ps
CPU time 64.56 seconds
Started Aug 12 05:14:22 PM PDT 24
Finished Aug 12 05:15:27 PM PDT 24
Peak memory 198204 kb
Host smart-b031634d-7ee6-4c83-82df-dc91f242ed49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589656174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2589656174
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.786857427
Short name T277
Test name
Test status
Simulation time 33040230 ps
CPU time 0.56 seconds
Started Aug 12 05:14:17 PM PDT 24
Finished Aug 12 05:14:18 PM PDT 24
Peak memory 193976 kb
Host smart-004f1324-92da-4561-8d52-8aeb6c4b3a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786857427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.786857427
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3402287563
Short name T150
Test name
Test status
Simulation time 330865636 ps
CPU time 0.88 seconds
Started Aug 12 05:14:16 PM PDT 24
Finished Aug 12 05:14:17 PM PDT 24
Peak memory 197128 kb
Host smart-570dc3dd-8fe6-4695-aea4-a6d113722aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402287563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3402287563
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2857879146
Short name T258
Test name
Test status
Simulation time 1294098766 ps
CPU time 12.02 seconds
Started Aug 12 05:14:12 PM PDT 24
Finished Aug 12 05:14:24 PM PDT 24
Peak memory 197032 kb
Host smart-3709a3b5-e0fe-4bb2-a62f-3890c56aa588
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857879146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2857879146
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1896222494
Short name T692
Test name
Test status
Simulation time 66519406 ps
CPU time 1.05 seconds
Started Aug 12 05:14:17 PM PDT 24
Finished Aug 12 05:14:19 PM PDT 24
Peak memory 196512 kb
Host smart-b733d468-e121-49c8-abef-fec5e13cfd45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896222494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1896222494
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.632150486
Short name T111
Test name
Test status
Simulation time 212222203 ps
CPU time 0.78 seconds
Started Aug 12 05:14:25 PM PDT 24
Finished Aug 12 05:14:26 PM PDT 24
Peak memory 195532 kb
Host smart-1d429d98-4596-4ace-b875-73fc6deb9b79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632150486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.632150486
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.743444249
Short name T290
Test name
Test status
Simulation time 61802457 ps
CPU time 2.42 seconds
Started Aug 12 05:14:15 PM PDT 24
Finished Aug 12 05:14:18 PM PDT 24
Peak memory 198172 kb
Host smart-53b476b4-ef8f-4c24-af7a-0633d80373c4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743444249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.743444249
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.403943352
Short name T651
Test name
Test status
Simulation time 141616925 ps
CPU time 1.94 seconds
Started Aug 12 05:14:21 PM PDT 24
Finished Aug 12 05:14:24 PM PDT 24
Peak memory 196192 kb
Host smart-a96e5130-3164-43c8-9c06-06833c587a4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403943352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
403943352
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1011563925
Short name T678
Test name
Test status
Simulation time 119631296 ps
CPU time 1.2 seconds
Started Aug 12 05:14:29 PM PDT 24
Finished Aug 12 05:14:30 PM PDT 24
Peak memory 198120 kb
Host smart-abafceb5-ccd5-4861-8e27-6114ea0f5eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011563925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1011563925
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.299041103
Short name T153
Test name
Test status
Simulation time 84770275 ps
CPU time 1.01 seconds
Started Aug 12 05:14:17 PM PDT 24
Finished Aug 12 05:14:19 PM PDT 24
Peak memory 196824 kb
Host smart-d73914e0-bd5e-4b4a-88be-687fab601cbb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299041103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.299041103
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.331200642
Short name T324
Test name
Test status
Simulation time 190156310 ps
CPU time 1.89 seconds
Started Aug 12 05:14:21 PM PDT 24
Finished Aug 12 05:14:23 PM PDT 24
Peak memory 198016 kb
Host smart-ce15a7b6-cf0b-44fd-982d-7d866f9f8f17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331200642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.331200642
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.296542069
Short name T292
Test name
Test status
Simulation time 268995891 ps
CPU time 1.4 seconds
Started Aug 12 05:14:20 PM PDT 24
Finished Aug 12 05:14:22 PM PDT 24
Peak memory 196768 kb
Host smart-3f2e5fda-8000-4dd1-b4e4-0ca800d7a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296542069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.296542069
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.269661370
Short name T520
Test name
Test status
Simulation time 1094101637 ps
CPU time 1.01 seconds
Started Aug 12 05:14:23 PM PDT 24
Finished Aug 12 05:14:24 PM PDT 24
Peak memory 195900 kb
Host smart-54e67b1f-33f5-42f1-b8cf-f3fe70f076b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269661370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.269661370
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2198099488
Short name T703
Test name
Test status
Simulation time 77606321334 ps
CPU time 215.99 seconds
Started Aug 12 05:14:22 PM PDT 24
Finished Aug 12 05:17:58 PM PDT 24
Peak memory 198308 kb
Host smart-b91f332c-1633-4f1d-80c7-971f24c1bb59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198099488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2198099488
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.736667330
Short name T415
Test name
Test status
Simulation time 19379735706 ps
CPU time 136.25 seconds
Started Aug 12 05:14:26 PM PDT 24
Finished Aug 12 05:16:43 PM PDT 24
Peak memory 198436 kb
Host smart-0fa6db85-ab6b-4c39-9b60-cc5f773b24ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=736667330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.736667330
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2367025426
Short name T476
Test name
Test status
Simulation time 52220868 ps
CPU time 0.56 seconds
Started Aug 12 05:14:20 PM PDT 24
Finished Aug 12 05:14:20 PM PDT 24
Peak memory 194592 kb
Host smart-c7411f55-82fa-44bf-8377-109dac6b1464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367025426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2367025426
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2630090625
Short name T146
Test name
Test status
Simulation time 126832469 ps
CPU time 0.88 seconds
Started Aug 12 05:14:28 PM PDT 24
Finished Aug 12 05:14:29 PM PDT 24
Peak memory 196416 kb
Host smart-c98b7848-4098-463c-bc80-cbd51f5b52f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630090625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2630090625
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1482890158
Short name T683
Test name
Test status
Simulation time 1330514161 ps
CPU time 18.28 seconds
Started Aug 12 05:14:26 PM PDT 24
Finished Aug 12 05:14:44 PM PDT 24
Peak memory 196980 kb
Host smart-1791294c-d269-46f8-ae14-ba42bbcdacd9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482890158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1482890158
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1285636534
Short name T210
Test name
Test status
Simulation time 38454946 ps
CPU time 0.74 seconds
Started Aug 12 05:14:17 PM PDT 24
Finished Aug 12 05:14:17 PM PDT 24
Peak memory 195948 kb
Host smart-02dfeb49-dc20-40ae-a942-4e536c5e6c7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285636534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1285636534
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3774039339
Short name T426
Test name
Test status
Simulation time 117135149 ps
CPU time 0.88 seconds
Started Aug 12 05:14:14 PM PDT 24
Finished Aug 12 05:14:15 PM PDT 24
Peak memory 195804 kb
Host smart-a5549337-d0e9-4563-acad-d8b8cfbc6e4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774039339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3774039339
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2717771519
Short name T659
Test name
Test status
Simulation time 97701191 ps
CPU time 2.97 seconds
Started Aug 12 05:14:25 PM PDT 24
Finished Aug 12 05:14:28 PM PDT 24
Peak memory 198136 kb
Host smart-6aeee672-bd30-43da-9972-a9378412c06d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717771519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2717771519
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1978128981
Short name T439
Test name
Test status
Simulation time 146547457 ps
CPU time 2.83 seconds
Started Aug 12 05:14:23 PM PDT 24
Finished Aug 12 05:14:26 PM PDT 24
Peak memory 197352 kb
Host smart-5aed8bb5-87ef-43a8-a05d-828513c0a7ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978128981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1978128981
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3735080169
Short name T187
Test name
Test status
Simulation time 135065635 ps
CPU time 1.32 seconds
Started Aug 12 05:14:23 PM PDT 24
Finished Aug 12 05:14:24 PM PDT 24
Peak memory 196744 kb
Host smart-d3e07789-b2fd-464b-9f1a-cf316319aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735080169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3735080169
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1541579832
Short name T284
Test name
Test status
Simulation time 53460282 ps
CPU time 1.13 seconds
Started Aug 12 05:14:19 PM PDT 24
Finished Aug 12 05:14:21 PM PDT 24
Peak memory 196960 kb
Host smart-8c67d87c-689f-4b8b-aea3-8ab7a898af7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541579832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1541579832
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3401826154
Short name T368
Test name
Test status
Simulation time 107860260 ps
CPU time 2.45 seconds
Started Aug 12 05:14:23 PM PDT 24
Finished Aug 12 05:14:26 PM PDT 24
Peak memory 198136 kb
Host smart-943b5d02-795e-41b3-994c-5ca9a9fc1b9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401826154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3401826154
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1071854588
Short name T162
Test name
Test status
Simulation time 86307380 ps
CPU time 1.16 seconds
Started Aug 12 05:14:20 PM PDT 24
Finished Aug 12 05:14:21 PM PDT 24
Peak memory 195808 kb
Host smart-5f799f83-25cb-4bb4-b218-97b58068d21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071854588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1071854588
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.151231827
Short name T595
Test name
Test status
Simulation time 140518715 ps
CPU time 1.21 seconds
Started Aug 12 05:14:22 PM PDT 24
Finished Aug 12 05:14:23 PM PDT 24
Peak memory 195780 kb
Host smart-3c4eb8f9-f14f-49d0-a36a-590cd5e4e545
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151231827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.151231827
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.804035254
Short name T653
Test name
Test status
Simulation time 4073365515 ps
CPU time 100.56 seconds
Started Aug 12 05:14:19 PM PDT 24
Finished Aug 12 05:16:00 PM PDT 24
Peak memory 198212 kb
Host smart-177c9ac3-0fef-4058-9262-38cb5accef54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804035254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.804035254
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1212646971
Short name T389
Test name
Test status
Simulation time 17884551 ps
CPU time 0.58 seconds
Started Aug 12 05:14:27 PM PDT 24
Finished Aug 12 05:14:28 PM PDT 24
Peak memory 193984 kb
Host smart-7936e8ec-4343-4ee9-8390-4d8b5956861a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212646971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1212646971
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1841956711
Short name T540
Test name
Test status
Simulation time 35785096 ps
CPU time 0.9 seconds
Started Aug 12 05:14:35 PM PDT 24
Finished Aug 12 05:14:36 PM PDT 24
Peak memory 195572 kb
Host smart-a493074f-7d65-46b1-bb6d-20e30815ffc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841956711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1841956711
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2911863583
Short name T465
Test name
Test status
Simulation time 4088293195 ps
CPU time 19.04 seconds
Started Aug 12 05:14:22 PM PDT 24
Finished Aug 12 05:14:41 PM PDT 24
Peak memory 196968 kb
Host smart-167f99d6-e408-4c91-a132-7b07a8c5ab42
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911863583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2911863583
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3351644860
Short name T687
Test name
Test status
Simulation time 50980753 ps
CPU time 0.94 seconds
Started Aug 12 05:14:25 PM PDT 24
Finished Aug 12 05:14:26 PM PDT 24
Peak memory 196564 kb
Host smart-1e035cb6-67d9-4823-a40a-264ec76119d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351644860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3351644860
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2219696357
Short name T688
Test name
Test status
Simulation time 90294158 ps
CPU time 0.8 seconds
Started Aug 12 05:14:39 PM PDT 24
Finished Aug 12 05:14:40 PM PDT 24
Peak memory 195400 kb
Host smart-e7acf68c-0803-4551-af8d-5d30d19d31a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219696357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2219696357
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3373822559
Short name T306
Test name
Test status
Simulation time 306478097 ps
CPU time 3.25 seconds
Started Aug 12 05:14:21 PM PDT 24
Finished Aug 12 05:14:25 PM PDT 24
Peak memory 198180 kb
Host smart-2e58d66c-caca-4f04-848b-3d1bf3c9aed0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373822559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3373822559
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1662570689
Short name T251
Test name
Test status
Simulation time 38856937 ps
CPU time 1.3 seconds
Started Aug 12 05:14:42 PM PDT 24
Finished Aug 12 05:14:44 PM PDT 24
Peak memory 196232 kb
Host smart-2135dc56-dfce-4ce7-846a-eca7f07120aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662570689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1662570689
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.910147999
Short name T411
Test name
Test status
Simulation time 19167573 ps
CPU time 0.73 seconds
Started Aug 12 05:14:26 PM PDT 24
Finished Aug 12 05:14:27 PM PDT 24
Peak memory 195040 kb
Host smart-65cff7c6-cd65-47f7-86ca-8afaebf0cf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910147999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.910147999
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.993529573
Short name T174
Test name
Test status
Simulation time 166683650 ps
CPU time 1.37 seconds
Started Aug 12 05:14:39 PM PDT 24
Finished Aug 12 05:14:40 PM PDT 24
Peak memory 197176 kb
Host smart-0f8a5531-355d-401d-a644-554c8eb12ad3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993529573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.993529573
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.886249698
Short name T245
Test name
Test status
Simulation time 903003026 ps
CPU time 5.13 seconds
Started Aug 12 05:14:20 PM PDT 24
Finished Aug 12 05:14:26 PM PDT 24
Peak memory 198120 kb
Host smart-0a68dd73-d895-45b0-af80-516c3f60c1ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886249698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.886249698
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2448243139
Short name T504
Test name
Test status
Simulation time 137431563 ps
CPU time 1.16 seconds
Started Aug 12 05:14:27 PM PDT 24
Finished Aug 12 05:14:28 PM PDT 24
Peak memory 195944 kb
Host smart-704751fd-55a2-4a45-980e-2cd58e600489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448243139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2448243139
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.945788466
Short name T533
Test name
Test status
Simulation time 43401115 ps
CPU time 1.1 seconds
Started Aug 12 05:14:22 PM PDT 24
Finished Aug 12 05:14:23 PM PDT 24
Peak memory 195892 kb
Host smart-349f7c7a-10ec-4d1d-9521-d1281b4f49b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945788466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.945788466
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.688556029
Short name T430
Test name
Test status
Simulation time 3940361839 ps
CPU time 99.09 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:16:29 PM PDT 24
Peak memory 198140 kb
Host smart-2a3121fd-1bd3-4fc9-a2cf-080aa77e4e74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688556029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.688556029
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3485322423
Short name T610
Test name
Test status
Simulation time 12634657 ps
CPU time 0.56 seconds
Started Aug 12 05:14:28 PM PDT 24
Finished Aug 12 05:14:29 PM PDT 24
Peak memory 193980 kb
Host smart-99a98f90-1023-453e-ab51-f3f31c78f53f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485322423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3485322423
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2862926165
Short name T54
Test name
Test status
Simulation time 99163413 ps
CPU time 0.91 seconds
Started Aug 12 05:14:28 PM PDT 24
Finished Aug 12 05:14:29 PM PDT 24
Peak memory 195956 kb
Host smart-89b49383-de13-4d76-ac82-4b7d5567836f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862926165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2862926165
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2839404214
Short name T365
Test name
Test status
Simulation time 533058178 ps
CPU time 15.1 seconds
Started Aug 12 05:14:45 PM PDT 24
Finished Aug 12 05:15:00 PM PDT 24
Peak memory 197200 kb
Host smart-670cdf2d-ab9f-431e-bf67-25923548c757
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839404214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2839404214
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2340669949
Short name T370
Test name
Test status
Simulation time 48014165 ps
CPU time 0.66 seconds
Started Aug 12 05:14:33 PM PDT 24
Finished Aug 12 05:14:33 PM PDT 24
Peak memory 195336 kb
Host smart-936dfd39-33e4-4658-ae6b-0d7584f04a38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340669949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2340669949
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.738344673
Short name T475
Test name
Test status
Simulation time 21630339 ps
CPU time 0.65 seconds
Started Aug 12 05:14:32 PM PDT 24
Finished Aug 12 05:14:33 PM PDT 24
Peak memory 195012 kb
Host smart-448de3e9-3565-49ad-88d4-431651c4e1fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738344673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.738344673
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1147566741
Short name T247
Test name
Test status
Simulation time 120727480 ps
CPU time 2.24 seconds
Started Aug 12 05:14:34 PM PDT 24
Finished Aug 12 05:14:36 PM PDT 24
Peak memory 196548 kb
Host smart-530275eb-4fd9-4fb7-b859-030f919092aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147566741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1147566741
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3292803050
Short name T242
Test name
Test status
Simulation time 76077836 ps
CPU time 2.19 seconds
Started Aug 12 05:14:24 PM PDT 24
Finished Aug 12 05:14:27 PM PDT 24
Peak memory 197252 kb
Host smart-0ec0b6c9-d6d7-4d2c-8125-c6bdd6e2a4dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292803050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3292803050
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3612502063
Short name T141
Test name
Test status
Simulation time 141164109 ps
CPU time 1.07 seconds
Started Aug 12 05:14:40 PM PDT 24
Finished Aug 12 05:14:41 PM PDT 24
Peak memory 196776 kb
Host smart-82dea35a-7510-4732-9f7d-e35a75adf823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612502063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3612502063
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.881536854
Short name T213
Test name
Test status
Simulation time 100425058 ps
CPU time 0.83 seconds
Started Aug 12 05:14:26 PM PDT 24
Finished Aug 12 05:14:27 PM PDT 24
Peak memory 197420 kb
Host smart-8a88ec03-e527-4799-8822-f286c8e54ff4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881536854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.881536854
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1758764243
Short name T189
Test name
Test status
Simulation time 449624450 ps
CPU time 5.02 seconds
Started Aug 12 05:14:44 PM PDT 24
Finished Aug 12 05:14:49 PM PDT 24
Peak memory 198076 kb
Host smart-b267243d-85a3-4916-a7f2-3af4fe2371de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758764243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1758764243
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.351715476
Short name T441
Test name
Test status
Simulation time 561044923 ps
CPU time 1.24 seconds
Started Aug 12 05:14:16 PM PDT 24
Finished Aug 12 05:14:17 PM PDT 24
Peak memory 196660 kb
Host smart-7cf4e2e9-d9b7-41c5-8399-f6a6db23efbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351715476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.351715476
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3156160415
Short name T509
Test name
Test status
Simulation time 48629269 ps
CPU time 0.95 seconds
Started Aug 12 05:14:35 PM PDT 24
Finished Aug 12 05:14:36 PM PDT 24
Peak memory 195584 kb
Host smart-709dfe3c-4a8f-4d73-a12f-c249119f8628
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156160415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3156160415
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.318480488
Short name T163
Test name
Test status
Simulation time 1315164553 ps
CPU time 30.52 seconds
Started Aug 12 05:14:27 PM PDT 24
Finished Aug 12 05:14:58 PM PDT 24
Peak memory 198200 kb
Host smart-be3492b4-16bd-4a62-bb58-7fb8dac55b6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318480488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.318480488
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3400413361
Short name T669
Test name
Test status
Simulation time 12590568 ps
CPU time 0.58 seconds
Started Aug 12 05:14:30 PM PDT 24
Finished Aug 12 05:14:31 PM PDT 24
Peak memory 194724 kb
Host smart-6f5bfe75-18a5-4a4d-9168-4e1e9c79d238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400413361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3400413361
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1783979788
Short name T142
Test name
Test status
Simulation time 29564592 ps
CPU time 0.89 seconds
Started Aug 12 05:14:44 PM PDT 24
Finished Aug 12 05:14:45 PM PDT 24
Peak memory 196764 kb
Host smart-185e24d6-de57-478e-839d-4e950b0eb7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783979788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1783979788
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1537936591
Short name T217
Test name
Test status
Simulation time 6068315977 ps
CPU time 17.3 seconds
Started Aug 12 05:14:30 PM PDT 24
Finished Aug 12 05:14:48 PM PDT 24
Peak memory 197128 kb
Host smart-c65e6bf6-e6bf-4131-ba7f-3373d72f8f56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537936591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1537936591
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3584308783
Short name T175
Test name
Test status
Simulation time 24988883 ps
CPU time 0.71 seconds
Started Aug 12 05:14:35 PM PDT 24
Finished Aug 12 05:14:35 PM PDT 24
Peak memory 194648 kb
Host smart-6da9229d-f541-40ff-b3d1-cb9ce6a8fc14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584308783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3584308783
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3893322597
Short name T565
Test name
Test status
Simulation time 87657791 ps
CPU time 1.26 seconds
Started Aug 12 05:14:27 PM PDT 24
Finished Aug 12 05:14:29 PM PDT 24
Peak memory 196080 kb
Host smart-3e326223-97a3-4a94-9fb9-c77ee9a3b4f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893322597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3893322597
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.294899005
Short name T481
Test name
Test status
Simulation time 163315249 ps
CPU time 3.28 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:41 PM PDT 24
Peak memory 197948 kb
Host smart-dfc0c114-56b6-40c2-9bca-6c6c8f0874da
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294899005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.294899005
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.61277416
Short name T587
Test name
Test status
Simulation time 100925767 ps
CPU time 0.85 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 194992 kb
Host smart-9a2cd1da-4f92-4ab1-9a31-80793ef5c193
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61277416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.61277416
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.938367740
Short name T317
Test name
Test status
Simulation time 124056560 ps
CPU time 1.02 seconds
Started Aug 12 05:14:33 PM PDT 24
Finished Aug 12 05:14:34 PM PDT 24
Peak memory 195884 kb
Host smart-82232fab-c59d-42cf-883c-6ef209182d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938367740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.938367740
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3473010918
Short name T300
Test name
Test status
Simulation time 85770019 ps
CPU time 0.93 seconds
Started Aug 12 05:14:26 PM PDT 24
Finished Aug 12 05:14:27 PM PDT 24
Peak memory 196820 kb
Host smart-00a0a5fd-f7a7-4a9a-9120-932c5a05f612
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473010918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3473010918
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.95969922
Short name T406
Test name
Test status
Simulation time 51945304 ps
CPU time 1.34 seconds
Started Aug 12 05:14:39 PM PDT 24
Finished Aug 12 05:14:41 PM PDT 24
Peak memory 197980 kb
Host smart-e9b2add1-3ff7-4ecd-bd8a-6f34759add8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95969922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand
om_long_reg_writes_reg_reads.95969922
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3792691918
Short name T278
Test name
Test status
Simulation time 72949280 ps
CPU time 1.33 seconds
Started Aug 12 05:14:30 PM PDT 24
Finished Aug 12 05:14:31 PM PDT 24
Peak memory 197316 kb
Host smart-9714220b-7fcf-4632-b5e2-705d8881aeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792691918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3792691918
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2927071067
Short name T403
Test name
Test status
Simulation time 92290438 ps
CPU time 1.36 seconds
Started Aug 12 05:14:24 PM PDT 24
Finished Aug 12 05:14:25 PM PDT 24
Peak memory 196828 kb
Host smart-5849fe11-b5b3-454e-902f-686576207e82
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927071067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2927071067
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3445067567
Short name T219
Test name
Test status
Simulation time 4263214834 ps
CPU time 113.71 seconds
Started Aug 12 05:14:29 PM PDT 24
Finished Aug 12 05:16:23 PM PDT 24
Peak memory 198256 kb
Host smart-152825c2-63fb-4c78-a3db-d5334e13bdb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445067567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3445067567
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2245128508
Short name T585
Test name
Test status
Simulation time 23325948 ps
CPU time 0.57 seconds
Started Aug 12 05:14:40 PM PDT 24
Finished Aug 12 05:14:41 PM PDT 24
Peak memory 193944 kb
Host smart-e20811bf-9099-449c-908c-f4a8e9d38d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245128508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2245128508
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.4171248700
Short name T282
Test name
Test status
Simulation time 39524927 ps
CPU time 0.64 seconds
Started Aug 12 05:14:30 PM PDT 24
Finished Aug 12 05:14:31 PM PDT 24
Peak memory 194192 kb
Host smart-d6288015-dc3d-474b-a94d-0043ffbcfa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171248700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.4171248700
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3384789939
Short name T524
Test name
Test status
Simulation time 312450347 ps
CPU time 10.74 seconds
Started Aug 12 05:14:30 PM PDT 24
Finished Aug 12 05:14:41 PM PDT 24
Peak memory 196856 kb
Host smart-159df55a-f27d-4940-9f08-b705eb539441
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384789939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3384789939
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2326160522
Short name T104
Test name
Test status
Simulation time 61505731 ps
CPU time 0.79 seconds
Started Aug 12 05:14:32 PM PDT 24
Finished Aug 12 05:14:33 PM PDT 24
Peak memory 194848 kb
Host smart-4ce4a561-7ddc-4a6a-9ce7-235cbcb70181
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326160522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2326160522
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1695675160
Short name T202
Test name
Test status
Simulation time 46110794 ps
CPU time 0.75 seconds
Started Aug 12 05:14:42 PM PDT 24
Finished Aug 12 05:14:43 PM PDT 24
Peak memory 194420 kb
Host smart-63342518-ef51-416e-b080-fa062f2381fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695675160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1695675160
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.223080903
Short name T102
Test name
Test status
Simulation time 174461710 ps
CPU time 1.93 seconds
Started Aug 12 05:14:38 PM PDT 24
Finished Aug 12 05:14:40 PM PDT 24
Peak memory 198136 kb
Host smart-8b1903b6-ac4b-45bf-9794-7c9de85dd4d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223080903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.223080903
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3898607915
Short name T530
Test name
Test status
Simulation time 68290282 ps
CPU time 1.93 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:39 PM PDT 24
Peak memory 197076 kb
Host smart-4582daea-605f-42fd-a898-d1b8181cf812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898607915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3898607915
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3526124078
Short name T486
Test name
Test status
Simulation time 113420762 ps
CPU time 0.74 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:38 PM PDT 24
Peak memory 196172 kb
Host smart-1ba66eef-b0d7-436f-9d39-94814bc737f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526124078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3526124078
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2910211684
Short name T285
Test name
Test status
Simulation time 57586852 ps
CPU time 1.03 seconds
Started Aug 12 05:14:45 PM PDT 24
Finished Aug 12 05:14:46 PM PDT 24
Peak memory 196048 kb
Host smart-62f547bc-66dc-471a-af45-985ca8e7d97b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910211684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2910211684
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3483668872
Short name T442
Test name
Test status
Simulation time 327971901 ps
CPU time 3.79 seconds
Started Aug 12 05:14:31 PM PDT 24
Finished Aug 12 05:14:34 PM PDT 24
Peak memory 198100 kb
Host smart-673b35c8-acc6-4575-97b2-a4db74b0a192
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483668872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3483668872
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.736815844
Short name T358
Test name
Test status
Simulation time 44626964 ps
CPU time 0.81 seconds
Started Aug 12 05:14:34 PM PDT 24
Finished Aug 12 05:14:35 PM PDT 24
Peak memory 195348 kb
Host smart-ce55405f-4dde-4fb9-b12e-d463f0ed148c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736815844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.736815844
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3062322292
Short name T431
Test name
Test status
Simulation time 196248558 ps
CPU time 1.05 seconds
Started Aug 12 05:14:46 PM PDT 24
Finished Aug 12 05:14:47 PM PDT 24
Peak memory 195840 kb
Host smart-babce7ec-1fdd-4e4d-a113-e468b507f4f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062322292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3062322292
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1078091073
Short name T556
Test name
Test status
Simulation time 14206430971 ps
CPU time 188.97 seconds
Started Aug 12 05:14:44 PM PDT 24
Finished Aug 12 05:17:53 PM PDT 24
Peak memory 198256 kb
Host smart-17588897-b1c5-4136-a1b9-c70da8ed8dbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078091073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1078091073
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2523153639
Short name T417
Test name
Test status
Simulation time 46676242 ps
CPU time 0.58 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 194908 kb
Host smart-cd86da91-0ea2-4adf-a175-5e0e939dafb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523153639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2523153639
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3935918491
Short name T631
Test name
Test status
Simulation time 162376163 ps
CPU time 0.87 seconds
Started Aug 12 05:14:31 PM PDT 24
Finished Aug 12 05:14:32 PM PDT 24
Peak memory 197092 kb
Host smart-db669518-4229-494c-8933-d63b3187928e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935918491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3935918491
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3593548515
Short name T660
Test name
Test status
Simulation time 646394294 ps
CPU time 8.58 seconds
Started Aug 12 05:14:30 PM PDT 24
Finished Aug 12 05:14:39 PM PDT 24
Peak memory 196872 kb
Host smart-38ef47bc-50b8-4595-b1a2-0e684aa3c027
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593548515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3593548515
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3862648270
Short name T190
Test name
Test status
Simulation time 324487464 ps
CPU time 1.01 seconds
Started Aug 12 05:14:33 PM PDT 24
Finished Aug 12 05:14:34 PM PDT 24
Peak memory 196720 kb
Host smart-e38c387e-0247-4b82-9221-d738e63fd935
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862648270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3862648270
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1521279879
Short name T518
Test name
Test status
Simulation time 469572138 ps
CPU time 1.36 seconds
Started Aug 12 05:14:46 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 197060 kb
Host smart-03de8754-be5b-497b-9104-b017f9342be4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521279879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1521279879
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3364229344
Short name T440
Test name
Test status
Simulation time 237983961 ps
CPU time 2.49 seconds
Started Aug 12 05:14:30 PM PDT 24
Finished Aug 12 05:14:33 PM PDT 24
Peak memory 198196 kb
Host smart-257e168e-4458-4994-a63d-3ad41fcffd8f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364229344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3364229344
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3628413999
Short name T424
Test name
Test status
Simulation time 1064487280 ps
CPU time 2.45 seconds
Started Aug 12 05:14:30 PM PDT 24
Finished Aug 12 05:14:32 PM PDT 24
Peak memory 197188 kb
Host smart-b614357b-227b-4d3d-ae96-013b5cefbc06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628413999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3628413999
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3256884445
Short name T549
Test name
Test status
Simulation time 69678037 ps
CPU time 0.87 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:49 PM PDT 24
Peak memory 196784 kb
Host smart-03ee3408-d873-4dba-8b72-59a9a91c55fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256884445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3256884445
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1000951666
Short name T222
Test name
Test status
Simulation time 75506169 ps
CPU time 1.02 seconds
Started Aug 12 05:14:45 PM PDT 24
Finished Aug 12 05:14:46 PM PDT 24
Peak memory 196160 kb
Host smart-a8cc7016-4646-47ac-828a-e9e0e7abbb8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000951666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1000951666
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1036668403
Short name T597
Test name
Test status
Simulation time 256560471 ps
CPU time 3.14 seconds
Started Aug 12 05:14:28 PM PDT 24
Finished Aug 12 05:14:31 PM PDT 24
Peak memory 198088 kb
Host smart-11ff16b2-55b1-4a3c-9a84-cb66e4089798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036668403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1036668403
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1224100850
Short name T125
Test name
Test status
Simulation time 65525397 ps
CPU time 1.21 seconds
Started Aug 12 05:14:32 PM PDT 24
Finished Aug 12 05:14:34 PM PDT 24
Peak memory 196556 kb
Host smart-548271b6-f090-4dfc-ab5a-3d697b8bbf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224100850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1224100850
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.441919872
Short name T491
Test name
Test status
Simulation time 592272321 ps
CPU time 1.14 seconds
Started Aug 12 05:14:38 PM PDT 24
Finished Aug 12 05:14:39 PM PDT 24
Peak memory 195892 kb
Host smart-b2695aca-355b-4b5c-8914-ab3c7002878f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441919872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.441919872
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2110737752
Short name T10
Test name
Test status
Simulation time 28693376136 ps
CPU time 129.76 seconds
Started Aug 12 05:14:42 PM PDT 24
Finished Aug 12 05:16:52 PM PDT 24
Peak memory 198276 kb
Host smart-5cdee096-7c45-4fcb-b1cf-927c46148c36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110737752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2110737752
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1399509966
Short name T309
Test name
Test status
Simulation time 12102336 ps
CPU time 0.55 seconds
Started Aug 12 05:13:55 PM PDT 24
Finished Aug 12 05:13:56 PM PDT 24
Peak memory 194672 kb
Host smart-c4648462-dfad-4bb6-9f02-81c9bd34be2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399509966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1399509966
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3058854795
Short name T276
Test name
Test status
Simulation time 32216213 ps
CPU time 0.9 seconds
Started Aug 12 05:13:54 PM PDT 24
Finished Aug 12 05:13:55 PM PDT 24
Peak memory 196768 kb
Host smart-adcc389d-dcfd-4c45-a256-74b04c793916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058854795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3058854795
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.4172148594
Short name T314
Test name
Test status
Simulation time 694010824 ps
CPU time 16.83 seconds
Started Aug 12 05:13:51 PM PDT 24
Finished Aug 12 05:14:08 PM PDT 24
Peak memory 197208 kb
Host smart-ec729a08-dc1c-4ee9-9677-5275371cb2c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172148594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.4172148594
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.777230639
Short name T312
Test name
Test status
Simulation time 795830986 ps
CPU time 0.93 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:13:59 PM PDT 24
Peak memory 196632 kb
Host smart-6faa42dc-4759-4033-9441-fc4eda0a39fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777230639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.777230639
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.777324230
Short name T193
Test name
Test status
Simulation time 261683658 ps
CPU time 2.7 seconds
Started Aug 12 05:13:55 PM PDT 24
Finished Aug 12 05:13:58 PM PDT 24
Peak memory 198132 kb
Host smart-6f8673a9-9914-433e-a265-6ea6c8ed862c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777324230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.777324230
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.4230929458
Short name T135
Test name
Test status
Simulation time 139605393 ps
CPU time 2.85 seconds
Started Aug 12 05:13:50 PM PDT 24
Finished Aug 12 05:13:54 PM PDT 24
Peak memory 198140 kb
Host smart-c8c16b21-330d-4c4e-97e5-29efff80511a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230929458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
4230929458
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3177107016
Short name T517
Test name
Test status
Simulation time 276923420 ps
CPU time 0.86 seconds
Started Aug 12 05:13:50 PM PDT 24
Finished Aug 12 05:13:51 PM PDT 24
Peak memory 196768 kb
Host smart-f993585b-9d79-49d5-b2f6-b25dcaee62fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177107016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3177107016
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.470122055
Short name T656
Test name
Test status
Simulation time 92398145 ps
CPU time 0.96 seconds
Started Aug 12 05:13:49 PM PDT 24
Finished Aug 12 05:13:50 PM PDT 24
Peak memory 195992 kb
Host smart-2f6762f5-74a5-4c4c-94b1-0714cce0329f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470122055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.470122055
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3474751218
Short name T546
Test name
Test status
Simulation time 109810502 ps
CPU time 4.79 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:14:02 PM PDT 24
Peak memory 198124 kb
Host smart-98da3fb9-3cb9-4b23-830b-097391517f51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474751218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3474751218
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1384502296
Short name T42
Test name
Test status
Simulation time 94482231 ps
CPU time 0.94 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:14:02 PM PDT 24
Peak memory 214184 kb
Host smart-03d828bd-c4f0-4ebe-928d-51ad037770f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384502296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1384502296
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1349679184
Short name T422
Test name
Test status
Simulation time 76566677 ps
CPU time 1.06 seconds
Started Aug 12 05:13:52 PM PDT 24
Finished Aug 12 05:13:53 PM PDT 24
Peak memory 196644 kb
Host smart-c1c9cc9c-1ecb-487b-a7f0-79443ab247a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349679184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1349679184
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3942468190
Short name T567
Test name
Test status
Simulation time 46874266 ps
CPU time 1.16 seconds
Started Aug 12 05:13:48 PM PDT 24
Finished Aug 12 05:13:49 PM PDT 24
Peak memory 196668 kb
Host smart-fb1f11f3-da9b-44cb-b776-f4b30f2b7769
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942468190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3942468190
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2390077509
Short name T5
Test name
Test status
Simulation time 28228114938 ps
CPU time 150.95 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:16:28 PM PDT 24
Peak memory 198220 kb
Host smart-4718744f-c694-4a8a-94a3-743ff92be7fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390077509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2390077509
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1683593330
Short name T543
Test name
Test status
Simulation time 6620850790 ps
CPU time 221.04 seconds
Started Aug 12 05:14:09 PM PDT 24
Finished Aug 12 05:17:51 PM PDT 24
Peak memory 198412 kb
Host smart-7faee340-e740-4d0e-a3cb-257e1e7fce11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1683593330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1683593330
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.156998369
Short name T511
Test name
Test status
Simulation time 13315870 ps
CPU time 0.58 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:38 PM PDT 24
Peak memory 194312 kb
Host smart-8fb8ec51-88c8-4781-8532-5873a94eedf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156998369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.156998369
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3074125846
Short name T206
Test name
Test status
Simulation time 78366724 ps
CPU time 0.76 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 195268 kb
Host smart-0a2d4b79-0df4-4c9c-88cc-c33500c48d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074125846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3074125846
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.191886601
Short name T537
Test name
Test status
Simulation time 775830387 ps
CPU time 19.84 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:57 PM PDT 24
Peak memory 197064 kb
Host smart-d5c96af1-a6b8-4409-93d3-6721555b0aac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191886601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.191886601
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2918294502
Short name T154
Test name
Test status
Simulation time 1621852275 ps
CPU time 0.93 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 197960 kb
Host smart-cb2c5eae-5038-4dfd-9cc3-642db98e8ee5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918294502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2918294502
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.347360006
Short name T423
Test name
Test status
Simulation time 297779666 ps
CPU time 1.33 seconds
Started Aug 12 05:14:30 PM PDT 24
Finished Aug 12 05:14:31 PM PDT 24
Peak memory 198208 kb
Host smart-6c4df8a0-f2cd-4150-9ce5-3ef1786f5f56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347360006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.347360006
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2110896164
Short name T160
Test name
Test status
Simulation time 84175541 ps
CPU time 3.43 seconds
Started Aug 12 05:14:32 PM PDT 24
Finished Aug 12 05:14:35 PM PDT 24
Peak memory 198180 kb
Host smart-faca8732-ba54-4ccd-9985-8dc990e0e6b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110896164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2110896164
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4117928635
Short name T338
Test name
Test status
Simulation time 81289991 ps
CPU time 1.77 seconds
Started Aug 12 05:14:33 PM PDT 24
Finished Aug 12 05:14:35 PM PDT 24
Peak memory 196912 kb
Host smart-135f44da-25df-4127-9db4-f2448b3fb44a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117928635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4117928635
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.567485771
Short name T178
Test name
Test status
Simulation time 36746013 ps
CPU time 0.66 seconds
Started Aug 12 05:14:46 PM PDT 24
Finished Aug 12 05:14:47 PM PDT 24
Peak memory 194268 kb
Host smart-4f9f7941-9183-4314-a3da-1e4a6168b32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567485771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.567485771
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1544557852
Short name T238
Test name
Test status
Simulation time 34879352 ps
CPU time 0.91 seconds
Started Aug 12 05:14:43 PM PDT 24
Finished Aug 12 05:14:44 PM PDT 24
Peak memory 196176 kb
Host smart-a79f10cb-9204-4d4c-aa3f-305c5970fbc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544557852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1544557852
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.902313171
Short name T641
Test name
Test status
Simulation time 225854899 ps
CPU time 2.75 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:40 PM PDT 24
Peak memory 198064 kb
Host smart-1f0af127-d1a4-4e37-9e9d-18224e619e04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902313171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.902313171
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.4136383772
Short name T209
Test name
Test status
Simulation time 163473657 ps
CPU time 1.22 seconds
Started Aug 12 05:14:42 PM PDT 24
Finished Aug 12 05:14:44 PM PDT 24
Peak memory 196908 kb
Host smart-de00bbb1-0a8e-4ad5-b202-dcb52a5b967b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136383772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.4136383772
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1115326533
Short name T470
Test name
Test status
Simulation time 622850496 ps
CPU time 1.11 seconds
Started Aug 12 05:14:36 PM PDT 24
Finished Aug 12 05:14:37 PM PDT 24
Peak memory 195772 kb
Host smart-3c323a7f-43b3-4732-b966-c430a9c2d17d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115326533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1115326533
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1866945844
Short name T107
Test name
Test status
Simulation time 41723363 ps
CPU time 0.55 seconds
Started Aug 12 05:14:42 PM PDT 24
Finished Aug 12 05:14:43 PM PDT 24
Peak memory 193980 kb
Host smart-5fe5c288-5989-4d47-ba04-ddd0eb9aadad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866945844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1866945844
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.858945290
Short name T275
Test name
Test status
Simulation time 22490262 ps
CPU time 0.67 seconds
Started Aug 12 05:14:28 PM PDT 24
Finished Aug 12 05:14:29 PM PDT 24
Peak memory 194788 kb
Host smart-ba3be0af-dbf8-43c4-a8f7-e091dfe7eabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858945290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.858945290
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3858218085
Short name T583
Test name
Test status
Simulation time 111568688 ps
CPU time 5.23 seconds
Started Aug 12 05:14:28 PM PDT 24
Finished Aug 12 05:14:34 PM PDT 24
Peak memory 196712 kb
Host smart-5cf226d6-0bb2-4b79-b9cf-bd21e1c9dee0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858218085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3858218085
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2139577505
Short name T674
Test name
Test status
Simulation time 68951875 ps
CPU time 0.96 seconds
Started Aug 12 05:14:47 PM PDT 24
Finished Aug 12 05:14:48 PM PDT 24
Peak memory 196540 kb
Host smart-8cbbc53a-1779-4504-88ea-ac8506a7ef98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139577505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2139577505
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3607680745
Short name T155
Test name
Test status
Simulation time 61106920 ps
CPU time 0.64 seconds
Started Aug 12 05:14:34 PM PDT 24
Finished Aug 12 05:14:34 PM PDT 24
Peak memory 194368 kb
Host smart-7c1218ac-2d55-400d-8252-70eefc6c17f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607680745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3607680745
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2720147124
Short name T100
Test name
Test status
Simulation time 282486327 ps
CPU time 2.71 seconds
Started Aug 12 05:14:46 PM PDT 24
Finished Aug 12 05:14:48 PM PDT 24
Peak memory 198132 kb
Host smart-3a49b399-3e4f-4232-8f5c-fb9204801b9a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720147124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2720147124
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1125149678
Short name T607
Test name
Test status
Simulation time 39716349 ps
CPU time 1.27 seconds
Started Aug 12 05:14:41 PM PDT 24
Finished Aug 12 05:14:42 PM PDT 24
Peak memory 195840 kb
Host smart-8291f766-c507-4d1e-9514-70d1cfe286a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125149678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1125149678
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2523839139
Short name T645
Test name
Test status
Simulation time 61705537 ps
CPU time 1.11 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:38 PM PDT 24
Peak memory 196540 kb
Host smart-583f512a-794a-411a-ba4a-b4d064fbb033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523839139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2523839139
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.828303716
Short name T510
Test name
Test status
Simulation time 30967784 ps
CPU time 0.63 seconds
Started Aug 12 05:14:29 PM PDT 24
Finished Aug 12 05:14:29 PM PDT 24
Peak memory 194192 kb
Host smart-79db1c1a-e150-4717-a1f3-5ef917873175
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828303716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.828303716
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.48906077
Short name T134
Test name
Test status
Simulation time 442602262 ps
CPU time 2.08 seconds
Started Aug 12 05:14:28 PM PDT 24
Finished Aug 12 05:14:30 PM PDT 24
Peak memory 196476 kb
Host smart-6397af37-6f05-4360-ba99-b4f0f3d281e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48906077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand
om_long_reg_writes_reg_reads.48906077
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3554320994
Short name T367
Test name
Test status
Simulation time 29806475 ps
CPU time 0.81 seconds
Started Aug 12 05:14:33 PM PDT 24
Finished Aug 12 05:14:33 PM PDT 24
Peak memory 195232 kb
Host smart-6b1032b0-4ae9-45a1-95b1-07299860a7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554320994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3554320994
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.4147299650
Short name T624
Test name
Test status
Simulation time 204049310 ps
CPU time 1.15 seconds
Started Aug 12 05:14:29 PM PDT 24
Finished Aug 12 05:14:31 PM PDT 24
Peak memory 195748 kb
Host smart-fee90502-bb54-4572-822d-60c81adfe08f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147299650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.4147299650
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.636626801
Short name T639
Test name
Test status
Simulation time 3392192063 ps
CPU time 45.73 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:15:34 PM PDT 24
Peak memory 198164 kb
Host smart-004014fe-f582-4007-95e2-796ec0019a07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636626801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.636626801
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.634013361
Short name T207
Test name
Test status
Simulation time 41527592 ps
CPU time 0.55 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:38 PM PDT 24
Peak memory 194620 kb
Host smart-7939a367-2c96-459b-a313-b07ca4d55c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634013361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.634013361
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1887583493
Short name T445
Test name
Test status
Simulation time 85199240 ps
CPU time 0.75 seconds
Started Aug 12 05:14:34 PM PDT 24
Finished Aug 12 05:14:35 PM PDT 24
Peak memory 194252 kb
Host smart-9f22ac84-90bd-4041-8068-f1961c3f4293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887583493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1887583493
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.112834251
Short name T342
Test name
Test status
Simulation time 1976880150 ps
CPU time 16.91 seconds
Started Aug 12 05:14:43 PM PDT 24
Finished Aug 12 05:15:00 PM PDT 24
Peak memory 197048 kb
Host smart-a01fc2cd-0060-4de9-ad80-5b6423c58628
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112834251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.112834251
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3987262203
Short name T566
Test name
Test status
Simulation time 37253455 ps
CPU time 0.62 seconds
Started Aug 12 05:14:42 PM PDT 24
Finished Aug 12 05:14:42 PM PDT 24
Peak memory 194312 kb
Host smart-da040a63-941e-46c8-960d-e0eebc90e347
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987262203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3987262203
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2071009992
Short name T590
Test name
Test status
Simulation time 65020571 ps
CPU time 1.22 seconds
Started Aug 12 05:14:29 PM PDT 24
Finished Aug 12 05:14:30 PM PDT 24
Peak memory 195932 kb
Host smart-0e20e0d6-9561-494c-952d-c96a18cfad88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071009992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2071009992
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.554495917
Short name T557
Test name
Test status
Simulation time 45965423 ps
CPU time 1.95 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 197836 kb
Host smart-77fa55b7-508f-4e1d-b11a-9d414bcefe10
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554495917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.554495917
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.763254184
Short name T140
Test name
Test status
Simulation time 154501244 ps
CPU time 1.3 seconds
Started Aug 12 05:14:32 PM PDT 24
Finished Aug 12 05:14:34 PM PDT 24
Peak memory 196056 kb
Host smart-1b460c32-d3e2-48a6-8764-ca2af0442300
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763254184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
763254184
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.561875195
Short name T299
Test name
Test status
Simulation time 51523856 ps
CPU time 1.16 seconds
Started Aug 12 05:14:30 PM PDT 24
Finished Aug 12 05:14:31 PM PDT 24
Peak memory 196792 kb
Host smart-9abecce8-d12c-4dbd-95c0-48e3e69db541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561875195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.561875195
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3915828525
Short name T280
Test name
Test status
Simulation time 267587292 ps
CPU time 0.7 seconds
Started Aug 12 05:14:32 PM PDT 24
Finished Aug 12 05:14:33 PM PDT 24
Peak memory 195324 kb
Host smart-4aaf1e30-d213-4b4f-ac4f-0cc25264d831
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915828525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3915828525
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3097242403
Short name T363
Test name
Test status
Simulation time 932513572 ps
CPU time 3.34 seconds
Started Aug 12 05:14:44 PM PDT 24
Finished Aug 12 05:14:48 PM PDT 24
Peak memory 198032 kb
Host smart-81144c21-60ec-4a38-9e57-9b6de00fee2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097242403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3097242403
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1664958986
Short name T561
Test name
Test status
Simulation time 150144583 ps
CPU time 0.98 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:49 PM PDT 24
Peak memory 195628 kb
Host smart-fa3784af-2578-4517-a14b-9f871e21a90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664958986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1664958986
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.4177826257
Short name T296
Test name
Test status
Simulation time 270471578 ps
CPU time 0.96 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:49 PM PDT 24
Peak memory 195936 kb
Host smart-9fbf8ff8-30d6-4ded-9986-c7ce555d24fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177826257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.4177826257
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2061089128
Short name T575
Test name
Test status
Simulation time 19079724867 ps
CPU time 190.1 seconds
Started Aug 12 05:14:47 PM PDT 24
Finished Aug 12 05:17:58 PM PDT 24
Peak memory 198224 kb
Host smart-815a57fa-eac5-40ac-af7e-7fafd225ad48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061089128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2061089128
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2189531404
Short name T377
Test name
Test status
Simulation time 13298988 ps
CPU time 0.56 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:14:53 PM PDT 24
Peak memory 193892 kb
Host smart-f1fd1d65-9c98-4f3f-b82e-6e3ea1262d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189531404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2189531404
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2284959050
Short name T151
Test name
Test status
Simulation time 66264941 ps
CPU time 0.77 seconds
Started Aug 12 05:14:30 PM PDT 24
Finished Aug 12 05:14:31 PM PDT 24
Peak memory 196056 kb
Host smart-9a32ba0e-9732-4a59-b7e8-1a7c5f23f57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284959050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2284959050
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.366266171
Short name T544
Test name
Test status
Simulation time 1663284540 ps
CPU time 7.26 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:57 PM PDT 24
Peak memory 197044 kb
Host smart-ad799a5d-d2b1-4db7-b2fe-45dc433df84c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366266171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.366266171
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3887325548
Short name T401
Test name
Test status
Simulation time 272670977 ps
CPU time 0.77 seconds
Started Aug 12 05:14:33 PM PDT 24
Finished Aug 12 05:14:33 PM PDT 24
Peak memory 196528 kb
Host smart-1596c536-a7e5-473a-bee9-98c20c60cf55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887325548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3887325548
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2871587289
Short name T686
Test name
Test status
Simulation time 30160284 ps
CPU time 0.74 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 196128 kb
Host smart-c035b5e3-a9b1-4a2c-a880-1ff276c64a63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871587289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2871587289
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.937293529
Short name T633
Test name
Test status
Simulation time 121003820 ps
CPU time 3.37 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:55 PM PDT 24
Peak memory 198072 kb
Host smart-d259d450-822c-4101-8b89-221d56c0dc19
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937293529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.937293529
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.900824097
Short name T655
Test name
Test status
Simulation time 313180994 ps
CPU time 1.66 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:55 PM PDT 24
Peak memory 196064 kb
Host smart-5b3aa340-b4dd-444a-aaaf-b464eedc5507
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900824097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
900824097
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2257129904
Short name T194
Test name
Test status
Simulation time 94644572 ps
CPU time 1.13 seconds
Started Aug 12 05:14:29 PM PDT 24
Finished Aug 12 05:14:30 PM PDT 24
Peak memory 196776 kb
Host smart-5faee798-85c9-469c-928d-71bacb23e26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257129904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2257129904
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3544430289
Short name T701
Test name
Test status
Simulation time 14292947 ps
CPU time 0.66 seconds
Started Aug 12 05:14:47 PM PDT 24
Finished Aug 12 05:14:48 PM PDT 24
Peak memory 194216 kb
Host smart-3955ba19-a2cc-4eca-b019-74caa98f7724
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544430289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3544430289
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3987974241
Short name T709
Test name
Test status
Simulation time 863705571 ps
CPU time 2.87 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:40 PM PDT 24
Peak memory 198020 kb
Host smart-183fdc03-8d11-4308-a32e-d9b4ad795938
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987974241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3987974241
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.68340123
Short name T33
Test name
Test status
Simulation time 378494286 ps
CPU time 1.39 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:55 PM PDT 24
Peak memory 195612 kb
Host smart-13c8c555-0ff8-4041-9320-3ed0db59e27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68340123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.68340123
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3971258411
Short name T224
Test name
Test status
Simulation time 905607723 ps
CPU time 1.13 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:38 PM PDT 24
Peak memory 195636 kb
Host smart-30da6a68-de62-4fd4-b66d-107837262f4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971258411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3971258411
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3833043571
Short name T551
Test name
Test status
Simulation time 65976307192 ps
CPU time 185.3 seconds
Started Aug 12 05:14:31 PM PDT 24
Finished Aug 12 05:17:37 PM PDT 24
Peak memory 198328 kb
Host smart-b0cda6dd-0e3b-465c-9d3c-6e79904d69d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833043571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3833043571
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3608749026
Short name T526
Test name
Test status
Simulation time 30703075 ps
CPU time 0.61 seconds
Started Aug 12 05:14:40 PM PDT 24
Finished Aug 12 05:14:41 PM PDT 24
Peak memory 194208 kb
Host smart-70285d31-f202-4ce4-b34a-36677883a5a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608749026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3608749026
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1167128567
Short name T665
Test name
Test status
Simulation time 25322329 ps
CPU time 0.67 seconds
Started Aug 12 05:14:40 PM PDT 24
Finished Aug 12 05:14:41 PM PDT 24
Peak memory 194136 kb
Host smart-b3c8231b-d70a-41b9-a0ca-2f5a2eb42938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167128567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1167128567
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1033330387
Short name T311
Test name
Test status
Simulation time 392739466 ps
CPU time 20.89 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:58 PM PDT 24
Peak memory 196264 kb
Host smart-3bc21e20-8aa6-4bd9-abc7-f7aa11fed6c0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033330387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1033330387
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3593067282
Short name T459
Test name
Test status
Simulation time 69412908 ps
CPU time 0.92 seconds
Started Aug 12 05:14:33 PM PDT 24
Finished Aug 12 05:14:34 PM PDT 24
Peak memory 196680 kb
Host smart-fabb41c6-e23f-45df-928b-0e9522cd4308
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593067282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3593067282
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2415979023
Short name T386
Test name
Test status
Simulation time 39471874 ps
CPU time 1.07 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:49 PM PDT 24
Peak memory 195996 kb
Host smart-163b5eec-3be6-45e3-b6cb-112501726f48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415979023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2415979023
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3273442268
Short name T608
Test name
Test status
Simulation time 57302467 ps
CPU time 1.31 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 198004 kb
Host smart-0ae54afe-bb15-487d-b1c8-c4e5760e40a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273442268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3273442268
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.918200829
Short name T327
Test name
Test status
Simulation time 552125220 ps
CPU time 2.28 seconds
Started Aug 12 05:14:39 PM PDT 24
Finished Aug 12 05:14:41 PM PDT 24
Peak memory 197332 kb
Host smart-a8477b03-f07b-4af3-8e63-a27a17fdc23a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918200829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
918200829
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3813533703
Short name T492
Test name
Test status
Simulation time 45924805 ps
CPU time 0.64 seconds
Started Aug 12 05:14:47 PM PDT 24
Finished Aug 12 05:14:48 PM PDT 24
Peak memory 194512 kb
Host smart-3cb09487-2d32-48f1-bea3-fa260863d930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813533703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3813533703
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1011853841
Short name T437
Test name
Test status
Simulation time 43506136 ps
CPU time 0.95 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:14:54 PM PDT 24
Peak memory 196152 kb
Host smart-89f14777-a137-42e1-903e-9eef592eba20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011853841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1011853841
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.345174084
Short name T228
Test name
Test status
Simulation time 252640770 ps
CPU time 2.45 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 198080 kb
Host smart-7341e731-e769-464b-bc08-5ceb81bf5225
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345174084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.345174084
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2667170186
Short name T501
Test name
Test status
Simulation time 88673228 ps
CPU time 1.51 seconds
Started Aug 12 05:14:36 PM PDT 24
Finished Aug 12 05:14:38 PM PDT 24
Peak memory 196396 kb
Host smart-2e368f46-932a-4439-b45c-8ab33185992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667170186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2667170186
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.493472563
Short name T208
Test name
Test status
Simulation time 38140346 ps
CPU time 0.98 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 194836 kb
Host smart-996eaf94-950d-4c55-af36-779ed4ed17d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493472563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.493472563
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2817838527
Short name T661
Test name
Test status
Simulation time 7707560036 ps
CPU time 169.21 seconds
Started Aug 12 05:14:40 PM PDT 24
Finished Aug 12 05:17:30 PM PDT 24
Peak memory 198220 kb
Host smart-99261785-049a-487a-8198-1b7ce651defb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817838527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2817838527
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2703460048
Short name T454
Test name
Test status
Simulation time 19699611911 ps
CPU time 175.3 seconds
Started Aug 12 05:14:44 PM PDT 24
Finished Aug 12 05:17:39 PM PDT 24
Peak memory 198256 kb
Host smart-30c8eff4-493e-4e86-8b59-6b9bcb8695e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2703460048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2703460048
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1727680127
Short name T43
Test name
Test status
Simulation time 10988017 ps
CPU time 0.58 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 193896 kb
Host smart-4d5c351c-3a55-46e9-a42b-bfdfef7c56c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727680127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1727680127
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1003234765
Short name T506
Test name
Test status
Simulation time 21325137 ps
CPU time 0.66 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 194048 kb
Host smart-fb344438-7df0-4967-a3ce-b95feab16c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003234765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1003234765
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1682291917
Short name T712
Test name
Test status
Simulation time 183044542 ps
CPU time 4.69 seconds
Started Aug 12 05:14:42 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 197072 kb
Host smart-abbda0f1-1632-484f-a7f5-2c05ba066b80
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682291917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1682291917
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1889834605
Short name T609
Test name
Test status
Simulation time 65077400 ps
CPU time 0.98 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:49 PM PDT 24
Peak memory 196512 kb
Host smart-ba6827f4-1707-4771-ac26-0fefea47f82f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889834605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1889834605
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2991819344
Short name T536
Test name
Test status
Simulation time 71271433 ps
CPU time 1.13 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 197004 kb
Host smart-ca8ba519-376d-480f-bde8-f7c1be808a06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991819344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2991819344
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3339757168
Short name T570
Test name
Test status
Simulation time 117497721 ps
CPU time 1.32 seconds
Started Aug 12 05:14:43 PM PDT 24
Finished Aug 12 05:14:44 PM PDT 24
Peak memory 196384 kb
Host smart-48996ae6-aa2b-493f-8dee-d95dd5fe8ebd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339757168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3339757168
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3142227660
Short name T497
Test name
Test status
Simulation time 102245066 ps
CPU time 0.9 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 196180 kb
Host smart-fc540964-9a1b-4f34-83ad-ce7017068a96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142227660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3142227660
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.748558641
Short name T572
Test name
Test status
Simulation time 46245616 ps
CPU time 0.69 seconds
Started Aug 12 05:14:39 PM PDT 24
Finished Aug 12 05:14:40 PM PDT 24
Peak memory 195416 kb
Host smart-604ca250-3b4d-4b1b-a90e-2b64b2e6244d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748558641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.748558641
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1285672773
Short name T372
Test name
Test status
Simulation time 168536183 ps
CPU time 0.9 seconds
Started Aug 12 05:14:36 PM PDT 24
Finished Aug 12 05:14:37 PM PDT 24
Peak memory 196012 kb
Host smart-eb7dffed-864f-4b76-8dbc-824f030d7157
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285672773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1285672773
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.317381428
Short name T237
Test name
Test status
Simulation time 174520910 ps
CPU time 1.97 seconds
Started Aug 12 05:14:52 PM PDT 24
Finished Aug 12 05:14:55 PM PDT 24
Peak memory 197964 kb
Host smart-c82c9f32-3f9c-4254-b7cb-b42eb45d4ee4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317381428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.317381428
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3937792493
Short name T23
Test name
Test status
Simulation time 1095252629 ps
CPU time 1.38 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 196768 kb
Host smart-0984d3a7-f734-4d0a-a8c0-b7b7abad367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937792493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3937792493
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2214170700
Short name T131
Test name
Test status
Simulation time 239113860 ps
CPU time 1.17 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 195812 kb
Host smart-8e88b366-141a-4298-986b-aedcab0a7ff8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214170700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2214170700
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.692718636
Short name T663
Test name
Test status
Simulation time 10995445661 ps
CPU time 54.55 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 198320 kb
Host smart-db500e4d-7767-4956-ae11-27af6fed9b86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692718636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.692718636
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.29152566
Short name T254
Test name
Test status
Simulation time 20344692 ps
CPU time 0.56 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 194008 kb
Host smart-2803789c-fd89-4185-9bc9-867bb39f5054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29152566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.29152566
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2564937382
Short name T593
Test name
Test status
Simulation time 44884957 ps
CPU time 0.9 seconds
Started Aug 12 05:14:37 PM PDT 24
Finished Aug 12 05:14:38 PM PDT 24
Peak memory 196588 kb
Host smart-d1b82f47-af3c-47c5-bb06-d5f5266ba7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564937382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2564937382
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3571176774
Short name T177
Test name
Test status
Simulation time 557716983 ps
CPU time 10.03 seconds
Started Aug 12 05:14:42 PM PDT 24
Finished Aug 12 05:15:02 PM PDT 24
Peak memory 197392 kb
Host smart-996c0dbb-4b95-4c1c-a832-37a207f82e59
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571176774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3571176774
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1312969856
Short name T662
Test name
Test status
Simulation time 462066866 ps
CPU time 1.42 seconds
Started Aug 12 05:14:47 PM PDT 24
Finished Aug 12 05:14:49 PM PDT 24
Peak memory 195984 kb
Host smart-358dc4ca-2c0e-40ae-abbb-8f5bb8e492b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312969856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1312969856
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.4281007600
Short name T197
Test name
Test status
Simulation time 557931386 ps
CPU time 2.51 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:53 PM PDT 24
Peak memory 196472 kb
Host smart-df377d8c-4aa7-429c-8f4a-515b32090c7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281007600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.4281007600
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.34553861
Short name T534
Test name
Test status
Simulation time 106208416 ps
CPU time 3.03 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:54 PM PDT 24
Peak memory 196052 kb
Host smart-08262c85-f850-45e6-b2a7-7a246668e13f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34553861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.34553861
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.50913242
Short name T123
Test name
Test status
Simulation time 181614854 ps
CPU time 1.1 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 196088 kb
Host smart-218645ba-4e3e-498f-99f5-9150b45f1ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50913242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.50913242
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3936046059
Short name T29
Test name
Test status
Simulation time 192405851 ps
CPU time 1.2 seconds
Started Aug 12 05:15:05 PM PDT 24
Finished Aug 12 05:15:07 PM PDT 24
Peak memory 198096 kb
Host smart-ac07cd73-5c75-406f-a974-6e3f26e1c5d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936046059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3936046059
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1351533001
Short name T425
Test name
Test status
Simulation time 871826884 ps
CPU time 2.78 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:54 PM PDT 24
Peak memory 198108 kb
Host smart-8e295a3f-9aa5-4475-b410-61414a727a3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351533001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1351533001
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.711719873
Short name T264
Test name
Test status
Simulation time 45897803 ps
CPU time 1.03 seconds
Started Aug 12 05:14:44 PM PDT 24
Finished Aug 12 05:14:45 PM PDT 24
Peak memory 195752 kb
Host smart-fd6a519f-f906-43f8-9ca5-7f6efa2bc530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711719873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.711719873
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2220734361
Short name T643
Test name
Test status
Simulation time 132181620 ps
CPU time 1.13 seconds
Started Aug 12 05:14:40 PM PDT 24
Finished Aug 12 05:14:42 PM PDT 24
Peak memory 195764 kb
Host smart-2a14b4fc-195e-42e9-9b05-4630b409e2bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220734361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2220734361
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3456691673
Short name T564
Test name
Test status
Simulation time 20817121747 ps
CPU time 148.86 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:17:18 PM PDT 24
Peak memory 198168 kb
Host smart-85a8c48f-9c2b-45af-9789-3e5de9368fae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456691673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3456691673
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3839916215
Short name T582
Test name
Test status
Simulation time 38781261 ps
CPU time 0.55 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 193972 kb
Host smart-0e5376f0-e2c1-4044-b510-10d5ddad302f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839916215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3839916215
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3470904687
Short name T281
Test name
Test status
Simulation time 20303391 ps
CPU time 0.68 seconds
Started Aug 12 05:14:47 PM PDT 24
Finished Aug 12 05:14:53 PM PDT 24
Peak memory 195180 kb
Host smart-3810d5fa-6bd2-40bc-8efa-501a70182249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470904687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3470904687
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2753847468
Short name T681
Test name
Test status
Simulation time 686409536 ps
CPU time 19.52 seconds
Started Aug 12 05:14:54 PM PDT 24
Finished Aug 12 05:15:13 PM PDT 24
Peak memory 196936 kb
Host smart-93f25e1f-34d3-4d19-bb33-2bd72febc64c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753847468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2753847468
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3445546702
Short name T204
Test name
Test status
Simulation time 100021399 ps
CPU time 0.86 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 196092 kb
Host smart-fa620df2-b057-4739-8e9f-f1fe5ea5033d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445546702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3445546702
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2196233594
Short name T221
Test name
Test status
Simulation time 247606472 ps
CPU time 1.38 seconds
Started Aug 12 05:14:58 PM PDT 24
Finished Aug 12 05:15:00 PM PDT 24
Peak memory 197168 kb
Host smart-d770736b-932c-4a1e-a8a0-23641d19e744
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196233594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2196233594
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1290868674
Short name T159
Test name
Test status
Simulation time 98814922 ps
CPU time 3.6 seconds
Started Aug 12 05:15:03 PM PDT 24
Finished Aug 12 05:15:06 PM PDT 24
Peak memory 198172 kb
Host smart-4ceaacf6-e511-4b1d-a961-48cb8162fae5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290868674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1290868674
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.322153255
Short name T273
Test name
Test status
Simulation time 1246976963 ps
CPU time 3.5 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:54 PM PDT 24
Peak memory 196644 kb
Host smart-ed0ab754-36f2-41c5-ae86-0bbb15483ec0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322153255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
322153255
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2933345255
Short name T602
Test name
Test status
Simulation time 196946516 ps
CPU time 0.94 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 196684 kb
Host smart-9af12bfc-d179-4376-a1b7-ddc598760f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933345255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2933345255
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3766427502
Short name T34
Test name
Test status
Simulation time 40053689 ps
CPU time 0.89 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 195940 kb
Host smart-5b3cc345-4c0d-401c-8dd1-5b751ffc882a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766427502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3766427502
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1386055046
Short name T483
Test name
Test status
Simulation time 873981995 ps
CPU time 3.67 seconds
Started Aug 12 05:15:01 PM PDT 24
Finished Aug 12 05:15:04 PM PDT 24
Peak memory 198036 kb
Host smart-66fd7063-bdc4-4aee-ae69-fc6b3600cf9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386055046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1386055046
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2406787155
Short name T297
Test name
Test status
Simulation time 133181758 ps
CPU time 0.88 seconds
Started Aug 12 05:14:42 PM PDT 24
Finished Aug 12 05:14:43 PM PDT 24
Peak memory 195424 kb
Host smart-47a17f67-22d8-4292-852c-5c1e1dde67c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406787155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2406787155
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1278510345
Short name T473
Test name
Test status
Simulation time 93878615 ps
CPU time 0.98 seconds
Started Aug 12 05:14:47 PM PDT 24
Finished Aug 12 05:14:48 PM PDT 24
Peak memory 195632 kb
Host smart-51a53c97-dd2a-4b38-8123-be403841a6c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278510345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1278510345
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3215193291
Short name T353
Test name
Test status
Simulation time 3881520875 ps
CPU time 102.87 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:16:34 PM PDT 24
Peak memory 198168 kb
Host smart-c0353629-f73a-4af0-b53a-4879c5fed6df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215193291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3215193291
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1098757274
Short name T617
Test name
Test status
Simulation time 48182524 ps
CPU time 0.58 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:14:54 PM PDT 24
Peak memory 194216 kb
Host smart-04cbb387-a206-4eca-ad67-dbda7d488d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098757274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1098757274
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2469416588
Short name T192
Test name
Test status
Simulation time 71628794 ps
CPU time 0.77 seconds
Started Aug 12 05:14:52 PM PDT 24
Finished Aug 12 05:14:53 PM PDT 24
Peak memory 195264 kb
Host smart-fb482a3c-1c7a-4a3e-9465-603def527989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469416588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2469416588
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.386810580
Short name T169
Test name
Test status
Simulation time 1112897496 ps
CPU time 6.75 seconds
Started Aug 12 05:14:52 PM PDT 24
Finished Aug 12 05:14:59 PM PDT 24
Peak memory 195600 kb
Host smart-e626c85f-466f-4049-a7fd-b40a1d4064f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386810580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.386810580
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2833370648
Short name T138
Test name
Test status
Simulation time 204841440 ps
CPU time 0.93 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:14:54 PM PDT 24
Peak memory 196420 kb
Host smart-a695e5ab-5b1c-4bfe-814c-b46b7916d033
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833370648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2833370648
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.346481621
Short name T328
Test name
Test status
Simulation time 74465141 ps
CPU time 0.64 seconds
Started Aug 12 05:14:47 PM PDT 24
Finished Aug 12 05:14:48 PM PDT 24
Peak memory 194328 kb
Host smart-2b66b2e8-9a2e-4b73-aed3-60be9e39d53f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346481621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.346481621
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1435196761
Short name T220
Test name
Test status
Simulation time 192124936 ps
CPU time 2.12 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 198092 kb
Host smart-77ae2209-8d51-483f-93dd-b12f8dcc1fee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435196761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1435196761
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.411708591
Short name T668
Test name
Test status
Simulation time 395696388 ps
CPU time 3.11 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 197216 kb
Host smart-4261279c-30a3-40d1-bf86-e8e3c75a0437
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411708591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
411708591
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.49454611
Short name T666
Test name
Test status
Simulation time 66281158 ps
CPU time 0.68 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 195104 kb
Host smart-1b73143e-4d15-4a6b-8e8a-8729cb7e128d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49454611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.49454611
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.396168802
Short name T261
Test name
Test status
Simulation time 26539158 ps
CPU time 0.7 seconds
Started Aug 12 05:15:06 PM PDT 24
Finished Aug 12 05:15:06 PM PDT 24
Peak memory 195472 kb
Host smart-3e70a726-40f6-444c-a4af-0860de54c4b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396168802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.396168802
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2536727337
Short name T240
Test name
Test status
Simulation time 1705770839 ps
CPU time 5.36 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:57 PM PDT 24
Peak memory 198028 kb
Host smart-abfc65e2-b99e-46dd-bf7a-03d32862f7a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536727337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2536727337
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.42683728
Short name T323
Test name
Test status
Simulation time 57447005 ps
CPU time 1.05 seconds
Started Aug 12 05:14:57 PM PDT 24
Finished Aug 12 05:14:58 PM PDT 24
Peak memory 196344 kb
Host smart-761464c7-f85e-4ed0-8f14-11234de6bf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42683728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.42683728
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3305025588
Short name T176
Test name
Test status
Simulation time 228859835 ps
CPU time 1.49 seconds
Started Aug 12 05:15:08 PM PDT 24
Finished Aug 12 05:15:09 PM PDT 24
Peak memory 196980 kb
Host smart-545c2331-e3de-4ea1-b147-003aaf2ee005
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305025588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3305025588
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2172270559
Short name T349
Test name
Test status
Simulation time 166577247104 ps
CPU time 198.92 seconds
Started Aug 12 05:14:57 PM PDT 24
Finished Aug 12 05:18:16 PM PDT 24
Peak memory 198256 kb
Host smart-7b5576e0-7ed5-490f-b34c-21513a49ed53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172270559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2172270559
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3917995246
Short name T67
Test name
Test status
Simulation time 13595937136 ps
CPU time 223.72 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:18:35 PM PDT 24
Peak memory 198432 kb
Host smart-a5539717-a7c3-4433-bb96-e6a41033358e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3917995246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3917995246
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4071540661
Short name T461
Test name
Test status
Simulation time 23269920 ps
CPU time 0.56 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 194016 kb
Host smart-5be367b5-32aa-4506-a66e-0966d31eb3a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071540661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4071540661
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4185517597
Short name T199
Test name
Test status
Simulation time 65474929 ps
CPU time 0.7 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 195884 kb
Host smart-9fb541a1-300a-4734-8e81-34c4bb82845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185517597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4185517597
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1951919833
Short name T133
Test name
Test status
Simulation time 680566864 ps
CPU time 9.41 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:58 PM PDT 24
Peak memory 196672 kb
Host smart-64d65c8a-bf50-42df-9606-590d1f2b012e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951919833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1951919833
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1025465777
Short name T658
Test name
Test status
Simulation time 575139739 ps
CPU time 1.01 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 197828 kb
Host smart-cc1076ff-9bbb-4dae-a67f-ce5a57ea4b41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025465777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1025465777
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2513990790
Short name T259
Test name
Test status
Simulation time 758863624 ps
CPU time 1.39 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 197312 kb
Host smart-2b6c89d3-c5a4-448d-995b-8e9a561ca92f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513990790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2513990790
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2493858951
Short name T584
Test name
Test status
Simulation time 35016756 ps
CPU time 0.91 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:49 PM PDT 24
Peak memory 196192 kb
Host smart-26daeeec-38d3-4a82-8add-1c7cf4b32457
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493858951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2493858951
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3561666676
Short name T514
Test name
Test status
Simulation time 774155967 ps
CPU time 2.21 seconds
Started Aug 12 05:14:47 PM PDT 24
Finished Aug 12 05:14:50 PM PDT 24
Peak memory 198212 kb
Host smart-1ad82468-7527-42d6-8396-d0c772e0aa8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561666676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3561666676
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1002130480
Short name T335
Test name
Test status
Simulation time 49506783 ps
CPU time 1.03 seconds
Started Aug 12 05:14:52 PM PDT 24
Finished Aug 12 05:14:53 PM PDT 24
Peak memory 196156 kb
Host smart-a8c474a9-137c-4273-9381-2a12dbef2f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002130480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1002130480
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3535092854
Short name T508
Test name
Test status
Simulation time 62984496 ps
CPU time 0.81 seconds
Started Aug 12 05:14:55 PM PDT 24
Finished Aug 12 05:14:56 PM PDT 24
Peak memory 196508 kb
Host smart-cd1a183f-f2b8-487e-9189-154c1a52dea6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535092854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3535092854
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2466478008
Short name T20
Test name
Test status
Simulation time 135953379 ps
CPU time 1.95 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 198016 kb
Host smart-35c3975f-20bf-4c3c-a602-f97b0e464550
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466478008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2466478008
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.945253395
Short name T507
Test name
Test status
Simulation time 91466192 ps
CPU time 1.06 seconds
Started Aug 12 05:14:52 PM PDT 24
Finished Aug 12 05:14:54 PM PDT 24
Peak memory 196540 kb
Host smart-9e1f45cb-0d7e-48ed-b2b3-e04f65dcba39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945253395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.945253395
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.719063751
Short name T340
Test name
Test status
Simulation time 72149041 ps
CPU time 0.81 seconds
Started Aug 12 05:14:48 PM PDT 24
Finished Aug 12 05:14:49 PM PDT 24
Peak memory 195420 kb
Host smart-63e075d9-3298-46f3-9b5b-ec1581538685
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719063751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.719063751
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2585971656
Short name T103
Test name
Test status
Simulation time 69326550136 ps
CPU time 146.34 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:17:20 PM PDT 24
Peak memory 198324 kb
Host smart-8d11582f-92aa-49f6-a427-d8d1e420dd4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585971656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2585971656
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1476518499
Short name T434
Test name
Test status
Simulation time 6335417251 ps
CPU time 212.05 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:18:26 PM PDT 24
Peak memory 198264 kb
Host smart-ad2afc7a-fbc1-4048-ae56-7f402e18dc53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1476518499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.1476518499
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1964200101
Short name T574
Test name
Test status
Simulation time 51410978 ps
CPU time 0.58 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:13:57 PM PDT 24
Peak memory 194032 kb
Host smart-2866a533-38ff-4c6e-bf99-92326d9bf8c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964200101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1964200101
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.747662158
Short name T637
Test name
Test status
Simulation time 41637146 ps
CPU time 0.93 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:13:57 PM PDT 24
Peak memory 196064 kb
Host smart-44cb7df2-b7a5-49a7-bc1f-e18aa7460f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747662158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.747662158
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.59739600
Short name T603
Test name
Test status
Simulation time 169411848 ps
CPU time 6.04 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:14:05 PM PDT 24
Peak memory 196888 kb
Host smart-c5644326-3b00-4ae0-8031-10a480c7ee0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59739600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress.59739600
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2129398623
Short name T516
Test name
Test status
Simulation time 74488417 ps
CPU time 0.79 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:13:57 PM PDT 24
Peak memory 196640 kb
Host smart-00e0108b-dc45-4dd9-a8a0-313e95ace71f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129398623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2129398623
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2148851254
Short name T331
Test name
Test status
Simulation time 76809276 ps
CPU time 1.25 seconds
Started Aug 12 05:14:04 PM PDT 24
Finished Aug 12 05:14:06 PM PDT 24
Peak memory 196136 kb
Host smart-5183a6bf-2aac-4667-9456-37c7fd820440
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148851254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2148851254
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1319056323
Short name T308
Test name
Test status
Simulation time 269174203 ps
CPU time 2.99 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:14:02 PM PDT 24
Peak memory 196568 kb
Host smart-ba0941d9-7e37-4769-8d19-07515e38fa52
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319056323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1319056323
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.4264118533
Short name T689
Test name
Test status
Simulation time 418829476 ps
CPU time 2.77 seconds
Started Aug 12 05:13:55 PM PDT 24
Finished Aug 12 05:13:58 PM PDT 24
Peak memory 196580 kb
Host smart-14576b95-9af8-462d-aae5-ea0837d05907
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264118533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
4264118533
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3931615282
Short name T623
Test name
Test status
Simulation time 33961936 ps
CPU time 0.67 seconds
Started Aug 12 05:13:55 PM PDT 24
Finished Aug 12 05:13:56 PM PDT 24
Peak memory 194320 kb
Host smart-7515ce43-7e05-4663-bfee-5ad12bf5686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931615282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3931615282
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3437808123
Short name T356
Test name
Test status
Simulation time 47369330 ps
CPU time 0.99 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:14:00 PM PDT 24
Peak memory 196776 kb
Host smart-44fd29be-5dc7-4726-8104-ec693dbc1a2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437808123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3437808123
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.106503741
Short name T559
Test name
Test status
Simulation time 594990750 ps
CPU time 6.92 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:14:05 PM PDT 24
Peak memory 198112 kb
Host smart-e161eaaf-0161-4008-ba4d-4f013f85f84b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106503741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.106503741
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.4096380551
Short name T52
Test name
Test status
Simulation time 89362611 ps
CPU time 0.89 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:13:58 PM PDT 24
Peak memory 214780 kb
Host smart-fcc65423-694c-4911-a376-4c9b702bc3b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096380551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.4096380551
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2552719104
Short name T672
Test name
Test status
Simulation time 583428706 ps
CPU time 1.05 seconds
Started Aug 12 05:13:59 PM PDT 24
Finished Aug 12 05:14:00 PM PDT 24
Peak memory 195640 kb
Host smart-5f7293db-6d65-49e0-acee-d8f85fd4fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552719104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2552719104
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2219330380
Short name T490
Test name
Test status
Simulation time 149521764 ps
CPU time 0.85 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:13:57 PM PDT 24
Peak memory 195460 kb
Host smart-55265aca-c593-47cd-a626-c3ac31ebd908
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219330380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2219330380
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1812395536
Short name T646
Test name
Test status
Simulation time 7637018346 ps
CPU time 179.42 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:16:58 PM PDT 24
Peak memory 198292 kb
Host smart-0163cf42-6009-476c-9197-af0ab874c30f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812395536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1812395536
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3774514406
Short name T124
Test name
Test status
Simulation time 24856615 ps
CPU time 0.6 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 194904 kb
Host smart-d5608371-6a9e-4ddf-ac06-85112487cc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774514406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3774514406
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3054675277
Short name T350
Test name
Test status
Simulation time 32102204 ps
CPU time 0.75 seconds
Started Aug 12 05:14:46 PM PDT 24
Finished Aug 12 05:14:47 PM PDT 24
Peak memory 196060 kb
Host smart-a3438e8a-4cb3-4e02-b5d1-bae4558bc27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054675277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3054675277
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.645654770
Short name T380
Test name
Test status
Simulation time 546876220 ps
CPU time 16.21 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:15:10 PM PDT 24
Peak memory 198060 kb
Host smart-0904df10-38c2-41d5-8fb7-741db7fa1c63
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645654770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.645654770
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3726291877
Short name T1
Test name
Test status
Simulation time 47014695 ps
CPU time 0.79 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 196588 kb
Host smart-6188b328-cc77-4848-b5f0-aca0646f6531
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726291877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3726291877
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1636755557
Short name T346
Test name
Test status
Simulation time 44504162 ps
CPU time 1.37 seconds
Started Aug 12 05:15:04 PM PDT 24
Finished Aug 12 05:15:06 PM PDT 24
Peak memory 198188 kb
Host smart-d2ae9f66-dcc1-4b2c-b0dc-488059562109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636755557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1636755557
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2556801421
Short name T449
Test name
Test status
Simulation time 96488582 ps
CPU time 1.8 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 198112 kb
Host smart-35f64f39-a065-4b60-9127-2bd23a250f4c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556801421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2556801421
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3772231504
Short name T373
Test name
Test status
Simulation time 225657584 ps
CPU time 3.3 seconds
Started Aug 12 05:14:40 PM PDT 24
Finished Aug 12 05:14:43 PM PDT 24
Peak memory 197324 kb
Host smart-11a75d23-daa8-4dbc-9466-5019265c149d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772231504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3772231504
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2685012949
Short name T705
Test name
Test status
Simulation time 296559469 ps
CPU time 1.16 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:14:54 PM PDT 24
Peak memory 196096 kb
Host smart-023573e8-8b13-4ca8-b00d-b53e86e8b647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685012949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2685012949
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1864090001
Short name T494
Test name
Test status
Simulation time 35682543 ps
CPU time 0.63 seconds
Started Aug 12 05:14:42 PM PDT 24
Finished Aug 12 05:14:43 PM PDT 24
Peak memory 194872 kb
Host smart-360d040c-5c19-43d8-b149-c4f85eb9ea7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864090001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1864090001
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2145688793
Short name T714
Test name
Test status
Simulation time 134358908 ps
CPU time 3.18 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:14:56 PM PDT 24
Peak memory 198092 kb
Host smart-39ff2269-a222-44c1-99bc-8626a91937bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145688793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2145688793
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2721674885
Short name T268
Test name
Test status
Simulation time 190256238 ps
CPU time 0.97 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 195756 kb
Host smart-5fc24a06-531e-40bf-b288-a125428e9174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721674885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2721674885
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3649568508
Short name T472
Test name
Test status
Simulation time 91785869 ps
CPU time 1.28 seconds
Started Aug 12 05:14:52 PM PDT 24
Finished Aug 12 05:14:53 PM PDT 24
Peak memory 196916 kb
Host smart-c25d0a5a-738c-4792-a080-34efe83c9ff2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649568508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3649568508
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1894385351
Short name T588
Test name
Test status
Simulation time 7681233798 ps
CPU time 94.34 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:16:25 PM PDT 24
Peak memory 198312 kb
Host smart-49b853a1-ba85-4974-9476-52168c94eca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894385351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1894385351
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.617046766
Short name T149
Test name
Test status
Simulation time 15371774 ps
CPU time 0.61 seconds
Started Aug 12 05:14:58 PM PDT 24
Finished Aug 12 05:14:59 PM PDT 24
Peak memory 194016 kb
Host smart-13b99db7-06cb-4de0-955e-33d5d5d99bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617046766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.617046766
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1737875665
Short name T379
Test name
Test status
Simulation time 26877386 ps
CPU time 0.8 seconds
Started Aug 12 05:14:52 PM PDT 24
Finished Aug 12 05:14:53 PM PDT 24
Peak memory 195468 kb
Host smart-e92ed90f-9fcd-401a-98cf-28546b14a2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737875665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1737875665
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3358397908
Short name T521
Test name
Test status
Simulation time 1813900970 ps
CPU time 26.85 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:15:20 PM PDT 24
Peak memory 196820 kb
Host smart-005f7736-ba11-4407-bb23-59d397a68c72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358397908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3358397908
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3270761443
Short name T555
Test name
Test status
Simulation time 48874540 ps
CPU time 0.77 seconds
Started Aug 12 05:14:57 PM PDT 24
Finished Aug 12 05:14:58 PM PDT 24
Peak memory 196564 kb
Host smart-b4e05fc1-2493-4a25-92ee-ff36fe6f4c86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270761443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3270761443
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2674930206
Short name T168
Test name
Test status
Simulation time 162341826 ps
CPU time 1.43 seconds
Started Aug 12 05:14:58 PM PDT 24
Finished Aug 12 05:15:00 PM PDT 24
Peak memory 197292 kb
Host smart-c1b56022-e64c-4921-9ae7-30a6459dc35e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674930206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2674930206
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.690887135
Short name T271
Test name
Test status
Simulation time 362749773 ps
CPU time 2.65 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:54 PM PDT 24
Peak memory 196596 kb
Host smart-b6c8e3f3-1ea1-44de-a7e9-b770fd0eb974
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690887135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.690887135
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2653634547
Short name T601
Test name
Test status
Simulation time 48579623 ps
CPU time 1.34 seconds
Started Aug 12 05:15:00 PM PDT 24
Finished Aug 12 05:15:01 PM PDT 24
Peak memory 197716 kb
Host smart-cc9f4c49-2adf-4e0c-b053-88ea52575322
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653634547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2653634547
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3678561190
Short name T270
Test name
Test status
Simulation time 18158440 ps
CPU time 0.66 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 194424 kb
Host smart-80e8f501-0cf7-47fc-a4a1-4e6062a63968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678561190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3678561190
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.753995376
Short name T539
Test name
Test status
Simulation time 51381889 ps
CPU time 0.73 seconds
Started Aug 12 05:15:18 PM PDT 24
Finished Aug 12 05:15:19 PM PDT 24
Peak memory 196236 kb
Host smart-e56a776d-5b3e-4fcc-98dd-f51c374363e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753995376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.753995376
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2521718750
Short name T652
Test name
Test status
Simulation time 412089878 ps
CPU time 4.85 seconds
Started Aug 12 05:15:01 PM PDT 24
Finished Aug 12 05:15:06 PM PDT 24
Peak memory 198132 kb
Host smart-39633303-2a3d-47f5-b313-674ae5cebb0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521718750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2521718750
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1942136071
Short name T407
Test name
Test status
Simulation time 120012862 ps
CPU time 0.74 seconds
Started Aug 12 05:15:06 PM PDT 24
Finished Aug 12 05:15:07 PM PDT 24
Peak memory 195968 kb
Host smart-e97d6691-dc56-4928-a26b-abc5ce7bf384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942136071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1942136071
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.956329507
Short name T14
Test name
Test status
Simulation time 33640333 ps
CPU time 0.91 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 195692 kb
Host smart-653608e4-24de-4321-ba90-2713e0b69d79
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956329507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.956329507
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1586243657
Short name T325
Test name
Test status
Simulation time 14665140935 ps
CPU time 147.09 seconds
Started Aug 12 05:14:55 PM PDT 24
Finished Aug 12 05:17:22 PM PDT 24
Peak memory 198276 kb
Host smart-4b626d72-3dda-40af-ad34-eb73d065f103
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586243657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1586243657
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.864845571
Short name T65
Test name
Test status
Simulation time 3128469468 ps
CPU time 48.69 seconds
Started Aug 12 05:15:05 PM PDT 24
Finished Aug 12 05:15:54 PM PDT 24
Peak memory 198312 kb
Host smart-dd638e42-3b1a-4518-8335-73ffa716a2f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=864845571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.864845571
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3169407477
Short name T398
Test name
Test status
Simulation time 102329241 ps
CPU time 0.57 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:49 PM PDT 24
Peak memory 194208 kb
Host smart-e1b1f6a2-f14e-4940-83c0-27cc32093334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169407477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3169407477
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.371863388
Short name T499
Test name
Test status
Simulation time 36497664 ps
CPU time 0.87 seconds
Started Aug 12 05:14:56 PM PDT 24
Finished Aug 12 05:14:57 PM PDT 24
Peak memory 197244 kb
Host smart-d8f82ce7-cf04-4cfd-aea4-44952a95b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371863388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.371863388
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2148125335
Short name T713
Test name
Test status
Simulation time 242370440 ps
CPU time 8.72 seconds
Started Aug 12 05:15:02 PM PDT 24
Finished Aug 12 05:15:11 PM PDT 24
Peak memory 197240 kb
Host smart-e82c7b39-0bcb-4819-9f6e-6ca12df0451d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148125335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2148125335
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2336831939
Short name T200
Test name
Test status
Simulation time 71618701 ps
CPU time 1.03 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:14:54 PM PDT 24
Peak memory 196624 kb
Host smart-e3eaad7d-d48d-4980-964f-8e11d0f7422f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336831939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2336831939
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3712374678
Short name T229
Test name
Test status
Simulation time 114500812 ps
CPU time 1.22 seconds
Started Aug 12 05:14:49 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 196636 kb
Host smart-8b701e6e-727c-49d9-8dac-e98fc6cdc283
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712374678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3712374678
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2673087285
Short name T447
Test name
Test status
Simulation time 77681294 ps
CPU time 0.93 seconds
Started Aug 12 05:14:57 PM PDT 24
Finished Aug 12 05:14:58 PM PDT 24
Peak memory 196180 kb
Host smart-7230b838-74d3-4738-bb2f-343bc1092729
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673087285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2673087285
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.877109116
Short name T592
Test name
Test status
Simulation time 619228605 ps
CPU time 2.16 seconds
Started Aug 12 05:14:54 PM PDT 24
Finished Aug 12 05:14:56 PM PDT 24
Peak memory 198128 kb
Host smart-92f80841-de56-4347-ba9a-ceed0a0d026d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877109116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
877109116
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1332596522
Short name T448
Test name
Test status
Simulation time 123217953 ps
CPU time 1.21 seconds
Started Aug 12 05:15:10 PM PDT 24
Finished Aug 12 05:15:11 PM PDT 24
Peak memory 195912 kb
Host smart-685e3009-ae7f-4289-a444-f9d666d10e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332596522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1332596522
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.688257036
Short name T402
Test name
Test status
Simulation time 57469633 ps
CPU time 1.16 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 197152 kb
Host smart-36214720-ee2f-43f9-a31d-da31244cf10e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688257036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.688257036
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.787752104
Short name T392
Test name
Test status
Simulation time 62716225 ps
CPU time 1.19 seconds
Started Aug 12 05:14:54 PM PDT 24
Finished Aug 12 05:14:55 PM PDT 24
Peak memory 198152 kb
Host smart-ee775d26-777f-4a86-bdf1-36f17a876eb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787752104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.787752104
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3982179202
Short name T113
Test name
Test status
Simulation time 44691581 ps
CPU time 1.31 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 196792 kb
Host smart-6d75b6d2-ad0c-41a7-bf1a-54b5eb220b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982179202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3982179202
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1257547940
Short name T579
Test name
Test status
Simulation time 32818770 ps
CPU time 1.16 seconds
Started Aug 12 05:14:58 PM PDT 24
Finished Aug 12 05:14:59 PM PDT 24
Peak memory 196640 kb
Host smart-dce48c6e-46bb-478c-a54d-79a2a7957b90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257547940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1257547940
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1462611792
Short name T272
Test name
Test status
Simulation time 33505761630 ps
CPU time 170.28 seconds
Started Aug 12 05:14:50 PM PDT 24
Finished Aug 12 05:17:40 PM PDT 24
Peak memory 198236 kb
Host smart-60a35eaa-af13-46d3-be2a-0190d6290bb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462611792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1462611792
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2042468598
Short name T64
Test name
Test status
Simulation time 2971481376 ps
CPU time 94.94 seconds
Started Aug 12 05:15:06 PM PDT 24
Finished Aug 12 05:16:41 PM PDT 24
Peak memory 198372 kb
Host smart-ac893151-1579-446b-8ff8-5deb9a5f54ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2042468598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2042468598
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3649145536
Short name T387
Test name
Test status
Simulation time 13878840 ps
CPU time 0.58 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:21 PM PDT 24
Peak memory 193588 kb
Host smart-1d611390-7b94-445e-a3df-42f13e09130e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649145536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3649145536
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2831403653
Short name T413
Test name
Test status
Simulation time 51113785 ps
CPU time 0.9 seconds
Started Aug 12 05:15:01 PM PDT 24
Finished Aug 12 05:15:02 PM PDT 24
Peak memory 196328 kb
Host smart-fad80e00-b038-4826-b627-b1f284a6d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831403653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2831403653
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.47560813
Short name T702
Test name
Test status
Simulation time 764354035 ps
CPU time 21.36 seconds
Started Aug 12 05:15:02 PM PDT 24
Finished Aug 12 05:15:23 PM PDT 24
Peak memory 195632 kb
Host smart-6f8e647d-91ab-431d-b8ed-3a6a0dae830c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47560813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stress
.47560813
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.404090656
Short name T638
Test name
Test status
Simulation time 58923017 ps
CPU time 0.9 seconds
Started Aug 12 05:15:00 PM PDT 24
Finished Aug 12 05:15:01 PM PDT 24
Peak memory 196800 kb
Host smart-065eb13a-0a81-40a6-af62-beffa8164859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404090656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.404090656
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1653336121
Short name T303
Test name
Test status
Simulation time 81832312 ps
CPU time 0.77 seconds
Started Aug 12 05:14:51 PM PDT 24
Finished Aug 12 05:14:52 PM PDT 24
Peak memory 196276 kb
Host smart-e2d13d27-7795-4eca-a5d3-9318dd704f06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653336121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1653336121
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2418841152
Short name T232
Test name
Test status
Simulation time 56898563 ps
CPU time 2.25 seconds
Started Aug 12 05:14:56 PM PDT 24
Finished Aug 12 05:14:58 PM PDT 24
Peak memory 198136 kb
Host smart-66992a19-fbb9-489e-9c96-63cd6287ea5c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418841152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2418841152
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.855576392
Short name T330
Test name
Test status
Simulation time 54296869 ps
CPU time 0.9 seconds
Started Aug 12 05:15:05 PM PDT 24
Finished Aug 12 05:15:06 PM PDT 24
Peak memory 195180 kb
Host smart-3689f27a-e327-4358-a907-7096bef83606
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855576392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
855576392
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1438094697
Short name T707
Test name
Test status
Simulation time 78661166 ps
CPU time 0.83 seconds
Started Aug 12 05:15:01 PM PDT 24
Finished Aug 12 05:15:02 PM PDT 24
Peak memory 195556 kb
Host smart-c296018e-fdc4-48f2-8c8f-4e566debd647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438094697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1438094697
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.747933650
Short name T216
Test name
Test status
Simulation time 51216675 ps
CPU time 0.94 seconds
Started Aug 12 05:14:59 PM PDT 24
Finished Aug 12 05:15:00 PM PDT 24
Peak memory 196152 kb
Host smart-9d802790-2a18-4d38-a5c5-52d4f7654835
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747933650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.747933650
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1525715769
Short name T496
Test name
Test status
Simulation time 217239456 ps
CPU time 3.49 seconds
Started Aug 12 05:15:10 PM PDT 24
Finished Aug 12 05:15:14 PM PDT 24
Peak memory 198092 kb
Host smart-31efaa75-fab3-4c95-a683-c5b375c51ea0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525715769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1525715769
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.278322477
Short name T145
Test name
Test status
Simulation time 102787337 ps
CPU time 0.8 seconds
Started Aug 12 05:15:07 PM PDT 24
Finished Aug 12 05:15:07 PM PDT 24
Peak memory 195992 kb
Host smart-5d6cc4bc-3983-48f9-b8f5-c6009719fddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278322477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.278322477
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3650644327
Short name T59
Test name
Test status
Simulation time 847487983 ps
CPU time 1.21 seconds
Started Aug 12 05:14:52 PM PDT 24
Finished Aug 12 05:14:53 PM PDT 24
Peak memory 195624 kb
Host smart-95b54338-ab03-48e2-9648-6a84fcc5714c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650644327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3650644327
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.748878079
Short name T390
Test name
Test status
Simulation time 15107184039 ps
CPU time 165.95 seconds
Started Aug 12 05:14:55 PM PDT 24
Finished Aug 12 05:17:41 PM PDT 24
Peak memory 198192 kb
Host smart-f454116b-295d-48a2-a374-a7133bf57df1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748878079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.748878079
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.4113685790
Short name T36
Test name
Test status
Simulation time 1432512574 ps
CPU time 29.26 seconds
Started Aug 12 05:14:55 PM PDT 24
Finished Aug 12 05:15:25 PM PDT 24
Peak memory 198236 kb
Host smart-da7efbea-ff69-4914-b0b4-61d36fd29f63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4113685790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.4113685790
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.4197361604
Short name T58
Test name
Test status
Simulation time 42462692 ps
CPU time 0.59 seconds
Started Aug 12 05:15:03 PM PDT 24
Finished Aug 12 05:15:03 PM PDT 24
Peak memory 194616 kb
Host smart-f62cbe8d-29af-4234-bf31-794dfc2f018b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197361604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.4197361604
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.716887779
Short name T410
Test name
Test status
Simulation time 77129351 ps
CPU time 0.56 seconds
Started Aug 12 05:15:18 PM PDT 24
Finished Aug 12 05:15:18 PM PDT 24
Peak memory 194024 kb
Host smart-0eabeea8-9e28-4e7f-98e7-51e22c8bc2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716887779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.716887779
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.4155864454
Short name T374
Test name
Test status
Simulation time 578033280 ps
CPU time 20.94 seconds
Started Aug 12 05:14:53 PM PDT 24
Finished Aug 12 05:15:14 PM PDT 24
Peak memory 196332 kb
Host smart-90c24bd1-9597-4196-94c9-26a3ab0599f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155864454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.4155864454
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2444771925
Short name T591
Test name
Test status
Simulation time 265199517 ps
CPU time 0.82 seconds
Started Aug 12 05:15:09 PM PDT 24
Finished Aug 12 05:15:10 PM PDT 24
Peak memory 195916 kb
Host smart-b79d9979-b497-43bb-a4dd-96e1ee0804dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444771925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2444771925
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.795803727
Short name T527
Test name
Test status
Simulation time 73454302 ps
CPU time 0.72 seconds
Started Aug 12 05:15:05 PM PDT 24
Finished Aug 12 05:15:06 PM PDT 24
Peak memory 196096 kb
Host smart-d602fbcc-826f-4338-a257-94ed489ef11f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795803727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.795803727
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1336120230
Short name T336
Test name
Test status
Simulation time 52066810 ps
CPU time 1.4 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:26 PM PDT 24
Peak memory 196296 kb
Host smart-e02a60cc-317e-4214-854e-3c5a7f807cae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336120230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1336120230
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3964232346
Short name T626
Test name
Test status
Simulation time 40410908 ps
CPU time 0.63 seconds
Started Aug 12 05:15:06 PM PDT 24
Finished Aug 12 05:15:07 PM PDT 24
Peak memory 194328 kb
Host smart-d800f87f-0e35-4aed-ab54-620a8314d755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964232346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3964232346
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2656385891
Short name T531
Test name
Test status
Simulation time 36619412 ps
CPU time 0.93 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:20 PM PDT 24
Peak memory 196164 kb
Host smart-c56d0869-30df-4dcc-8bb6-418caafba7d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656385891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2656385891
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2727403322
Short name T236
Test name
Test status
Simulation time 26176139 ps
CPU time 1.22 seconds
Started Aug 12 05:15:04 PM PDT 24
Finished Aug 12 05:15:05 PM PDT 24
Peak memory 197932 kb
Host smart-d0b10a85-809f-4558-8b58-3be3708123fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727403322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2727403322
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1253739071
Short name T348
Test name
Test status
Simulation time 141116049 ps
CPU time 0.84 seconds
Started Aug 12 05:15:17 PM PDT 24
Finished Aug 12 05:15:19 PM PDT 24
Peak memory 195472 kb
Host smart-00218597-5d4f-47d1-bae4-b81e0db7e62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253739071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1253739071
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2721732261
Short name T256
Test name
Test status
Simulation time 26627711 ps
CPU time 0.83 seconds
Started Aug 12 05:14:54 PM PDT 24
Finished Aug 12 05:14:55 PM PDT 24
Peak memory 195980 kb
Host smart-2a5b7195-e97a-4c70-8340-adf344b12545
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721732261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2721732261
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1683494850
Short name T184
Test name
Test status
Simulation time 7450327704 ps
CPU time 50.38 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:16:10 PM PDT 24
Peak memory 197808 kb
Host smart-df83ae89-eeea-41e3-8103-2c2bf15bd62d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683494850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1683494850
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1941694214
Short name T697
Test name
Test status
Simulation time 57167447 ps
CPU time 0.59 seconds
Started Aug 12 05:15:08 PM PDT 24
Finished Aug 12 05:15:09 PM PDT 24
Peak memory 194124 kb
Host smart-4d9b2f2e-12fa-4cf4-a582-8b21315eea37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941694214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1941694214
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1769695972
Short name T711
Test name
Test status
Simulation time 28975812 ps
CPU time 0.71 seconds
Started Aug 12 05:14:59 PM PDT 24
Finished Aug 12 05:15:00 PM PDT 24
Peak memory 195960 kb
Host smart-0e6766f3-3a5a-4589-9091-1265b13b0337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769695972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1769695972
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.331986071
Short name T26
Test name
Test status
Simulation time 1676099129 ps
CPU time 15.1 seconds
Started Aug 12 05:15:12 PM PDT 24
Finished Aug 12 05:15:27 PM PDT 24
Peak memory 196956 kb
Host smart-4e56c975-14c5-4f15-ac2e-0139f8e6e8dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331986071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.331986071
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2745028064
Short name T554
Test name
Test status
Simulation time 93500423 ps
CPU time 0.73 seconds
Started Aug 12 05:15:13 PM PDT 24
Finished Aug 12 05:15:14 PM PDT 24
Peak memory 195376 kb
Host smart-52edb539-518b-4546-a0b6-40aa8d809460
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745028064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2745028064
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2673305716
Short name T357
Test name
Test status
Simulation time 28435515 ps
CPU time 0.77 seconds
Started Aug 12 05:15:13 PM PDT 24
Finished Aug 12 05:15:14 PM PDT 24
Peak memory 195232 kb
Host smart-72cf0352-b7ab-4c90-b89c-953be1093f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673305716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2673305716
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1505908005
Short name T466
Test name
Test status
Simulation time 156722979 ps
CPU time 1.67 seconds
Started Aug 12 05:15:07 PM PDT 24
Finished Aug 12 05:15:09 PM PDT 24
Peak memory 196820 kb
Host smart-c499b47d-2add-47ee-aab7-93582160b546
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505908005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1505908005
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2100312396
Short name T298
Test name
Test status
Simulation time 117987649 ps
CPU time 2.48 seconds
Started Aug 12 05:15:06 PM PDT 24
Finished Aug 12 05:15:08 PM PDT 24
Peak memory 197032 kb
Host smart-9020d1f6-2abd-4591-bd1a-75e5e4264491
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100312396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2100312396
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2576647275
Short name T635
Test name
Test status
Simulation time 127037590 ps
CPU time 1.17 seconds
Started Aug 12 05:15:04 PM PDT 24
Finished Aug 12 05:15:06 PM PDT 24
Peak memory 196088 kb
Host smart-804473bc-ac8e-4742-92c7-74ab424e15da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576647275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2576647275
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3191855014
Short name T498
Test name
Test status
Simulation time 33669367 ps
CPU time 1.05 seconds
Started Aug 12 05:15:05 PM PDT 24
Finished Aug 12 05:15:06 PM PDT 24
Peak memory 195880 kb
Host smart-6bfbe315-3046-46fc-95d8-0b2410a7983b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191855014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3191855014
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3901928732
Short name T455
Test name
Test status
Simulation time 1512654701 ps
CPU time 5.01 seconds
Started Aug 12 05:15:10 PM PDT 24
Finished Aug 12 05:15:15 PM PDT 24
Peak memory 198060 kb
Host smart-81026059-e22c-4d08-b36d-6a3327d6e5d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901928732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3901928732
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1099335399
Short name T235
Test name
Test status
Simulation time 492652486 ps
CPU time 1.44 seconds
Started Aug 12 05:15:00 PM PDT 24
Finished Aug 12 05:15:01 PM PDT 24
Peak memory 196912 kb
Host smart-64c29d85-d9fa-4275-a149-a19f46e40206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099335399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1099335399
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.428715429
Short name T394
Test name
Test status
Simulation time 45368082 ps
CPU time 1.14 seconds
Started Aug 12 05:15:05 PM PDT 24
Finished Aug 12 05:15:06 PM PDT 24
Peak memory 195600 kb
Host smart-9dfc91d0-d631-4270-b0c1-08cec9253c6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428715429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.428715429
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1047136332
Short name T7
Test name
Test status
Simulation time 19658848874 ps
CPU time 104.81 seconds
Started Aug 12 05:15:10 PM PDT 24
Finished Aug 12 05:16:55 PM PDT 24
Peak memory 198284 kb
Host smart-538775f7-7a78-4e82-8a5a-d6c7fd5fca3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047136332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1047136332
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.643234382
Short name T57
Test name
Test status
Simulation time 26030183 ps
CPU time 0.57 seconds
Started Aug 12 05:15:05 PM PDT 24
Finished Aug 12 05:15:05 PM PDT 24
Peak memory 193948 kb
Host smart-633416e9-baa1-4e57-9d47-1ea1624e9012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643234382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.643234382
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1024443602
Short name T246
Test name
Test status
Simulation time 190442442 ps
CPU time 0.97 seconds
Started Aug 12 05:15:09 PM PDT 24
Finished Aug 12 05:15:10 PM PDT 24
Peak memory 195988 kb
Host smart-30a850ff-6f5e-4d3c-8f55-eb5070ee004c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024443602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1024443602
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2111324514
Short name T529
Test name
Test status
Simulation time 838749486 ps
CPU time 6.14 seconds
Started Aug 12 05:15:16 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 196764 kb
Host smart-67d55ff1-c9b3-4831-8bce-d8a8655e7276
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111324514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2111324514
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.4137332103
Short name T634
Test name
Test status
Simulation time 304591181 ps
CPU time 0.69 seconds
Started Aug 12 05:15:14 PM PDT 24
Finished Aug 12 05:15:15 PM PDT 24
Peak memory 194760 kb
Host smart-6ff49404-036f-4d94-9607-007b5b5c734c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137332103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.4137332103
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.442103791
Short name T130
Test name
Test status
Simulation time 289975473 ps
CPU time 0.94 seconds
Started Aug 12 05:15:15 PM PDT 24
Finished Aug 12 05:15:16 PM PDT 24
Peak memory 196044 kb
Host smart-4ccf4959-3179-4a28-92bf-fb185fcef826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442103791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.442103791
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2282287266
Short name T321
Test name
Test status
Simulation time 42332209 ps
CPU time 1.75 seconds
Started Aug 12 05:15:10 PM PDT 24
Finished Aug 12 05:15:12 PM PDT 24
Peak memory 198080 kb
Host smart-b7bdc1c3-1e54-4886-9ab5-c0fda58ceaa8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282287266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2282287266
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2683544841
Short name T614
Test name
Test status
Simulation time 139172704 ps
CPU time 1.13 seconds
Started Aug 12 05:15:06 PM PDT 24
Finished Aug 12 05:15:07 PM PDT 24
Peak memory 196132 kb
Host smart-43ae2d92-b638-45cc-938b-794b81845ee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683544841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2683544841
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2626536417
Short name T528
Test name
Test status
Simulation time 188931382 ps
CPU time 1.05 seconds
Started Aug 12 05:15:10 PM PDT 24
Finished Aug 12 05:15:11 PM PDT 24
Peak memory 196060 kb
Host smart-f7d9084c-bb48-4c36-9ec8-911ba4e670da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626536417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2626536417
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1934483652
Short name T478
Test name
Test status
Simulation time 76634287 ps
CPU time 0.83 seconds
Started Aug 12 05:15:13 PM PDT 24
Finished Aug 12 05:15:14 PM PDT 24
Peak memory 196704 kb
Host smart-903c885b-9f0a-4645-bb0e-04ea7188b525
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934483652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1934483652
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1741993461
Short name T469
Test name
Test status
Simulation time 175023073 ps
CPU time 2.88 seconds
Started Aug 12 05:15:06 PM PDT 24
Finished Aug 12 05:15:09 PM PDT 24
Peak memory 198020 kb
Host smart-b707197f-05fc-4bea-86e9-99b6fdd52962
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741993461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1741993461
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2206221045
Short name T558
Test name
Test status
Simulation time 179343925 ps
CPU time 1.27 seconds
Started Aug 12 05:15:07 PM PDT 24
Finished Aug 12 05:15:08 PM PDT 24
Peak memory 196864 kb
Host smart-220ddfa1-2803-4b43-843e-711353a78c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206221045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2206221045
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.978702098
Short name T693
Test name
Test status
Simulation time 38631707 ps
CPU time 1.13 seconds
Started Aug 12 05:15:18 PM PDT 24
Finished Aug 12 05:15:19 PM PDT 24
Peak memory 195940 kb
Host smart-752e3686-27b8-41eb-a059-afa9b7037f03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978702098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.978702098
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3725673336
Short name T171
Test name
Test status
Simulation time 75617456933 ps
CPU time 170.79 seconds
Started Aug 12 05:15:05 PM PDT 24
Finished Aug 12 05:17:56 PM PDT 24
Peak memory 198232 kb
Host smart-3eb583fd-e890-48fd-9597-091b4eb9175c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725673336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3725673336
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1157615787
Short name T301
Test name
Test status
Simulation time 45851337 ps
CPU time 0.58 seconds
Started Aug 12 05:15:12 PM PDT 24
Finished Aug 12 05:15:12 PM PDT 24
Peak memory 193992 kb
Host smart-e62cbe6f-c9fe-41a6-8748-033abc8c134a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157615787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1157615787
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3013865486
Short name T337
Test name
Test status
Simulation time 691355234 ps
CPU time 0.84 seconds
Started Aug 12 05:15:08 PM PDT 24
Finished Aug 12 05:15:09 PM PDT 24
Peak memory 195396 kb
Host smart-db4a7abd-2e6f-46de-ac49-62a1dcc64fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013865486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3013865486
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.787073762
Short name T137
Test name
Test status
Simulation time 3067113765 ps
CPU time 27.57 seconds
Started Aug 12 05:15:14 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 197144 kb
Host smart-bbd799aa-6e5c-432f-a703-dab21463c1fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787073762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.787073762
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.4109015390
Short name T647
Test name
Test status
Simulation time 189545604 ps
CPU time 0.91 seconds
Started Aug 12 05:15:18 PM PDT 24
Finished Aug 12 05:15:19 PM PDT 24
Peak memory 197280 kb
Host smart-03e802e1-6634-4ad4-88a3-605f328085c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109015390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.4109015390
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1068277305
Short name T205
Test name
Test status
Simulation time 78391974 ps
CPU time 1.33 seconds
Started Aug 12 05:15:15 PM PDT 24
Finished Aug 12 05:15:17 PM PDT 24
Peak memory 196112 kb
Host smart-288620c1-9401-41db-b4d8-c0aca2e33c15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068277305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1068277305
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.999467395
Short name T474
Test name
Test status
Simulation time 97098385 ps
CPU time 3.58 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:28 PM PDT 24
Peak memory 198244 kb
Host smart-1df86b20-875d-4b64-a20f-6d70da5093e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999467395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.999467395
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2736579218
Short name T183
Test name
Test status
Simulation time 91992800 ps
CPU time 1.48 seconds
Started Aug 12 05:15:14 PM PDT 24
Finished Aug 12 05:15:16 PM PDT 24
Peak memory 196152 kb
Host smart-22a72f56-64e5-4669-ab43-c436b26ec405
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736579218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2736579218
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.643209195
Short name T115
Test name
Test status
Simulation time 86318745 ps
CPU time 1 seconds
Started Aug 12 05:15:14 PM PDT 24
Finished Aug 12 05:15:15 PM PDT 24
Peak memory 196676 kb
Host smart-4f6be407-316e-4a74-8ac0-a0ca3d95a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643209195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.643209195
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.4087524657
Short name T438
Test name
Test status
Simulation time 61305746 ps
CPU time 0.71 seconds
Started Aug 12 05:15:05 PM PDT 24
Finished Aug 12 05:15:06 PM PDT 24
Peak memory 196156 kb
Host smart-711308fb-0475-4e96-9431-ff0f45abf835
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087524657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.4087524657
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1259434517
Short name T505
Test name
Test status
Simulation time 1065770833 ps
CPU time 2.64 seconds
Started Aug 12 05:15:15 PM PDT 24
Finished Aug 12 05:15:18 PM PDT 24
Peak memory 198124 kb
Host smart-b7457522-4351-4e12-b1f4-3e50efc9c5a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259434517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1259434517
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2778253576
Short name T489
Test name
Test status
Simulation time 161682385 ps
CPU time 1.3 seconds
Started Aug 12 05:15:09 PM PDT 24
Finished Aug 12 05:15:11 PM PDT 24
Peak memory 196860 kb
Host smart-15083289-bf6d-4c58-ad72-30f37da65280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778253576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2778253576
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3064810630
Short name T136
Test name
Test status
Simulation time 739936379 ps
CPU time 1.01 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:20 PM PDT 24
Peak memory 197360 kb
Host smart-fcf2cb57-66fc-4386-b205-f353de89d4fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064810630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3064810630
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2488403610
Short name T452
Test name
Test status
Simulation time 2285832900 ps
CPU time 53.02 seconds
Started Aug 12 05:15:17 PM PDT 24
Finished Aug 12 05:16:10 PM PDT 24
Peak memory 198144 kb
Host smart-d4720c55-529c-4d88-8fe9-70c7bb03bd55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488403610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2488403610
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.449945095
Short name T63
Test name
Test status
Simulation time 6577694572 ps
CPU time 50.77 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:16:15 PM PDT 24
Peak memory 198304 kb
Host smart-df314151-83ac-46b2-a87d-be14be4816bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=449945095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.449945095
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.964101206
Short name T132
Test name
Test status
Simulation time 80218062 ps
CPU time 0.57 seconds
Started Aug 12 05:15:09 PM PDT 24
Finished Aug 12 05:15:10 PM PDT 24
Peak memory 194224 kb
Host smart-3191d756-4b59-490d-9279-58bfb172db20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964101206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.964101206
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.432106241
Short name T170
Test name
Test status
Simulation time 68257975 ps
CPU time 0.68 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:21 PM PDT 24
Peak memory 195296 kb
Host smart-4fcb6fe1-401d-4dcc-ab8b-f5f7f68e04d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432106241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.432106241
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.768842461
Short name T464
Test name
Test status
Simulation time 508184620 ps
CPU time 14.88 seconds
Started Aug 12 05:15:17 PM PDT 24
Finished Aug 12 05:15:32 PM PDT 24
Peak memory 196964 kb
Host smart-02449ce1-b8b9-42a4-9a54-c2073a7532c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768842461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.768842461
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.423223047
Short name T231
Test name
Test status
Simulation time 70171582 ps
CPU time 0.77 seconds
Started Aug 12 05:15:16 PM PDT 24
Finished Aug 12 05:15:17 PM PDT 24
Peak memory 195956 kb
Host smart-ef8e60b1-24dc-4ae9-b09b-959c9c24a834
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423223047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.423223047
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.23291228
Short name T203
Test name
Test status
Simulation time 95603026 ps
CPU time 0.89 seconds
Started Aug 12 05:15:14 PM PDT 24
Finished Aug 12 05:15:15 PM PDT 24
Peak memory 196476 kb
Host smart-aa136b8c-cd80-4c35-b69e-318e5cf08ffa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23291228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.23291228
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.4036903115
Short name T165
Test name
Test status
Simulation time 97291238 ps
CPU time 1.24 seconds
Started Aug 12 05:15:15 PM PDT 24
Finished Aug 12 05:15:16 PM PDT 24
Peak memory 197928 kb
Host smart-c8feb593-5086-47da-b5b7-26f60eb8c165
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036903115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.4036903115
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2079180521
Short name T266
Test name
Test status
Simulation time 786425948 ps
CPU time 1.66 seconds
Started Aug 12 05:15:17 PM PDT 24
Finished Aug 12 05:15:19 PM PDT 24
Peak memory 196152 kb
Host smart-d0c9dccf-84ef-4877-873d-8acf0b6ad392
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079180521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2079180521
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3318698727
Short name T198
Test name
Test status
Simulation time 211667799 ps
CPU time 1.26 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:21 PM PDT 24
Peak memory 195868 kb
Host smart-e67dfc37-b116-4c44-91e5-30791ab54f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318698727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3318698727
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.4120361232
Short name T376
Test name
Test status
Simulation time 44624763 ps
CPU time 1 seconds
Started Aug 12 05:15:13 PM PDT 24
Finished Aug 12 05:15:14 PM PDT 24
Peak memory 196652 kb
Host smart-2f676dc9-96be-43df-9e21-4c251083984e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120361232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.4120361232
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3586581955
Short name T453
Test name
Test status
Simulation time 1552922187 ps
CPU time 6.61 seconds
Started Aug 12 05:15:11 PM PDT 24
Finished Aug 12 05:15:18 PM PDT 24
Peak memory 197980 kb
Host smart-35462d28-efb8-4898-99d2-26c2745077e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586581955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3586581955
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1914015630
Short name T698
Test name
Test status
Simulation time 258484110 ps
CPU time 1.25 seconds
Started Aug 12 05:15:07 PM PDT 24
Finished Aug 12 05:15:08 PM PDT 24
Peak memory 196272 kb
Host smart-59a5144b-8fae-4c3b-bcc3-45b52bb1a3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914015630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1914015630
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3986078792
Short name T195
Test name
Test status
Simulation time 97940951 ps
CPU time 0.97 seconds
Started Aug 12 05:15:06 PM PDT 24
Finished Aug 12 05:15:08 PM PDT 24
Peak memory 195784 kb
Host smart-b1693eaa-2af5-425f-9123-f082f31bc484
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986078792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3986078792
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.129202587
Short name T108
Test name
Test status
Simulation time 13344139781 ps
CPU time 175.29 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:18:14 PM PDT 24
Peak memory 198124 kb
Host smart-78dd2e75-147b-4dc4-8a33-29a4a06c4c5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129202587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.129202587
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1575261323
Short name T56
Test name
Test status
Simulation time 18806285366 ps
CPU time 174.76 seconds
Started Aug 12 05:15:11 PM PDT 24
Finished Aug 12 05:18:06 PM PDT 24
Peak memory 198452 kb
Host smart-fd621293-546a-412a-92d5-5a3e63e973eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1575261323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1575261323
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1515459340
Short name T126
Test name
Test status
Simulation time 14235417 ps
CPU time 0.56 seconds
Started Aug 12 05:15:17 PM PDT 24
Finished Aug 12 05:15:18 PM PDT 24
Peak memory 192796 kb
Host smart-4ebe2466-672e-495b-a1dc-27e6c08e33e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515459340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1515459340
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.289792779
Short name T548
Test name
Test status
Simulation time 45749380 ps
CPU time 0.86 seconds
Started Aug 12 05:15:11 PM PDT 24
Finished Aug 12 05:15:12 PM PDT 24
Peak memory 196540 kb
Host smart-eb0a265c-7dc6-45be-a944-c340e3287fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289792779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.289792779
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3078577066
Short name T121
Test name
Test status
Simulation time 334281747 ps
CPU time 11.51 seconds
Started Aug 12 05:15:18 PM PDT 24
Finished Aug 12 05:15:29 PM PDT 24
Peak memory 197036 kb
Host smart-8cf4eb57-f62c-4d8b-959d-453490641a88
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078577066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3078577066
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1834572345
Short name T550
Test name
Test status
Simulation time 718689736 ps
CPU time 1.06 seconds
Started Aug 12 05:15:18 PM PDT 24
Finished Aug 12 05:15:19 PM PDT 24
Peak memory 198148 kb
Host smart-0935e6e9-2b5d-4b83-9a66-a4a3d19f0bca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834572345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1834572345
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1839955782
Short name T542
Test name
Test status
Simulation time 239770381 ps
CPU time 1.42 seconds
Started Aug 12 05:15:16 PM PDT 24
Finished Aug 12 05:15:17 PM PDT 24
Peak memory 197008 kb
Host smart-7b8c1b86-b013-4781-8cf3-50ff3bc07a5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839955782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1839955782
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.524305830
Short name T315
Test name
Test status
Simulation time 163614282 ps
CPU time 1.75 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 198104 kb
Host smart-ce4e666d-c985-4267-bdfa-71ab8ff66d7f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524305830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.524305830
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3857282877
Short name T287
Test name
Test status
Simulation time 141586894 ps
CPU time 1.71 seconds
Started Aug 12 05:15:18 PM PDT 24
Finished Aug 12 05:15:19 PM PDT 24
Peak memory 196124 kb
Host smart-71ef7623-7388-4621-9a8a-58a65abc9421
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857282877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3857282877
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1711489729
Short name T289
Test name
Test status
Simulation time 22037094 ps
CPU time 0.7 seconds
Started Aug 12 05:15:07 PM PDT 24
Finished Aug 12 05:15:08 PM PDT 24
Peak memory 194332 kb
Host smart-93aecc8c-d4df-4678-8b70-17ce2543fabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711489729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1711489729
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.4268455533
Short name T620
Test name
Test status
Simulation time 83714681 ps
CPU time 0.93 seconds
Started Aug 12 05:15:18 PM PDT 24
Finished Aug 12 05:15:19 PM PDT 24
Peak memory 196064 kb
Host smart-3c5fa7e9-2a88-4857-a6b5-bac857d6de35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268455533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.4268455533
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2644702349
Short name T553
Test name
Test status
Simulation time 78511669 ps
CPU time 1.52 seconds
Started Aug 12 05:15:11 PM PDT 24
Finished Aug 12 05:15:13 PM PDT 24
Peak memory 198040 kb
Host smart-63c13df8-8efa-477e-8954-c513abe27e2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644702349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2644702349
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.181100022
Short name T28
Test name
Test status
Simulation time 200734971 ps
CPU time 0.92 seconds
Started Aug 12 05:15:12 PM PDT 24
Finished Aug 12 05:15:13 PM PDT 24
Peak memory 195872 kb
Host smart-d095a240-9278-4fb9-a373-d7ca6e579d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181100022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.181100022
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.152223710
Short name T30
Test name
Test status
Simulation time 52672749 ps
CPU time 1.05 seconds
Started Aug 12 05:15:11 PM PDT 24
Finished Aug 12 05:15:12 PM PDT 24
Peak memory 197184 kb
Host smart-3fca96e1-b91c-4a51-82fa-d2c5ae2253c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152223710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.152223710
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2119564371
Short name T563
Test name
Test status
Simulation time 7667158689 ps
CPU time 99.23 seconds
Started Aug 12 05:15:15 PM PDT 24
Finished Aug 12 05:16:55 PM PDT 24
Peak memory 198324 kb
Host smart-c869cef1-6f73-4bf8-b257-9b0374648131
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119564371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2119564371
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.454419466
Short name T419
Test name
Test status
Simulation time 12885492 ps
CPU time 0.56 seconds
Started Aug 12 05:13:55 PM PDT 24
Finished Aug 12 05:13:55 PM PDT 24
Peak memory 194004 kb
Host smart-ba00d5a4-b104-4390-bc3e-4a32dab00740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454419466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.454419466
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.680322308
Short name T487
Test name
Test status
Simulation time 41638700 ps
CPU time 0.9 seconds
Started Aug 12 05:13:55 PM PDT 24
Finished Aug 12 05:13:56 PM PDT 24
Peak memory 196132 kb
Host smart-2037be0e-054b-4dc4-9265-acb378e0aca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680322308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.680322308
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.4170017103
Short name T164
Test name
Test status
Simulation time 16099296558 ps
CPU time 26.64 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:14:25 PM PDT 24
Peak memory 197120 kb
Host smart-5c2158e6-21c6-43bc-bab3-1607e80a5e49
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170017103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.4170017103
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.4154664226
Short name T186
Test name
Test status
Simulation time 84566667 ps
CPU time 0.64 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:13:57 PM PDT 24
Peak memory 194548 kb
Host smart-d54920d1-c30f-43b3-85d9-c5253a2c26ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154664226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.4154664226
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1454937706
Short name T393
Test name
Test status
Simulation time 51608300 ps
CPU time 1.34 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:13:59 PM PDT 24
Peak memory 198204 kb
Host smart-f2118e9b-7c86-4f99-9dda-800a123ff775
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454937706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1454937706
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3223951218
Short name T313
Test name
Test status
Simulation time 339531128 ps
CPU time 3.4 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:14:00 PM PDT 24
Peak memory 198176 kb
Host smart-3532b308-2636-4563-ba24-4dde5cf2620d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223951218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3223951218
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2454244880
Short name T480
Test name
Test status
Simulation time 490191082 ps
CPU time 2.85 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:14:01 PM PDT 24
Peak memory 198184 kb
Host smart-49ae8551-43e1-4256-a423-bb2dd512b4ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454244880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2454244880
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.585505030
Short name T547
Test name
Test status
Simulation time 150939647 ps
CPU time 0.87 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:14:03 PM PDT 24
Peak memory 196588 kb
Host smart-62a11236-7d85-4704-b183-59f3943fc3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585505030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.585505030
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3205921191
Short name T427
Test name
Test status
Simulation time 112056110 ps
CPU time 1.15 seconds
Started Aug 12 05:13:53 PM PDT 24
Finished Aug 12 05:13:54 PM PDT 24
Peak memory 197252 kb
Host smart-4f2455d3-5a9d-438b-9437-8fbed5e378dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205921191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3205921191
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1778836096
Short name T640
Test name
Test status
Simulation time 1182153892 ps
CPU time 6.72 seconds
Started Aug 12 05:13:59 PM PDT 24
Finished Aug 12 05:14:06 PM PDT 24
Peak memory 198112 kb
Host smart-e33ca23e-0b8a-4cc3-b70e-832c9328502f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778836096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1778836096
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2598860176
Short name T41
Test name
Test status
Simulation time 321778649 ps
CPU time 1.16 seconds
Started Aug 12 05:14:15 PM PDT 24
Finished Aug 12 05:14:16 PM PDT 24
Peak memory 214988 kb
Host smart-064f1e2b-9595-44e3-b958-6443fe79f95b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598860176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2598860176
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2014699242
Short name T381
Test name
Test status
Simulation time 149896894 ps
CPU time 1.12 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:13:57 PM PDT 24
Peak memory 195940 kb
Host smart-27cdf2e7-3366-4e38-ad79-870c25eded61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014699242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2014699242
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2375999737
Short name T120
Test name
Test status
Simulation time 137374627 ps
CPU time 0.99 seconds
Started Aug 12 05:14:06 PM PDT 24
Finished Aug 12 05:14:07 PM PDT 24
Peak memory 195884 kb
Host smart-02f5ff8f-ae11-4c25-a3b4-af3d97d283dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375999737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2375999737
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2805859452
Short name T16
Test name
Test status
Simulation time 44300740753 ps
CPU time 195.37 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:17:12 PM PDT 24
Peak memory 198288 kb
Host smart-c2103789-5cbf-43cd-bf1e-a67c19a6fc0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805859452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2805859452
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.288684075
Short name T636
Test name
Test status
Simulation time 31002083 ps
CPU time 0.78 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:20 PM PDT 24
Peak memory 196052 kb
Host smart-ebac0b5c-0577-437a-b46b-d8330e1ad461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288684075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.288684075
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1563604037
Short name T654
Test name
Test status
Simulation time 249287581 ps
CPU time 11.58 seconds
Started Aug 12 05:15:16 PM PDT 24
Finished Aug 12 05:15:28 PM PDT 24
Peak memory 196572 kb
Host smart-cd01a7db-f0e1-4eaa-988f-45cb9221782d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563604037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1563604037
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1426456631
Short name T148
Test name
Test status
Simulation time 70644038 ps
CPU time 0.93 seconds
Started Aug 12 05:15:16 PM PDT 24
Finished Aug 12 05:15:17 PM PDT 24
Peak memory 197200 kb
Host smart-f39cd726-317a-4553-a6cc-1816f485112c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426456631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1426456631
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2127407150
Short name T244
Test name
Test status
Simulation time 34427604 ps
CPU time 0.75 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:20 PM PDT 24
Peak memory 195448 kb
Host smart-ef9c651a-638a-4d80-b671-441ca451849c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127407150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2127407150
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3311675934
Short name T182
Test name
Test status
Simulation time 56384993 ps
CPU time 1.94 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 198184 kb
Host smart-7dd4e5fe-f671-4f82-8e15-cf534b0bcaea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311675934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3311675934
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2119057794
Short name T307
Test name
Test status
Simulation time 352448427 ps
CPU time 2.64 seconds
Started Aug 12 05:15:17 PM PDT 24
Finished Aug 12 05:15:19 PM PDT 24
Peak memory 196636 kb
Host smart-6792264d-9016-4bd2-a955-d1eda3a8f693
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119057794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2119057794
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2212311160
Short name T106
Test name
Test status
Simulation time 29541713 ps
CPU time 1.03 seconds
Started Aug 12 05:15:17 PM PDT 24
Finished Aug 12 05:15:18 PM PDT 24
Peak memory 196016 kb
Host smart-d54d6c87-25a1-4647-aab9-22de3caaa890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212311160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2212311160
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.459863055
Short name T541
Test name
Test status
Simulation time 406306494 ps
CPU time 1.2 seconds
Started Aug 12 05:15:16 PM PDT 24
Finished Aug 12 05:15:17 PM PDT 24
Peak memory 198196 kb
Host smart-00e26412-caf9-46e4-badb-63f123bee4f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459863055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.459863055
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2486316912
Short name T545
Test name
Test status
Simulation time 344351379 ps
CPU time 3.93 seconds
Started Aug 12 05:15:17 PM PDT 24
Finished Aug 12 05:15:21 PM PDT 24
Peak memory 197996 kb
Host smart-a3757c88-9e8b-498f-bf07-01db469b1f23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486316912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2486316912
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3379583074
Short name T613
Test name
Test status
Simulation time 74263934 ps
CPU time 1.39 seconds
Started Aug 12 05:15:18 PM PDT 24
Finished Aug 12 05:15:20 PM PDT 24
Peak memory 198240 kb
Host smart-75e8f3af-2387-4781-b2d8-cb54549ba8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379583074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3379583074
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2972271447
Short name T679
Test name
Test status
Simulation time 33026509 ps
CPU time 0.96 seconds
Started Aug 12 05:15:15 PM PDT 24
Finished Aug 12 05:15:16 PM PDT 24
Peak memory 197276 kb
Host smart-fbe44667-52ff-4483-9a6d-d7a81bdb3ea9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972271447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2972271447
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3346947199
Short name T502
Test name
Test status
Simulation time 59592428748 ps
CPU time 156.69 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:17:56 PM PDT 24
Peak memory 198284 kb
Host smart-35e5d528-3f76-430d-acb8-1ab1b0216b35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346947199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3346947199
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.2045849010
Short name T444
Test name
Test status
Simulation time 1314513656 ps
CPU time 21.35 seconds
Started Aug 12 05:15:18 PM PDT 24
Finished Aug 12 05:15:39 PM PDT 24
Peak memory 198428 kb
Host smart-9d89f5f1-0725-40c4-a535-ce3b216906b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2045849010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.2045849010
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2410765703
Short name T450
Test name
Test status
Simulation time 12543034 ps
CPU time 0.58 seconds
Started Aug 12 05:15:23 PM PDT 24
Finished Aug 12 05:15:24 PM PDT 24
Peak memory 193960 kb
Host smart-abcb7741-1412-4ccf-b87a-8eb6451fa426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410765703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2410765703
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1554214977
Short name T577
Test name
Test status
Simulation time 57927987 ps
CPU time 1.01 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 196032 kb
Host smart-06c9673d-d122-4b65-a279-4da54adef1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554214977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1554214977
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2900283697
Short name T18
Test name
Test status
Simulation time 231462098 ps
CPU time 12.1 seconds
Started Aug 12 05:15:21 PM PDT 24
Finished Aug 12 05:15:33 PM PDT 24
Peak memory 196864 kb
Host smart-29d265f2-75c4-402e-b342-786cb19997c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900283697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2900283697
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.4096735970
Short name T364
Test name
Test status
Simulation time 26429768 ps
CPU time 0.64 seconds
Started Aug 12 05:15:29 PM PDT 24
Finished Aug 12 05:15:30 PM PDT 24
Peak memory 194404 kb
Host smart-1781ee2d-302a-47f6-b9e0-99e4bab4302b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096735970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.4096735970
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2171212118
Short name T391
Test name
Test status
Simulation time 40433616 ps
CPU time 1.21 seconds
Started Aug 12 05:15:56 PM PDT 24
Finished Aug 12 05:15:57 PM PDT 24
Peak memory 196104 kb
Host smart-1da24901-367c-4ca8-a8a6-91cf6e4dd90f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171212118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2171212118
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.754347564
Short name T596
Test name
Test status
Simulation time 33668802 ps
CPU time 0.9 seconds
Started Aug 12 05:15:22 PM PDT 24
Finished Aug 12 05:15:23 PM PDT 24
Peak memory 196948 kb
Host smart-dc69979d-b47a-4964-bf26-52a1426584e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754347564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.754347564
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3901584530
Short name T119
Test name
Test status
Simulation time 1081964127 ps
CPU time 2.8 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 197384 kb
Host smart-f5cee3f3-6657-4663-a281-28f20aefe886
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901584530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3901584530
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3013632705
Short name T60
Test name
Test status
Simulation time 101822934 ps
CPU time 0.96 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 196160 kb
Host smart-276dc87d-b66d-4b45-a464-f753b3f2819d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013632705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3013632705
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1066688115
Short name T355
Test name
Test status
Simulation time 34236178 ps
CPU time 1.11 seconds
Started Aug 12 05:15:37 PM PDT 24
Finished Aug 12 05:15:38 PM PDT 24
Peak memory 196712 kb
Host smart-be269e5f-95bd-4f83-a3e2-a403472a54cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066688115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1066688115
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3043988118
Short name T4
Test name
Test status
Simulation time 261111697 ps
CPU time 3.92 seconds
Started Aug 12 05:15:40 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 198080 kb
Host smart-eb0597b0-fa58-4b64-af8d-8047bce6f560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043988118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3043988118
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1237583272
Short name T462
Test name
Test status
Simulation time 27179724 ps
CPU time 0.98 seconds
Started Aug 12 05:15:16 PM PDT 24
Finished Aug 12 05:15:17 PM PDT 24
Peak memory 196356 kb
Host smart-37b62433-ddea-4dae-85d4-a35a211061f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237583272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1237583272
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2226266943
Short name T535
Test name
Test status
Simulation time 1029410155 ps
CPU time 1.15 seconds
Started Aug 12 05:15:12 PM PDT 24
Finished Aug 12 05:15:13 PM PDT 24
Peak memory 196016 kb
Host smart-96e5ea6a-741d-45b4-b1aa-57c52e637aec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226266943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2226266943
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.861405843
Short name T600
Test name
Test status
Simulation time 7112003427 ps
CPU time 75.91 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:16:59 PM PDT 24
Peak memory 198232 kb
Host smart-45451efd-2c0e-46b0-a844-d18b69538dcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861405843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.861405843
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3981965232
Short name T362
Test name
Test status
Simulation time 20372416 ps
CPU time 0.57 seconds
Started Aug 12 05:15:16 PM PDT 24
Finished Aug 12 05:15:16 PM PDT 24
Peak memory 193992 kb
Host smart-9f7c4839-203e-4462-9269-58866d3b5d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981965232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3981965232
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3885908312
Short name T429
Test name
Test status
Simulation time 19253156 ps
CPU time 0.71 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:20 PM PDT 24
Peak memory 195172 kb
Host smart-a9948e6f-350e-47e4-b2c5-68fdfdaa3b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885908312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3885908312
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.217553366
Short name T493
Test name
Test status
Simulation time 1062772818 ps
CPU time 19.7 seconds
Started Aug 12 05:15:46 PM PDT 24
Finished Aug 12 05:16:06 PM PDT 24
Peak memory 195592 kb
Host smart-2b573bc5-dc8c-45bb-8bba-258fb4a5f59f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217553366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.217553366
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2361781637
Short name T334
Test name
Test status
Simulation time 185844693 ps
CPU time 0.99 seconds
Started Aug 12 05:15:27 PM PDT 24
Finished Aug 12 05:15:28 PM PDT 24
Peak memory 196812 kb
Host smart-ad636aaa-08bf-47ef-a145-10e0e5dcf3b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361781637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2361781637
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2305935460
Short name T110
Test name
Test status
Simulation time 20069247 ps
CPU time 0.76 seconds
Started Aug 12 05:15:23 PM PDT 24
Finished Aug 12 05:15:24 PM PDT 24
Peak memory 196288 kb
Host smart-71cb14ca-9a0b-41cf-aa1d-744c6dce81e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305935460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2305935460
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1154424669
Short name T594
Test name
Test status
Simulation time 152000763 ps
CPU time 3.08 seconds
Started Aug 12 05:15:27 PM PDT 24
Finished Aug 12 05:15:31 PM PDT 24
Peak memory 196348 kb
Host smart-380e4024-1771-492c-8b4d-c8e58bd4fe3e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154424669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1154424669
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3970146119
Short name T333
Test name
Test status
Simulation time 366697806 ps
CPU time 3.03 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 198080 kb
Host smart-a1b18184-d1b0-4b45-a282-70ee8e7f25e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970146119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3970146119
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3748586901
Short name T568
Test name
Test status
Simulation time 107714761 ps
CPU time 1 seconds
Started Aug 12 05:15:15 PM PDT 24
Finished Aug 12 05:15:16 PM PDT 24
Peak memory 195980 kb
Host smart-fe79151f-f323-48ad-aab6-976998f48199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748586901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3748586901
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2439964393
Short name T457
Test name
Test status
Simulation time 81414534 ps
CPU time 1.32 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:21 PM PDT 24
Peak memory 197188 kb
Host smart-552e45c3-0483-4b2a-84e7-7fec4912300d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439964393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2439964393
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.190913721
Short name T436
Test name
Test status
Simulation time 1689840232 ps
CPU time 4.87 seconds
Started Aug 12 05:15:39 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 198088 kb
Host smart-2787666d-18d5-4675-aea0-a5653587f155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190913721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.190913721
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2649884953
Short name T339
Test name
Test status
Simulation time 67928471 ps
CPU time 1.27 seconds
Started Aug 12 05:15:30 PM PDT 24
Finished Aug 12 05:15:31 PM PDT 24
Peak memory 196364 kb
Host smart-52e8d99f-96ac-4f79-99a8-4c7e6140e575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649884953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2649884953
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3079537269
Short name T670
Test name
Test status
Simulation time 75320171 ps
CPU time 0.76 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:21 PM PDT 24
Peak memory 196084 kb
Host smart-491ec982-b1a4-4742-b46f-8c96affc4f19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079537269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3079537269
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.8544291
Short name T122
Test name
Test status
Simulation time 4019155283 ps
CPU time 51.18 seconds
Started Aug 12 05:15:21 PM PDT 24
Finished Aug 12 05:16:12 PM PDT 24
Peak memory 198224 kb
Host smart-d75e26a9-5ac0-461d-976d-0e3338b4bef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8544291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpi
o_stress_all.8544291
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2060372153
Short name T35
Test name
Test status
Simulation time 2644974942 ps
CPU time 83.6 seconds
Started Aug 12 05:15:21 PM PDT 24
Finished Aug 12 05:16:45 PM PDT 24
Peak memory 197796 kb
Host smart-845ee536-7ab9-48e9-a979-f93ae6cc4912
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2060372153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2060372153
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3130288795
Short name T371
Test name
Test status
Simulation time 33863896 ps
CPU time 0.56 seconds
Started Aug 12 05:15:12 PM PDT 24
Finished Aug 12 05:15:12 PM PDT 24
Peak memory 194016 kb
Host smart-09d70263-ac91-4adf-81b9-5430d1503907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130288795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3130288795
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.56104216
Short name T682
Test name
Test status
Simulation time 260969875 ps
CPU time 0.97 seconds
Started Aug 12 05:15:18 PM PDT 24
Finished Aug 12 05:15:19 PM PDT 24
Peak memory 196844 kb
Host smart-cc660a15-2ddf-4c82-bde9-a86f7a7dd257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56104216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.56104216
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2964327334
Short name T326
Test name
Test status
Simulation time 616169960 ps
CPU time 11.06 seconds
Started Aug 12 05:15:22 PM PDT 24
Finished Aug 12 05:15:33 PM PDT 24
Peak memory 196320 kb
Host smart-cb4ae6b3-fa67-4bf6-8d59-31aa5ebe3026
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964327334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2964327334
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2659432629
Short name T695
Test name
Test status
Simulation time 930792949 ps
CPU time 1.03 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 196752 kb
Host smart-dfd8f031-0ccb-48d0-acbe-20451604ca01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659432629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2659432629
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1091828109
Short name T291
Test name
Test status
Simulation time 204405902 ps
CPU time 1.07 seconds
Started Aug 12 05:15:22 PM PDT 24
Finished Aug 12 05:15:23 PM PDT 24
Peak memory 196204 kb
Host smart-b7700a43-864e-4ae4-9fda-bd768d3b8d7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091828109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1091828109
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.4027189650
Short name T467
Test name
Test status
Simulation time 45009164 ps
CPU time 1.75 seconds
Started Aug 12 05:15:17 PM PDT 24
Finished Aug 12 05:15:19 PM PDT 24
Peak memory 196860 kb
Host smart-29001e0c-0dbe-4df6-84e5-c6dd9b38d5ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027189650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.4027189650
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.195249770
Short name T503
Test name
Test status
Simulation time 59642232 ps
CPU time 1.34 seconds
Started Aug 12 05:15:32 PM PDT 24
Finished Aug 12 05:15:34 PM PDT 24
Peak memory 196692 kb
Host smart-a745be15-cd64-450d-9d90-f8e5d626540a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195249770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
195249770
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1567783254
Short name T706
Test name
Test status
Simulation time 57568208 ps
CPU time 0.79 seconds
Started Aug 12 05:15:22 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 197160 kb
Host smart-1ef7205c-2ba8-4734-a0b7-5e7f148a2b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567783254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1567783254
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3451933422
Short name T191
Test name
Test status
Simulation time 307950943 ps
CPU time 1.09 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:20 PM PDT 24
Peak memory 195920 kb
Host smart-004298f6-5355-47fd-b6df-9adacb1a2420
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451933422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3451933422
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1545075496
Short name T420
Test name
Test status
Simulation time 448366078 ps
CPU time 3.58 seconds
Started Aug 12 05:15:23 PM PDT 24
Finished Aug 12 05:15:26 PM PDT 24
Peak memory 198104 kb
Host smart-16608d51-dd80-4a99-9f19-b26dee810efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545075496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1545075496
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1012658597
Short name T249
Test name
Test status
Simulation time 151305925 ps
CPU time 0.97 seconds
Started Aug 12 05:15:36 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 196544 kb
Host smart-67df1cf8-fb1c-4060-b1f5-fd1ac089642d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012658597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1012658597
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.4173752438
Short name T32
Test name
Test status
Simulation time 27813646 ps
CPU time 0.94 seconds
Started Aug 12 05:15:25 PM PDT 24
Finished Aug 12 05:15:26 PM PDT 24
Peak memory 195920 kb
Host smart-a37b79cf-6bbb-4ddb-bcec-17de9216f436
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173752438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.4173752438
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1708475687
Short name T515
Test name
Test status
Simulation time 11134066372 ps
CPU time 157.89 seconds
Started Aug 12 05:15:38 PM PDT 24
Finished Aug 12 05:18:16 PM PDT 24
Peak memory 198332 kb
Host smart-d5b1b435-1d64-4c61-a6c9-1ef9d3115e2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708475687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1708475687
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1851826176
Short name T44
Test name
Test status
Simulation time 12017960 ps
CPU time 0.55 seconds
Started Aug 12 05:15:38 PM PDT 24
Finished Aug 12 05:15:39 PM PDT 24
Peak memory 194584 kb
Host smart-de5d7019-3556-4c43-8b10-f14bcb9da8cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851826176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1851826176
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1976063357
Short name T201
Test name
Test status
Simulation time 379018512 ps
CPU time 0.88 seconds
Started Aug 12 05:15:25 PM PDT 24
Finished Aug 12 05:15:26 PM PDT 24
Peak memory 196212 kb
Host smart-43623bc0-d4c7-4db7-a9ec-251b5b94b3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976063357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1976063357
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3481339265
Short name T460
Test name
Test status
Simulation time 326466357 ps
CPU time 9.79 seconds
Started Aug 12 05:15:17 PM PDT 24
Finished Aug 12 05:15:27 PM PDT 24
Peak memory 197184 kb
Host smart-a326a91a-1475-45d7-9d1c-8da0628bf64d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481339265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3481339265
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1688630413
Short name T612
Test name
Test status
Simulation time 277958698 ps
CPU time 0.96 seconds
Started Aug 12 05:15:17 PM PDT 24
Finished Aug 12 05:15:18 PM PDT 24
Peak memory 197084 kb
Host smart-6fee7518-4b7e-40b7-a850-7eb03b012558
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688630413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1688630413
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3039750545
Short name T715
Test name
Test status
Simulation time 26461015 ps
CPU time 0.73 seconds
Started Aug 12 05:15:15 PM PDT 24
Finished Aug 12 05:15:16 PM PDT 24
Peak memory 195212 kb
Host smart-0a7de610-33e6-4c20-a587-eb8adc01177f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039750545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3039750545
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.135168351
Short name T302
Test name
Test status
Simulation time 220138252 ps
CPU time 2.2 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 196572 kb
Host smart-d72e8e3c-2dfc-4e57-abd7-8aac4b755ee6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135168351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.135168351
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3629465526
Short name T405
Test name
Test status
Simulation time 33128905 ps
CPU time 1.02 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:20 PM PDT 24
Peak memory 196288 kb
Host smart-a466db30-8468-4903-87de-a58a72b8b3fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629465526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3629465526
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4018340273
Short name T512
Test name
Test status
Simulation time 29760040 ps
CPU time 0.89 seconds
Started Aug 12 05:15:21 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 196680 kb
Host smart-331cf844-19c0-4b12-a6c9-ea338aba0918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018340273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4018340273
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.833530631
Short name T699
Test name
Test status
Simulation time 141941771 ps
CPU time 1.4 seconds
Started Aug 12 05:15:23 PM PDT 24
Finished Aug 12 05:15:24 PM PDT 24
Peak memory 197116 kb
Host smart-a6edce5e-4140-4d01-b641-ebb48d29f900
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833530631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.833530631
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3180670501
Short name T571
Test name
Test status
Simulation time 106867296 ps
CPU time 2.09 seconds
Started Aug 12 05:15:35 PM PDT 24
Finished Aug 12 05:15:37 PM PDT 24
Peak memory 197136 kb
Host smart-6c62bc1f-b9d6-4472-8b24-e5316ece9db5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180670501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3180670501
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1342211024
Short name T22
Test name
Test status
Simulation time 115535560 ps
CPU time 0.82 seconds
Started Aug 12 05:15:21 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 196316 kb
Host smart-7ba3d9a8-acea-4834-b9d3-19761795fae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342211024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1342211024
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.197702639
Short name T167
Test name
Test status
Simulation time 274907228 ps
CPU time 1.2 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 195872 kb
Host smart-7be5feb1-09e7-4f0d-8446-379f3e6cb902
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197702639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.197702639
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1532606952
Short name T360
Test name
Test status
Simulation time 6513964336 ps
CPU time 44.37 seconds
Started Aug 12 05:15:21 PM PDT 24
Finished Aug 12 05:16:05 PM PDT 24
Peak memory 198280 kb
Host smart-dc181e18-5147-4e5d-8bfe-2a9b19e81829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532606952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1532606952
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.421316552
Short name T667
Test name
Test status
Simulation time 8060841258 ps
CPU time 302.53 seconds
Started Aug 12 05:15:31 PM PDT 24
Finished Aug 12 05:20:33 PM PDT 24
Peak memory 198408 kb
Host smart-26eef3c7-0740-4360-826f-60d80f2f9eff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=421316552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.421316552
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.482341333
Short name T625
Test name
Test status
Simulation time 13786614 ps
CPU time 0.57 seconds
Started Aug 12 05:15:38 PM PDT 24
Finished Aug 12 05:15:39 PM PDT 24
Peak memory 194968 kb
Host smart-c28971e0-ddb4-4bff-b648-17531a9b1b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482341333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.482341333
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3892103136
Short name T27
Test name
Test status
Simulation time 36867869 ps
CPU time 0.61 seconds
Started Aug 12 05:15:34 PM PDT 24
Finished Aug 12 05:15:35 PM PDT 24
Peak memory 193884 kb
Host smart-a8820d5e-024a-4214-a47a-a0f39d20fdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892103136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3892103136
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1448762629
Short name T31
Test name
Test status
Simulation time 7304704486 ps
CPU time 16.6 seconds
Started Aug 12 05:15:24 PM PDT 24
Finished Aug 12 05:15:40 PM PDT 24
Peak memory 198184 kb
Host smart-8d349378-ed03-4d42-b0de-343a9db31392
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448762629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1448762629
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1465538813
Short name T319
Test name
Test status
Simulation time 349873555 ps
CPU time 1 seconds
Started Aug 12 05:15:24 PM PDT 24
Finished Aug 12 05:15:25 PM PDT 24
Peak memory 196472 kb
Host smart-a7700387-e3c2-4736-bf9c-c64f99d0e5e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465538813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1465538813
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3224690167
Short name T255
Test name
Test status
Simulation time 232117261 ps
CPU time 1.55 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:21 PM PDT 24
Peak memory 197148 kb
Host smart-11eb45ad-0d18-4a74-b922-a99c3ec8116c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224690167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3224690167
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.4101087335
Short name T416
Test name
Test status
Simulation time 201474541 ps
CPU time 2.01 seconds
Started Aug 12 05:15:23 PM PDT 24
Finished Aug 12 05:15:27 PM PDT 24
Peak memory 198116 kb
Host smart-caf89b86-1e45-45cf-adfc-fe7f1297a947
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101087335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.4101087335
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3791958719
Short name T569
Test name
Test status
Simulation time 110953418 ps
CPU time 1.29 seconds
Started Aug 12 05:15:19 PM PDT 24
Finished Aug 12 05:15:21 PM PDT 24
Peak memory 197488 kb
Host smart-4b3798fc-cc89-4ce7-b91b-abae61ddfb30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791958719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3791958719
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3639119641
Short name T468
Test name
Test status
Simulation time 178468299 ps
CPU time 0.71 seconds
Started Aug 12 05:15:38 PM PDT 24
Finished Aug 12 05:15:39 PM PDT 24
Peak memory 195456 kb
Host smart-70787317-cdf3-4ac6-b0f1-6e915f76a212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639119641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3639119641
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1877554841
Short name T114
Test name
Test status
Simulation time 28224636 ps
CPU time 0.61 seconds
Started Aug 12 05:15:34 PM PDT 24
Finished Aug 12 05:15:35 PM PDT 24
Peak memory 194276 kb
Host smart-0e3a4359-a061-404a-b065-5b8ebd3d5c21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877554841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1877554841
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3069951819
Short name T704
Test name
Test status
Simulation time 1821566545 ps
CPU time 5.96 seconds
Started Aug 12 05:15:22 PM PDT 24
Finished Aug 12 05:15:28 PM PDT 24
Peak memory 198028 kb
Host smart-20810db8-edc1-4350-9b2c-2492011a11cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069951819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3069951819
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2106151303
Short name T286
Test name
Test status
Simulation time 80736626 ps
CPU time 0.8 seconds
Started Aug 12 05:15:29 PM PDT 24
Finished Aug 12 05:15:30 PM PDT 24
Peak memory 195996 kb
Host smart-d03d7378-a55b-49d6-a31b-745950d4ef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106151303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2106151303
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2827500280
Short name T532
Test name
Test status
Simulation time 96027732 ps
CPU time 1.09 seconds
Started Aug 12 05:15:24 PM PDT 24
Finished Aug 12 05:15:25 PM PDT 24
Peak memory 196552 kb
Host smart-30d8db73-ddf0-4f50-b709-089ddfc11ad1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827500280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2827500280
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3927510662
Short name T173
Test name
Test status
Simulation time 4201847538 ps
CPU time 54.32 seconds
Started Aug 12 05:15:23 PM PDT 24
Finished Aug 12 05:16:17 PM PDT 24
Peak memory 198140 kb
Host smart-8b995d8d-8be4-4b7a-b2c2-5cd1b4ad914d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927510662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3927510662
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2918214437
Short name T66
Test name
Test status
Simulation time 6271442070 ps
CPU time 197.54 seconds
Started Aug 12 05:15:35 PM PDT 24
Finished Aug 12 05:18:53 PM PDT 24
Peak memory 198424 kb
Host smart-db97b9a8-18cd-451b-bcf4-6aa7cf060afb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2918214437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2918214437
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1042965250
Short name T62
Test name
Test status
Simulation time 23881933 ps
CPU time 0.61 seconds
Started Aug 12 05:15:48 PM PDT 24
Finished Aug 12 05:15:49 PM PDT 24
Peak memory 194104 kb
Host smart-0541848b-0cff-4fc3-92cc-fe3327eb520b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042965250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1042965250
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4140611174
Short name T690
Test name
Test status
Simulation time 179481485 ps
CPU time 0.76 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 195324 kb
Host smart-a27a8bb9-9378-408a-88aa-2f302b277c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140611174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4140611174
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2651970663
Short name T118
Test name
Test status
Simulation time 401337862 ps
CPU time 20.45 seconds
Started Aug 12 05:15:31 PM PDT 24
Finished Aug 12 05:15:52 PM PDT 24
Peak memory 196764 kb
Host smart-6ec2d83b-eafd-4974-a6b1-adbe37555c8f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651970663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2651970663
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3549280122
Short name T230
Test name
Test status
Simulation time 113029048 ps
CPU time 0.71 seconds
Started Aug 12 05:15:30 PM PDT 24
Finished Aug 12 05:15:31 PM PDT 24
Peak memory 196528 kb
Host smart-3ace5eff-574a-4e06-a044-b7dc4e553d2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549280122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3549280122
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2282585327
Short name T676
Test name
Test status
Simulation time 121970531 ps
CPU time 1.09 seconds
Started Aug 12 05:15:33 PM PDT 24
Finished Aug 12 05:15:35 PM PDT 24
Peak memory 195788 kb
Host smart-20b5ccc5-20ab-4c4c-9f17-698733c2465c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282585327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2282585327
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1736332433
Short name T288
Test name
Test status
Simulation time 138707100 ps
CPU time 2.56 seconds
Started Aug 12 05:15:55 PM PDT 24
Finished Aug 12 05:15:58 PM PDT 24
Peak memory 198212 kb
Host smart-649fe823-fca3-4750-a824-fe64fc277dee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736332433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1736332433
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3270913143
Short name T618
Test name
Test status
Simulation time 175442081 ps
CPU time 2.01 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 196908 kb
Host smart-f22e7974-9da3-404f-80c7-33187f9d4335
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270913143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3270913143
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3829498582
Short name T385
Test name
Test status
Simulation time 73960447 ps
CPU time 0.86 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 196640 kb
Host smart-e978e5ac-1d13-4ddd-bdd3-134786fa2257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829498582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3829498582
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.4088714117
Short name T418
Test name
Test status
Simulation time 290583385 ps
CPU time 1.38 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 196608 kb
Host smart-a60a411d-77ab-4ede-b05b-0c67fec87b73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088714117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.4088714117
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1228925778
Short name T369
Test name
Test status
Simulation time 62115321 ps
CPU time 1.59 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:45 PM PDT 24
Peak memory 198036 kb
Host smart-04f7e48c-aca0-4775-98ac-b4a1a8c43598
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228925778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1228925778
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3368276479
Short name T223
Test name
Test status
Simulation time 28708224 ps
CPU time 0.92 seconds
Started Aug 12 05:15:38 PM PDT 24
Finished Aug 12 05:15:39 PM PDT 24
Peak memory 195756 kb
Host smart-f46070be-1e2a-4bb0-be48-825c4d326903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368276479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3368276479
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.188966651
Short name T598
Test name
Test status
Simulation time 32689600 ps
CPU time 0.97 seconds
Started Aug 12 05:15:35 PM PDT 24
Finished Aug 12 05:15:36 PM PDT 24
Peak memory 195940 kb
Host smart-5f29b961-2a5c-434f-882b-1a6cd9866198
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188966651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.188966651
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3792019325
Short name T8
Test name
Test status
Simulation time 24090288130 ps
CPU time 156.41 seconds
Started Aug 12 05:15:38 PM PDT 24
Finished Aug 12 05:18:14 PM PDT 24
Peak memory 198184 kb
Host smart-151b76ce-86ce-4518-b335-cf6840107184
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792019325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3792019325
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.786804464
Short name T456
Test name
Test status
Simulation time 20942094 ps
CPU time 0.55 seconds
Started Aug 12 05:15:24 PM PDT 24
Finished Aug 12 05:15:24 PM PDT 24
Peak memory 194020 kb
Host smart-89149b4c-9262-4bca-9a6e-5ceaeb3a7a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786804464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.786804464
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2566603031
Short name T650
Test name
Test status
Simulation time 20463469 ps
CPU time 0.68 seconds
Started Aug 12 05:15:49 PM PDT 24
Finished Aug 12 05:15:50 PM PDT 24
Peak memory 195308 kb
Host smart-935d994b-afc4-4c01-a244-1ae29458cf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566603031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2566603031
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3933336012
Short name T404
Test name
Test status
Simulation time 307344731 ps
CPU time 9.36 seconds
Started Aug 12 05:15:40 PM PDT 24
Finished Aug 12 05:15:49 PM PDT 24
Peak memory 198116 kb
Host smart-afac5c80-0798-444e-999f-a57de83cbe12
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933336012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3933336012
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.4178008029
Short name T388
Test name
Test status
Simulation time 249966794 ps
CPU time 0.92 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 197772 kb
Host smart-6fdc9bc4-adf6-4ee9-a3e1-616f2275a2c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178008029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.4178008029
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2744472061
Short name T621
Test name
Test status
Simulation time 147699948 ps
CPU time 1.13 seconds
Started Aug 12 05:15:40 PM PDT 24
Finished Aug 12 05:15:41 PM PDT 24
Peak memory 195944 kb
Host smart-fb642106-62a1-4027-88e4-d8f47b345d99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744472061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2744472061
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2346156303
Short name T451
Test name
Test status
Simulation time 65301466 ps
CPU time 2.59 seconds
Started Aug 12 05:15:26 PM PDT 24
Finished Aug 12 05:15:29 PM PDT 24
Peak memory 198088 kb
Host smart-a3b8f1d7-0470-4e7b-9d99-d25e6a2bb970
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346156303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2346156303
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.119470230
Short name T129
Test name
Test status
Simulation time 75438326 ps
CPU time 1.38 seconds
Started Aug 12 05:15:25 PM PDT 24
Finished Aug 12 05:15:26 PM PDT 24
Peak memory 196256 kb
Host smart-79009520-0dba-4afd-bf9d-a596ac3a602f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119470230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
119470230
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3298427212
Short name T397
Test name
Test status
Simulation time 64308826 ps
CPU time 0.69 seconds
Started Aug 12 05:15:34 PM PDT 24
Finished Aug 12 05:15:35 PM PDT 24
Peak memory 194392 kb
Host smart-834c0dbd-19b4-4f2e-aed2-9f5157a02c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298427212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3298427212
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2399677409
Short name T157
Test name
Test status
Simulation time 311020192 ps
CPU time 1.2 seconds
Started Aug 12 05:15:28 PM PDT 24
Finished Aug 12 05:15:29 PM PDT 24
Peak memory 198064 kb
Host smart-ad96b9b8-7257-43ff-88fb-5c7fef55a0f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399677409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2399677409
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2928114101
Short name T344
Test name
Test status
Simulation time 97938502 ps
CPU time 4.3 seconds
Started Aug 12 05:15:20 PM PDT 24
Finished Aug 12 05:15:25 PM PDT 24
Peak memory 198112 kb
Host smart-a95cfce6-9137-4344-9dfa-a72364b55397
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928114101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2928114101
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1947562586
Short name T471
Test name
Test status
Simulation time 113013432 ps
CPU time 1.1 seconds
Started Aug 12 05:15:21 PM PDT 24
Finished Aug 12 05:15:22 PM PDT 24
Peak memory 195636 kb
Host smart-2b044d23-5352-4d4d-945f-a01d72548a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947562586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1947562586
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1111449218
Short name T127
Test name
Test status
Simulation time 176266219 ps
CPU time 0.88 seconds
Started Aug 12 05:15:23 PM PDT 24
Finished Aug 12 05:15:24 PM PDT 24
Peak memory 196116 kb
Host smart-9a994be2-ca3b-412a-8e40-ccadf5dcf3fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111449218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1111449218
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2392133541
Short name T9
Test name
Test status
Simulation time 12605637515 ps
CPU time 143.11 seconds
Started Aug 12 05:15:29 PM PDT 24
Finished Aug 12 05:17:52 PM PDT 24
Peak memory 198312 kb
Host smart-a461d07f-2e9d-42b8-ac6e-15174a81c0cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392133541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2392133541
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.413344990
Short name T211
Test name
Test status
Simulation time 15835564 ps
CPU time 0.57 seconds
Started Aug 12 05:15:44 PM PDT 24
Finished Aug 12 05:15:45 PM PDT 24
Peak memory 194060 kb
Host smart-07cad686-878e-45d8-a074-4e7fbb4be41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413344990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.413344990
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2957886666
Short name T139
Test name
Test status
Simulation time 34236910 ps
CPU time 0.61 seconds
Started Aug 12 05:15:52 PM PDT 24
Finished Aug 12 05:15:52 PM PDT 24
Peak memory 193904 kb
Host smart-9cfae718-7652-414f-9970-afd92f906f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957886666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2957886666
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2922676929
Short name T622
Test name
Test status
Simulation time 3813922143 ps
CPU time 24.88 seconds
Started Aug 12 05:15:32 PM PDT 24
Finished Aug 12 05:15:57 PM PDT 24
Peak memory 196712 kb
Host smart-2e2a8d3c-c486-4051-a86e-44fbe7af7410
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922676929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2922676929
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1369250371
Short name T485
Test name
Test status
Simulation time 479340387 ps
CPU time 0.68 seconds
Started Aug 12 05:15:30 PM PDT 24
Finished Aug 12 05:15:31 PM PDT 24
Peak memory 194744 kb
Host smart-656fb403-9bdf-48c7-9cff-e7e2c491d657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369250371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1369250371
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2092990882
Short name T677
Test name
Test status
Simulation time 52457793 ps
CPU time 0.95 seconds
Started Aug 12 05:15:39 PM PDT 24
Finished Aug 12 05:15:40 PM PDT 24
Peak memory 196748 kb
Host smart-42446842-3d33-4b00-b460-4757badb14a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092990882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2092990882
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.479548440
Short name T332
Test name
Test status
Simulation time 55966853 ps
CPU time 2.11 seconds
Started Aug 12 05:15:46 PM PDT 24
Finished Aug 12 05:15:49 PM PDT 24
Peak memory 196544 kb
Host smart-68aabbdb-354e-4ace-8897-3458e768ef25
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479548440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.479548440
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2575315384
Short name T428
Test name
Test status
Simulation time 95075830 ps
CPU time 1.88 seconds
Started Aug 12 05:15:45 PM PDT 24
Finished Aug 12 05:15:47 PM PDT 24
Peak memory 195844 kb
Host smart-9f3b59c2-370e-4e88-b519-5bb473f30d3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575315384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2575315384
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1130036137
Short name T589
Test name
Test status
Simulation time 29343027 ps
CPU time 1.18 seconds
Started Aug 12 05:15:54 PM PDT 24
Finished Aug 12 05:15:55 PM PDT 24
Peak memory 198152 kb
Host smart-6a985d4c-5719-4e0d-be0d-ab3f6add7e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130036137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1130036137
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.115325894
Short name T578
Test name
Test status
Simulation time 45999156 ps
CPU time 1.06 seconds
Started Aug 12 05:15:30 PM PDT 24
Finished Aug 12 05:15:32 PM PDT 24
Peak memory 196712 kb
Host smart-171486fc-15b9-43ff-a017-ded558f8379b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115325894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.115325894
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1978825041
Short name T212
Test name
Test status
Simulation time 90327409 ps
CPU time 1.55 seconds
Started Aug 12 05:15:28 PM PDT 24
Finished Aug 12 05:15:30 PM PDT 24
Peak memory 198100 kb
Host smart-0c1c66a9-aa10-4dd1-b27f-83cce1ddabd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978825041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1978825041
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.907679942
Short name T599
Test name
Test status
Simulation time 610811212 ps
CPU time 0.98 seconds
Started Aug 12 05:15:22 PM PDT 24
Finished Aug 12 05:15:23 PM PDT 24
Peak memory 195076 kb
Host smart-19f5a937-bc10-4b80-9a7d-d4efc12ea4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907679942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.907679942
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3842138270
Short name T61
Test name
Test status
Simulation time 41900618 ps
CPU time 1.19 seconds
Started Aug 12 05:15:50 PM PDT 24
Finished Aug 12 05:15:51 PM PDT 24
Peak memory 195944 kb
Host smart-01489711-077c-4e31-a29d-ed089930c4c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842138270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3842138270
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.4057701635
Short name T294
Test name
Test status
Simulation time 9723401163 ps
CPU time 134.04 seconds
Started Aug 12 05:15:33 PM PDT 24
Finished Aug 12 05:17:47 PM PDT 24
Peak memory 198128 kb
Host smart-ee13cd73-b492-4fc7-8e9c-ae0824fafdc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057701635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.4057701635
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2131225275
Short name T68
Test name
Test status
Simulation time 5583425082 ps
CPU time 157.64 seconds
Started Aug 12 05:15:35 PM PDT 24
Finished Aug 12 05:18:13 PM PDT 24
Peak memory 198396 kb
Host smart-3d588fae-5e32-4819-bd02-442e8c4c2157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2131225275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2131225275
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2089022684
Short name T657
Test name
Test status
Simulation time 47601716 ps
CPU time 0.59 seconds
Started Aug 12 05:15:35 PM PDT 24
Finished Aug 12 05:15:36 PM PDT 24
Peak memory 194868 kb
Host smart-5c0d455e-c6ca-45d6-9d2f-b1cf888a847e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089022684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2089022684
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.413057808
Short name T147
Test name
Test status
Simulation time 45731084 ps
CPU time 0.78 seconds
Started Aug 12 05:15:39 PM PDT 24
Finished Aug 12 05:15:40 PM PDT 24
Peak memory 195240 kb
Host smart-b700d87d-ba77-4348-ab20-2f133290a4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413057808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.413057808
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2339045390
Short name T378
Test name
Test status
Simulation time 1823912194 ps
CPU time 25.62 seconds
Started Aug 12 05:15:32 PM PDT 24
Finished Aug 12 05:15:58 PM PDT 24
Peak memory 197204 kb
Host smart-ba871bd6-caa1-4ec8-bf39-b83a113ab6c2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339045390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2339045390
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2152033503
Short name T250
Test name
Test status
Simulation time 318018822 ps
CPU time 0.83 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 195868 kb
Host smart-2a873680-932b-43d2-b30c-2bd266299c3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152033503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2152033503
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.427617263
Short name T414
Test name
Test status
Simulation time 20977487 ps
CPU time 0.73 seconds
Started Aug 12 05:15:32 PM PDT 24
Finished Aug 12 05:15:32 PM PDT 24
Peak memory 195496 kb
Host smart-d8b958ee-3468-40a2-bec5-dda9ec19d640
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427617263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.427617263
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.440002160
Short name T605
Test name
Test status
Simulation time 577941173 ps
CPU time 2.7 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 198204 kb
Host smart-25e73cf3-15b9-40e9-8fca-4ecc523f5866
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440002160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.440002160
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2175167070
Short name T345
Test name
Test status
Simulation time 28920511 ps
CPU time 0.89 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 195560 kb
Host smart-cfec0279-3d4c-4b1b-9a41-7101e08ab126
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175167070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2175167070
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.4263421947
Short name T181
Test name
Test status
Simulation time 251393287 ps
CPU time 1.27 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 195904 kb
Host smart-a59bc55e-8cd5-407f-b923-b8f76e9c26dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263421947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.4263421947
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2423436006
Short name T253
Test name
Test status
Simulation time 135312018 ps
CPU time 0.95 seconds
Started Aug 12 05:15:30 PM PDT 24
Finished Aug 12 05:15:31 PM PDT 24
Peak memory 196760 kb
Host smart-3dfbcb79-265b-435c-a08f-1ba399ca0271
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423436006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2423436006
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1385898976
Short name T218
Test name
Test status
Simulation time 62384450 ps
CPU time 2.71 seconds
Started Aug 12 05:15:50 PM PDT 24
Finished Aug 12 05:15:53 PM PDT 24
Peak memory 198088 kb
Host smart-0dc8e550-af0c-425f-8b03-c86d008d1407
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385898976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1385898976
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3278985082
Short name T310
Test name
Test status
Simulation time 87118873 ps
CPU time 1.32 seconds
Started Aug 12 05:15:33 PM PDT 24
Finished Aug 12 05:15:34 PM PDT 24
Peak memory 196812 kb
Host smart-c4971705-021b-42bf-9692-e9b941fb8f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278985082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3278985082
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2551206017
Short name T55
Test name
Test status
Simulation time 51156297 ps
CPU time 1.29 seconds
Started Aug 12 05:15:33 PM PDT 24
Finished Aug 12 05:15:35 PM PDT 24
Peak memory 195664 kb
Host smart-b49d76f9-dd1a-43d4-9f3e-6e8df11d9218
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551206017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2551206017
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2295460263
Short name T3
Test name
Test status
Simulation time 37949384501 ps
CPU time 90.03 seconds
Started Aug 12 05:15:33 PM PDT 24
Finished Aug 12 05:17:03 PM PDT 24
Peak memory 198264 kb
Host smart-48f71d2b-3d63-4e6d-bae6-36bafa132734
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295460263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2295460263
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1931094796
Short name T522
Test name
Test status
Simulation time 66655091 ps
CPU time 0.61 seconds
Started Aug 12 05:14:00 PM PDT 24
Finished Aug 12 05:14:01 PM PDT 24
Peak memory 194724 kb
Host smart-beec145d-7d0a-43ea-9eda-84679cc0c4ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931094796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1931094796
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1577356272
Short name T347
Test name
Test status
Simulation time 95436369 ps
CPU time 0.69 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:13:56 PM PDT 24
Peak memory 194268 kb
Host smart-3f714c5f-683e-4048-93a7-431d02ff0431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577356272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1577356272
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1093088677
Short name T619
Test name
Test status
Simulation time 1501131676 ps
CPU time 27.11 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:14:25 PM PDT 24
Peak memory 197076 kb
Host smart-ef3ab16b-7763-4f11-968a-59665944add9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093088677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1093088677
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.661702581
Short name T412
Test name
Test status
Simulation time 88728055 ps
CPU time 1 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:13:58 PM PDT 24
Peak memory 196752 kb
Host smart-9cec96bf-a7d0-4168-84ba-b50bb856911a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661702581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.661702581
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3139965049
Short name T684
Test name
Test status
Simulation time 149737640 ps
CPU time 0.82 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:13:58 PM PDT 24
Peak memory 196372 kb
Host smart-923c9a95-ca04-4f17-abb8-b7a2539f80cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139965049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3139965049
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2580671627
Short name T408
Test name
Test status
Simulation time 156649384 ps
CPU time 1.79 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:13:59 PM PDT 24
Peak memory 198196 kb
Host smart-bd210a71-4ab3-460c-baa7-71d44f08164e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580671627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2580671627
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3073811434
Short name T117
Test name
Test status
Simulation time 73514693 ps
CPU time 1.68 seconds
Started Aug 12 05:14:00 PM PDT 24
Finished Aug 12 05:14:02 PM PDT 24
Peak memory 196880 kb
Host smart-2707301d-6c8c-4e07-8726-0da6c20c81b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073811434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3073811434
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2449784682
Short name T156
Test name
Test status
Simulation time 485852587 ps
CPU time 1.17 seconds
Started Aug 12 05:14:13 PM PDT 24
Finished Aug 12 05:14:15 PM PDT 24
Peak memory 196096 kb
Host smart-b7d847d9-7b8d-4874-b2e3-050d7f2a92cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449784682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2449784682
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3441691792
Short name T112
Test name
Test status
Simulation time 20541532 ps
CPU time 0.81 seconds
Started Aug 12 05:14:04 PM PDT 24
Finished Aug 12 05:14:05 PM PDT 24
Peak memory 195064 kb
Host smart-c571ee7c-975a-47cf-a9c2-15aaca8f65b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441691792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3441691792
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2760740466
Short name T523
Test name
Test status
Simulation time 353270158 ps
CPU time 4.03 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:14:00 PM PDT 24
Peak memory 198108 kb
Host smart-dda922d4-bb24-48b8-ae40-a2b8b1672aa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760740466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2760740466
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.625866324
Short name T488
Test name
Test status
Simulation time 285739577 ps
CPU time 1.23 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:13:59 PM PDT 24
Peak memory 195720 kb
Host smart-f3d7cd7e-a546-40e4-b607-4d9f0e1fdcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625866324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.625866324
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.310312658
Short name T185
Test name
Test status
Simulation time 122773257 ps
CPU time 1.21 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:13:58 PM PDT 24
Peak memory 196404 kb
Host smart-b3bdd1b9-83a8-46ec-81ac-25701bd6cd99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310312658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.310312658
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1766030349
Short name T484
Test name
Test status
Simulation time 15214681524 ps
CPU time 181.18 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:16:59 PM PDT 24
Peak memory 198276 kb
Host smart-769616c9-c75d-4602-8b11-465fa98626e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766030349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1766030349
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2171897091
Short name T293
Test name
Test status
Simulation time 18234407651 ps
CPU time 48.07 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:14:46 PM PDT 24
Peak memory 206544 kb
Host smart-9db8b0c9-c5bc-4223-8370-8c477b8e65ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2171897091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2171897091
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3573496491
Short name T616
Test name
Test status
Simulation time 57543896 ps
CPU time 0.58 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:13:58 PM PDT 24
Peak memory 194896 kb
Host smart-f34dfa55-4daa-4baf-8a2d-883571da426e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573496491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3573496491
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.138083169
Short name T384
Test name
Test status
Simulation time 199030028 ps
CPU time 0.72 seconds
Started Aug 12 05:14:00 PM PDT 24
Finished Aug 12 05:14:01 PM PDT 24
Peak memory 194192 kb
Host smart-2ee21f1a-61a3-49a5-a5e1-b4001fd9d1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138083169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.138083169
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.4224138177
Short name T318
Test name
Test status
Simulation time 669930299 ps
CPU time 18.12 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:14:16 PM PDT 24
Peak memory 196856 kb
Host smart-373b83ef-c918-4c78-bdb3-7326ceceaa6b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224138177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.4224138177
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3744401835
Short name T500
Test name
Test status
Simulation time 110871301 ps
CPU time 0.65 seconds
Started Aug 12 05:13:59 PM PDT 24
Finished Aug 12 05:14:00 PM PDT 24
Peak memory 194572 kb
Host smart-1927fca9-6f2a-4fd9-a001-cef9c01f361e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744401835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3744401835
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3816173714
Short name T400
Test name
Test status
Simulation time 63665617 ps
CPU time 1.05 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:13:58 PM PDT 24
Peak memory 196840 kb
Host smart-cda7b9f3-c26f-404f-b412-98263935b89e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816173714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3816173714
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1132356423
Short name T383
Test name
Test status
Simulation time 285124214 ps
CPU time 3.01 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:14:00 PM PDT 24
Peak memory 198196 kb
Host smart-1de10087-8339-4019-9021-7b335dbdd0fb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132356423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1132356423
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2384606226
Short name T116
Test name
Test status
Simulation time 31833830 ps
CPU time 1.04 seconds
Started Aug 12 05:13:59 PM PDT 24
Finished Aug 12 05:14:00 PM PDT 24
Peak memory 195628 kb
Host smart-c55f8fd7-d07a-4e42-b2d8-19946cedea1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384606226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2384606226
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3784541690
Short name T19
Test name
Test status
Simulation time 27287913 ps
CPU time 1 seconds
Started Aug 12 05:13:59 PM PDT 24
Finished Aug 12 05:14:00 PM PDT 24
Peak memory 196136 kb
Host smart-6fafac5e-c315-4587-a690-8c5de7210a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784541690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3784541690
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2982180386
Short name T227
Test name
Test status
Simulation time 134091182 ps
CPU time 1.02 seconds
Started Aug 12 05:13:56 PM PDT 24
Finished Aug 12 05:13:57 PM PDT 24
Peak memory 196120 kb
Host smart-a6c08450-9919-458f-87a4-0a0ef8062035
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982180386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2982180386
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.81640146
Short name T214
Test name
Test status
Simulation time 791055723 ps
CPU time 3.52 seconds
Started Aug 12 05:13:57 PM PDT 24
Finished Aug 12 05:14:00 PM PDT 24
Peak memory 198112 kb
Host smart-73a0e37e-7300-490b-9def-9f359d3160f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81640146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rando
m_long_reg_writes_reg_reads.81640146
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2959858739
Short name T628
Test name
Test status
Simulation time 50772329 ps
CPU time 1.32 seconds
Started Aug 12 05:13:55 PM PDT 24
Finished Aug 12 05:13:56 PM PDT 24
Peak memory 198044 kb
Host smart-2b9bcf86-e508-4bf6-9cdc-161864f77e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959858739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2959858739
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1868232892
Short name T351
Test name
Test status
Simulation time 39913917 ps
CPU time 0.72 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:13:59 PM PDT 24
Peak memory 195336 kb
Host smart-4ecea925-4826-4b75-9cbd-7bfac0891b67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868232892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1868232892
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.819737445
Short name T432
Test name
Test status
Simulation time 12007170722 ps
CPU time 133.3 seconds
Started Aug 12 05:14:00 PM PDT 24
Finished Aug 12 05:16:14 PM PDT 24
Peak memory 198316 kb
Host smart-b29781a2-9df3-4434-878d-cef8371aa247
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819737445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.819737445
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1985771621
Short name T479
Test name
Test status
Simulation time 1576666151 ps
CPU time 52.84 seconds
Started Aug 12 05:13:58 PM PDT 24
Finished Aug 12 05:14:51 PM PDT 24
Peak memory 198276 kb
Host smart-51fe7ec2-3769-4e6d-b384-533d2f5220c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1985771621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1985771621
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.529223671
Short name T305
Test name
Test status
Simulation time 49666321 ps
CPU time 0.57 seconds
Started Aug 12 05:14:13 PM PDT 24
Finished Aug 12 05:14:14 PM PDT 24
Peak memory 194156 kb
Host smart-cd384361-dcbf-40de-a45c-3b80a669e1e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529223671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.529223671
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1266070939
Short name T648
Test name
Test status
Simulation time 55700637 ps
CPU time 0.91 seconds
Started Aug 12 05:14:10 PM PDT 24
Finished Aug 12 05:14:11 PM PDT 24
Peak memory 196588 kb
Host smart-bf118ef2-5058-446f-a10a-a9a9fdb63da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266070939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1266070939
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1705333252
Short name T708
Test name
Test status
Simulation time 816970190 ps
CPU time 10.79 seconds
Started Aug 12 05:14:03 PM PDT 24
Finished Aug 12 05:14:14 PM PDT 24
Peak memory 195620 kb
Host smart-30799e21-9708-40c0-a068-ebeb1cc58f1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705333252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1705333252
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1368586034
Short name T304
Test name
Test status
Simulation time 81663200 ps
CPU time 0.95 seconds
Started Aug 12 05:14:05 PM PDT 24
Finished Aug 12 05:14:06 PM PDT 24
Peak memory 197156 kb
Host smart-270e132d-702e-454b-ad62-64aa9f98d899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368586034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1368586034
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1765644885
Short name T11
Test name
Test status
Simulation time 250334834 ps
CPU time 1.04 seconds
Started Aug 12 05:14:03 PM PDT 24
Finished Aug 12 05:14:04 PM PDT 24
Peak memory 195888 kb
Host smart-65eecef6-ca0d-4924-a11e-e7344defc922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765644885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1765644885
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2163680094
Short name T257
Test name
Test status
Simulation time 44578031 ps
CPU time 1.78 seconds
Started Aug 12 05:14:15 PM PDT 24
Finished Aug 12 05:14:17 PM PDT 24
Peak memory 197288 kb
Host smart-5de840f5-c982-4270-9c4c-9debb482033c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163680094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2163680094
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1127387536
Short name T354
Test name
Test status
Simulation time 97456507 ps
CPU time 2 seconds
Started Aug 12 05:14:10 PM PDT 24
Finished Aug 12 05:14:12 PM PDT 24
Peak memory 196280 kb
Host smart-b3368432-1d7a-40cf-8fc1-dc8aa78bef37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127387536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1127387536
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.161631372
Short name T458
Test name
Test status
Simulation time 75028391 ps
CPU time 1.26 seconds
Started Aug 12 05:14:02 PM PDT 24
Finished Aug 12 05:14:04 PM PDT 24
Peak memory 198196 kb
Host smart-dcd3dd6c-e9bc-434a-af83-b69da0ace8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161631372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.161631372
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2001377364
Short name T649
Test name
Test status
Simulation time 43769490 ps
CPU time 1.1 seconds
Started Aug 12 05:14:15 PM PDT 24
Finished Aug 12 05:14:17 PM PDT 24
Peak memory 196880 kb
Host smart-4022fdce-da52-4a7c-91fd-595c0672f398
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001377364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2001377364
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.954133936
Short name T395
Test name
Test status
Simulation time 292802451 ps
CPU time 4.79 seconds
Started Aug 12 05:14:09 PM PDT 24
Finished Aug 12 05:14:14 PM PDT 24
Peak memory 198060 kb
Host smart-b18a18c9-7078-4c3c-b2b9-8f02f5fc3434
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954133936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.954133936
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1326996675
Short name T538
Test name
Test status
Simulation time 50695255 ps
CPU time 1.01 seconds
Started Aug 12 05:14:00 PM PDT 24
Finished Aug 12 05:14:01 PM PDT 24
Peak memory 196332 kb
Host smart-25340cfb-ac28-40d6-950b-b7ca6f513026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326996675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1326996675
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.693371128
Short name T283
Test name
Test status
Simulation time 57573481 ps
CPU time 1.2 seconds
Started Aug 12 05:14:03 PM PDT 24
Finished Aug 12 05:14:05 PM PDT 24
Peak memory 195676 kb
Host smart-04704c3c-404a-4640-89e9-3d0a828d9f7f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693371128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.693371128
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3145844999
Short name T128
Test name
Test status
Simulation time 1682044427 ps
CPU time 41.5 seconds
Started Aug 12 05:14:18 PM PDT 24
Finished Aug 12 05:15:00 PM PDT 24
Peak memory 198144 kb
Host smart-016d36d7-2cae-44e3-b494-354e32c52a14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145844999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3145844999
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3648925873
Short name T172
Test name
Test status
Simulation time 33434062 ps
CPU time 0.58 seconds
Started Aug 12 05:14:09 PM PDT 24
Finished Aug 12 05:14:10 PM PDT 24
Peak memory 194712 kb
Host smart-137ad31d-f72e-489a-a069-0e60c607654a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648925873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3648925873
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3132105342
Short name T691
Test name
Test status
Simulation time 55552449 ps
CPU time 0.74 seconds
Started Aug 12 05:14:21 PM PDT 24
Finished Aug 12 05:14:22 PM PDT 24
Peak memory 195296 kb
Host smart-2ab5e75b-d435-4539-8bed-a310a9938a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132105342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3132105342
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2910684028
Short name T352
Test name
Test status
Simulation time 124516313 ps
CPU time 6.32 seconds
Started Aug 12 05:14:08 PM PDT 24
Finished Aug 12 05:14:15 PM PDT 24
Peak memory 196800 kb
Host smart-d39fcc9d-cf1d-4552-8c92-10a2979c8529
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910684028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2910684028
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1787979861
Short name T143
Test name
Test status
Simulation time 212501746 ps
CPU time 0.95 seconds
Started Aug 12 05:14:10 PM PDT 24
Finished Aug 12 05:14:11 PM PDT 24
Peak memory 196880 kb
Host smart-123b74b8-6626-44bb-952b-2676b4ff3415
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787979861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1787979861
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1183247238
Short name T477
Test name
Test status
Simulation time 193519536 ps
CPU time 1.34 seconds
Started Aug 12 05:14:10 PM PDT 24
Finished Aug 12 05:14:12 PM PDT 24
Peak memory 197008 kb
Host smart-be2e7e68-f9f7-4c85-82b2-03781c49cb29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183247238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1183247238
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2710782403
Short name T267
Test name
Test status
Simulation time 83034333 ps
CPU time 3.11 seconds
Started Aug 12 05:14:05 PM PDT 24
Finished Aug 12 05:14:09 PM PDT 24
Peak memory 198144 kb
Host smart-099bc629-fd6e-4d42-961a-f5bc775baafc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710782403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2710782403
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2193376248
Short name T241
Test name
Test status
Simulation time 658273953 ps
CPU time 3.02 seconds
Started Aug 12 05:14:13 PM PDT 24
Finished Aug 12 05:14:16 PM PDT 24
Peak memory 196864 kb
Host smart-2a6fb1ad-d45a-4724-ab0f-7b604cb72e54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193376248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2193376248
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3315111488
Short name T710
Test name
Test status
Simulation time 45893065 ps
CPU time 1.11 seconds
Started Aug 12 05:14:05 PM PDT 24
Finished Aug 12 05:14:07 PM PDT 24
Peak memory 196640 kb
Host smart-31427c77-bab2-4c9d-ad1d-ef8b6c233862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315111488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3315111488
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3323290469
Short name T632
Test name
Test status
Simulation time 35693237 ps
CPU time 0.94 seconds
Started Aug 12 05:14:09 PM PDT 24
Finished Aug 12 05:14:11 PM PDT 24
Peak memory 195904 kb
Host smart-f8a3b0cc-6fec-4897-aac2-5ebdb02bb2bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323290469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3323290469
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2119366607
Short name T243
Test name
Test status
Simulation time 2200471362 ps
CPU time 4.95 seconds
Started Aug 12 05:14:04 PM PDT 24
Finished Aug 12 05:14:09 PM PDT 24
Peak memory 198188 kb
Host smart-b2e3d183-1a8c-4e92-b1c8-48f245ae0c0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119366607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2119366607
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.4245841424
Short name T179
Test name
Test status
Simulation time 51298652 ps
CPU time 0.67 seconds
Started Aug 12 05:14:08 PM PDT 24
Finished Aug 12 05:14:09 PM PDT 24
Peak memory 194152 kb
Host smart-e509f7f9-cbc8-4647-a8ed-44ed239dc353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245841424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.4245841424
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.32227175
Short name T482
Test name
Test status
Simulation time 181234247 ps
CPU time 0.97 seconds
Started Aug 12 05:14:20 PM PDT 24
Finished Aug 12 05:14:21 PM PDT 24
Peak memory 196444 kb
Host smart-35dec780-0ef7-4b7b-9aee-6e1d553a6d69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32227175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.32227175
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2272364670
Short name T109
Test name
Test status
Simulation time 6798251545 ps
CPU time 165.9 seconds
Started Aug 12 05:14:02 PM PDT 24
Finished Aug 12 05:16:48 PM PDT 24
Peak memory 198232 kb
Host smart-6e3e5e0f-6608-4178-87d7-3d4324f50f10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272364670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2272364670
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3286395108
Short name T463
Test name
Test status
Simulation time 44954243497 ps
CPU time 78.14 seconds
Started Aug 12 05:14:09 PM PDT 24
Finished Aug 12 05:15:27 PM PDT 24
Peak memory 198356 kb
Host smart-50b5967c-6bfb-4107-a6e4-d3cb13d8a63d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3286395108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3286395108
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3068723514
Short name T581
Test name
Test status
Simulation time 33896441 ps
CPU time 0.58 seconds
Started Aug 12 05:14:18 PM PDT 24
Finished Aug 12 05:14:18 PM PDT 24
Peak memory 193912 kb
Host smart-ef491e5a-bcef-4d0f-8d32-5cba23907be5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068723514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3068723514
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1885318478
Short name T316
Test name
Test status
Simulation time 128933417 ps
CPU time 0.72 seconds
Started Aug 12 05:14:03 PM PDT 24
Finished Aug 12 05:14:04 PM PDT 24
Peak memory 194180 kb
Host smart-92f90ee9-c462-416c-a4a5-981da7e64fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885318478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1885318478
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1709871530
Short name T573
Test name
Test status
Simulation time 1741394162 ps
CPU time 24.62 seconds
Started Aug 12 05:14:06 PM PDT 24
Finished Aug 12 05:14:30 PM PDT 24
Peak memory 195572 kb
Host smart-45f606d3-6ad2-43ca-8c83-fed30eef2944
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709871530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1709871530
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2872579592
Short name T226
Test name
Test status
Simulation time 38013845 ps
CPU time 0.69 seconds
Started Aug 12 05:14:06 PM PDT 24
Finished Aug 12 05:14:06 PM PDT 24
Peak memory 194604 kb
Host smart-134f8c76-b902-4e4d-8a19-1c30bebb2739
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872579592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2872579592
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1133126119
Short name T366
Test name
Test status
Simulation time 91777769 ps
CPU time 1.48 seconds
Started Aug 12 05:14:18 PM PDT 24
Finished Aug 12 05:14:20 PM PDT 24
Peak memory 196580 kb
Host smart-022a3676-3fb6-48d7-9e61-b3d90066a304
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133126119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1133126119
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1156473156
Short name T196
Test name
Test status
Simulation time 46512978 ps
CPU time 1.05 seconds
Started Aug 12 05:14:10 PM PDT 24
Finished Aug 12 05:14:11 PM PDT 24
Peak memory 196296 kb
Host smart-0540e336-b933-4601-a6df-5091a52b1b7e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156473156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1156473156
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.4092377079
Short name T262
Test name
Test status
Simulation time 121309363 ps
CPU time 0.96 seconds
Started Aug 12 05:14:16 PM PDT 24
Finished Aug 12 05:14:17 PM PDT 24
Peak memory 194480 kb
Host smart-9b783d60-e9df-4bfc-a105-b7d2e7d32a3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092377079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
4092377079
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.940242543
Short name T644
Test name
Test status
Simulation time 279212993 ps
CPU time 1.24 seconds
Started Aug 12 05:14:04 PM PDT 24
Finished Aug 12 05:14:06 PM PDT 24
Peak memory 197296 kb
Host smart-556e8cff-1758-4c73-8ec3-b9bdfd8c6bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940242543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.940242543
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.153377589
Short name T560
Test name
Test status
Simulation time 48942787 ps
CPU time 1.11 seconds
Started Aug 12 05:14:09 PM PDT 24
Finished Aug 12 05:14:11 PM PDT 24
Peak memory 196964 kb
Host smart-79a53b13-1aaf-482b-94f2-2afd36e201b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153377589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.153377589
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.854469290
Short name T144
Test name
Test status
Simulation time 117784141 ps
CPU time 5.59 seconds
Started Aug 12 05:14:10 PM PDT 24
Finished Aug 12 05:14:16 PM PDT 24
Peak memory 198000 kb
Host smart-ebf26d7c-c35a-481e-9b61-2830f5dd3d12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854469290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.854469290
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.112425808
Short name T396
Test name
Test status
Simulation time 71670113 ps
CPU time 0.8 seconds
Started Aug 12 05:14:04 PM PDT 24
Finished Aug 12 05:14:05 PM PDT 24
Peak memory 195340 kb
Host smart-db03d40b-a0a4-42ce-97ef-1d8caffcf81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112425808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.112425808
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.4254611285
Short name T239
Test name
Test status
Simulation time 196233391 ps
CPU time 1.02 seconds
Started Aug 12 05:14:12 PM PDT 24
Finished Aug 12 05:14:13 PM PDT 24
Peak memory 195976 kb
Host smart-64fc0ddd-52b9-4e36-8783-4aa2df11418e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254611285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.4254611285
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1952432285
Short name T274
Test name
Test status
Simulation time 33874045708 ps
CPU time 98.62 seconds
Started Aug 12 05:14:08 PM PDT 24
Finished Aug 12 05:15:47 PM PDT 24
Peak memory 198316 kb
Host smart-6ddeeaa1-3feb-49c5-bbd0-84cca5703376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952432285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1952432285
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3496121263
Short name T936
Test name
Test status
Simulation time 151807142 ps
CPU time 1.14 seconds
Started Aug 12 05:13:40 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 191484 kb
Host smart-d02f9632-604f-4322-85fa-64c4a77e123a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3496121263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3496121263
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2357045382
Short name T892
Test name
Test status
Simulation time 95544026 ps
CPU time 1.06 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 196740 kb
Host smart-695ee607-0353-4246-9cef-68324a03c117
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357045382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2357045382
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4241289326
Short name T861
Test name
Test status
Simulation time 135478435 ps
CPU time 1.57 seconds
Started Aug 12 05:13:40 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 191408 kb
Host smart-3c776a1a-6df9-4e6d-bde4-89d15ee125fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4241289326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.4241289326
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1957832681
Short name T925
Test name
Test status
Simulation time 513067746 ps
CPU time 1.04 seconds
Started Aug 12 05:13:40 PM PDT 24
Finished Aug 12 05:13:41 PM PDT 24
Peak memory 191444 kb
Host smart-edba3fda-36d4-4301-8aed-b2379745d578
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957832681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1957832681
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1335102362
Short name T893
Test name
Test status
Simulation time 88104305 ps
CPU time 1.06 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191480 kb
Host smart-947e5d33-099d-4953-a87f-6a13fa2dacac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1335102362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1335102362
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1118653805
Short name T916
Test name
Test status
Simulation time 105625575 ps
CPU time 1.19 seconds
Started Aug 12 05:13:39 PM PDT 24
Finished Aug 12 05:13:40 PM PDT 24
Peak memory 191400 kb
Host smart-60013888-34f8-431c-80b3-da35d6cf1d87
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118653805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1118653805
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1642760765
Short name T870
Test name
Test status
Simulation time 125155021 ps
CPU time 1.23 seconds
Started Aug 12 05:13:38 PM PDT 24
Finished Aug 12 05:13:40 PM PDT 24
Peak memory 191412 kb
Host smart-11ed1881-abd3-4c8a-b253-2860f9ea7b04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1642760765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1642760765
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.441586774
Short name T846
Test name
Test status
Simulation time 54224010 ps
CPU time 1.13 seconds
Started Aug 12 05:13:40 PM PDT 24
Finished Aug 12 05:13:41 PM PDT 24
Peak memory 191464 kb
Host smart-ddccb76c-77af-4e03-aa4f-44a8756e5d10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441586774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.441586774
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1021984517
Short name T921
Test name
Test status
Simulation time 231183649 ps
CPU time 1.06 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191472 kb
Host smart-bc15af15-8a4a-479d-bc76-7c24683b9700
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1021984517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1021984517
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.79201302
Short name T899
Test name
Test status
Simulation time 152368788 ps
CPU time 1.31 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 197828 kb
Host smart-91fcecd8-b217-4f0d-b18c-794ae82df87d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79201302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.79201302
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3860345664
Short name T884
Test name
Test status
Simulation time 39205426 ps
CPU time 1.03 seconds
Started Aug 12 05:13:40 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 191416 kb
Host smart-2e8279e4-49bf-4148-8f63-8d44e25f89a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3860345664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3860345664
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.692583856
Short name T911
Test name
Test status
Simulation time 29267411 ps
CPU time 0.9 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191216 kb
Host smart-23ff7dc2-3361-448e-8052-3d19a896bd17
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692583856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.692583856
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.428639376
Short name T849
Test name
Test status
Simulation time 64269694 ps
CPU time 1.35 seconds
Started Aug 12 05:13:40 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 191580 kb
Host smart-0cc7bf21-8640-4c0e-9c4a-d09e7dc21a3a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=428639376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.428639376
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4278919814
Short name T886
Test name
Test status
Simulation time 44964471 ps
CPU time 0.97 seconds
Started Aug 12 05:13:40 PM PDT 24
Finished Aug 12 05:13:41 PM PDT 24
Peak memory 191444 kb
Host smart-eb309c2b-7d61-4c8a-bd64-61558fbdf9af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278919814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4278919814
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1356492324
Short name T865
Test name
Test status
Simulation time 241766476 ps
CPU time 0.79 seconds
Started Aug 12 05:13:45 PM PDT 24
Finished Aug 12 05:13:46 PM PDT 24
Peak memory 195736 kb
Host smart-c648ca19-0808-47c7-a39d-5d3b71818219
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1356492324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1356492324
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3271412384
Short name T894
Test name
Test status
Simulation time 145269670 ps
CPU time 1.34 seconds
Started Aug 12 05:13:39 PM PDT 24
Finished Aug 12 05:13:40 PM PDT 24
Peak memory 197704 kb
Host smart-aecc2b4d-f799-4d2e-ab99-c68ad0a65f7b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271412384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3271412384
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2375578088
Short name T856
Test name
Test status
Simulation time 42746669 ps
CPU time 1.2 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 197724 kb
Host smart-2ebbb759-1326-4735-a4e9-0eaab8b182d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2375578088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2375578088
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.801135317
Short name T873
Test name
Test status
Simulation time 955016460 ps
CPU time 1.26 seconds
Started Aug 12 05:13:40 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 191476 kb
Host smart-45e2dc4d-3978-47b6-90bf-2d4fa5e71ec7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801135317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.801135317
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1230963262
Short name T890
Test name
Test status
Simulation time 62142360 ps
CPU time 1.2 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191424 kb
Host smart-01a99a35-0fe5-47b2-8469-28ab2d187b2d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1230963262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1230963262
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2052096130
Short name T881
Test name
Test status
Simulation time 144006346 ps
CPU time 1.23 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 197680 kb
Host smart-86a0efe5-3b2e-4a00-9caf-098a44d81fe9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052096130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2052096130
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.4202651658
Short name T935
Test name
Test status
Simulation time 291870881 ps
CPU time 1.28 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191372 kb
Host smart-aad4e5ea-ab5b-4828-8255-514aef46e7c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4202651658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.4202651658
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4017182597
Short name T900
Test name
Test status
Simulation time 679831478 ps
CPU time 1.18 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191428 kb
Host smart-bbd143a3-a17e-4804-b391-d035e6d27fc0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017182597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4017182597
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1222034423
Short name T860
Test name
Test status
Simulation time 98334645 ps
CPU time 1.17 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 197692 kb
Host smart-b89e021b-7d14-4e86-8cc8-d532bc326b62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1222034423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1222034423
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.127700791
Short name T913
Test name
Test status
Simulation time 120768294 ps
CPU time 1.19 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191320 kb
Host smart-ccfc3254-297d-4695-bd7e-58ef536be8fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127700791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.127700791
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.477029396
Short name T851
Test name
Test status
Simulation time 56155302 ps
CPU time 0.95 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 191368 kb
Host smart-1466b39e-ef05-4138-8835-b14034dec462
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=477029396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.477029396
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2628699773
Short name T897
Test name
Test status
Simulation time 54834219 ps
CPU time 0.95 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 196800 kb
Host smart-08e43a50-d105-432f-91e1-21076ef80b1a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628699773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2628699773
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3324137084
Short name T919
Test name
Test status
Simulation time 45055742 ps
CPU time 1.24 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191432 kb
Host smart-8d5fc223-81db-4ca1-a3a6-f3cbdf070d94
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3324137084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3324137084
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3650043198
Short name T934
Test name
Test status
Simulation time 147460812 ps
CPU time 1.39 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191332 kb
Host smart-158a69b7-f611-408f-8391-e75c28ecc84f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650043198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3650043198
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3453194825
Short name T869
Test name
Test status
Simulation time 210632746 ps
CPU time 1.2 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191440 kb
Host smart-b18a081b-f5b3-47b8-845b-86ea8dab39b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3453194825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3453194825
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2689199607
Short name T844
Test name
Test status
Simulation time 112322198 ps
CPU time 1.02 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 196976 kb
Host smart-257bb17f-89a4-4430-9c1e-8dacae0ddffe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689199607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2689199607
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.275465310
Short name T852
Test name
Test status
Simulation time 66820475 ps
CPU time 1.13 seconds
Started Aug 12 05:13:44 PM PDT 24
Finished Aug 12 05:13:45 PM PDT 24
Peak memory 191432 kb
Host smart-4cd2e022-9347-4968-a54b-c206b30e42cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=275465310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.275465310
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.17292739
Short name T848
Test name
Test status
Simulation time 46829138 ps
CPU time 0.99 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 195904 kb
Host smart-8e45e49d-4ebc-4c5a-bff2-d6af390c9180
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17292739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.17292739
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1193374927
Short name T895
Test name
Test status
Simulation time 197028760 ps
CPU time 1.05 seconds
Started Aug 12 05:13:44 PM PDT 24
Finished Aug 12 05:13:45 PM PDT 24
Peak memory 196212 kb
Host smart-ddaf14a1-2344-450f-beea-96e7e869b0c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1193374927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1193374927
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2010266249
Short name T931
Test name
Test status
Simulation time 43798195 ps
CPU time 0.96 seconds
Started Aug 12 05:13:46 PM PDT 24
Finished Aug 12 05:13:47 PM PDT 24
Peak memory 197064 kb
Host smart-2ff286a3-e978-4d1e-9bf7-a486b22adc7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010266249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2010266249
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.337640327
Short name T917
Test name
Test status
Simulation time 46017705 ps
CPU time 1.12 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 197716 kb
Host smart-91975c1e-38dc-4df2-a692-87b9f3915bd7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=337640327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.337640327
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.794288882
Short name T910
Test name
Test status
Simulation time 275215499 ps
CPU time 1.1 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 190592 kb
Host smart-3b3c9c69-d9be-4a92-9238-ad386b58bb59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794288882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.794288882
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2802134002
Short name T891
Test name
Test status
Simulation time 175488397 ps
CPU time 1.4 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191440 kb
Host smart-1f228b70-5076-4b97-ba24-6048abbd7d3f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2802134002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2802134002
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2780703216
Short name T924
Test name
Test status
Simulation time 121391772 ps
CPU time 1.25 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:45 PM PDT 24
Peak memory 197560 kb
Host smart-6c4812d5-dac5-48b8-853d-5b3a1e9c6c63
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780703216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2780703216
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1814088070
Short name T927
Test name
Test status
Simulation time 50452264 ps
CPU time 1.14 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 197232 kb
Host smart-c8756b5c-00b1-4dee-bfd1-632eb76a2e68
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1814088070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1814088070
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1801858601
Short name T845
Test name
Test status
Simulation time 70480192 ps
CPU time 1.29 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191312 kb
Host smart-5b601293-cfac-439c-aca2-d5393bd12143
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801858601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1801858601
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.73643242
Short name T918
Test name
Test status
Simulation time 42388253 ps
CPU time 1.08 seconds
Started Aug 12 05:13:44 PM PDT 24
Finished Aug 12 05:13:45 PM PDT 24
Peak memory 196892 kb
Host smart-162a8f7e-e7c3-442f-9567-f99797d0b8cf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=73643242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.73643242
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.768094969
Short name T862
Test name
Test status
Simulation time 228507908 ps
CPU time 1.2 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191344 kb
Host smart-6b8ddc56-c0be-4025-9fed-a3807075429f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768094969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.768094969
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2975374152
Short name T868
Test name
Test status
Simulation time 153801872 ps
CPU time 1.14 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 191440 kb
Host smart-f646db21-29ad-4fff-b194-8103860fc1d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2975374152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2975374152
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.192461092
Short name T915
Test name
Test status
Simulation time 80419234 ps
CPU time 1.27 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191428 kb
Host smart-588ef4ca-b340-474c-a364-b93d206a5801
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192461092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.192461092
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1520692396
Short name T863
Test name
Test status
Simulation time 31544051 ps
CPU time 0.89 seconds
Started Aug 12 05:13:44 PM PDT 24
Finished Aug 12 05:13:45 PM PDT 24
Peak memory 191208 kb
Host smart-786e77c8-5b0a-4d9c-a633-4af1d871e7a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1520692396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1520692396
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3447005098
Short name T914
Test name
Test status
Simulation time 38535929 ps
CPU time 1.04 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:45 PM PDT 24
Peak memory 191344 kb
Host smart-5044e04c-216a-4123-8ba7-f758cbfd17f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447005098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3447005098
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2178652729
Short name T903
Test name
Test status
Simulation time 57331659 ps
CPU time 1.25 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191432 kb
Host smart-aa8bf735-bbf2-4dc8-be52-e060b37124f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2178652729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2178652729
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1391884265
Short name T888
Test name
Test status
Simulation time 59090042 ps
CPU time 1.18 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191312 kb
Host smart-ff2055d0-c3c8-4b69-9e38-dd59753a8f2c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391884265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1391884265
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1686616642
Short name T904
Test name
Test status
Simulation time 47190363 ps
CPU time 0.95 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191160 kb
Host smart-a5eb1d33-4f75-454e-9a99-3993fc8497da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1686616642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1686616642
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2247081598
Short name T905
Test name
Test status
Simulation time 106565592 ps
CPU time 1.13 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191352 kb
Host smart-72e8f582-39a2-4773-80ae-1d883af5237c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247081598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2247081598
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3268929628
Short name T855
Test name
Test status
Simulation time 343312084 ps
CPU time 1.3 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 190316 kb
Host smart-edbef486-ff12-42bd-803a-812efa4f1cef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3268929628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3268929628
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3858415816
Short name T879
Test name
Test status
Simulation time 78734142 ps
CPU time 1.25 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 197764 kb
Host smart-8dfb8110-472a-4956-ac53-8150a4a3dda6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858415816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3858415816
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.538104442
Short name T922
Test name
Test status
Simulation time 214851024 ps
CPU time 1.1 seconds
Started Aug 12 05:13:45 PM PDT 24
Finished Aug 12 05:13:46 PM PDT 24
Peak memory 197640 kb
Host smart-62bc81da-a783-46c9-9218-bde998b26cd8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=538104442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.538104442
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3772960784
Short name T850
Test name
Test status
Simulation time 63616305 ps
CPU time 1.21 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191412 kb
Host smart-57f71fe8-277b-4e94-9f7e-95e5b43f5b28
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772960784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3772960784
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3464630631
Short name T908
Test name
Test status
Simulation time 76229617 ps
CPU time 1.28 seconds
Started Aug 12 05:13:44 PM PDT 24
Finished Aug 12 05:13:45 PM PDT 24
Peak memory 191352 kb
Host smart-d5fcdaf8-7b55-4159-beb8-96f431b5dd47
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3464630631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3464630631
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3772144090
Short name T875
Test name
Test status
Simulation time 35192581 ps
CPU time 1.06 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:45 PM PDT 24
Peak memory 191440 kb
Host smart-c93823db-751d-4e95-855e-03dc1d640e15
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772144090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3772144090
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.65373429
Short name T933
Test name
Test status
Simulation time 40798850 ps
CPU time 1.35 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191384 kb
Host smart-3f39e490-3fd2-4dc4-957c-81dc94cd1cfb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=65373429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.65373429
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.624898471
Short name T930
Test name
Test status
Simulation time 277614079 ps
CPU time 1.16 seconds
Started Aug 12 05:13:44 PM PDT 24
Finished Aug 12 05:13:46 PM PDT 24
Peak memory 191460 kb
Host smart-cff6f7da-ab81-471e-9764-5d7076127c9c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624898471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.624898471
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.857836931
Short name T854
Test name
Test status
Simulation time 1619947551 ps
CPU time 1.36 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191440 kb
Host smart-28903d98-6ec8-4f4a-b061-4c60b5a0eeaf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=857836931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.857836931
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2693303831
Short name T853
Test name
Test status
Simulation time 106161777 ps
CPU time 1.11 seconds
Started Aug 12 05:13:47 PM PDT 24
Finished Aug 12 05:13:49 PM PDT 24
Peak memory 191472 kb
Host smart-790aad2a-2146-4044-85cb-dbbda392f2ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693303831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2693303831
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2094660425
Short name T907
Test name
Test status
Simulation time 56378890 ps
CPU time 1.2 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 197788 kb
Host smart-1350ca01-100b-45d0-8276-209bde1d1255
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2094660425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2094660425
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4044358573
Short name T932
Test name
Test status
Simulation time 31985635 ps
CPU time 1.1 seconds
Started Aug 12 05:13:44 PM PDT 24
Finished Aug 12 05:13:46 PM PDT 24
Peak memory 191420 kb
Host smart-6f5e6751-239d-4f3a-8c0f-6307822a20f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044358573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4044358573
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1579304692
Short name T929
Test name
Test status
Simulation time 77912257 ps
CPU time 0.94 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 196900 kb
Host smart-64aa8372-4a9a-4a7a-8f7b-d2e2deba5ddc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1579304692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1579304692
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1310370522
Short name T938
Test name
Test status
Simulation time 64201956 ps
CPU time 1.28 seconds
Started Aug 12 05:13:47 PM PDT 24
Finished Aug 12 05:13:48 PM PDT 24
Peak memory 196448 kb
Host smart-a0bc1e20-6f8a-48fb-8ae4-67d32c16f30a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310370522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1310370522
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2623790465
Short name T842
Test name
Test status
Simulation time 66145900 ps
CPU time 1.16 seconds
Started Aug 12 05:13:44 PM PDT 24
Finished Aug 12 05:13:46 PM PDT 24
Peak memory 196968 kb
Host smart-82e7af01-30db-429c-8abe-f6b123f3af52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2623790465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2623790465
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.594450009
Short name T939
Test name
Test status
Simulation time 56726264 ps
CPU time 1.02 seconds
Started Aug 12 05:13:47 PM PDT 24
Finished Aug 12 05:13:48 PM PDT 24
Peak memory 191464 kb
Host smart-c31885c5-41c0-442a-bc1d-5a49b128b3f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594450009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.594450009
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1849531666
Short name T906
Test name
Test status
Simulation time 59805886 ps
CPU time 1.08 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 191484 kb
Host smart-12926ae0-6e27-4d98-a244-25db4afb82aa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1849531666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1849531666
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.273358260
Short name T880
Test name
Test status
Simulation time 159483402 ps
CPU time 0.95 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 196804 kb
Host smart-6e97f314-c240-4d83-9d76-28b059b0f32f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273358260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.273358260
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2980396340
Short name T872
Test name
Test status
Simulation time 240884889 ps
CPU time 1.3 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191504 kb
Host smart-54ec391a-5d14-4983-86ed-7256775ccffb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2980396340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2980396340
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.382527136
Short name T866
Test name
Test status
Simulation time 26491131 ps
CPU time 0.92 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191104 kb
Host smart-00293c2b-446a-48e9-b16a-f42735897730
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382527136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.382527136
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2787209204
Short name T937
Test name
Test status
Simulation time 105416151 ps
CPU time 0.9 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 196956 kb
Host smart-f7418936-6797-4800-896d-fafa024c7c7f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2787209204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2787209204
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1532688445
Short name T926
Test name
Test status
Simulation time 118357348 ps
CPU time 1.17 seconds
Started Aug 12 05:13:47 PM PDT 24
Finished Aug 12 05:13:48 PM PDT 24
Peak memory 191448 kb
Host smart-fbff3ab8-68b2-408f-949f-0b0570081961
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532688445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1532688445
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2418253055
Short name T864
Test name
Test status
Simulation time 53749707 ps
CPU time 1.42 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:44 PM PDT 24
Peak memory 191360 kb
Host smart-a20666ff-406b-4ba5-ba74-fbc784bb4d2c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2418253055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2418253055
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4250042366
Short name T885
Test name
Test status
Simulation time 36385448 ps
CPU time 1.12 seconds
Started Aug 12 05:13:47 PM PDT 24
Finished Aug 12 05:13:48 PM PDT 24
Peak memory 191408 kb
Host smart-bdf02fba-592d-4504-903d-0cd11ae38dd5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250042366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4250042366
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.735762378
Short name T901
Test name
Test status
Simulation time 78713017 ps
CPU time 1.03 seconds
Started Aug 12 05:13:46 PM PDT 24
Finished Aug 12 05:13:48 PM PDT 24
Peak memory 191416 kb
Host smart-15a21143-9499-4b36-bfc6-575b05c70e82
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=735762378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.735762378
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2860471481
Short name T876
Test name
Test status
Simulation time 158892222 ps
CPU time 1.1 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191412 kb
Host smart-3c4a0e3a-ba7c-4a90-99cd-15170be85285
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860471481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2860471481
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.713424310
Short name T902
Test name
Test status
Simulation time 47805564 ps
CPU time 0.97 seconds
Started Aug 12 05:13:47 PM PDT 24
Finished Aug 12 05:13:48 PM PDT 24
Peak memory 191464 kb
Host smart-6f15e5cd-c072-4f1f-8386-935a3b5f809e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=713424310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.713424310
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3076996758
Short name T859
Test name
Test status
Simulation time 290644743 ps
CPU time 1.56 seconds
Started Aug 12 05:13:43 PM PDT 24
Finished Aug 12 05:13:45 PM PDT 24
Peak memory 191356 kb
Host smart-94266fd5-b0d5-4255-9c7f-bc988d218b42
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076996758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3076996758
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.921954850
Short name T871
Test name
Test status
Simulation time 93606102 ps
CPU time 0.97 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191412 kb
Host smart-e9633670-6162-4873-a487-53a7f10220fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=921954850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.921954850
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2891493171
Short name T858
Test name
Test status
Simulation time 83865931 ps
CPU time 1.33 seconds
Started Aug 12 05:13:44 PM PDT 24
Finished Aug 12 05:13:46 PM PDT 24
Peak memory 197816 kb
Host smart-0b975cde-b314-446e-8b5c-288316355656
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891493171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2891493171
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3142669036
Short name T940
Test name
Test status
Simulation time 116600263 ps
CPU time 1.01 seconds
Started Aug 12 05:13:49 PM PDT 24
Finished Aug 12 05:13:50 PM PDT 24
Peak memory 191392 kb
Host smart-ed7ae2a7-872f-4832-9a0c-6db987018b20
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3142669036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3142669036
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1341328283
Short name T847
Test name
Test status
Simulation time 30560808 ps
CPU time 0.79 seconds
Started Aug 12 05:13:47 PM PDT 24
Finished Aug 12 05:13:48 PM PDT 24
Peak memory 191240 kb
Host smart-ff1c7bad-969d-47c0-b8cf-8ae554bd0269
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341328283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1341328283
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2185985467
Short name T920
Test name
Test status
Simulation time 67023515 ps
CPU time 1.15 seconds
Started Aug 12 05:13:50 PM PDT 24
Finished Aug 12 05:13:52 PM PDT 24
Peak memory 191448 kb
Host smart-9c1e7ea5-ff29-4542-a373-0155967ad477
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2185985467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2185985467
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3305087950
Short name T883
Test name
Test status
Simulation time 25405460 ps
CPU time 0.77 seconds
Started Aug 12 05:13:51 PM PDT 24
Finished Aug 12 05:13:52 PM PDT 24
Peak memory 191228 kb
Host smart-198649a3-6070-447f-92df-990df8544aab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305087950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3305087950
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2998780857
Short name T882
Test name
Test status
Simulation time 91856954 ps
CPU time 0.84 seconds
Started Aug 12 05:13:50 PM PDT 24
Finished Aug 12 05:13:50 PM PDT 24
Peak memory 191240 kb
Host smart-ebbaa514-d398-477c-886c-4cefa441b0e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2998780857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2998780857
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2598321162
Short name T877
Test name
Test status
Simulation time 49554250 ps
CPU time 0.98 seconds
Started Aug 12 05:13:51 PM PDT 24
Finished Aug 12 05:13:52 PM PDT 24
Peak memory 191164 kb
Host smart-b35cb5be-16f2-4745-96d7-ec86e42af729
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598321162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2598321162
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4243165617
Short name T896
Test name
Test status
Simulation time 107144895 ps
CPU time 0.96 seconds
Started Aug 12 05:13:50 PM PDT 24
Finished Aug 12 05:13:52 PM PDT 24
Peak memory 197216 kb
Host smart-4cc9324e-63db-4e0d-a799-b0ebcafd0b45
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4243165617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.4243165617
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3908835214
Short name T843
Test name
Test status
Simulation time 57520932 ps
CPU time 1.07 seconds
Started Aug 12 05:13:47 PM PDT 24
Finished Aug 12 05:13:48 PM PDT 24
Peak memory 196952 kb
Host smart-df4c40e5-ea17-49fc-95e7-1492d7361d13
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908835214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3908835214
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1134381961
Short name T928
Test name
Test status
Simulation time 89277708 ps
CPU time 0.92 seconds
Started Aug 12 05:13:49 PM PDT 24
Finished Aug 12 05:13:50 PM PDT 24
Peak memory 196168 kb
Host smart-7cbfde7f-c2bb-43c1-94f9-482bcbbc004f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1134381961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1134381961
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2684037794
Short name T874
Test name
Test status
Simulation time 143859895 ps
CPU time 1.05 seconds
Started Aug 12 05:13:48 PM PDT 24
Finished Aug 12 05:13:49 PM PDT 24
Peak memory 197104 kb
Host smart-044de81d-60ce-4e26-ba0f-e258e542cdbf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684037794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2684037794
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1406986482
Short name T841
Test name
Test status
Simulation time 93449978 ps
CPU time 1.11 seconds
Started Aug 12 05:13:38 PM PDT 24
Finished Aug 12 05:13:39 PM PDT 24
Peak memory 197252 kb
Host smart-a9b19941-2602-41c8-bde8-ee061fc07f56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1406986482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1406986482
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.397935178
Short name T909
Test name
Test status
Simulation time 42765240 ps
CPU time 1.13 seconds
Started Aug 12 05:13:39 PM PDT 24
Finished Aug 12 05:13:40 PM PDT 24
Peak memory 191432 kb
Host smart-b8db6ae6-de3c-4bf7-b717-e85420d365fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397935178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.397935178
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3306983777
Short name T887
Test name
Test status
Simulation time 157951897 ps
CPU time 1.64 seconds
Started Aug 12 05:13:38 PM PDT 24
Finished Aug 12 05:13:40 PM PDT 24
Peak memory 197732 kb
Host smart-8f965105-1c2d-4963-a71c-0f5f4fdcd1ee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3306983777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3306983777
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2584822270
Short name T923
Test name
Test status
Simulation time 68921098 ps
CPU time 1.42 seconds
Started Aug 12 05:13:40 PM PDT 24
Finished Aug 12 05:13:41 PM PDT 24
Peak memory 191504 kb
Host smart-346f1e4e-9bd5-4b7a-8b16-35965b4a88f7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584822270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2584822270
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2465162159
Short name T867
Test name
Test status
Simulation time 52477754 ps
CPU time 1.01 seconds
Started Aug 12 05:13:42 PM PDT 24
Finished Aug 12 05:13:43 PM PDT 24
Peak memory 191272 kb
Host smart-66c99d3d-1e67-4abf-a37e-493745b7a21e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2465162159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2465162159
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4265740728
Short name T912
Test name
Test status
Simulation time 90695623 ps
CPU time 1.24 seconds
Started Aug 12 05:13:38 PM PDT 24
Finished Aug 12 05:13:40 PM PDT 24
Peak memory 191368 kb
Host smart-1836db0e-aebf-4745-b89d-c0931754f790
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265740728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4265740728
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.56055924
Short name T889
Test name
Test status
Simulation time 61756727 ps
CPU time 0.92 seconds
Started Aug 12 05:13:41 PM PDT 24
Finished Aug 12 05:13:42 PM PDT 24
Peak memory 191216 kb
Host smart-7b98a4f0-0d23-443b-a391-9ed7ea66b018
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=56055924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.56055924
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3809291456
Short name T878
Test name
Test status
Simulation time 145540042 ps
CPU time 0.98 seconds
Started Aug 12 05:13:39 PM PDT 24
Finished Aug 12 05:13:40 PM PDT 24
Peak memory 197084 kb
Host smart-23999125-5775-4dd8-bd0a-2b4e4f32afcf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809291456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3809291456
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3930304855
Short name T898
Test name
Test status
Simulation time 144069457 ps
CPU time 1.09 seconds
Started Aug 12 05:13:40 PM PDT 24
Finished Aug 12 05:13:41 PM PDT 24
Peak memory 191372 kb
Host smart-96b0e61f-83ba-42a3-a86e-76de3b14d21d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3930304855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3930304855
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2498937412
Short name T857
Test name
Test status
Simulation time 103378727 ps
CPU time 1.36 seconds
Started Aug 12 05:13:37 PM PDT 24
Finished Aug 12 05:13:38 PM PDT 24
Peak memory 197744 kb
Host smart-c46040d5-a224-4079-97c2-afefafff9be9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498937412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2498937412
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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