Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6086013	1			T34	1		T35	306		T36	1
all_values[1]	6086013	1			T34	1		T35	306		T36	1
all_values[2]	6086013	1			T34	1		T35	306		T36	1
all_values[3]	6086013	1			T34	1		T35	306		T36	1
all_values[4]	6086013	1			T34	1		T35	306		T36	1
all_values[5]	6086013	1			T34	1		T35	306		T36	1
all_values[6]	6086013	1			T34	1		T35	306		T36	1
all_values[7]	6086013	1			T34	1		T35	306		T36	1
all_values[8]	6086013	1			T34	1		T35	306		T36	1
all_values[9]	6086013	1			T34	1		T35	306		T36	1
all_values[10]	6086013	1			T34	1		T35	306		T36	1
all_values[11]	6086013	1			T34	1		T35	306		T36	1
all_values[12]	6086013	1			T34	1		T35	306		T36	1
all_values[13]	6086013	1			T34	1		T35	306		T36	1
all_values[14]	6086013	1			T34	1		T35	306		T36	1
all_values[15]	6086013	1			T34	1		T35	306		T36	1
all_values[16]	6086013	1			T34	1		T35	306		T36	1
all_values[17]	6086013	1			T34	1		T35	306		T36	1
all_values[18]	6086013	1			T34	1		T35	306		T36	1
all_values[19]	6086013	1			T34	1		T35	306		T36	1
all_values[20]	6086013	1			T34	1		T35	306		T36	1
all_values[21]	6086013	1			T34	1		T35	306		T36	1
all_values[22]	6086013	1			T34	1		T35	306		T36	1
all_values[23]	6086013	1			T34	1		T35	306		T36	1
all_values[24]	6086013	1			T34	1		T35	306		T36	1
all_values[25]	6086013	1			T34	1		T35	306		T36	1
all_values[26]	6086013	1			T34	1		T35	306		T36	1
all_values[27]	6086013	1			T34	1		T35	306		T36	1
all_values[28]	6086013	1			T34	1		T35	306		T36	1
all_values[29]	6086013	1			T34	1		T35	306		T36	1
all_values[30]	6086013	1			T34	1		T35	306		T36	1
all_values[31]	6086013	1			T34	1		T35	306		T36	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130083557

1

T34

32

T35

9792

T36

32

auto[1]

64668859

1

T38

3146

T39

2854

T41

990

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78123235

1

T34

32

T35

9792

T36

32

auto[1]

116629181

1

T38

5383

T39

5590

T41

1480

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2234914	1			T34	1		T35	306		T36	1
all_values[0]	auto[0]	auto[1]	1827311	1			T38	77		T39	70		T41	13
all_values[0]	auto[1]	auto[0]	200757	1			T38	7		T39	11		T41	22
all_values[0]	auto[1]	auto[1]	1823031	1			T38	106		T39	113		T41	17
all_values[1]	auto[0]	auto[0]	2237231	1			T34	1		T35	306		T36	1
all_values[1]	auto[0]	auto[1]	1844205	1			T38	86		T39	124		T41	12
all_values[1]	auto[1]	auto[0]	199221	1			T38	37		T39	3		T41	4
all_values[1]	auto[1]	auto[1]	1805356	1			T38	68		T39	57		T41	33
all_values[2]	auto[0]	auto[0]	2240449	1			T34	1		T35	306		T36	1
all_values[2]	auto[0]	auto[1]	1827693	1			T38	41		T39	112		T41	29
all_values[2]	auto[1]	auto[0]	199353	1			T38	28		T39	5		T41	3
all_values[2]	auto[1]	auto[1]	1818518	1			T38	122		T39	68		T41	17
all_values[3]	auto[0]	auto[0]	2237849	1			T34	1		T35	306		T36	1
all_values[3]	auto[0]	auto[1]	1829233	1			T38	71		T39	90		T41	34
all_values[3]	auto[1]	auto[0]	204725	1			T38	23		T39	16		T41	3
all_values[3]	auto[1]	auto[1]	1814206	1			T38	77		T39	86		T41	21
all_values[4]	auto[0]	auto[0]	2240035	1			T34	1		T35	306		T36	1
all_values[4]	auto[0]	auto[1]	1821893	1			T38	69		T39	96		T41	34
all_values[4]	auto[1]	auto[0]	203190	1			T38	11		T39	13		T42	4
all_values[4]	auto[1]	auto[1]	1820895	1			T38	102		T39	81		T41	12
all_values[5]	auto[0]	auto[0]	2240071	1			T34	1		T35	306		T36	1
all_values[5]	auto[0]	auto[1]	1835308	1			T38	88		T39	82		T41	27
all_values[5]	auto[1]	auto[0]	196808	1			T38	9		T39	9		T41	9
all_values[5]	auto[1]	auto[1]	1813826	1			T38	86		T39	101		T41	27
all_values[6]	auto[0]	auto[0]	2240329	1			T34	1		T35	306		T36	1
all_values[6]	auto[0]	auto[1]	1832818	1			T38	85		T39	67		T41	9
all_values[6]	auto[1]	auto[0]	202886	1			T38	12		T39	9		T41	12
all_values[6]	auto[1]	auto[1]	1809980	1			T38	84		T39	116		T41	36
all_values[7]	auto[0]	auto[0]	2239748	1			T34	1		T35	306		T36	1
all_values[7]	auto[0]	auto[1]	1818549	1			T38	52		T39	47		T41	12
all_values[7]	auto[1]	auto[0]	202082	1			T38	18		T39	5		T41	9
all_values[7]	auto[1]	auto[1]	1825634	1			T38	114		T39	146		T41	39
all_values[8]	auto[0]	auto[0]	2239491	1			T34	1		T35	306		T36	1
all_values[8]	auto[0]	auto[1]	1834950	1			T38	105		T39	98		T41	27
all_values[8]	auto[1]	auto[0]	198341	1			T39	1		T41	9		T44	5370
all_values[8]	auto[1]	auto[1]	1813231	1			T38	54		T39	82		T41	22
all_values[9]	auto[0]	auto[0]	2236415	1			T34	1		T35	306		T36	1
all_values[9]	auto[0]	auto[1]	1814715	1			T38	114		T39	129		T41	29
all_values[9]	auto[1]	auto[0]	205488	1			T38	8		T39	2		T41	1
all_values[9]	auto[1]	auto[1]	1829395	1			T38	60		T39	47		T41	18
all_values[10]	auto[0]	auto[0]	2236357	1			T34	1		T35	306		T36	1
all_values[10]	auto[0]	auto[1]	1830930	1			T38	84		T39	97		T41	29
all_values[10]	auto[1]	auto[0]	197099	1			T38	22		T39	10		T41	7
all_values[10]	auto[1]	auto[1]	1821627	1			T38	90		T39	74		T41	18
all_values[11]	auto[0]	auto[0]	2238629	1			T34	1		T35	306		T36	1
all_values[11]	auto[0]	auto[1]	1837321	1			T38	113		T39	75		T41	31
all_values[11]	auto[1]	auto[0]	202897	1			T38	14		T39	18		T41	3
all_values[11]	auto[1]	auto[1]	1807166	1			T38	56		T39	81		T41	26
all_values[12]	auto[0]	auto[0]	2240508	1			T34	1		T35	306		T36	1
all_values[12]	auto[0]	auto[1]	1833875	1			T38	101		T39	150		T41	25
all_values[12]	auto[1]	auto[0]	204840	1			T38	5		T39	14		T41	8
all_values[12]	auto[1]	auto[1]	1806790	1			T38	84		T39	24		T41	13
all_values[13]	auto[0]	auto[0]	2239554	1			T34	1		T35	306		T36	1
all_values[13]	auto[0]	auto[1]	1833814	1			T38	62		T39	52		T41	29
all_values[13]	auto[1]	auto[0]	203645	1			T38	18		T39	16		T41	16
all_values[13]	auto[1]	auto[1]	1809000	1			T38	107		T39	107		T41	15
all_values[14]	auto[0]	auto[0]	2241600	1			T34	1		T35	306		T36	1
all_values[14]	auto[0]	auto[1]	1821676	1			T38	81		T39	115		T41	17
all_values[14]	auto[1]	auto[0]	202278	1			T38	8		T39	8		T41	3
all_values[14]	auto[1]	auto[1]	1820459	1			T38	96		T39	75		T41	33
all_values[15]	auto[0]	auto[0]	2237479	1			T34	1		T35	306		T36	1
all_values[15]	auto[0]	auto[1]	1823898	1			T38	50		T39	101		T41	8
all_values[15]	auto[1]	auto[0]	203221	1			T38	18		T39	29		T41	12
all_values[15]	auto[1]	auto[1]	1821415	1			T38	115		T39	57		T41	25
all_values[16]	auto[0]	auto[0]	2242663	1			T34	1		T35	306		T36	1
all_values[16]	auto[0]	auto[1]	1813641	1			T38	102		T39	90		T41	30
all_values[16]	auto[1]	auto[0]	205230	1			T38	13		T39	12		T42	8
all_values[16]	auto[1]	auto[1]	1824479	1			T38	74		T39	78		T41	29
all_values[17]	auto[0]	auto[0]	2240727	1			T34	1		T35	306		T36	1
all_values[17]	auto[0]	auto[1]	1812709	1			T38	78		T39	95		T41	30
all_values[17]	auto[1]	auto[0]	201417	1			T38	13		T39	6		T41	4
all_values[17]	auto[1]	auto[1]	1831160	1			T38	106		T39	74		T41	17
all_values[18]	auto[0]	auto[0]	2234924	1			T34	1		T35	306		T36	1
all_values[18]	auto[0]	auto[1]	1814798	1			T38	101		T39	131		T41	17
all_values[18]	auto[1]	auto[0]	204293	1			T38	8		T39	14		T41	8
all_values[18]	auto[1]	auto[1]	1831998	1			T38	51		T39	43		T41	26
all_values[19]	auto[0]	auto[0]	2243769	1			T34	1		T35	306		T36	1
all_values[19]	auto[0]	auto[1]	1830242	1			T38	61		T39	99		T41	27
all_values[19]	auto[1]	auto[0]	200684	1			T38	26		T39	9		T41	14
all_values[19]	auto[1]	auto[1]	1811318	1			T38	93		T39	73		T41	21
all_values[20]	auto[0]	auto[0]	2239974	1			T34	1		T35	306		T36	1
all_values[20]	auto[0]	auto[1]	1825044	1			T38	90		T39	92		T41	32
all_values[20]	auto[1]	auto[0]	206140	1			T38	18		T39	5		T41	7
all_values[20]	auto[1]	auto[1]	1814855	1			T38	84		T39	86		T41	8
all_values[21]	auto[0]	auto[0]	2239031	1			T34	1		T35	306		T36	1
all_values[21]	auto[0]	auto[1]	1818987	1			T38	83		T39	95		T41	34
all_values[21]	auto[1]	auto[0]	205004	1			T38	18		T39	3		T41	4
all_values[21]	auto[1]	auto[1]	1822991	1			T38	87		T39	99		T41	20
all_values[22]	auto[0]	auto[0]	2243292	1			T34	1		T35	306		T36	1
all_values[22]	auto[0]	auto[1]	1825483	1			T38	79		T39	98		T41	27
all_values[22]	auto[1]	auto[0]	199504	1			T38	19		T39	6		T42	3
all_values[22]	auto[1]	auto[1]	1817734	1			T38	87		T39	76		T41	28
all_values[23]	auto[0]	auto[0]	2242311	1			T34	1		T35	306		T36	1
all_values[23]	auto[0]	auto[1]	1832639	1			T38	89		T39	101		T41	17
all_values[23]	auto[1]	auto[0]	200911	1			T38	18		T39	2		T41	8
all_values[23]	auto[1]	auto[1]	1810152	1			T38	78		T39	61		T41	20
all_values[24]	auto[0]	auto[0]	2241150	1			T34	1		T35	306		T36	1
all_values[24]	auto[0]	auto[1]	1813484	1			T38	108		T39	58		T41	17
all_values[24]	auto[1]	auto[0]	200216	1			T39	10		T41	2		T42	9
all_values[24]	auto[1]	auto[1]	1831163	1			T38	81		T39	112		T41	41
all_values[25]	auto[0]	auto[0]	2237893	1			T34	1		T35	306		T36	1
all_values[25]	auto[0]	auto[1]	1837796	1			T38	110		T39	88		T41	38
all_values[25]	auto[1]	auto[0]	202561	1			T38	21		T39	14		T41	9
all_values[25]	auto[1]	auto[1]	1807763	1			T38	49		T39	86		T41	13
all_values[26]	auto[0]	auto[0]	2235439	1			T34	1		T35	306		T36	1
all_values[26]	auto[0]	auto[1]	1820983	1			T38	81		T39	77		T41	15
all_values[26]	auto[1]	auto[0]	202959	1			T38	25		T39	14		T41	28
all_values[26]	auto[1]	auto[1]	1826632	1			T38	79		T39	98		T41	19
all_values[27]	auto[0]	auto[0]	2238126	1			T34	1		T35	306		T36	1
all_values[27]	auto[0]	auto[1]	1821893	1			T38	118		T39	98		T41	17
all_values[27]	auto[1]	auto[0]	202679	1			T38	12		T39	6		T41	3
all_values[27]	auto[1]	auto[1]	1823315	1			T38	55		T39	81		T41	39
all_values[28]	auto[0]	auto[0]	2238433	1			T34	1		T35	306		T36	1
all_values[28]	auto[0]	auto[1]	1820296	1			T38	81		T39	114		T41	10
all_values[28]	auto[1]	auto[0]	202193	1			T38	12		T41	18		T42	5
all_values[28]	auto[1]	auto[1]	1825091	1			T38	84		T39	58		T41	34
all_values[29]	auto[0]	auto[0]	2240508	1			T34	1		T35	306		T36	1
all_values[29]	auto[0]	auto[1]	1835648	1			T38	71		T39	94		T41	23
all_values[29]	auto[1]	auto[0]	201042	1			T38	19		T39	20		T41	9
all_values[29]	auto[1]	auto[1]	1808815	1			T38	81		T39	77		T41	20
all_values[30]	auto[0]	auto[0]	2239973	1			T34	1		T35	306		T36	1
all_values[30]	auto[0]	auto[1]	1814170	1			T38	81		T39	101		T41	32
all_values[30]	auto[1]	auto[0]	207033	1			T38	12		T39	8		T41	19
all_values[30]	auto[1]	auto[1]	1824837	1			T38	91		T39	55		T41	2
all_values[31]	auto[0]	auto[0]	2236636	1			T34	1		T35	306		T36	1
all_values[31]	auto[0]	auto[1]	1822047	1			T38	111		T39	104		T41	28
all_values[31]	auto[1]	auto[0]	199030	1			T38	14		T39	6		T41	15
all_values[31]	auto[1]	auto[1]	1828300	1			T38	59		T39	78		T41	12