Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1474972	1			T34	1		T35	28		T36	1
all_pins[1]	1474972	1			T34	1		T35	28		T36	1
all_pins[2]	1474972	1			T34	1		T35	28		T36	1
all_pins[3]	1474972	1			T34	1		T35	28		T36	1
all_pins[4]	1474972	1			T34	1		T35	28		T36	1
all_pins[5]	1474972	1			T34	1		T35	28		T36	1
all_pins[6]	1474972	1			T34	1		T35	28		T36	1
all_pins[7]	1474972	1			T34	1		T35	28		T36	1
all_pins[8]	1474972	1			T34	1		T35	28		T36	1
all_pins[9]	1474972	1			T34	1		T35	28		T36	1
all_pins[10]	1474972	1			T34	1		T35	28		T36	1
all_pins[11]	1474972	1			T34	1		T35	28		T36	1
all_pins[12]	1474972	1			T34	1		T35	28		T36	1
all_pins[13]	1474972	1			T34	1		T35	28		T36	1
all_pins[14]	1474972	1			T34	1		T35	28		T36	1
all_pins[15]	1474972	1			T34	1		T35	28		T36	1
all_pins[16]	1474972	1			T34	1		T35	28		T36	1
all_pins[17]	1474972	1			T34	1		T35	28		T36	1
all_pins[18]	1474972	1			T34	1		T35	28		T36	1
all_pins[19]	1474972	1			T34	1		T35	28		T36	1
all_pins[20]	1474972	1			T34	1		T35	28		T36	1
all_pins[21]	1474972	1			T34	1		T35	28		T36	1
all_pins[22]	1474972	1			T34	1		T35	28		T36	1
all_pins[23]	1474972	1			T34	1		T35	28		T36	1
all_pins[24]	1474972	1			T34	1		T35	28		T36	1
all_pins[25]	1474972	1			T34	1		T35	28		T36	1
all_pins[26]	1474972	1			T34	1		T35	28		T36	1
all_pins[27]	1474972	1			T34	1		T35	28		T36	1
all_pins[28]	1474972	1			T34	1		T35	28		T36	1
all_pins[29]	1474972	1			T34	1		T35	28		T36	1
all_pins[30]	1474972	1			T34	1		T35	28		T36	1
all_pins[31]	1474972	1			T34	1		T35	28		T36	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	29334751	1			T34	32		T35	525		T36	32
values[0x1]	17864353	1			T35	371		T38	1280		T39	1263
transitions[0x0=>0x1]	10691464	1			T35	197		T38	828		T39	706
transitions[0x1=>0x0]	10691327	1			T35	197		T38	828		T39	706

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	914612	1			T34	1		T35	18		T36	1
all_pins[0]	values[0x1]	560360	1			T35	10		T38	42		T39	55
all_pins[0]	transitions[0x0=>0x1]	346651	1			T35	3		T38	36		T39	34
all_pins[0]	transitions[0x1=>0x0]	348195	1			T35	6		T38	21		T39	25
all_pins[1]	values[0x0]	920286	1			T34	1		T35	13		T36	1
all_pins[1]	values[0x1]	554686	1			T35	15		T38	30		T39	30
all_pins[1]	transitions[0x0=>0x1]	331160	1			T35	12		T38	15		T39	3
all_pins[1]	transitions[0x1=>0x0]	336834	1			T35	7		T38	27		T39	28
all_pins[2]	values[0x0]	918727	1			T34	1		T35	11		T36	1
all_pins[2]	values[0x1]	556245	1			T35	17		T38	57		T39	26
all_pins[2]	transitions[0x0=>0x1]	333392	1			T35	11		T38	42		T39	21
all_pins[2]	transitions[0x1=>0x0]	331833	1			T35	9		T38	15		T39	25
all_pins[3]	values[0x0]	916108	1			T34	1		T35	21		T36	1
all_pins[3]	values[0x1]	558864	1			T35	7		T38	40		T39	53
all_pins[3]	transitions[0x0=>0x1]	334965	1			T35	2		T38	19		T39	50
all_pins[3]	transitions[0x1=>0x0]	332346	1			T35	12		T38	36		T39	23
all_pins[4]	values[0x0]	919190	1			T34	1		T35	20		T36	1
all_pins[4]	values[0x1]	555782	1			T35	8		T38	51		T39	48
all_pins[4]	transitions[0x0=>0x1]	333282	1			T35	5		T38	46		T39	19
all_pins[4]	transitions[0x1=>0x0]	336364	1			T35	4		T38	35		T39	24
all_pins[5]	values[0x0]	916093	1			T34	1		T35	19		T36	1
all_pins[5]	values[0x1]	558879	1			T35	9		T38	49		T39	45
all_pins[5]	transitions[0x0=>0x1]	333192	1			T35	5		T38	34		T39	21
all_pins[5]	transitions[0x1=>0x0]	330095	1			T35	4		T38	36		T39	24
all_pins[6]	values[0x0]	919574	1			T34	1		T35	23		T36	1
all_pins[6]	values[0x1]	555398	1			T35	5		T38	42		T39	57
all_pins[6]	transitions[0x0=>0x1]	332031	1			T35	3		T38	12		T39	26
all_pins[6]	transitions[0x1=>0x0]	335512	1			T35	7		T38	19		T39	14
all_pins[7]	values[0x0]	918516	1			T34	1		T35	16		T36	1
all_pins[7]	values[0x1]	556456	1			T35	12		T38	53		T39	77
all_pins[7]	transitions[0x0=>0x1]	332771	1			T35	9		T38	34		T39	32
all_pins[7]	transitions[0x1=>0x0]	331713	1			T35	2		T38	23		T39	12
all_pins[8]	values[0x0]	920625	1			T34	1		T35	18		T36	1
all_pins[8]	values[0x1]	554347	1			T35	10		T38	26		T39	42
all_pins[8]	transitions[0x0=>0x1]	331818	1			T35	3		T38	9		T39	9
all_pins[8]	transitions[0x1=>0x0]	333927	1			T35	5		T38	36		T39	44
all_pins[9]	values[0x0]	915218	1			T34	1		T35	15		T36	1
all_pins[9]	values[0x1]	559754	1			T35	13		T38	39		T39	22
all_pins[9]	transitions[0x0=>0x1]	336674	1			T35	9		T38	35		T39	9
all_pins[9]	transitions[0x1=>0x0]	331267	1			T35	6		T38	22		T39	29
all_pins[10]	values[0x0]	915550	1			T34	1		T35	13		T36	1
all_pins[10]	values[0x1]	559422	1			T35	15		T38	43		T39	31
all_pins[10]	transitions[0x0=>0x1]	333743	1			T35	7		T38	23		T39	30
all_pins[10]	transitions[0x1=>0x0]	334075	1			T35	5		T38	19		T39	21
all_pins[11]	values[0x0]	916962	1			T34	1		T35	7		T36	1
all_pins[11]	values[0x1]	558010	1			T35	21		T38	29		T39	35
all_pins[11]	transitions[0x0=>0x1]	333061	1			T35	7		T38	21		T39	14
all_pins[11]	transitions[0x1=>0x0]	334473	1			T35	1		T38	35		T39	10
all_pins[12]	values[0x0]	915693	1			T34	1		T35	16		T36	1
all_pins[12]	values[0x1]	559279	1			T35	12		T38	53		T39	14
all_pins[12]	transitions[0x0=>0x1]	335178	1			T38	30		T39	10		T40	8
all_pins[12]	transitions[0x1=>0x0]	333909	1			T35	9		T38	6		T39	31
all_pins[13]	values[0x0]	915740	1			T34	1		T35	19		T36	1
all_pins[13]	values[0x1]	559232	1			T35	9		T38	47		T39	54
all_pins[13]	transitions[0x0=>0x1]	334084	1			T35	5		T38	31		T39	47
all_pins[13]	transitions[0x1=>0x0]	334131	1			T35	8		T38	37		T39	7
all_pins[14]	values[0x0]	913912	1			T34	1		T35	20		T36	1
all_pins[14]	values[0x1]	561060	1			T35	8		T38	41		T39	39
all_pins[14]	transitions[0x0=>0x1]	333904	1			T35	5		T38	13		T39	11
all_pins[14]	transitions[0x1=>0x0]	332076	1			T35	6		T38	19		T39	26
all_pins[15]	values[0x0]	916289	1			T34	1		T35	17		T36	1
all_pins[15]	values[0x1]	558683	1			T35	11		T38	44		T39	30
all_pins[15]	transitions[0x0=>0x1]	332338	1			T35	8		T38	28		T39	17
all_pins[15]	transitions[0x1=>0x0]	334715	1			T35	5		T38	25		T39	26
all_pins[16]	values[0x0]	914798	1			T34	1		T35	19		T36	1
all_pins[16]	values[0x1]	560174	1			T35	9		T38	31		T39	42
all_pins[16]	transitions[0x0=>0x1]	333780	1			T35	4		T38	16		T39	21
all_pins[16]	transitions[0x1=>0x0]	332289	1			T35	6		T38	29		T39	9
all_pins[17]	values[0x0]	913749	1			T34	1		T35	11		T36	1
all_pins[17]	values[0x1]	561223	1			T35	17		T38	53		T39	31
all_pins[17]	transitions[0x0=>0x1]	333910	1			T35	10		T38	32		T39	12
all_pins[17]	transitions[0x1=>0x0]	332861	1			T35	2		T38	10		T39	23
all_pins[18]	values[0x0]	913573	1			T34	1		T35	13		T36	1
all_pins[18]	values[0x1]	561399	1			T35	15		T38	26		T39	26
all_pins[18]	transitions[0x0=>0x1]	333483	1			T35	3		T38	18		T39	19
all_pins[18]	transitions[0x1=>0x0]	333307	1			T35	5		T38	45		T39	24
all_pins[19]	values[0x0]	919912	1			T34	1		T35	14		T36	1
all_pins[19]	values[0x1]	555060	1			T35	14		T38	46		T39	39
all_pins[19]	transitions[0x0=>0x1]	331293	1			T35	7		T38	35		T39	27
all_pins[19]	transitions[0x1=>0x0]	337632	1			T35	8		T38	15		T39	14
all_pins[20]	values[0x0]	918308	1			T34	1		T35	22		T36	1
all_pins[20]	values[0x1]	556664	1			T35	6		T38	52		T39	42
all_pins[20]	transitions[0x0=>0x1]	334512	1			T35	2		T38	27		T39	28
all_pins[20]	transitions[0x1=>0x0]	332908	1			T35	10		T38	21		T39	25
all_pins[21]	values[0x0]	918310	1			T34	1		T35	15		T36	1
all_pins[21]	values[0x1]	556662	1			T35	13		T38	40		T39	54
all_pins[21]	transitions[0x0=>0x1]	333609	1			T35	11		T38	26		T39	20
all_pins[21]	transitions[0x1=>0x0]	333611	1			T35	4		T38	38		T39	8
all_pins[22]	values[0x0]	918242	1			T34	1		T35	19		T36	1
all_pins[22]	values[0x1]	556730	1			T35	9		T38	35		T39	37
all_pins[22]	transitions[0x0=>0x1]	333890	1			T35	1		T38	25		T39	13
all_pins[22]	transitions[0x1=>0x0]	333822	1			T35	5		T38	30		T39	30
all_pins[23]	values[0x0]	919235	1			T34	1		T35	13		T36	1
all_pins[23]	values[0x1]	555737	1			T35	15		T38	44		T39	28
all_pins[23]	transitions[0x0=>0x1]	331676	1			T35	12		T38	34		T39	23
all_pins[23]	transitions[0x1=>0x0]	332669	1			T35	6		T38	25		T39	32
all_pins[24]	values[0x0]	913605	1			T34	1		T35	20		T36	1
all_pins[24]	values[0x1]	561367	1			T35	8		T38	44		T39	44
all_pins[24]	transitions[0x0=>0x1]	337484	1			T35	4		T38	20		T39	23
all_pins[24]	transitions[0x1=>0x0]	331854	1			T35	11		T38	20		T39	7
all_pins[25]	values[0x0]	919537	1			T34	1		T35	12		T36	1
all_pins[25]	values[0x1]	555435	1			T35	16		T38	26		T39	41
all_pins[25]	transitions[0x0=>0x1]	331029	1			T35	11		T38	15		T39	20
all_pins[25]	transitions[0x1=>0x0]	336961	1			T35	3		T38	33		T39	23
all_pins[26]	values[0x0]	914235	1			T34	1		T35	21		T36	1
all_pins[26]	values[0x1]	560737	1			T35	7		T38	38		T39	44
all_pins[26]	transitions[0x0=>0x1]	337508	1			T35	3		T38	24		T39	28
all_pins[26]	transitions[0x1=>0x0]	332206	1			T35	12		T38	12		T39	25
all_pins[27]	values[0x0]	916912	1			T34	1		T35	13		T36	1
all_pins[27]	values[0x1]	558060	1			T35	15		T38	19		T39	39
all_pins[27]	transitions[0x0=>0x1]	332738	1			T35	13		T38	11		T39	25
all_pins[27]	transitions[0x1=>0x0]	335415	1			T35	5		T38	30		T39	30
all_pins[28]	values[0x0]	913646	1			T34	1		T35	12		T36	1
all_pins[28]	values[0x1]	561326	1			T35	16		T38	34		T39	33
all_pins[28]	transitions[0x0=>0x1]	335974	1			T35	5		T38	31		T39	20
all_pins[28]	transitions[0x1=>0x0]	332708	1			T35	4		T38	16		T39	26
all_pins[29]	values[0x0]	917160	1			T34	1		T35	20		T36	1
all_pins[29]	values[0x1]	557812	1			T35	8		T38	43		T39	34
all_pins[29]	transitions[0x0=>0x1]	332301	1			T35	3		T38	38		T39	20
all_pins[29]	transitions[0x1=>0x0]	335815	1			T35	11		T38	29		T39	19
all_pins[30]	values[0x0]	917503	1			T34	1		T35	20		T36	1
all_pins[30]	values[0x1]	557469	1			T35	8		T38	36		T39	25
all_pins[30]	transitions[0x0=>0x1]	334330	1			T35	4		T38	25		T39	24
all_pins[30]	transitions[0x1=>0x0]	334673	1			T35	4		T38	32		T39	33
all_pins[31]	values[0x0]	912931	1			T34	1		T35	15		T36	1
all_pins[31]	values[0x1]	562041	1			T35	13		T38	27		T39	46
all_pins[31]	transitions[0x0=>0x1]	335703	1			T35	10		T38	23		T39	30
all_pins[31]	transitions[0x1=>0x0]	331131	1			T35	5		T38	32		T39	9