Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6086013	1			T34	1		T35	306		T36	1
all_values[1]	6086013	1			T34	1		T35	306		T36	1
all_values[2]	6086013	1			T34	1		T35	306		T36	1
all_values[3]	6086013	1			T34	1		T35	306		T36	1
all_values[4]	6086013	1			T34	1		T35	306		T36	1
all_values[5]	6086013	1			T34	1		T35	306		T36	1
all_values[6]	6086013	1			T34	1		T35	306		T36	1
all_values[7]	6086013	1			T34	1		T35	306		T36	1
all_values[8]	6086013	1			T34	1		T35	306		T36	1
all_values[9]	6086013	1			T34	1		T35	306		T36	1
all_values[10]	6086013	1			T34	1		T35	306		T36	1
all_values[11]	6086013	1			T34	1		T35	306		T36	1
all_values[12]	6086013	1			T34	1		T35	306		T36	1
all_values[13]	6086013	1			T34	1		T35	306		T36	1
all_values[14]	6086013	1			T34	1		T35	306		T36	1
all_values[15]	6086013	1			T34	1		T35	306		T36	1
all_values[16]	6086013	1			T34	1		T35	306		T36	1
all_values[17]	6086013	1			T34	1		T35	306		T36	1
all_values[18]	6086013	1			T34	1		T35	306		T36	1
all_values[19]	6086013	1			T34	1		T35	306		T36	1
all_values[20]	6086013	1			T34	1		T35	306		T36	1
all_values[21]	6086013	1			T34	1		T35	306		T36	1
all_values[22]	6086013	1			T34	1		T35	306		T36	1
all_values[23]	6086013	1			T34	1		T35	306		T36	1
all_values[24]	6086013	1			T34	1		T35	306		T36	1
all_values[25]	6086013	1			T34	1		T35	306		T36	1
all_values[26]	6086013	1			T34	1		T35	306		T36	1
all_values[27]	6086013	1			T34	1		T35	306		T36	1
all_values[28]	6086013	1			T34	1		T35	306		T36	1
all_values[29]	6086013	1			T34	1		T35	306		T36	1
all_values[30]	6086013	1			T34	1		T35	306		T36	1
all_values[31]	6086013	1			T34	1		T35	306		T36	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130083557

1

T34

32

T35

9792

T36

32

auto[1]

64668859

1

T38

3146

T39

2854

T41

990

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78123235

1

T34

32

T35

9792

T36

32

auto[1]

116629181

1

T38

5383

T39

5590

T41

1480

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193031286

1

T34

32

T35

9792

T36

32

auto[1]

1721130

1

T44

40679

T45

207

T20

142

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2234914	1			T34	1		T35	306		T36	1
all_values[0]	auto[0]	auto[0]	auto[1]	1800451	1			T38	77		T39	70		T41	13
all_values[0]	auto[0]	auto[1]	auto[0]	200757	1			T38	7		T39	11		T41	22
all_values[0]	auto[0]	auto[1]	auto[1]	1795916	1			T38	106		T39	113		T41	17
all_values[0]	auto[1]	auto[0]	auto[1]	26860	1			T44	606		T45	5		T20	5
all_values[0]	auto[1]	auto[1]	auto[1]	27115	1			T44	653		T45	3		T25	24
all_values[1]	auto[0]	auto[0]	auto[0]	2237231	1			T34	1		T35	306		T36	1
all_values[1]	auto[0]	auto[0]	auto[1]	1816954	1			T38	86		T39	124		T41	12
all_values[1]	auto[0]	auto[1]	auto[0]	199221	1			T38	37		T39	3		T41	4
all_values[1]	auto[0]	auto[1]	auto[1]	1778834	1			T38	68		T39	57		T41	33
all_values[1]	auto[1]	auto[0]	auto[1]	27251	1			T44	631		T45	6		T20	2
all_values[1]	auto[1]	auto[1]	auto[1]	26522	1			T44	633		T20	3		T25	15
all_values[2]	auto[0]	auto[0]	auto[0]	2240449	1			T34	1		T35	306		T36	1
all_values[2]	auto[0]	auto[0]	auto[1]	1800733	1			T38	41		T39	112		T41	29
all_values[2]	auto[0]	auto[1]	auto[0]	199353	1			T38	28		T39	5		T41	3
all_values[2]	auto[0]	auto[1]	auto[1]	1791575	1			T38	122		T39	68		T41	17
all_values[2]	auto[1]	auto[0]	auto[1]	26960	1			T44	622		T45	4		T20	5
all_values[2]	auto[1]	auto[1]	auto[1]	26943	1			T44	671		T45	1		T25	20
all_values[3]	auto[0]	auto[0]	auto[0]	2237849	1			T34	1		T35	306		T36	1
all_values[3]	auto[0]	auto[0]	auto[1]	1802360	1			T38	71		T39	90		T41	34
all_values[3]	auto[0]	auto[1]	auto[0]	204725	1			T38	23		T39	16		T41	3
all_values[3]	auto[0]	auto[1]	auto[1]	1787211	1			T38	77		T39	86		T41	21
all_values[3]	auto[1]	auto[0]	auto[1]	26873	1			T44	666		T45	5		T20	1
all_values[3]	auto[1]	auto[1]	auto[1]	26995	1			T44	598		T45	2		T20	2
all_values[4]	auto[0]	auto[0]	auto[0]	2240035	1			T34	1		T35	306		T36	1
all_values[4]	auto[0]	auto[0]	auto[1]	1794749	1			T38	69		T39	96		T41	34
all_values[4]	auto[0]	auto[1]	auto[0]	203190	1			T38	11		T39	13		T42	4
all_values[4]	auto[0]	auto[1]	auto[1]	1794161	1			T38	102		T39	81		T41	12
all_values[4]	auto[1]	auto[0]	auto[1]	27144	1			T44	657		T45	5		T20	2
all_values[4]	auto[1]	auto[1]	auto[1]	26734	1			T44	632		T20	2		T25	20
all_values[5]	auto[0]	auto[0]	auto[0]	2240071	1			T34	1		T35	306		T36	1
all_values[5]	auto[0]	auto[0]	auto[1]	1807767	1			T38	88		T39	82		T41	27
all_values[5]	auto[0]	auto[1]	auto[0]	196808	1			T38	9		T39	9		T41	9
all_values[5]	auto[0]	auto[1]	auto[1]	1787505	1			T38	86		T39	101		T41	27
all_values[5]	auto[1]	auto[0]	auto[1]	27541	1			T44	651		T45	2		T20	5
all_values[5]	auto[1]	auto[1]	auto[1]	26321	1			T44	614		T45	3		T20	2
all_values[6]	auto[0]	auto[0]	auto[0]	2240329	1			T34	1		T35	306		T36	1
all_values[6]	auto[0]	auto[0]	auto[1]	1805470	1			T38	85		T39	67		T41	9
all_values[6]	auto[0]	auto[1]	auto[0]	202886	1			T38	12		T39	9		T41	12
all_values[6]	auto[0]	auto[1]	auto[1]	1783610	1			T38	84		T39	116		T41	36
all_values[6]	auto[1]	auto[0]	auto[1]	27348	1			T44	629		T45	3		T20	3
all_values[6]	auto[1]	auto[1]	auto[1]	26370	1			T44	625		T45	3		T20	2
all_values[7]	auto[0]	auto[0]	auto[0]	2239748	1			T34	1		T35	306		T36	1
all_values[7]	auto[0]	auto[0]	auto[1]	1791548	1			T38	52		T39	47		T41	12
all_values[7]	auto[0]	auto[1]	auto[0]	202082	1			T38	18		T39	5		T41	9
all_values[7]	auto[0]	auto[1]	auto[1]	1798987	1			T38	114		T39	146		T41	39
all_values[7]	auto[1]	auto[0]	auto[1]	27001	1			T44	670		T45	5		T20	3
all_values[7]	auto[1]	auto[1]	auto[1]	26647	1			T44	613		T45	3		T25	23
all_values[8]	auto[0]	auto[0]	auto[0]	2239491	1			T34	1		T35	306		T36	1
all_values[8]	auto[0]	auto[0]	auto[1]	1807790	1			T38	105		T39	98		T41	27
all_values[8]	auto[0]	auto[1]	auto[0]	198341	1			T39	1		T41	9		T44	5370
all_values[8]	auto[0]	auto[1]	auto[1]	1786571	1			T38	54		T39	82		T41	22
all_values[8]	auto[1]	auto[0]	auto[1]	27160	1			T44	647		T45	6		T20	6
all_values[8]	auto[1]	auto[1]	auto[1]	26660	1			T44	615		T45	3		T25	18
all_values[9]	auto[0]	auto[0]	auto[0]	2236415	1			T34	1		T35	306		T36	1
all_values[9]	auto[0]	auto[0]	auto[1]	1787714	1			T38	114		T39	129		T41	29
all_values[9]	auto[0]	auto[1]	auto[0]	205488	1			T38	8		T39	2		T41	1
all_values[9]	auto[0]	auto[1]	auto[1]	1802590	1			T38	60		T39	47		T41	18
all_values[9]	auto[1]	auto[0]	auto[1]	27001	1			T44	640		T45	8		T20	2
all_values[9]	auto[1]	auto[1]	auto[1]	26805	1			T44	635		T45	1		T20	2
all_values[10]	auto[0]	auto[0]	auto[0]	2236357	1			T34	1		T35	306		T36	1
all_values[10]	auto[0]	auto[0]	auto[1]	1803642	1			T38	84		T39	97		T41	29
all_values[10]	auto[0]	auto[1]	auto[0]	197099	1			T38	22		T39	10		T41	7
all_values[10]	auto[0]	auto[1]	auto[1]	1795051	1			T38	90		T39	74		T41	18
all_values[10]	auto[1]	auto[0]	auto[1]	27288	1			T44	638		T45	7		T20	2
all_values[10]	auto[1]	auto[1]	auto[1]	26576	1			T44	670		T45	2		T20	1
all_values[11]	auto[0]	auto[0]	auto[0]	2238629	1			T34	1		T35	306		T36	1
all_values[11]	auto[0]	auto[0]	auto[1]	1810209	1			T38	113		T39	75		T41	31
all_values[11]	auto[0]	auto[1]	auto[0]	202897	1			T38	14		T39	18		T41	3
all_values[11]	auto[0]	auto[1]	auto[1]	1780353	1			T38	56		T39	81		T41	26
all_values[11]	auto[1]	auto[0]	auto[1]	27112	1			T44	668		T45	4		T20	1
all_values[11]	auto[1]	auto[1]	auto[1]	26813	1			T44	582		T45	1		T20	2
all_values[12]	auto[0]	auto[0]	auto[0]	2240508	1			T34	1		T35	306		T36	1
all_values[12]	auto[0]	auto[0]	auto[1]	1806933	1			T38	101		T39	150		T41	25
all_values[12]	auto[0]	auto[1]	auto[0]	204840	1			T38	5		T39	14		T41	8
all_values[12]	auto[0]	auto[1]	auto[1]	1780076	1			T38	84		T39	24		T41	13
all_values[12]	auto[1]	auto[0]	auto[1]	26942	1			T44	605		T45	6		T20	4
all_values[12]	auto[1]	auto[1]	auto[1]	26714	1			T44	623		T45	1		T25	20
all_values[13]	auto[0]	auto[0]	auto[0]	2239554	1			T34	1		T35	306		T36	1
all_values[13]	auto[0]	auto[0]	auto[1]	1806305	1			T38	62		T39	52		T41	29
all_values[13]	auto[0]	auto[1]	auto[0]	203645	1			T38	18		T39	16		T41	16
all_values[13]	auto[0]	auto[1]	auto[1]	1782454	1			T38	107		T39	107		T41	15
all_values[13]	auto[1]	auto[0]	auto[1]	27509	1			T44	664		T45	3		T20	5
all_values[13]	auto[1]	auto[1]	auto[1]	26546	1			T44	643		T45	3		T25	30
all_values[14]	auto[0]	auto[0]	auto[0]	2241600	1			T34	1		T35	306		T36	1
all_values[14]	auto[0]	auto[0]	auto[1]	1794479	1			T38	81		T39	115		T41	17
all_values[14]	auto[0]	auto[1]	auto[0]	202278	1			T38	8		T39	8		T41	3
all_values[14]	auto[0]	auto[1]	auto[1]	1794168	1			T38	96		T39	75		T41	33
all_values[14]	auto[1]	auto[0]	auto[1]	27197	1			T44	665		T45	5		T20	5
all_values[14]	auto[1]	auto[1]	auto[1]	26291	1			T44	565		T45	2		T20	1
all_values[15]	auto[0]	auto[0]	auto[0]	2237479	1			T34	1		T35	306		T36	1
all_values[15]	auto[0]	auto[0]	auto[1]	1796770	1			T38	50		T39	101		T41	8
all_values[15]	auto[0]	auto[1]	auto[0]	203221	1			T38	18		T39	29		T41	12
all_values[15]	auto[0]	auto[1]	auto[1]	1794760	1			T38	115		T39	57		T41	25
all_values[15]	auto[1]	auto[0]	auto[1]	27128	1			T44	629		T45	4		T20	4
all_values[15]	auto[1]	auto[1]	auto[1]	26655	1			T44	653		T45	3		T20	3
all_values[16]	auto[0]	auto[0]	auto[0]	2242663	1			T34	1		T35	306		T36	1
all_values[16]	auto[0]	auto[0]	auto[1]	1786656	1			T38	102		T39	90		T41	30
all_values[16]	auto[0]	auto[1]	auto[0]	205230	1			T38	13		T39	12		T42	8
all_values[16]	auto[0]	auto[1]	auto[1]	1798070	1			T38	74		T39	78		T41	29
all_values[16]	auto[1]	auto[0]	auto[1]	26985	1			T44	644		T45	5		T20	3
all_values[16]	auto[1]	auto[1]	auto[1]	26409	1			T44	632		T20	1		T25	20
all_values[17]	auto[0]	auto[0]	auto[0]	2240727	1			T34	1		T35	306		T36	1
all_values[17]	auto[0]	auto[0]	auto[1]	1785862	1			T38	78		T39	95		T41	30
all_values[17]	auto[0]	auto[1]	auto[0]	201417	1			T38	13		T39	6		T41	4
all_values[17]	auto[0]	auto[1]	auto[1]	1804416	1			T38	106		T39	74		T41	17
all_values[17]	auto[1]	auto[0]	auto[1]	26847	1			T44	604		T45	7		T20	5
all_values[17]	auto[1]	auto[1]	auto[1]	26744	1			T44	658		T45	2		T20	1
all_values[18]	auto[0]	auto[0]	auto[0]	2234924	1			T34	1		T35	306		T36	1
all_values[18]	auto[0]	auto[0]	auto[1]	1787651	1			T38	101		T39	131		T41	17
all_values[18]	auto[0]	auto[1]	auto[0]	204293	1			T38	8		T39	14		T41	8
all_values[18]	auto[0]	auto[1]	auto[1]	1805498	1			T38	51		T39	43		T41	26
all_values[18]	auto[1]	auto[0]	auto[1]	27147	1			T44	691		T45	8		T20	1
all_values[18]	auto[1]	auto[1]	auto[1]	26500	1			T44	606		T45	1		T25	10
all_values[19]	auto[0]	auto[0]	auto[0]	2243769	1			T34	1		T35	306		T36	1
all_values[19]	auto[0]	auto[0]	auto[1]	1802940	1			T38	61		T39	99		T41	27
all_values[19]	auto[0]	auto[1]	auto[0]	200684	1			T38	26		T39	9		T41	14
all_values[19]	auto[0]	auto[1]	auto[1]	1784840	1			T38	93		T39	73		T41	21
all_values[19]	auto[1]	auto[0]	auto[1]	27302	1			T44	662		T45	7		T20	1
all_values[19]	auto[1]	auto[1]	auto[1]	26478	1			T44	638		T20	1		T25	21
all_values[20]	auto[0]	auto[0]	auto[0]	2239974	1			T34	1		T35	306		T36	1
all_values[20]	auto[0]	auto[0]	auto[1]	1797861	1			T38	90		T39	92		T41	32
all_values[20]	auto[0]	auto[1]	auto[0]	206140	1			T38	18		T39	5		T41	7
all_values[20]	auto[0]	auto[1]	auto[1]	1788199	1			T38	84		T39	86		T41	8
all_values[20]	auto[1]	auto[0]	auto[1]	27183	1			T44	595		T45	3		T20	4
all_values[20]	auto[1]	auto[1]	auto[1]	26656	1			T44	624		T20	1		T25	21
all_values[21]	auto[0]	auto[0]	auto[0]	2239031	1			T34	1		T35	306		T36	1
all_values[21]	auto[0]	auto[0]	auto[1]	1791904	1			T38	83		T39	95		T41	34
all_values[21]	auto[0]	auto[1]	auto[0]	205004	1			T38	18		T39	3		T41	4
all_values[21]	auto[0]	auto[1]	auto[1]	1796304	1			T38	87		T39	99		T41	20
all_values[21]	auto[1]	auto[0]	auto[1]	27083	1			T44	632		T45	4		T20	4
all_values[21]	auto[1]	auto[1]	auto[1]	26687	1			T44	649		T45	1		T20	1
all_values[22]	auto[0]	auto[0]	auto[0]	2243292	1			T34	1		T35	306		T36	1
all_values[22]	auto[0]	auto[0]	auto[1]	1798465	1			T38	79		T39	98		T41	27
all_values[22]	auto[0]	auto[1]	auto[0]	199504	1			T38	19		T39	6		T42	3
all_values[22]	auto[0]	auto[1]	auto[1]	1790984	1			T38	87		T39	76		T41	28
all_values[22]	auto[1]	auto[0]	auto[1]	27018	1			T44	696		T45	2		T20	4
all_values[22]	auto[1]	auto[1]	auto[1]	26750	1			T44	593		T45	1		T20	1
all_values[23]	auto[0]	auto[0]	auto[0]	2242311	1			T34	1		T35	306		T36	1
all_values[23]	auto[0]	auto[0]	auto[1]	1805428	1			T38	89		T39	101		T41	17
all_values[23]	auto[0]	auto[1]	auto[0]	200911	1			T38	18		T39	2		T41	8
all_values[23]	auto[0]	auto[1]	auto[1]	1783556	1			T38	78		T39	61		T41	20
all_values[23]	auto[1]	auto[0]	auto[1]	27211	1			T44	638		T45	7		T20	4
all_values[23]	auto[1]	auto[1]	auto[1]	26596	1			T44	622		T45	2		T20	1
all_values[24]	auto[0]	auto[0]	auto[0]	2241150	1			T34	1		T35	306		T36	1
all_values[24]	auto[0]	auto[0]	auto[1]	1786013	1			T38	108		T39	58		T41	17
all_values[24]	auto[0]	auto[1]	auto[0]	200216	1			T39	10		T41	2		T42	9
all_values[24]	auto[0]	auto[1]	auto[1]	1804482	1			T38	81		T39	112		T41	41
all_values[24]	auto[1]	auto[0]	auto[1]	27471	1			T44	669		T45	1		T20	3
all_values[24]	auto[1]	auto[1]	auto[1]	26681	1			T44	603		T45	4		T20	3
all_values[25]	auto[0]	auto[0]	auto[0]	2237893	1			T34	1		T35	306		T36	1
all_values[25]	auto[0]	auto[0]	auto[1]	1810938	1			T38	110		T39	88		T41	38
all_values[25]	auto[0]	auto[1]	auto[0]	202561	1			T38	21		T39	14		T41	9
all_values[25]	auto[0]	auto[1]	auto[1]	1780947	1			T38	49		T39	86		T41	13
all_values[25]	auto[1]	auto[0]	auto[1]	26858	1			T44	634		T45	6		T20	1
all_values[25]	auto[1]	auto[1]	auto[1]	26816	1			T44	621		T45	1		T20	5
all_values[26]	auto[0]	auto[0]	auto[0]	2235439	1			T34	1		T35	306		T36	1
all_values[26]	auto[0]	auto[0]	auto[1]	1793948	1			T38	81		T39	77		T41	15
all_values[26]	auto[0]	auto[1]	auto[0]	202959	1			T38	25		T39	14		T41	28
all_values[26]	auto[0]	auto[1]	auto[1]	1799892	1			T38	79		T39	98		T41	19
all_values[26]	auto[1]	auto[0]	auto[1]	27035	1			T44	565		T45	4		T20	2
all_values[26]	auto[1]	auto[1]	auto[1]	26740	1			T44	689		T45	3		T25	15
all_values[27]	auto[0]	auto[0]	auto[0]	2238126	1			T34	1		T35	306		T36	1
all_values[27]	auto[0]	auto[0]	auto[1]	1794771	1			T38	118		T39	98		T41	17
all_values[27]	auto[0]	auto[1]	auto[0]	202679	1			T38	12		T39	6		T41	3
all_values[27]	auto[0]	auto[1]	auto[1]	1796823	1			T38	55		T39	81		T41	39
all_values[27]	auto[1]	auto[0]	auto[1]	27122	1			T44	624		T45	2		T20	2
all_values[27]	auto[1]	auto[1]	auto[1]	26492	1			T44	634		T45	2		T20	1
all_values[28]	auto[0]	auto[0]	auto[0]	2238433	1			T34	1		T35	306		T36	1
all_values[28]	auto[0]	auto[0]	auto[1]	1793124	1			T38	81		T39	114		T41	10
all_values[28]	auto[0]	auto[1]	auto[0]	202193	1			T38	12		T41	18		T42	5
all_values[28]	auto[0]	auto[1]	auto[1]	1798457	1			T38	84		T39	58		T41	34
all_values[28]	auto[1]	auto[0]	auto[1]	27172	1			T44	582		T45	4		T20	3
all_values[28]	auto[1]	auto[1]	auto[1]	26634	1			T44	673		T45	2		T20	2
all_values[29]	auto[0]	auto[0]	auto[0]	2240508	1			T34	1		T35	306		T36	1
all_values[29]	auto[0]	auto[0]	auto[1]	1808396	1			T38	71		T39	94		T41	23
all_values[29]	auto[0]	auto[1]	auto[0]	201042	1			T38	19		T39	20		T41	9
all_values[29]	auto[0]	auto[1]	auto[1]	1782157	1			T38	81		T39	77		T41	20
all_values[29]	auto[1]	auto[0]	auto[1]	27252	1			T44	671		T45	4		T20	3
all_values[29]	auto[1]	auto[1]	auto[1]	26658	1			T44	656		T45	2		T20	1
all_values[30]	auto[0]	auto[0]	auto[0]	2239973	1			T34	1		T35	306		T36	1
all_values[30]	auto[0]	auto[0]	auto[1]	1786890	1			T38	81		T39	101		T41	32
all_values[30]	auto[0]	auto[1]	auto[0]	207033	1			T38	12		T39	8		T41	19
all_values[30]	auto[0]	auto[1]	auto[1]	1798346	1			T38	91		T39	55		T41	2
all_values[30]	auto[1]	auto[0]	auto[1]	27280	1			T44	688		T45	6		T20	1
all_values[30]	auto[1]	auto[1]	auto[1]	26491	1			T44	592		T45	1		T25	24
all_values[31]	auto[0]	auto[0]	auto[0]	2236636	1			T34	1		T35	306		T36	1
all_values[31]	auto[0]	auto[0]	auto[1]	1795052	1			T38	111		T39	104		T41	28
all_values[31]	auto[0]	auto[1]	auto[0]	199030	1			T38	14		T39	6		T41	15
all_values[31]	auto[0]	auto[1]	auto[1]	1801485	1			T38	59		T39	78		T41	12
all_values[31]	auto[1]	auto[0]	auto[1]	26995	1			T44	656		T45	3		T20	5
all_values[31]	auto[1]	auto[1]	auto[1]	26815	1			T44	625		T45	3		T20	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal