Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[1]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[2]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[3]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[4]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[5]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[6]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[7]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[8]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[9]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[10]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[11]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[12]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[13]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[14]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[15]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[16]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[17]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[18]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[19]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[20]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[21]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[22]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[23]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[24]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[25]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[26]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[27]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[28]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[29]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[30]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[31]	6058671	1			T34	1		T35	306		T36	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101506379

1

T34

32

T35

5178

T36

32

auto[1]

92371093

1

T35

4614

T37

5257

T38

2132

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161424755

1

T34

32

T35

9792

T36

32

auto[1]

32452717

1

T37

766

T43

1706

T44

769290

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152019530

1

T34

32

T35

9792

T36

32

auto[1]

41857942

1

T37

3578

T43

2673

T44

996961

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2197433	1			T34	1		T35	137		T36	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2040240	1			T35	169		T37	54		T38	68
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	510169	1			T37	14		T43	14		T44	12147
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	470193	1			T37	28		T43	85		T44	1345
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	334041	1			T37	103		T43	6		T44	17659
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	506595	1			T37	11		T43	28		T44	11911
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2189168	1			T34	1		T35	109		T36	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2053045	1			T35	197		T37	76		T38	62
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	512478	1			T37	16		T43	20		T44	12028
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	467899	1			T37	11		T43	70		T44	1130
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	330378	1			T37	77		T43	7		T44	17429
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	505703	1			T37	18		T43	50		T44	12251
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2194799	1			T34	1		T35	155		T36	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2047924	1			T35	151		T37	96		T38	65
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	512090	1			T37	16		T43	8		T44	12356
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	467061	1			T37	20		T43	50		T44	1344
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	331307	1			T37	57		T43	13		T44	18054
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	505490	1			T37	10		T43	48		T44	11393
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2196906	1			T34	1		T35	175		T36	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2041920	1			T35	131		T37	96		T38	63
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	510181	1			T37	20		T43	38		T44	12362
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	469017	1			T37	22		T43	58		T44	1328
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	332956	1			T37	44		T43	6		T44	18159
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	507691	1			T37	14		T43	20		T44	12247
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2192496	1			T34	1		T35	185		T36	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2047577	1			T35	121		T37	79		T38	66
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	509367	1			T37	16		T43	20		T44	12057
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	471313	1			T37	21		T43	67		T44	1242
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	331584	1			T37	70		T43	9		T44	17732
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	506334	1			T37	12		T43	40		T44	12192
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2195076	1			T34	1		T35	157		T36	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2047308	1			T35	149		T37	112		T38	67
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	511641	1			T37	10		T43	32		T44	12140
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	469147	1			T37	20		T43	90		T44	1253
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	329981	1			T37	48		T43	7		T44	17544
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	505518	1			T37	2		T43	16		T44	12028
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2200578	1			T34	1		T35	172		T36	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2040516	1			T35	134		T37	97		T38	66
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	512233	1			T37	16		T43	46		T44	12699
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	470137	1			T37	20		T43	47		T44	1229
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	330712	1			T37	75		T43	4		T44	17029
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	504495	1			T37	6		T43	18		T44	11899
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2187255	1			T34	1		T35	145		T36	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2054030	1			T35	161		T37	57		T38	70
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	511613	1			T43	38		T44	12161		T45	1
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	468530	1			T37	27		T43	62		T44	1243
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	331205	1			T37	105		T43	3		T44	17469
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	506038	1			T37	17		T43	16		T44	12009
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2189600	1			T34	1		T35	187		T36	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2048202	1			T35	119		T37	59		T38	81
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	511212	1			T37	8		T43	24		T44	12001
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	470244	1			T37	36		T43	104		T44	1345
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	331868	1			T37	84		T43	6		T44	18351
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	507545	1			T37	15		T43	14		T44	11690
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2185104	1			T34	1		T35	186		T36	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2057998	1			T35	120		T37	74		T38	62
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	509640	1			T37	14		T43	44		T44	12204
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	472599	1			T37	12		T43	42		T44	1242
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	330266	1			T37	78		T43	3		T44	17320
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	503064	1			T37	13		T43	14		T44	11739
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2181924	1			T34	1		T35	164		T36	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2059015	1			T35	142		T37	82		T38	62
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	511532	1			T37	8		T43	38		T44	11675
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	469724	1			T37	23		T43	14		T44	1252
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	331621	1			T37	80		T43	1		T44	18259
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	504855	1			T37	4		T43	10		T44	12201
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2188706	1			T34	1		T35	137		T36	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2051955	1			T35	169		T37	88		T38	69
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	510048	1			T37	22		T43	34		T44	11992
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	469207	1			T37	16		T43	57		T44	1313
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	333072	1			T37	60		T43	8		T44	18149
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	505683	1			T37	4		T43	16		T44	12128
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2187125	1			T34	1		T35	190		T36	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2049610	1			T35	116		T37	82		T38	70
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	512265	1			T37	13		T43	32		T44	12302
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	472035	1			T37	29		T43	28		T44	1295
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	333308	1			T37	65		T43	1		T44	18146
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	504328	1			T37	14		T43	2		T44	12107
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2195968	1			T34	1		T35	150		T36	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2043146	1			T35	156		T37	100		T38	69
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	510577	1			T37	12		T43	50		T44	11736
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	469195	1			T37	11		T43	49		T44	1223
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	333333	1			T37	67		T43	3		T44	17693
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	506452	1			T43	16		T44	12239		T45	32
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2184419	1			T34	1		T35	133		T36	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2054647	1			T35	173		T37	56		T38	77
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	507935	1			T37	16		T43	8		T44	11578
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	473322	1			T37	20		T43	81		T44	1328
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	331885	1			T37	90		T43	10		T44	18638
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	506463	1			T37	22		T43	42		T44	11997
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2186870	1			T34	1		T35	155		T36	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2050155	1			T35	151		T37	96		T38	46
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	510129	1			T37	10		T43	16		T44	12164
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	474738	1			T37	18		T43	26		T44	1426
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	331831	1			T37	63		T43	2		T44	17706
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	504948	1			T37	9		T43	10		T44	11933
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2181235	1			T34	1		T35	208		T36	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2060422	1			T35	98		T37	90		T38	66
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	509738	1			T37	12		T43	28		T44	12516
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	475145	1			T37	22		T43	59		T44	1273
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	330388	1			T37	66		T43	8		T44	17398
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	501743	1			T37	4		T43	34		T44	11768
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2198549	1			T34	1		T35	176		T36	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2044391	1			T35	130		T37	110		T38	62
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	505465	1			T37	25		T43	40		T44	12195
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	473642	1			T37	20		T43	58		T44	1290
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	334757	1			T37	36		T43	6		T44	17948
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	501867	1			T37	4		T43	32		T44	11504
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2190235	1			T34	1		T35	126		T36	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2053238	1			T35	180		T37	114		T38	78
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	508172	1			T37	14		T43	28		T44	11664
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	473365	1			T37	16		T43	51		T44	1320
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	333609	1			T37	46		T43	8		T44	18546
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	500052	1			T37	8		T43	40		T44	11758
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2194317	1			T34	1		T35	188		T36	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2047789	1			T35	118		T37	53		T38	73
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	508740	1			T37	4		T43	38		T44	12367
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	471634	1			T37	36		T43	14		T44	1328
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	331308	1			T37	89		T43	1		T44	17998
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	504883	1			T37	14		T43	4		T44	11676
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2183105	1			T34	1		T35	131		T36	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2062243	1			T35	175		T37	100		T38	50
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	509161	1			T37	4		T43	18		T44	12091
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	468154	1			T37	25		T43	43		T44	1362
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	331840	1			T37	66		T43	5		T44	17740
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	504168	1			T37	2		T43	48		T44	12085
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2192026	1			T34	1		T35	181		T36	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2045484	1			T35	125		T37	94		T38	55
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	508335	1			T37	10		T43	22		T44	12120
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	473071	1			T37	18		T43	43		T44	1336
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	334347	1			T37	83		T43	8		T44	18017
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	505408	1			T37	4		T43	44		T44	11667
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2199526	1			T34	1		T35	153		T36	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2043479	1			T35	153		T37	72		T38	68
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	506985	1			T37	31		T43	52		T44	11674
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	471188	1			T37	12		T43	54		T44	1402
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	334075	1			T37	67		T43	7		T44	18251
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	503418	1			T37	8		T43	16		T44	12195
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2192302	1			T34	1		T35	164		T36	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2048635	1			T35	142		T37	61		T38	67
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	508637	1			T37	10		T43	26		T44	12109
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	471759	1			T37	28		T43	22		T44	1299
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	333401	1			T37	96		T44	17600		T45	19
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	503937	1			T37	14		T43	8		T44	12005
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2198327	1			T34	1		T35	211		T36	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2043445	1			T35	95		T37	68		T38	59
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	506407	1			T37	18		T43	8		T44	11910
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	471676	1			T37	21		T43	60		T44	1396
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	332991	1			T37	92		T43	3		T44	18311
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	505825	1			T37	8		T43	16		T44	11848
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2173658	1			T34	1		T35	177		T36	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2069126	1			T35	129		T37	55		T38	75
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	507600	1			T37	14		T43	28		T44	11865
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	473958	1			T37	24		T43	35		T44	1283
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	330071	1			T37	97		T43	7		T44	17557
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	504258	1			T37	14		T43	32		T44	12046
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2197343	1			T34	1		T35	155		T36	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2043635	1			T35	151		T37	35		T38	69
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	505715	1			T37	6		T43	38		T44	11740
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	474239	1			T37	43		T43	40		T44	1287
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	335398	1			T37	107		T43	6		T44	18114
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	502341	1			T37	24		T43	30		T44	11787
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2189841	1			T34	1		T35	157		T36	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2053742	1			T35	149		T37	59		T38	82
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	508394	1			T37	14		T43	8		T44	12077
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	471381	1			T37	25		T43	75		T44	1422
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	333605	1			T37	102		T43	12		T44	17795
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	501708	1			T37	12		T43	54		T44	12302
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2197052	1			T34	1		T35	150		T36	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2049063	1			T35	156		T37	58		T38	64
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	510668	1			T37	10		T43	10		T44	12385
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	469087	1			T37	43		T43	58		T44	1371
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	331113	1			T37	89		T43	8		T44	18043
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	501688	1			T37	12		T43	58		T44	11669
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2192381	1			T34	1		T35	154		T36	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2048874	1			T35	152		T37	41		T38	70
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	508064	1			T37	12		T43	30		T44	12158
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	470982	1			T37	39		T43	35		T44	1287
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	332945	1			T37	116		T43	4		T44	17652
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	505425	1			T37	10		T43	18		T44	12166
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2189931	1			T34	1		T35	136		T36	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2051098	1			T35	170		T37	63		T38	66
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	508854	1			T37	20		T43	4		T44	12137
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	471497	1			T37	34		T43	55		T44	1397
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	332178	1			T37	70		T43	5		T44	18169
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	505113	1			T37	18		T43	20		T44	11807
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2202969	1			T34	1		T35	174		T36	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2036659	1			T35	132		T37	70		T38	65
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	510650	1			T37	10		T43	44		T44	11928
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	470321	1			T37	28		T43	39		T44	1333
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	333086	1			T37	81		T43	3		T44	17809
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	504986	1			T37	14		T43	8		T44	12505

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal