Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[1]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[2]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[3]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[4]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[5]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[6]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[7]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[8]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[9]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[10]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[11]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[12]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[13]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[14]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[15]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[16]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[17]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[18]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[19]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[20]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[21]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[22]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[23]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[24]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[25]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[26]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[27]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[28]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[29]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[30]	6058671	1			T34	1		T35	306		T36	1
bins_for_gpio_bits[31]	6058671	1			T34	1		T35	306		T36	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101506379

1

T34

32

T35

5178

T36

32

auto[1]

92371093

1

T35

4614

T37

5257

T38

2132

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101497746

1

T34

32

T35

5178

T36

32

auto[1]

92379726

1

T35

4614

T37

5257

T38

2132

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3084687	1			T34	1		T35	137		T36	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	92786	1			T37	3		T43	3		T44	2232
bins_for_gpio_bits[0]	auto[1]	auto[0]	93108	1			T37	3		T43	3		T44	2227
bins_for_gpio_bits[0]	auto[1]	auto[1]	2788090	1			T35	169		T37	165		T38	68
bins_for_gpio_bits[1]	auto[0]	auto[0]	3076369	1			T34	1		T35	109		T36	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	92950	1			T37	5		T43	6		T44	2247
bins_for_gpio_bits[1]	auto[1]	auto[0]	93176	1			T37	5		T43	6		T44	2242
bins_for_gpio_bits[1]	auto[1]	auto[1]	2796176	1			T35	197		T37	166		T38	62
bins_for_gpio_bits[2]	auto[0]	auto[0]	3080862	1			T34	1		T35	155		T36	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	92804	1			T37	6		T43	7		T44	2193
bins_for_gpio_bits[2]	auto[1]	auto[0]	93088	1			T37	6		T43	7		T44	2187
bins_for_gpio_bits[2]	auto[1]	auto[1]	2791917	1			T35	151		T37	157		T38	65
bins_for_gpio_bits[3]	auto[0]	auto[0]	3083187	1			T34	1		T35	175		T36	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	92645	1			T37	5		T43	4		T44	2265
bins_for_gpio_bits[3]	auto[1]	auto[0]	92917	1			T37	5		T43	4		T44	2260
bins_for_gpio_bits[3]	auto[1]	auto[1]	2789922	1			T35	131		T37	149		T38	63
bins_for_gpio_bits[4]	auto[0]	auto[0]	3080416	1			T34	1		T35	185		T36	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	92493	1			T37	5		T43	6		T44	2221
bins_for_gpio_bits[4]	auto[1]	auto[0]	92760	1			T37	5		T43	6		T44	2213
bins_for_gpio_bits[4]	auto[1]	auto[1]	2793002	1			T35	121		T37	156		T38	66
bins_for_gpio_bits[5]	auto[0]	auto[0]	3083013	1			T34	1		T35	157		T36	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	92579	1			T37	4		T43	4		T44	2235
bins_for_gpio_bits[5]	auto[1]	auto[0]	92851	1			T37	4		T43	4		T44	2226
bins_for_gpio_bits[5]	auto[1]	auto[1]	2790228	1			T35	149		T37	158		T38	67
bins_for_gpio_bits[6]	auto[0]	auto[0]	3089702	1			T34	1		T35	172		T36	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	92953	1			T37	5		T43	4		T44	2272
bins_for_gpio_bits[6]	auto[1]	auto[0]	93246	1			T37	5		T43	4		T44	2261
bins_for_gpio_bits[6]	auto[1]	auto[1]	2782770	1			T35	134		T37	173		T38	66
bins_for_gpio_bits[7]	auto[0]	auto[0]	3074504	1			T34	1		T35	145		T36	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	92576	1			T43	3		T44	2254		T45	1
bins_for_gpio_bits[7]	auto[1]	auto[0]	92894	1			T43	3		T44	2251		T45	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	2798697	1			T35	161		T37	179		T38	70
bins_for_gpio_bits[8]	auto[0]	auto[0]	3077998	1			T34	1		T35	187		T36	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	92839	1			T37	1		T43	3		T44	2149
bins_for_gpio_bits[8]	auto[1]	auto[0]	93058	1			T37	1		T43	3		T44	2138
bins_for_gpio_bits[8]	auto[1]	auto[1]	2794776	1			T35	119		T37	157		T38	81
bins_for_gpio_bits[9]	auto[0]	auto[0]	3074506	1			T34	1		T35	186		T36	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	92543	1			T37	3		T43	2		T44	2256
bins_for_gpio_bits[9]	auto[1]	auto[0]	92837	1			T37	3		T43	2		T44	2246
bins_for_gpio_bits[9]	auto[1]	auto[1]	2798785	1			T35	120		T37	162		T38	62
bins_for_gpio_bits[10]	auto[0]	auto[0]	3070233	1			T34	1		T35	164		T36	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	92696	1			T37	4		T43	2		T44	2182
bins_for_gpio_bits[10]	auto[1]	auto[0]	92947	1			T37	4		T43	2		T44	2175
bins_for_gpio_bits[10]	auto[1]	auto[1]	2802795	1			T35	142		T37	162		T38	62
bins_for_gpio_bits[11]	auto[0]	auto[0]	3074902	1			T34	1		T35	137		T36	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	92774	1			T37	5		T43	3		T44	2220
bins_for_gpio_bits[11]	auto[1]	auto[0]	93059	1			T37	5		T43	3		T44	2215
bins_for_gpio_bits[11]	auto[1]	auto[1]	2797936	1			T35	169		T37	147		T38	69
bins_for_gpio_bits[12]	auto[0]	auto[0]	3078892	1			T34	1		T35	190		T36	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	92273	1			T37	5		T43	1		T44	2182
bins_for_gpio_bits[12]	auto[1]	auto[0]	92533	1			T37	5		T43	1		T44	2179
bins_for_gpio_bits[12]	auto[1]	auto[1]	2794973	1			T35	116		T37	156		T38	70
bins_for_gpio_bits[13]	auto[0]	auto[0]	3082997	1			T34	1		T35	150		T36	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	92503	1			T37	2		T43	4		T44	2165
bins_for_gpio_bits[13]	auto[1]	auto[0]	92743	1			T37	2		T43	4		T44	2153
bins_for_gpio_bits[13]	auto[1]	auto[1]	2790428	1			T35	156		T37	165		T38	69
bins_for_gpio_bits[14]	auto[0]	auto[0]	3072854	1			T34	1		T35	133		T36	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	92539	1			T37	5		T43	7		T44	2185
bins_for_gpio_bits[14]	auto[1]	auto[0]	92822	1			T37	5		T43	7		T44	2180
bins_for_gpio_bits[14]	auto[1]	auto[1]	2800456	1			T35	173		T37	163		T38	77
bins_for_gpio_bits[15]	auto[0]	auto[0]	3078406	1			T34	1		T35	155		T36	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	93025	1			T37	2		T43	2		T44	2248
bins_for_gpio_bits[15]	auto[1]	auto[0]	93331	1			T37	2		T43	2		T44	2241
bins_for_gpio_bits[15]	auto[1]	auto[1]	2793909	1			T35	151		T37	166		T38	46
bins_for_gpio_bits[16]	auto[0]	auto[0]	3073063	1			T34	1		T35	208		T36	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	92803	1			T37	4		T43	7		T44	2275
bins_for_gpio_bits[16]	auto[1]	auto[0]	93055	1			T37	4		T43	7		T44	2266
bins_for_gpio_bits[16]	auto[1]	auto[1]	2799750	1			T35	98		T37	156		T38	66
bins_for_gpio_bits[17]	auto[0]	auto[0]	3084707	1			T34	1		T35	176		T36	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	92671	1			T37	8		T43	6		T44	2221
bins_for_gpio_bits[17]	auto[1]	auto[0]	92949	1			T37	8		T43	6		T44	2213
bins_for_gpio_bits[17]	auto[1]	auto[1]	2788344	1			T35	130		T37	142		T38	62
bins_for_gpio_bits[18]	auto[0]	auto[0]	3079158	1			T34	1		T35	126		T36	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	92365	1			T37	4		T43	9		T44	2135
bins_for_gpio_bits[18]	auto[1]	auto[0]	92614	1			T37	4		T43	9		T44	2126
bins_for_gpio_bits[18]	auto[1]	auto[1]	2794534	1			T35	180		T37	164		T38	78
bins_for_gpio_bits[19]	auto[0]	auto[0]	3081974	1			T34	1		T35	188		T36	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	92411	1			T37	1		T43	1		T44	2223
bins_for_gpio_bits[19]	auto[1]	auto[0]	92717	1			T37	1		T43	1		T44	2214
bins_for_gpio_bits[19]	auto[1]	auto[1]	2791569	1			T35	118		T37	155		T38	73
bins_for_gpio_bits[20]	auto[0]	auto[0]	3067645	1			T34	1		T35	131		T36	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	92481	1			T37	2		T43	6		T44	2183
bins_for_gpio_bits[20]	auto[1]	auto[0]	92775	1			T37	2		T43	6		T44	2176
bins_for_gpio_bits[20]	auto[1]	auto[1]	2805770	1			T35	175		T37	166		T38	50
bins_for_gpio_bits[21]	auto[0]	auto[0]	3080329	1			T34	1		T35	181		T36	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	92852	1			T37	3		T43	7		T44	2199
bins_for_gpio_bits[21]	auto[1]	auto[0]	93103	1			T37	3		T43	7		T44	2190
bins_for_gpio_bits[21]	auto[1]	auto[1]	2792387	1			T35	125		T37	178		T38	55
bins_for_gpio_bits[22]	auto[0]	auto[0]	3085016	1			T34	1		T35	153		T36	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	92388	1			T37	6		T43	4		T44	2197
bins_for_gpio_bits[22]	auto[1]	auto[0]	92683	1			T37	6		T43	4		T44	2193
bins_for_gpio_bits[22]	auto[1]	auto[1]	2788584	1			T35	153		T37	141		T38	68
bins_for_gpio_bits[23]	auto[0]	auto[0]	3079855	1			T34	1		T35	164		T36	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	92580	1			T37	3		T43	2		T44	2178
bins_for_gpio_bits[23]	auto[1]	auto[0]	92843	1			T37	3		T43	2		T44	2169
bins_for_gpio_bits[23]	auto[1]	auto[1]	2793393	1			T35	142		T37	168		T38	67
bins_for_gpio_bits[24]	auto[0]	auto[0]	3083551	1			T34	1		T35	211		T36	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	92614	1			T37	5		T43	4		T44	2225
bins_for_gpio_bits[24]	auto[1]	auto[0]	92859	1			T37	5		T43	4		T44	2217
bins_for_gpio_bits[24]	auto[1]	auto[1]	2789647	1			T35	95		T37	163		T38	59
bins_for_gpio_bits[25]	auto[0]	auto[0]	3062522	1			T34	1		T35	177		T36	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	92388	1			T37	5		T43	5		T44	2206
bins_for_gpio_bits[25]	auto[1]	auto[0]	92694	1			T37	5		T43	5		T44	2199
bins_for_gpio_bits[25]	auto[1]	auto[1]	2811067	1			T35	129		T37	161		T38	75
bins_for_gpio_bits[26]	auto[0]	auto[0]	3084560	1			T34	1		T35	155		T36	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	92470	1			T37	3		T43	4		T44	2199
bins_for_gpio_bits[26]	auto[1]	auto[0]	92737	1			T37	3		T43	4		T44	2197
bins_for_gpio_bits[26]	auto[1]	auto[1]	2788904	1			T35	151		T37	163		T38	69
bins_for_gpio_bits[27]	auto[0]	auto[0]	3076690	1			T34	1		T35	157		T36	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	92661	1			T37	6		T43	7		T44	2190
bins_for_gpio_bits[27]	auto[1]	auto[0]	92926	1			T37	6		T43	7		T44	2183
bins_for_gpio_bits[27]	auto[1]	auto[1]	2796394	1			T35	149		T37	167		T38	82
bins_for_gpio_bits[28]	auto[0]	auto[0]	3083938	1			T34	1		T35	150		T36	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	92632	1			T37	2		T43	6		T44	2231
bins_for_gpio_bits[28]	auto[1]	auto[0]	92869	1			T37	2		T43	6		T44	2226
bins_for_gpio_bits[28]	auto[1]	auto[1]	2789232	1			T35	156		T37	157		T38	64
bins_for_gpio_bits[29]	auto[0]	auto[0]	3078327	1			T34	1		T35	154		T36	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	92861	1			T37	2		T43	5		T44	2252
bins_for_gpio_bits[29]	auto[1]	auto[0]	93100	1			T37	2		T43	5		T44	2247
bins_for_gpio_bits[29]	auto[1]	auto[1]	2794383	1			T35	152		T37	165		T38	70
bins_for_gpio_bits[30]	auto[0]	auto[0]	3077310	1			T34	1		T35	136		T36	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	92712	1			T37	6		T43	4		T44	2239
bins_for_gpio_bits[30]	auto[1]	auto[0]	92972	1			T37	6		T43	4		T44	2234
bins_for_gpio_bits[30]	auto[1]	auto[1]	2795677	1			T35	170		T37	145		T38	66
bins_for_gpio_bits[31]	auto[0]	auto[0]	3090687	1			T34	1		T35	174		T36	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	93019	1			T37	4		T43	3		T44	2258
bins_for_gpio_bits[31]	auto[1]	auto[0]	93253	1			T37	4		T43	3		T44	2249
bins_for_gpio_bits[31]	auto[1]	auto[1]	2781712	1			T35	132		T37	161		T38	65