Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4062225 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2023788 |
1 |
|
|
T38 |
113 |
|
T39 |
124 |
|
T41 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5827386 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
258627 |
1 |
|
|
T38 |
4 |
|
T39 |
5 |
|
T44 |
7806 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4087828 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
1998185 |
1 |
|
|
T38 |
73 |
|
T39 |
70 |
|
T41 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
870017 |
1 |
|
|
T38 |
31 |
|
T39 |
26 |
|
T41 |
4 |
| auto[1] |
auto[0] |
auto[1] |
129516 |
1 |
|
|
T38 |
2 |
|
T44 |
3912 |
|
T115 |
45 |
| auto[1] |
auto[1] |
auto[0] |
869541 |
1 |
|
|
T38 |
38 |
|
T39 |
39 |
|
T41 |
9 |
| auto[1] |
auto[1] |
auto[1] |
129111 |
1 |
|
|
T38 |
2 |
|
T39 |
5 |
|
T44 |
3894 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4081436 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2004577 |
1 |
|
|
T38 |
105 |
|
T39 |
60 |
|
T41 |
37 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5825971 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
260042 |
1 |
|
|
T38 |
9 |
|
T39 |
7 |
|
T41 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4073897 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2012116 |
1 |
|
|
T38 |
96 |
|
T39 |
106 |
|
T41 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
891322 |
1 |
|
|
T38 |
32 |
|
T39 |
67 |
|
T41 |
21 |
| auto[1] |
auto[0] |
auto[1] |
132810 |
1 |
|
|
T38 |
3 |
|
T39 |
5 |
|
T44 |
4255 |
| auto[1] |
auto[1] |
auto[0] |
860752 |
1 |
|
|
T38 |
55 |
|
T39 |
32 |
|
T41 |
21 |
| auto[1] |
auto[1] |
auto[1] |
127232 |
1 |
|
|
T38 |
6 |
|
T39 |
2 |
|
T41 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4067287 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2018726 |
1 |
|
|
T38 |
112 |
|
T39 |
84 |
|
T41 |
25 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5826308 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
259705 |
1 |
|
|
T38 |
5 |
|
T39 |
11 |
|
T41 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4066635 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2019378 |
1 |
|
|
T38 |
72 |
|
T39 |
131 |
|
T41 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
883532 |
1 |
|
|
T38 |
43 |
|
T39 |
66 |
|
T41 |
21 |
| auto[1] |
auto[0] |
auto[1] |
130437 |
1 |
|
|
T38 |
5 |
|
T39 |
6 |
|
T42 |
1 |
| auto[1] |
auto[1] |
auto[0] |
876141 |
1 |
|
|
T38 |
24 |
|
T39 |
54 |
|
T41 |
10 |
| auto[1] |
auto[1] |
auto[1] |
129268 |
1 |
|
|
T39 |
5 |
|
T41 |
1 |
|
T44 |
4072 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4075950 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2010063 |
1 |
|
|
T38 |
70 |
|
T39 |
99 |
|
T41 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5825811 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
260202 |
1 |
|
|
T38 |
3 |
|
T39 |
14 |
|
T41 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4068249 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2017764 |
1 |
|
|
T38 |
75 |
|
T39 |
134 |
|
T41 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
884484 |
1 |
|
|
T38 |
34 |
|
T39 |
76 |
|
T41 |
9 |
| auto[1] |
auto[0] |
auto[1] |
131147 |
1 |
|
|
T38 |
1 |
|
T39 |
7 |
|
T41 |
3 |
| auto[1] |
auto[1] |
auto[0] |
873078 |
1 |
|
|
T38 |
38 |
|
T39 |
44 |
|
T41 |
17 |
| auto[1] |
auto[1] |
auto[1] |
129055 |
1 |
|
|
T38 |
2 |
|
T39 |
7 |
|
T41 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4074383 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2011630 |
1 |
|
|
T38 |
89 |
|
T39 |
38 |
|
T41 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5826043 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
259970 |
1 |
|
|
T38 |
9 |
|
T39 |
8 |
|
T41 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4072671 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2013342 |
1 |
|
|
T38 |
101 |
|
T39 |
113 |
|
T41 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
883598 |
1 |
|
|
T38 |
48 |
|
T39 |
87 |
|
T41 |
6 |
| auto[1] |
auto[0] |
auto[1] |
131530 |
1 |
|
|
T38 |
6 |
|
T39 |
8 |
|
T41 |
1 |
| auto[1] |
auto[1] |
auto[0] |
869774 |
1 |
|
|
T38 |
44 |
|
T39 |
18 |
|
T41 |
4 |
| auto[1] |
auto[1] |
auto[1] |
128440 |
1 |
|
|
T38 |
3 |
|
T42 |
2 |
|
T44 |
4014 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4073368 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2012645 |
1 |
|
|
T38 |
125 |
|
T39 |
123 |
|
T41 |
31 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5824908 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
261105 |
1 |
|
|
T38 |
11 |
|
T39 |
7 |
|
T41 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4064123 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2021890 |
1 |
|
|
T38 |
113 |
|
T39 |
119 |
|
T41 |
47 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
882364 |
1 |
|
|
T38 |
46 |
|
T39 |
39 |
|
T41 |
25 |
| auto[1] |
auto[0] |
auto[1] |
130043 |
1 |
|
|
T38 |
5 |
|
T39 |
2 |
|
T41 |
3 |
| auto[1] |
auto[1] |
auto[0] |
878421 |
1 |
|
|
T38 |
56 |
|
T39 |
73 |
|
T41 |
17 |
| auto[1] |
auto[1] |
auto[1] |
131062 |
1 |
|
|
T38 |
6 |
|
T39 |
5 |
|
T41 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4063276 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2022737 |
1 |
|
|
T38 |
104 |
|
T39 |
83 |
|
T41 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5826773 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
259240 |
1 |
|
|
T38 |
5 |
|
T39 |
7 |
|
T41 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4076756 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2009257 |
1 |
|
|
T38 |
75 |
|
T39 |
83 |
|
T41 |
34 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
875674 |
1 |
|
|
T38 |
41 |
|
T39 |
45 |
|
T41 |
11 |
| auto[1] |
auto[0] |
auto[1] |
129290 |
1 |
|
|
T38 |
3 |
|
T39 |
5 |
|
T41 |
2 |
| auto[1] |
auto[1] |
auto[0] |
874343 |
1 |
|
|
T38 |
29 |
|
T39 |
31 |
|
T41 |
20 |
| auto[1] |
auto[1] |
auto[1] |
129950 |
1 |
|
|
T38 |
2 |
|
T39 |
2 |
|
T41 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4061377 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2024636 |
1 |
|
|
T38 |
133 |
|
T39 |
86 |
|
T41 |
37 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5825623 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
260390 |
1 |
|
|
T38 |
6 |
|
T39 |
5 |
|
T41 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4069875 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2016138 |
1 |
|
|
T38 |
89 |
|
T39 |
93 |
|
T41 |
57 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
879054 |
1 |
|
|
T38 |
24 |
|
T39 |
54 |
|
T41 |
25 |
| auto[1] |
auto[0] |
auto[1] |
130436 |
1 |
|
|
T38 |
2 |
|
T39 |
4 |
|
T41 |
1 |
| auto[1] |
auto[1] |
auto[0] |
876694 |
1 |
|
|
T38 |
59 |
|
T39 |
34 |
|
T41 |
28 |
| auto[1] |
auto[1] |
auto[1] |
129954 |
1 |
|
|
T38 |
4 |
|
T39 |
1 |
|
T41 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4056304 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2029709 |
1 |
|
|
T38 |
87 |
|
T39 |
90 |
|
T41 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5827151 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
258862 |
1 |
|
|
T38 |
10 |
|
T39 |
8 |
|
T41 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4074091 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2011922 |
1 |
|
|
T38 |
106 |
|
T39 |
126 |
|
T41 |
58 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
870680 |
1 |
|
|
T38 |
59 |
|
T39 |
65 |
|
T41 |
30 |
| auto[1] |
auto[0] |
auto[1] |
128303 |
1 |
|
|
T38 |
6 |
|
T39 |
2 |
|
T41 |
3 |
| auto[1] |
auto[1] |
auto[0] |
882380 |
1 |
|
|
T38 |
37 |
|
T39 |
53 |
|
T41 |
23 |
| auto[1] |
auto[1] |
auto[1] |
130559 |
1 |
|
|
T38 |
4 |
|
T39 |
6 |
|
T41 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4053436 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2032577 |
1 |
|
|
T38 |
119 |
|
T39 |
80 |
|
T41 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5825212 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
260801 |
1 |
|
|
T38 |
6 |
|
T39 |
6 |
|
T42 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4063829 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2022184 |
1 |
|
|
T38 |
102 |
|
T39 |
112 |
|
T41 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
877924 |
1 |
|
|
T38 |
28 |
|
T39 |
45 |
|
T41 |
4 |
| auto[1] |
auto[0] |
auto[1] |
129694 |
1 |
|
|
T38 |
2 |
|
T39 |
3 |
|
T42 |
2 |
| auto[1] |
auto[1] |
auto[0] |
883459 |
1 |
|
|
T38 |
68 |
|
T39 |
61 |
|
T41 |
1 |
| auto[1] |
auto[1] |
auto[1] |
131107 |
1 |
|
|
T38 |
4 |
|
T39 |
3 |
|
T42 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4049722 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2036291 |
1 |
|
|
T38 |
59 |
|
T39 |
57 |
|
T41 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5826461 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
259552 |
1 |
|
|
T38 |
11 |
|
T39 |
9 |
|
T41 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4072400 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2013613 |
1 |
|
|
T38 |
99 |
|
T39 |
107 |
|
T41 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
873571 |
1 |
|
|
T38 |
55 |
|
T39 |
75 |
|
T41 |
8 |
| auto[1] |
auto[0] |
auto[1] |
128988 |
1 |
|
|
T38 |
3 |
|
T39 |
8 |
|
T42 |
1 |
| auto[1] |
auto[1] |
auto[0] |
880490 |
1 |
|
|
T38 |
33 |
|
T39 |
23 |
|
T41 |
4 |
| auto[1] |
auto[1] |
auto[1] |
130564 |
1 |
|
|
T38 |
8 |
|
T39 |
1 |
|
T41 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4074011 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2012002 |
1 |
|
|
T38 |
119 |
|
T39 |
82 |
|
T41 |
35 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5824903 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
261110 |
1 |
|
|
T38 |
9 |
|
T39 |
9 |
|
T41 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4068360 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2017653 |
1 |
|
|
T38 |
117 |
|
T39 |
119 |
|
T41 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
876045 |
1 |
|
|
T38 |
54 |
|
T39 |
67 |
|
T41 |
5 |
| auto[1] |
auto[0] |
auto[1] |
129952 |
1 |
|
|
T38 |
3 |
|
T39 |
6 |
|
T42 |
2 |
| auto[1] |
auto[1] |
auto[0] |
880498 |
1 |
|
|
T38 |
54 |
|
T39 |
43 |
|
T41 |
9 |
| auto[1] |
auto[1] |
auto[1] |
131158 |
1 |
|
|
T38 |
6 |
|
T39 |
3 |
|
T41 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4068142 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2017871 |
1 |
|
|
T38 |
150 |
|
T39 |
73 |
|
T41 |
20 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5826929 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
259084 |
1 |
|
|
T38 |
10 |
|
T39 |
7 |
|
T41 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4078395 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2007618 |
1 |
|
|
T38 |
106 |
|
T39 |
124 |
|
T41 |
62 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
877737 |
1 |
|
|
T38 |
24 |
|
T39 |
75 |
|
T41 |
39 |
| auto[1] |
auto[0] |
auto[1] |
130236 |
1 |
|
|
T38 |
2 |
|
T39 |
3 |
|
T41 |
3 |
| auto[1] |
auto[1] |
auto[0] |
870797 |
1 |
|
|
T38 |
72 |
|
T39 |
42 |
|
T41 |
19 |
| auto[1] |
auto[1] |
auto[1] |
128848 |
1 |
|
|
T38 |
8 |
|
T39 |
4 |
|
T41 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4065018 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2020995 |
1 |
|
|
T38 |
102 |
|
T39 |
91 |
|
T41 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5827659 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
258354 |
1 |
|
|
T38 |
15 |
|
T39 |
13 |
|
T44 |
8386 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4076993 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2009020 |
1 |
|
|
T38 |
121 |
|
T39 |
161 |
|
T42 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
878053 |
1 |
|
|
T38 |
48 |
|
T39 |
88 |
|
T42 |
18 |
| auto[1] |
auto[0] |
auto[1] |
129029 |
1 |
|
|
T38 |
9 |
|
T39 |
8 |
|
T44 |
4142 |
| auto[1] |
auto[1] |
auto[0] |
872613 |
1 |
|
|
T38 |
58 |
|
T39 |
60 |
|
T42 |
13 |
| auto[1] |
auto[1] |
auto[1] |
129325 |
1 |
|
|
T38 |
6 |
|
T39 |
5 |
|
T44 |
4244 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4058018 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2027995 |
1 |
|
|
T38 |
105 |
|
T39 |
102 |
|
T41 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5828503 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
257510 |
1 |
|
|
T38 |
6 |
|
T39 |
12 |
|
T41 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4087130 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
1998883 |
1 |
|
|
T38 |
97 |
|
T39 |
116 |
|
T41 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
870597 |
1 |
|
|
T38 |
33 |
|
T39 |
56 |
|
T41 |
11 |
| auto[1] |
auto[0] |
auto[1] |
128827 |
1 |
|
|
T38 |
2 |
|
T39 |
6 |
|
T41 |
2 |
| auto[1] |
auto[1] |
auto[0] |
870776 |
1 |
|
|
T38 |
58 |
|
T39 |
48 |
|
T42 |
16 |
| auto[1] |
auto[1] |
auto[1] |
128683 |
1 |
|
|
T38 |
4 |
|
T39 |
6 |
|
T42 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4068775 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2017238 |
1 |
|
|
T38 |
106 |
|
T39 |
82 |
|
T41 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5825452 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
260561 |
1 |
|
|
T38 |
9 |
|
T39 |
8 |
|
T41 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4061769 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2024244 |
1 |
|
|
T38 |
81 |
|
T39 |
95 |
|
T41 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
877848 |
1 |
|
|
T38 |
33 |
|
T39 |
38 |
|
T41 |
20 |
| auto[1] |
auto[0] |
auto[1] |
129444 |
1 |
|
|
T38 |
1 |
|
T39 |
3 |
|
T41 |
2 |
| auto[1] |
auto[1] |
auto[0] |
885835 |
1 |
|
|
T38 |
39 |
|
T39 |
49 |
|
T41 |
20 |
| auto[1] |
auto[1] |
auto[1] |
131117 |
1 |
|
|
T38 |
8 |
|
T39 |
5 |
|
T41 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4074950 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2011063 |
1 |
|
|
T38 |
96 |
|
T39 |
63 |
|
T41 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5826104 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
259909 |
1 |
|
|
T38 |
9 |
|
T39 |
3 |
|
T41 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4074089 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2011924 |
1 |
|
|
T38 |
104 |
|
T39 |
59 |
|
T41 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
878064 |
1 |
|
|
T38 |
52 |
|
T39 |
44 |
|
T41 |
13 |
| auto[1] |
auto[0] |
auto[1] |
129900 |
1 |
|
|
T38 |
7 |
|
T39 |
3 |
|
T44 |
3926 |
| auto[1] |
auto[1] |
auto[0] |
873951 |
1 |
|
|
T38 |
43 |
|
T39 |
12 |
|
T41 |
14 |
| auto[1] |
auto[1] |
auto[1] |
130009 |
1 |
|
|
T38 |
2 |
|
T41 |
3 |
|
T42 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4054634 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2031379 |
1 |
|
|
T38 |
81 |
|
T39 |
122 |
|
T41 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5826000 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
260013 |
1 |
|
|
T38 |
7 |
|
T39 |
5 |
|
T41 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4073246 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2012767 |
1 |
|
|
T38 |
77 |
|
T39 |
91 |
|
T41 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
873005 |
1 |
|
|
T38 |
39 |
|
T39 |
31 |
|
T41 |
12 |
| auto[1] |
auto[0] |
auto[1] |
128698 |
1 |
|
|
T38 |
3 |
|
T39 |
2 |
|
T41 |
3 |
| auto[1] |
auto[1] |
auto[0] |
879749 |
1 |
|
|
T38 |
31 |
|
T39 |
55 |
|
T41 |
21 |
| auto[1] |
auto[1] |
auto[1] |
131315 |
1 |
|
|
T38 |
4 |
|
T39 |
3 |
|
T41 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4075689 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2010324 |
1 |
|
|
T38 |
70 |
|
T39 |
100 |
|
T41 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5827787 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
258226 |
1 |
|
|
T38 |
5 |
|
T39 |
12 |
|
T41 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4082022 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2003991 |
1 |
|
|
T38 |
71 |
|
T39 |
136 |
|
T41 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
877384 |
1 |
|
|
T38 |
49 |
|
T39 |
60 |
|
T41 |
25 |
| auto[1] |
auto[0] |
auto[1] |
129916 |
1 |
|
|
T38 |
4 |
|
T39 |
6 |
|
T41 |
3 |
| auto[1] |
auto[1] |
auto[0] |
868381 |
1 |
|
|
T38 |
17 |
|
T39 |
64 |
|
T41 |
16 |
| auto[1] |
auto[1] |
auto[1] |
128310 |
1 |
|
|
T38 |
1 |
|
T39 |
6 |
|
T42 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4056422 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2029591 |
1 |
|
|
T38 |
104 |
|
T39 |
112 |
|
T41 |
47 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5824768 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
261245 |
1 |
|
|
T38 |
7 |
|
T39 |
4 |
|
T41 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4059140 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2026873 |
1 |
|
|
T38 |
97 |
|
T39 |
60 |
|
T41 |
40 |