Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4058297 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2027716 |
1 |
|
|
T38 |
132 |
|
T39 |
151 |
|
T41 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5825552 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
260461 |
1 |
|
|
T38 |
12 |
|
T39 |
11 |
|
T41 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4067106 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2018907 |
1 |
|
|
T38 |
114 |
|
T39 |
95 |
|
T41 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
879762 |
1 |
|
|
T38 |
27 |
|
T39 |
24 |
|
T41 |
4 |
| auto[1] |
auto[0] |
auto[1] |
130371 |
1 |
|
|
T38 |
3 |
|
T44 |
4161 |
|
T115 |
54 |
| auto[1] |
auto[1] |
auto[0] |
878684 |
1 |
|
|
T38 |
75 |
|
T39 |
60 |
|
T41 |
11 |
| auto[1] |
auto[1] |
auto[1] |
130090 |
1 |
|
|
T38 |
9 |
|
T39 |
11 |
|
T41 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |