Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4073368 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2012645 |
1 |
|
|
T38 |
125 |
|
T39 |
123 |
|
T41 |
31 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5117459 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
968554 |
1 |
|
|
T38 |
35 |
|
T39 |
37 |
|
T41 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4055016 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2030997 |
1 |
|
|
T38 |
71 |
|
T39 |
70 |
|
T41 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
536422 |
1 |
|
|
T38 |
16 |
|
T39 |
16 |
|
T41 |
5 |
| auto[1] |
auto[0] |
auto[1] |
484849 |
1 |
|
|
T38 |
13 |
|
T39 |
14 |
|
T41 |
9 |
| auto[1] |
auto[1] |
auto[0] |
526021 |
1 |
|
|
T38 |
20 |
|
T39 |
17 |
|
T44 |
12991 |
| auto[1] |
auto[1] |
auto[1] |
483705 |
1 |
|
|
T38 |
22 |
|
T39 |
23 |
|
T42 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |