Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4076156 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2009857 |
1 |
|
|
T38 |
100 |
|
T39 |
97 |
|
T41 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5824060 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
261953 |
1 |
|
|
T38 |
11 |
|
T39 |
8 |
|
T42 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4059099 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2026914 |
1 |
|
|
T38 |
125 |
|
T39 |
142 |
|
T41 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
893489 |
1 |
|
|
T38 |
52 |
|
T39 |
81 |
|
T41 |
7 |
| auto[1] |
auto[0] |
auto[1] |
132858 |
1 |
|
|
T38 |
5 |
|
T39 |
2 |
|
T44 |
4340 |
| auto[1] |
auto[1] |
auto[0] |
871472 |
1 |
|
|
T38 |
62 |
|
T39 |
53 |
|
T41 |
12 |
| auto[1] |
auto[1] |
auto[1] |
129095 |
1 |
|
|
T38 |
6 |
|
T39 |
6 |
|
T42 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |