Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4058683 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2027330 |
1 |
|
|
T38 |
73 |
|
T39 |
84 |
|
T41 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5827364 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
258649 |
1 |
|
|
T38 |
7 |
|
T39 |
5 |
|
T41 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4078350 |
1 |
|
|
T34 |
1 |
|
T35 |
306 |
|
T36 |
1 |
| auto[1] |
2007663 |
1 |
|
|
T38 |
103 |
|
T39 |
102 |
|
T41 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
872400 |
1 |
|
|
T38 |
73 |
|
T39 |
71 |
|
T41 |
12 |
| auto[1] |
auto[0] |
auto[1] |
128582 |
1 |
|
|
T38 |
6 |
|
T39 |
5 |
|
T41 |
2 |
| auto[1] |
auto[1] |
auto[0] |
876614 |
1 |
|
|
T38 |
23 |
|
T39 |
26 |
|
T41 |
4 |
| auto[1] |
auto[1] |
auto[1] |
130067 |
1 |
|
|
T38 |
1 |
|
T42 |
1 |
|
T44 |
4006 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |