Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 937
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T102 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3472942023 Aug 13 06:42:45 PM PDT 24 Aug 13 06:42:46 PM PDT 24 117699889 ps
T765 /workspace/coverage/cover_reg_top/34.gpio_intr_test.315154687 Aug 13 06:43:10 PM PDT 24 Aug 13 06:43:11 PM PDT 24 17283032 ps
T90 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3238714751 Aug 13 06:42:39 PM PDT 24 Aug 13 06:42:39 PM PDT 24 58482817 ps
T766 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3347132701 Aug 13 06:42:37 PM PDT 24 Aug 13 06:42:38 PM PDT 24 73715278 ps
T767 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3925265175 Aug 13 06:42:37 PM PDT 24 Aug 13 06:42:39 PM PDT 24 258659722 ps
T768 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1699658704 Aug 13 06:42:43 PM PDT 24 Aug 13 06:42:43 PM PDT 24 33460666 ps
T769 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3448044734 Aug 13 06:42:33 PM PDT 24 Aug 13 06:42:34 PM PDT 24 47263071 ps
T770 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1575239367 Aug 13 06:42:41 PM PDT 24 Aug 13 06:42:43 PM PDT 24 103365500 ps
T771 /workspace/coverage/cover_reg_top/27.gpio_intr_test.3660974815 Aug 13 06:43:16 PM PDT 24 Aug 13 06:43:17 PM PDT 24 22856269 ps
T103 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2177233263 Aug 13 06:42:33 PM PDT 24 Aug 13 06:42:34 PM PDT 24 56082321 ps
T104 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2222739773 Aug 13 06:43:07 PM PDT 24 Aug 13 06:43:08 PM PDT 24 110712013 ps
T96 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3528596913 Aug 13 06:42:23 PM PDT 24 Aug 13 06:42:26 PM PDT 24 81998078 ps
T105 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1119939126 Aug 13 06:42:20 PM PDT 24 Aug 13 06:42:21 PM PDT 24 17229582 ps
T772 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3883686871 Aug 13 06:42:41 PM PDT 24 Aug 13 06:42:41 PM PDT 24 128431636 ps
T773 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.976058233 Aug 13 06:42:44 PM PDT 24 Aug 13 06:42:45 PM PDT 24 169367479 ps
T114 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2078507801 Aug 13 06:43:11 PM PDT 24 Aug 13 06:43:13 PM PDT 24 85930707 ps
T774 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.806396368 Aug 13 06:42:46 PM PDT 24 Aug 13 06:42:47 PM PDT 24 41808363 ps
T106 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.503470864 Aug 13 06:42:32 PM PDT 24 Aug 13 06:42:33 PM PDT 24 129172643 ps
T775 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2058998133 Aug 13 06:42:54 PM PDT 24 Aug 13 06:42:54 PM PDT 24 25809688 ps
T776 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4253735092 Aug 13 06:42:54 PM PDT 24 Aug 13 06:42:55 PM PDT 24 22946546 ps
T777 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1169244440 Aug 13 06:42:55 PM PDT 24 Aug 13 06:42:55 PM PDT 24 38292233 ps
T778 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1653176224 Aug 13 06:42:31 PM PDT 24 Aug 13 06:42:33 PM PDT 24 36789107 ps
T779 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3212826992 Aug 13 06:42:36 PM PDT 24 Aug 13 06:42:38 PM PDT 24 364466368 ps
T780 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3584198195 Aug 13 06:42:35 PM PDT 24 Aug 13 06:42:35 PM PDT 24 15947623 ps
T781 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3659981676 Aug 13 06:42:45 PM PDT 24 Aug 13 06:42:46 PM PDT 24 17362069 ps
T782 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.4150444102 Aug 13 06:42:36 PM PDT 24 Aug 13 06:42:36 PM PDT 24 36221903 ps
T783 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1469299299 Aug 13 06:42:19 PM PDT 24 Aug 13 06:42:20 PM PDT 24 302903442 ps
T784 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1727028298 Aug 13 06:42:34 PM PDT 24 Aug 13 06:42:36 PM PDT 24 905074710 ps
T785 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.394411953 Aug 13 06:42:48 PM PDT 24 Aug 13 06:42:49 PM PDT 24 117880512 ps
T786 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.962987690 Aug 13 06:42:31 PM PDT 24 Aug 13 06:42:32 PM PDT 24 147388197 ps
T787 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2767208233 Aug 13 06:42:50 PM PDT 24 Aug 13 06:42:50 PM PDT 24 47881556 ps
T788 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2089176919 Aug 13 06:42:45 PM PDT 24 Aug 13 06:42:46 PM PDT 24 38076684 ps
T789 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1889892434 Aug 13 06:42:45 PM PDT 24 Aug 13 06:42:47 PM PDT 24 342140630 ps
T790 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2183142375 Aug 13 06:42:36 PM PDT 24 Aug 13 06:42:37 PM PDT 24 169609582 ps
T791 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4237487768 Aug 13 06:42:24 PM PDT 24 Aug 13 06:42:25 PM PDT 24 92131693 ps
T792 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1622098961 Aug 13 06:42:39 PM PDT 24 Aug 13 06:42:41 PM PDT 24 463853588 ps
T793 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2268411012 Aug 13 06:42:46 PM PDT 24 Aug 13 06:42:47 PM PDT 24 41729155 ps
T794 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.93251591 Aug 13 06:42:42 PM PDT 24 Aug 13 06:42:45 PM PDT 24 768261930 ps
T795 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2245672361 Aug 13 06:42:53 PM PDT 24 Aug 13 06:42:53 PM PDT 24 12347657 ps
T796 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3931175197 Aug 13 06:42:51 PM PDT 24 Aug 13 06:42:51 PM PDT 24 17309329 ps
T91 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1046671123 Aug 13 06:42:47 PM PDT 24 Aug 13 06:42:48 PM PDT 24 12171609 ps
T797 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1588350346 Aug 13 06:42:22 PM PDT 24 Aug 13 06:42:23 PM PDT 24 115269498 ps
T798 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.667642931 Aug 13 06:42:45 PM PDT 24 Aug 13 06:42:46 PM PDT 24 19120522 ps
T799 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1379302017 Aug 13 06:42:45 PM PDT 24 Aug 13 06:42:45 PM PDT 24 18887390 ps
T800 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2170205913 Aug 13 06:42:43 PM PDT 24 Aug 13 06:42:44 PM PDT 24 229999671 ps
T801 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3652286168 Aug 13 06:42:41 PM PDT 24 Aug 13 06:42:42 PM PDT 24 161216109 ps
T802 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1187831124 Aug 13 06:42:24 PM PDT 24 Aug 13 06:42:26 PM PDT 24 146984501 ps
T803 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3677197006 Aug 13 06:42:44 PM PDT 24 Aug 13 06:42:45 PM PDT 24 162214030 ps
T804 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1137500006 Aug 13 06:42:26 PM PDT 24 Aug 13 06:42:28 PM PDT 24 28541112 ps
T92 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2795415393 Aug 13 06:42:35 PM PDT 24 Aug 13 06:42:36 PM PDT 24 18821685 ps
T805 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1383256601 Aug 13 06:42:32 PM PDT 24 Aug 13 06:42:35 PM PDT 24 457610082 ps
T806 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3103068312 Aug 13 06:42:45 PM PDT 24 Aug 13 06:42:46 PM PDT 24 25751198 ps
T807 /workspace/coverage/cover_reg_top/41.gpio_intr_test.4222300035 Aug 13 06:42:51 PM PDT 24 Aug 13 06:42:51 PM PDT 24 13774375 ps
T93 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1712197993 Aug 13 06:42:39 PM PDT 24 Aug 13 06:42:40 PM PDT 24 76250814 ps
T808 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1272486539 Aug 13 06:42:23 PM PDT 24 Aug 13 06:42:24 PM PDT 24 27592971 ps
T809 /workspace/coverage/cover_reg_top/31.gpio_intr_test.295106811 Aug 13 06:42:53 PM PDT 24 Aug 13 06:42:54 PM PDT 24 28701944 ps
T810 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3981665921 Aug 13 06:42:30 PM PDT 24 Aug 13 06:42:31 PM PDT 24 112499980 ps
T811 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.539746316 Aug 13 06:42:50 PM PDT 24 Aug 13 06:42:51 PM PDT 24 236639826 ps
T812 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1669484957 Aug 13 06:42:40 PM PDT 24 Aug 13 06:42:41 PM PDT 24 78265790 ps
T813 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.4095375617 Aug 13 06:42:48 PM PDT 24 Aug 13 06:42:50 PM PDT 24 432245015 ps
T814 /workspace/coverage/cover_reg_top/22.gpio_intr_test.4120287876 Aug 13 06:42:54 PM PDT 24 Aug 13 06:42:54 PM PDT 24 81774600 ps
T815 /workspace/coverage/cover_reg_top/19.gpio_intr_test.2188115279 Aug 13 06:43:07 PM PDT 24 Aug 13 06:43:08 PM PDT 24 11553819 ps
T816 /workspace/coverage/cover_reg_top/38.gpio_intr_test.545617899 Aug 13 06:42:47 PM PDT 24 Aug 13 06:42:48 PM PDT 24 19149055 ps
T817 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3953318650 Aug 13 06:42:43 PM PDT 24 Aug 13 06:42:43 PM PDT 24 43788516 ps
T818 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3432420227 Aug 13 06:42:33 PM PDT 24 Aug 13 06:42:34 PM PDT 24 31206718 ps
T819 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1135777087 Aug 13 06:42:46 PM PDT 24 Aug 13 06:42:47 PM PDT 24 13610921 ps
T820 /workspace/coverage/cover_reg_top/39.gpio_intr_test.512519704 Aug 13 06:42:47 PM PDT 24 Aug 13 06:42:48 PM PDT 24 14811755 ps
T821 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2256321557 Aug 13 06:42:34 PM PDT 24 Aug 13 06:42:36 PM PDT 24 108215748 ps
T822 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1381984654 Aug 13 06:42:24 PM PDT 24 Aug 13 06:42:25 PM PDT 24 31539744 ps
T823 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.117195931 Aug 13 06:42:36 PM PDT 24 Aug 13 06:42:37 PM PDT 24 47925344 ps
T94 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.317879058 Aug 13 06:42:48 PM PDT 24 Aug 13 06:42:49 PM PDT 24 22930493 ps
T824 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1868360072 Aug 13 06:42:18 PM PDT 24 Aug 13 06:42:19 PM PDT 24 12729429 ps
T825 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3130991145 Aug 13 06:42:27 PM PDT 24 Aug 13 06:42:28 PM PDT 24 32139977 ps
T95 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1770208819 Aug 13 06:42:28 PM PDT 24 Aug 13 06:42:29 PM PDT 24 37860084 ps
T826 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1056870331 Aug 13 06:42:44 PM PDT 24 Aug 13 06:42:45 PM PDT 24 163469437 ps
T827 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2591391906 Aug 13 06:42:40 PM PDT 24 Aug 13 06:42:42 PM PDT 24 132592542 ps
T828 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1774429249 Aug 13 06:42:19 PM PDT 24 Aug 13 06:42:19 PM PDT 24 18973051 ps
T829 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1360118423 Aug 13 06:42:33 PM PDT 24 Aug 13 06:42:34 PM PDT 24 39076791 ps
T830 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2827807236 Aug 13 06:42:46 PM PDT 24 Aug 13 06:42:49 PM PDT 24 162403013 ps
T831 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3312628929 Aug 13 06:42:41 PM PDT 24 Aug 13 06:42:42 PM PDT 24 108625472 ps
T832 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.4190294053 Aug 13 06:42:53 PM PDT 24 Aug 13 06:42:55 PM PDT 24 36024369 ps
T833 /workspace/coverage/cover_reg_top/28.gpio_intr_test.728210328 Aug 13 06:42:54 PM PDT 24 Aug 13 06:42:55 PM PDT 24 63484455 ps
T834 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3613978341 Aug 13 06:42:37 PM PDT 24 Aug 13 06:42:37 PM PDT 24 14316404 ps
T97 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3377252220 Aug 13 06:42:26 PM PDT 24 Aug 13 06:42:27 PM PDT 24 55992898 ps
T835 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3221562684 Aug 13 06:42:48 PM PDT 24 Aug 13 06:42:49 PM PDT 24 61185282 ps
T836 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.480576027 Aug 13 06:42:26 PM PDT 24 Aug 13 06:42:29 PM PDT 24 64019238 ps
T837 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1314743610 Aug 13 06:42:42 PM PDT 24 Aug 13 06:42:43 PM PDT 24 41182755 ps
T838 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3627390232 Aug 13 06:31:13 PM PDT 24 Aug 13 06:31:15 PM PDT 24 199440464 ps
T839 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.407075155 Aug 13 06:31:05 PM PDT 24 Aug 13 06:31:06 PM PDT 24 600997715 ps
T840 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1436575283 Aug 13 06:31:20 PM PDT 24 Aug 13 06:31:22 PM PDT 24 146347884 ps
T841 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2108833553 Aug 13 06:31:13 PM PDT 24 Aug 13 06:31:14 PM PDT 24 45087415 ps
T842 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3172614496 Aug 13 06:31:23 PM PDT 24 Aug 13 06:31:25 PM PDT 24 892463391 ps
T843 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2835302363 Aug 13 06:31:06 PM PDT 24 Aug 13 06:31:07 PM PDT 24 79042425 ps
T844 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1910858034 Aug 13 06:31:15 PM PDT 24 Aug 13 06:31:16 PM PDT 24 42353248 ps
T845 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1816610431 Aug 13 06:31:18 PM PDT 24 Aug 13 06:31:20 PM PDT 24 228858593 ps
T846 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.428060126 Aug 13 06:31:13 PM PDT 24 Aug 13 06:31:14 PM PDT 24 64173822 ps
T847 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1983617786 Aug 13 06:31:16 PM PDT 24 Aug 13 06:31:17 PM PDT 24 68682563 ps
T848 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1497233158 Aug 13 06:31:14 PM PDT 24 Aug 13 06:31:16 PM PDT 24 57696915 ps
T849 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.162247906 Aug 13 06:31:21 PM PDT 24 Aug 13 06:31:22 PM PDT 24 111321977 ps
T850 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2680197231 Aug 13 06:31:15 PM PDT 24 Aug 13 06:31:16 PM PDT 24 33351715 ps
T851 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3880472709 Aug 13 06:31:15 PM PDT 24 Aug 13 06:31:16 PM PDT 24 65163349 ps
T852 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3415265288 Aug 13 06:31:04 PM PDT 24 Aug 13 06:31:05 PM PDT 24 70603829 ps
T853 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1339439121 Aug 13 06:31:19 PM PDT 24 Aug 13 06:31:21 PM PDT 24 45774411 ps
T854 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2158901380 Aug 13 06:31:17 PM PDT 24 Aug 13 06:31:19 PM PDT 24 491845726 ps
T855 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2578461363 Aug 13 06:31:22 PM PDT 24 Aug 13 06:31:23 PM PDT 24 32766677 ps
T856 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1530443437 Aug 13 06:31:21 PM PDT 24 Aug 13 06:31:22 PM PDT 24 74816421 ps
T857 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.690534102 Aug 13 06:31:19 PM PDT 24 Aug 13 06:31:20 PM PDT 24 292830931 ps
T858 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3474731862 Aug 13 06:31:18 PM PDT 24 Aug 13 06:31:19 PM PDT 24 110137995 ps
T859 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.306748314 Aug 13 06:31:18 PM PDT 24 Aug 13 06:31:19 PM PDT 24 86510455 ps
T860 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1226337786 Aug 13 06:31:13 PM PDT 24 Aug 13 06:31:14 PM PDT 24 22201786 ps
T861 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.114865450 Aug 13 06:31:17 PM PDT 24 Aug 13 06:31:18 PM PDT 24 57411375 ps
T862 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2634029325 Aug 13 06:31:22 PM PDT 24 Aug 13 06:31:23 PM PDT 24 47240680 ps
T863 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.774521941 Aug 13 06:31:01 PM PDT 24 Aug 13 06:31:02 PM PDT 24 129129033 ps
T864 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4114764414 Aug 13 06:31:19 PM PDT 24 Aug 13 06:31:21 PM PDT 24 77377518 ps
T865 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2719434874 Aug 13 06:31:06 PM PDT 24 Aug 13 06:31:07 PM PDT 24 26772246 ps
T866 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.535214667 Aug 13 06:31:21 PM PDT 24 Aug 13 06:31:22 PM PDT 24 300405201 ps
T867 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2385974003 Aug 13 06:31:20 PM PDT 24 Aug 13 06:31:21 PM PDT 24 54038336 ps
T868 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1609814763 Aug 13 06:31:21 PM PDT 24 Aug 13 06:31:22 PM PDT 24 32567177 ps
T869 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3359238540 Aug 13 06:31:13 PM PDT 24 Aug 13 06:31:15 PM PDT 24 140932047 ps
T870 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1013478605 Aug 13 06:31:03 PM PDT 24 Aug 13 06:31:05 PM PDT 24 189973728 ps
T871 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3783697919 Aug 13 06:31:17 PM PDT 24 Aug 13 06:31:19 PM PDT 24 208257290 ps
T872 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2990602911 Aug 13 06:31:04 PM PDT 24 Aug 13 06:31:05 PM PDT 24 205015553 ps
T873 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1131345373 Aug 13 06:31:06 PM PDT 24 Aug 13 06:31:07 PM PDT 24 30875029 ps
T874 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2419209898 Aug 13 06:31:20 PM PDT 24 Aug 13 06:31:22 PM PDT 24 108319951 ps
T875 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3247907595 Aug 13 06:31:03 PM PDT 24 Aug 13 06:31:04 PM PDT 24 82010946 ps
T876 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2281046145 Aug 13 06:31:16 PM PDT 24 Aug 13 06:31:17 PM PDT 24 246743310 ps
T877 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4208269716 Aug 13 06:31:18 PM PDT 24 Aug 13 06:31:19 PM PDT 24 213939404 ps
T878 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.438753157 Aug 13 06:30:59 PM PDT 24 Aug 13 06:31:00 PM PDT 24 89393765 ps
T879 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2485950646 Aug 13 06:31:15 PM PDT 24 Aug 13 06:31:16 PM PDT 24 46716331 ps
T880 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1737724539 Aug 13 06:31:04 PM PDT 24 Aug 13 06:31:05 PM PDT 24 132694162 ps
T881 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1030685072 Aug 13 06:31:12 PM PDT 24 Aug 13 06:31:13 PM PDT 24 64985955 ps
T882 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2283331437 Aug 13 06:31:21 PM PDT 24 Aug 13 06:31:22 PM PDT 24 109802254 ps
T883 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2998288970 Aug 13 06:31:05 PM PDT 24 Aug 13 06:31:06 PM PDT 24 94127044 ps
T884 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.286269744 Aug 13 06:31:14 PM PDT 24 Aug 13 06:31:15 PM PDT 24 129862643 ps
T885 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.4126827989 Aug 13 06:31:18 PM PDT 24 Aug 13 06:31:19 PM PDT 24 26082351 ps
T886 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3991830366 Aug 13 06:31:16 PM PDT 24 Aug 13 06:31:17 PM PDT 24 38436312 ps
T887 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.910461521 Aug 13 06:30:59 PM PDT 24 Aug 13 06:31:01 PM PDT 24 63226888 ps
T888 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.242471157 Aug 13 06:31:09 PM PDT 24 Aug 13 06:31:11 PM PDT 24 52809485 ps
T889 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1341396885 Aug 13 06:31:03 PM PDT 24 Aug 13 06:31:04 PM PDT 24 291030231 ps
T890 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1905764030 Aug 13 06:31:20 PM PDT 24 Aug 13 06:31:22 PM PDT 24 49710378 ps
T891 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.338622035 Aug 13 06:31:07 PM PDT 24 Aug 13 06:31:09 PM PDT 24 100319298 ps
T892 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2355158197 Aug 13 06:31:20 PM PDT 24 Aug 13 06:31:21 PM PDT 24 226764405 ps
T893 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3312003401 Aug 13 06:31:05 PM PDT 24 Aug 13 06:31:06 PM PDT 24 456199100 ps
T894 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.864245162 Aug 13 06:31:12 PM PDT 24 Aug 13 06:31:13 PM PDT 24 32066767 ps
T895 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3257710104 Aug 13 06:31:23 PM PDT 24 Aug 13 06:31:29 PM PDT 24 567593385 ps
T896 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1347519411 Aug 13 06:31:08 PM PDT 24 Aug 13 06:31:09 PM PDT 24 202031540 ps
T897 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1639928742 Aug 13 06:31:16 PM PDT 24 Aug 13 06:31:17 PM PDT 24 101175407 ps
T898 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2867418641 Aug 13 06:31:18 PM PDT 24 Aug 13 06:31:20 PM PDT 24 325588168 ps
T899 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2943696385 Aug 13 06:31:23 PM PDT 24 Aug 13 06:31:24 PM PDT 24 21554244 ps
T900 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1708456703 Aug 13 06:31:20 PM PDT 24 Aug 13 06:31:21 PM PDT 24 56025482 ps
T901 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.24029635 Aug 13 06:31:17 PM PDT 24 Aug 13 06:31:18 PM PDT 24 45247280 ps
T902 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1609125370 Aug 13 06:31:01 PM PDT 24 Aug 13 06:31:02 PM PDT 24 320871763 ps
T903 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.4042582467 Aug 13 06:31:17 PM PDT 24 Aug 13 06:31:19 PM PDT 24 219236824 ps
T904 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.82097137 Aug 13 06:31:05 PM PDT 24 Aug 13 06:31:06 PM PDT 24 70663109 ps
T905 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1641640168 Aug 13 06:31:19 PM PDT 24 Aug 13 06:31:21 PM PDT 24 73876715 ps
T906 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3918169445 Aug 13 06:31:17 PM PDT 24 Aug 13 06:31:18 PM PDT 24 138587276 ps
T907 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2880972033 Aug 13 06:31:16 PM PDT 24 Aug 13 06:31:17 PM PDT 24 254848923 ps
T908 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4068000010 Aug 13 06:31:13 PM PDT 24 Aug 13 06:31:14 PM PDT 24 32989636 ps
T909 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1063264671 Aug 13 06:31:21 PM PDT 24 Aug 13 06:31:22 PM PDT 24 173473321 ps
T910 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.834944611 Aug 13 06:31:19 PM PDT 24 Aug 13 06:31:21 PM PDT 24 43682584 ps
T911 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2882152037 Aug 13 06:31:19 PM PDT 24 Aug 13 06:31:20 PM PDT 24 102069157 ps
T912 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3044744604 Aug 13 06:31:18 PM PDT 24 Aug 13 06:31:20 PM PDT 24 85749033 ps
T913 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1555012778 Aug 13 06:31:00 PM PDT 24 Aug 13 06:31:01 PM PDT 24 53199910 ps
T914 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3276300021 Aug 13 06:31:42 PM PDT 24 Aug 13 06:31:43 PM PDT 24 326543648 ps
T915 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1148284382 Aug 13 06:31:20 PM PDT 24 Aug 13 06:31:22 PM PDT 24 609368298 ps
T916 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.169845592 Aug 13 06:31:10 PM PDT 24 Aug 13 06:31:11 PM PDT 24 36736447 ps
T917 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1549529418 Aug 13 06:31:18 PM PDT 24 Aug 13 06:31:20 PM PDT 24 732790712 ps
T918 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466368302 Aug 13 06:30:52 PM PDT 24 Aug 13 06:30:53 PM PDT 24 245043611 ps
T919 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4143258084 Aug 13 06:31:50 PM PDT 24 Aug 13 06:31:51 PM PDT 24 56151936 ps
T920 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2863377081 Aug 13 06:31:13 PM PDT 24 Aug 13 06:31:14 PM PDT 24 47862474 ps
T921 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3354840059 Aug 13 06:31:14 PM PDT 24 Aug 13 06:31:15 PM PDT 24 42937115 ps
T922 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3413940211 Aug 13 06:30:58 PM PDT 24 Aug 13 06:30:59 PM PDT 24 209024570 ps
T923 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.783183263 Aug 13 06:31:17 PM PDT 24 Aug 13 06:31:19 PM PDT 24 170430420 ps
T924 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2684769589 Aug 13 06:31:15 PM PDT 24 Aug 13 06:31:16 PM PDT 24 970087882 ps
T925 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.465588893 Aug 13 06:31:09 PM PDT 24 Aug 13 06:31:10 PM PDT 24 37320751 ps
T926 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3855859871 Aug 13 06:31:13 PM PDT 24 Aug 13 06:31:14 PM PDT 24 311540910 ps
T927 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2707228038 Aug 13 06:31:22 PM PDT 24 Aug 13 06:31:24 PM PDT 24 185196446 ps
T928 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2330212240 Aug 13 06:31:15 PM PDT 24 Aug 13 06:31:16 PM PDT 24 75638992 ps
T929 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4275665162 Aug 13 06:31:18 PM PDT 24 Aug 13 06:31:19 PM PDT 24 143265664 ps
T930 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1639156821 Aug 13 06:31:15 PM PDT 24 Aug 13 06:31:16 PM PDT 24 51043776 ps
T931 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3710644344 Aug 13 06:31:17 PM PDT 24 Aug 13 06:31:18 PM PDT 24 41132734 ps
T932 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.869017303 Aug 13 06:31:14 PM PDT 24 Aug 13 06:31:15 PM PDT 24 136108839 ps
T933 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2501854027 Aug 13 06:31:18 PM PDT 24 Aug 13 06:31:20 PM PDT 24 99180799 ps
T934 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2202322019 Aug 13 06:31:15 PM PDT 24 Aug 13 06:31:16 PM PDT 24 121563293 ps
T935 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4153360301 Aug 13 06:31:10 PM PDT 24 Aug 13 06:31:12 PM PDT 24 160434919 ps
T936 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1729103919 Aug 13 06:30:52 PM PDT 24 Aug 13 06:30:54 PM PDT 24 1142990564 ps
T937 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.665232709 Aug 13 06:31:17 PM PDT 24 Aug 13 06:31:19 PM PDT 24 321690624 ps

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3357243505
Short name T35
Test name
Test status
Simulation time 81132506 ps
CPU time 1.1 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 198028 kb
Host smart-36e021ff-11ee-4716-8b14-cc960c81d25a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357243505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3357243505
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_stress_all.464563235
Short name T44
Test name
Test status
Simulation time 58007099418 ps
CPU time 202.66 seconds
Started Aug 13 04:59:45 PM PDT 24
Finished Aug 13 05:03:08 PM PDT 24
Peak memory 198336 kb
Host smart-6868fa28-5bf7-44ae-97fb-f8ebf4db4ec4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464563235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.464563235
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.163679335
Short name T27
Test name
Test status
Simulation time 3557435611 ps
CPU time 27.58 seconds
Started Aug 13 05:00:02 PM PDT 24
Finished Aug 13 05:00:33 PM PDT 24
Peak memory 198432 kb
Host smart-f2fcfc39-ca7a-4b09-91ee-913192bcda08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=163679335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.163679335
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3308421159
Short name T51
Test name
Test status
Simulation time 83501917 ps
CPU time 0.97 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 04:59:23 PM PDT 24
Peak memory 215080 kb
Host smart-8320cbb8-ef7a-4542-98ed-f96ff3eb35dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308421159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3308421159
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3241124037
Short name T1
Test name
Test status
Simulation time 296406278 ps
CPU time 4.08 seconds
Started Aug 13 05:00:30 PM PDT 24
Finished Aug 13 05:00:35 PM PDT 24
Peak memory 198060 kb
Host smart-fa1ba94a-a21d-4038-84b7-59e7bc144885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241124037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3241124037
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.485598913
Short name T50
Test name
Test status
Simulation time 1510548713 ps
CPU time 1.45 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:47 PM PDT 24
Peak memory 198600 kb
Host smart-7835a188-abab-427f-971c-3a37bee8a2c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485598913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.485598913
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1712197993
Short name T93
Test name
Test status
Simulation time 76250814 ps
CPU time 0.87 seconds
Started Aug 13 06:42:39 PM PDT 24
Finished Aug 13 06:42:40 PM PDT 24
Peak memory 196536 kb
Host smart-2d048bb9-7cde-49b9-b56c-b23488826c3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712197993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1712197993
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2887677089
Short name T180
Test name
Test status
Simulation time 21278827 ps
CPU time 0.58 seconds
Started Aug 13 04:59:30 PM PDT 24
Finished Aug 13 04:59:30 PM PDT 24
Peak memory 193888 kb
Host smart-2b3d5a01-387f-4798-9e0b-999c15d62d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887677089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2887677089
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3298053094
Short name T87
Test name
Test status
Simulation time 19165656 ps
CPU time 0.64 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:42:52 PM PDT 24
Peak memory 195292 kb
Host smart-da7388f5-0169-4d16-8582-70d2cf163af6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298053094 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3298053094
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1574495997
Short name T108
Test name
Test status
Simulation time 41068735 ps
CPU time 0.58 seconds
Started Aug 13 06:42:39 PM PDT 24
Finished Aug 13 06:42:40 PM PDT 24
Peak memory 194960 kb
Host smart-fb8cbd4f-aab3-49ae-b522-84b16cc874e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574495997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1574495997
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3377252220
Short name T97
Test name
Test status
Simulation time 55992898 ps
CPU time 0.82 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:27 PM PDT 24
Peak memory 196444 kb
Host smart-7e6ab519-5a75-48b0-9a6c-a321ca51fadb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377252220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3377252220
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.4095375617
Short name T813
Test name
Test status
Simulation time 432245015 ps
CPU time 1.49 seconds
Started Aug 13 06:42:48 PM PDT 24
Finished Aug 13 06:42:50 PM PDT 24
Peak memory 198464 kb
Host smart-f68872e7-ce6e-4953-8b56-b549019a62d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095375617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.4095375617
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4020620569
Short name T28
Test name
Test status
Simulation time 309061658 ps
CPU time 3.26 seconds
Started Aug 13 04:59:48 PM PDT 24
Finished Aug 13 04:59:51 PM PDT 24
Peak memory 198144 kb
Host smart-5a7cbe14-6623-4a3f-a019-15953bd98aa6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020620569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4020620569
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3212826992
Short name T779
Test name
Test status
Simulation time 364466368 ps
CPU time 1.46 seconds
Started Aug 13 06:42:36 PM PDT 24
Finished Aug 13 06:42:38 PM PDT 24
Peak memory 198424 kb
Host smart-7ce7ea4a-3a44-403e-b360-50597a0aca9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212826992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3212826992
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3652286168
Short name T801
Test name
Test status
Simulation time 161216109 ps
CPU time 0.69 seconds
Started Aug 13 06:42:41 PM PDT 24
Finished Aug 13 06:42:42 PM PDT 24
Peak memory 195908 kb
Host smart-67eb939c-1442-4c59-ae35-e5c69a09973f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652286168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3652286168
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2436595924
Short name T736
Test name
Test status
Simulation time 25004600 ps
CPU time 1.13 seconds
Started Aug 13 06:42:36 PM PDT 24
Finished Aug 13 06:42:38 PM PDT 24
Peak memory 198608 kb
Host smart-0798205c-e739-4cc9-adeb-c73678e7f6f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436595924 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2436595924
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3613978341
Short name T834
Test name
Test status
Simulation time 14316404 ps
CPU time 0.6 seconds
Started Aug 13 06:42:37 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 194852 kb
Host smart-9aff1333-2edf-44cf-b1ad-357f1cbba1be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613978341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3613978341
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1588350346
Short name T797
Test name
Test status
Simulation time 115269498 ps
CPU time 0.87 seconds
Started Aug 13 06:42:22 PM PDT 24
Finished Aug 13 06:42:23 PM PDT 24
Peak memory 197500 kb
Host smart-30ad0c97-a450-46a2-8051-bf55c0403f13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588350346 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1588350346
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1383256601
Short name T805
Test name
Test status
Simulation time 457610082 ps
CPU time 2.46 seconds
Started Aug 13 06:42:32 PM PDT 24
Finished Aug 13 06:42:35 PM PDT 24
Peak memory 198516 kb
Host smart-323e7414-f47e-44b1-b82c-ba1178baf2ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383256601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1383256601
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1288038990
Short name T57
Test name
Test status
Simulation time 216285487 ps
CPU time 1.46 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:27 PM PDT 24
Peak memory 198332 kb
Host smart-d6e89ebd-ed56-48f9-b85b-a03c55e4fd72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288038990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1288038990
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3528596913
Short name T96
Test name
Test status
Simulation time 81998078 ps
CPU time 2.99 seconds
Started Aug 13 06:42:23 PM PDT 24
Finished Aug 13 06:42:26 PM PDT 24
Peak memory 197644 kb
Host smart-d1d8fb32-fdcc-4ce4-b1e3-e06b632d6c40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528596913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3528596913
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3221562684
Short name T835
Test name
Test status
Simulation time 61185282 ps
CPU time 0.59 seconds
Started Aug 13 06:42:48 PM PDT 24
Finished Aug 13 06:42:49 PM PDT 24
Peak memory 194872 kb
Host smart-9afd3d0b-4460-40e9-b00e-6963a97f4698
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221562684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3221562684
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1137500006
Short name T804
Test name
Test status
Simulation time 28541112 ps
CPU time 1.1 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 198624 kb
Host smart-4255fe22-e6fc-48cb-9ab2-fa4ff9da8ac8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137500006 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1137500006
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3584198195
Short name T780
Test name
Test status
Simulation time 15947623 ps
CPU time 0.6 seconds
Started Aug 13 06:42:35 PM PDT 24
Finished Aug 13 06:42:35 PM PDT 24
Peak memory 194892 kb
Host smart-bc25e66d-02db-45a1-a53f-bb06cae1d8cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584198195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3584198195
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.702597292
Short name T756
Test name
Test status
Simulation time 15418432 ps
CPU time 0.6 seconds
Started Aug 13 06:42:40 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 194232 kb
Host smart-a29f7c1f-8809-451d-a9cd-e214ac2cf248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702597292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.702597292
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3554072152
Short name T100
Test name
Test status
Simulation time 15329040 ps
CPU time 0.76 seconds
Started Aug 13 06:42:21 PM PDT 24
Finished Aug 13 06:42:22 PM PDT 24
Peak memory 196556 kb
Host smart-758e4d74-6654-4a5c-b20b-3b3fc1de5d15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554072152 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3554072152
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1304548642
Short name T719
Test name
Test status
Simulation time 44229520 ps
CPU time 2.15 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:26 PM PDT 24
Peak memory 198612 kb
Host smart-4dbd5955-52ee-49c0-9e99-fc33a42efdf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304548642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1304548642
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.4162213059
Short name T56
Test name
Test status
Simulation time 154917846 ps
CPU time 1.17 seconds
Started Aug 13 06:42:41 PM PDT 24
Finished Aug 13 06:42:42 PM PDT 24
Peak memory 198504 kb
Host smart-cc6533d0-dfbc-4752-a23d-e3e9292d281e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162213059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.4162213059
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1622098961
Short name T792
Test name
Test status
Simulation time 463853588 ps
CPU time 0.98 seconds
Started Aug 13 06:42:39 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 198324 kb
Host smart-d3ca1493-a99d-4767-8263-dc513223c231
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622098961 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1622098961
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2549291224
Short name T85
Test name
Test status
Simulation time 22260472 ps
CPU time 0.61 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:46 PM PDT 24
Peak memory 195212 kb
Host smart-8f440f41-97de-4854-abdd-a79c2accf6eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549291224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2549291224
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2638319225
Short name T715
Test name
Test status
Simulation time 13652450 ps
CPU time 0.57 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:46 PM PDT 24
Peak memory 194076 kb
Host smart-05e40cbe-2866-4e66-812d-faa899d67cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638319225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2638319225
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1314743610
Short name T837
Test name
Test status
Simulation time 41182755 ps
CPU time 0.76 seconds
Started Aug 13 06:42:42 PM PDT 24
Finished Aug 13 06:42:43 PM PDT 24
Peak memory 197308 kb
Host smart-4c3a81be-4be4-469f-9655-d6ec05d8b60c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314743610 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1314743610
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1109497392
Short name T744
Test name
Test status
Simulation time 225698914 ps
CPU time 1.61 seconds
Started Aug 13 06:42:28 PM PDT 24
Finished Aug 13 06:42:30 PM PDT 24
Peak memory 198588 kb
Host smart-d3984682-36d3-4a65-81ad-59dc816dfd20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109497392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1109497392
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1099329815
Short name T112
Test name
Test status
Simulation time 405563621 ps
CPU time 1.39 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:42:53 PM PDT 24
Peak memory 198500 kb
Host smart-be005e7e-d876-45fa-a622-9fc0af38840c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099329815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1099329815
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4253735092
Short name T776
Test name
Test status
Simulation time 22946546 ps
CPU time 1.1 seconds
Started Aug 13 06:42:54 PM PDT 24
Finished Aug 13 06:42:55 PM PDT 24
Peak memory 198588 kb
Host smart-33d45acb-41a9-4f1f-8de1-b511811a54ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253735092 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.4253735092
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2993568900
Short name T88
Test name
Test status
Simulation time 84435220 ps
CPU time 0.59 seconds
Started Aug 13 06:42:47 PM PDT 24
Finished Aug 13 06:42:48 PM PDT 24
Peak memory 195112 kb
Host smart-317f4cd3-73a2-4079-a350-3c5eca78fcc6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993568900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2993568900
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2187399790
Short name T749
Test name
Test status
Simulation time 39519623 ps
CPU time 0.58 seconds
Started Aug 13 06:42:41 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 194208 kb
Host smart-d7520df1-1c12-4180-a042-eadb1a7dd0a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187399790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2187399790
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1889892434
Short name T789
Test name
Test status
Simulation time 342140630 ps
CPU time 1.92 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:47 PM PDT 24
Peak memory 198660 kb
Host smart-bb89003b-34fe-4106-ad4d-cbab226f3f94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889892434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1889892434
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2078507801
Short name T114
Test name
Test status
Simulation time 85930707 ps
CPU time 1.19 seconds
Started Aug 13 06:43:11 PM PDT 24
Finished Aug 13 06:43:13 PM PDT 24
Peak memory 198584 kb
Host smart-c694e031-37fd-4fc7-b2ec-d20c89229dab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078507801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2078507801
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2256321557
Short name T821
Test name
Test status
Simulation time 108215748 ps
CPU time 1.17 seconds
Started Aug 13 06:42:34 PM PDT 24
Finished Aug 13 06:42:36 PM PDT 24
Peak memory 198568 kb
Host smart-bb4fa7c2-3481-4b2a-a498-ea4702ce887f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256321557 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2256321557
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3611577379
Short name T111
Test name
Test status
Simulation time 15119980 ps
CPU time 0.63 seconds
Started Aug 13 06:42:42 PM PDT 24
Finished Aug 13 06:42:43 PM PDT 24
Peak memory 195464 kb
Host smart-2befda8d-637d-4509-9450-2c721f8ffe16
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611577379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3611577379
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.638208381
Short name T731
Test name
Test status
Simulation time 23511417 ps
CPU time 0.6 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:47 PM PDT 24
Peak memory 194240 kb
Host smart-e38d7b66-0d14-43dd-a927-408d54ecafdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638208381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.638208381
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.117195931
Short name T823
Test name
Test status
Simulation time 47925344 ps
CPU time 0.68 seconds
Started Aug 13 06:42:36 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 196004 kb
Host smart-85b1cc40-f23a-41aa-ab3e-e1f08aefb8e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117195931 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.117195931
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.299307832
Short name T753
Test name
Test status
Simulation time 134478253 ps
CPU time 2.21 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:52 PM PDT 24
Peak memory 198564 kb
Host smart-6d9874ac-5e43-4ebb-a025-7f6c5aa85dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299307832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.299307832
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1669484957
Short name T812
Test name
Test status
Simulation time 78265790 ps
CPU time 0.9 seconds
Started Aug 13 06:42:40 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 198216 kb
Host smart-962214e8-6835-4ae6-b7ac-3a72a0b0e50d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669484957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1669484957
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.420579998
Short name T738
Test name
Test status
Simulation time 205435157 ps
CPU time 0.85 seconds
Started Aug 13 06:42:47 PM PDT 24
Finished Aug 13 06:42:53 PM PDT 24
Peak memory 198356 kb
Host smart-6bf367be-b253-4e87-b2bc-0b9e722b1756
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420579998 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.420579998
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2421584457
Short name T109
Test name
Test status
Simulation time 15824027 ps
CPU time 0.62 seconds
Started Aug 13 06:42:44 PM PDT 24
Finished Aug 13 06:42:45 PM PDT 24
Peak memory 196044 kb
Host smart-d6443e85-2d30-4cab-a4e9-5a04c9cbba60
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421584457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2421584457
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3659981676
Short name T781
Test name
Test status
Simulation time 17362069 ps
CPU time 0.58 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:46 PM PDT 24
Peak memory 194328 kb
Host smart-e24bc45c-a587-468f-94df-515d86a79342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659981676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3659981676
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3472942023
Short name T102
Test name
Test status
Simulation time 117699889 ps
CPU time 0.87 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:46 PM PDT 24
Peak memory 197340 kb
Host smart-cebbf854-d6ac-40c2-9bbe-25c34e8bbd24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472942023 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3472942023
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.962987690
Short name T786
Test name
Test status
Simulation time 147388197 ps
CPU time 1.15 seconds
Started Aug 13 06:42:31 PM PDT 24
Finished Aug 13 06:42:32 PM PDT 24
Peak memory 198604 kb
Host smart-88a78b6c-1480-46f1-879b-240ca6c2138f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962987690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.962987690
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3537262102
Short name T754
Test name
Test status
Simulation time 118508508 ps
CPU time 1.35 seconds
Started Aug 13 06:42:33 PM PDT 24
Finished Aug 13 06:42:35 PM PDT 24
Peak memory 198580 kb
Host smart-e7accae0-858f-40cc-96d5-0f4f27e8cc35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537262102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3537262102
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3742441420
Short name T718
Test name
Test status
Simulation time 88551185 ps
CPU time 0.75 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:48 PM PDT 24
Peak memory 198216 kb
Host smart-0e38f26d-8280-4dfc-af0d-fe03acc86a9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742441420 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3742441420
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.317879058
Short name T94
Test name
Test status
Simulation time 22930493 ps
CPU time 0.62 seconds
Started Aug 13 06:42:48 PM PDT 24
Finished Aug 13 06:42:49 PM PDT 24
Peak memory 195264 kb
Host smart-644a8a8d-4456-4559-b114-ba33bdbfc1de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317879058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.317879058
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2779121955
Short name T727
Test name
Test status
Simulation time 26909028 ps
CPU time 0.61 seconds
Started Aug 13 06:42:41 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 194236 kb
Host smart-50cb5fa8-61ed-4a25-b139-90ad056c4bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779121955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2779121955
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3432420227
Short name T818
Test name
Test status
Simulation time 31206718 ps
CPU time 0.61 seconds
Started Aug 13 06:42:33 PM PDT 24
Finished Aug 13 06:42:34 PM PDT 24
Peak memory 195084 kb
Host smart-ff63035a-b107-48ad-90cc-d1d5515157a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432420227 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3432420227
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2183142375
Short name T790
Test name
Test status
Simulation time 169609582 ps
CPU time 1.3 seconds
Started Aug 13 06:42:36 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 198600 kb
Host smart-d8a7e2b1-955d-4bae-8915-69e1cdecd6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183142375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2183142375
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3185014239
Short name T741
Test name
Test status
Simulation time 22405283 ps
CPU time 0.75 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:46 PM PDT 24
Peak memory 198432 kb
Host smart-238e95e1-38a9-462a-ad69-84e2dffa1d5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185014239 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3185014239
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.724121766
Short name T84
Test name
Test status
Simulation time 29920544 ps
CPU time 0.63 seconds
Started Aug 13 06:42:38 PM PDT 24
Finished Aug 13 06:42:39 PM PDT 24
Peak memory 195180 kb
Host smart-e914b98b-b6be-4736-ad16-3220bdf9a159
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724121766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.724121766
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3883686871
Short name T772
Test name
Test status
Simulation time 128431636 ps
CPU time 0.63 seconds
Started Aug 13 06:42:41 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 194192 kb
Host smart-4500e5bc-00c5-4c98-b60b-b40ba32a4908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883686871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3883686871
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.4150444102
Short name T782
Test name
Test status
Simulation time 36221903 ps
CPU time 0.73 seconds
Started Aug 13 06:42:36 PM PDT 24
Finished Aug 13 06:42:36 PM PDT 24
Peak memory 195340 kb
Host smart-00831259-b2a4-4b77-8a1f-e50bb5c8f857
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150444102 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.4150444102
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.93251591
Short name T794
Test name
Test status
Simulation time 768261930 ps
CPU time 3.04 seconds
Started Aug 13 06:42:42 PM PDT 24
Finished Aug 13 06:42:45 PM PDT 24
Peak memory 198516 kb
Host smart-ac2c3bfa-764e-4b34-a4a1-2e936005d0df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93251591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.93251591
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2591391906
Short name T827
Test name
Test status
Simulation time 132592542 ps
CPU time 1.54 seconds
Started Aug 13 06:42:40 PM PDT 24
Finished Aug 13 06:42:42 PM PDT 24
Peak memory 198584 kb
Host smart-6bbb6025-94be-459a-ae5f-02a073bbcff4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591391906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2591391906
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2670486268
Short name T722
Test name
Test status
Simulation time 44712372 ps
CPU time 1.19 seconds
Started Aug 13 06:42:49 PM PDT 24
Finished Aug 13 06:42:50 PM PDT 24
Peak memory 198628 kb
Host smart-1b9d4e5d-d5a9-4506-a779-7340e22cad57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670486268 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2670486268
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4047167914
Short name T717
Test name
Test status
Simulation time 104777025 ps
CPU time 0.57 seconds
Started Aug 13 06:42:36 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 194424 kb
Host smart-fb9de028-91af-4c58-b07f-579c79ca7af9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047167914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.4047167914
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1386930566
Short name T720
Test name
Test status
Simulation time 14342995 ps
CPU time 0.6 seconds
Started Aug 13 06:42:49 PM PDT 24
Finished Aug 13 06:42:49 PM PDT 24
Peak memory 194240 kb
Host smart-23d7fcce-6951-49d6-9339-a1f4ea5a089d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386930566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1386930566
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2275516146
Short name T99
Test name
Test status
Simulation time 36066761 ps
CPU time 0.63 seconds
Started Aug 13 06:42:43 PM PDT 24
Finished Aug 13 06:42:44 PM PDT 24
Peak memory 194800 kb
Host smart-90488a05-1bd4-42cc-8a49-cfc2b6e1d917
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275516146 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2275516146
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3925265175
Short name T767
Test name
Test status
Simulation time 258659722 ps
CPU time 2.2 seconds
Started Aug 13 06:42:37 PM PDT 24
Finished Aug 13 06:42:39 PM PDT 24
Peak memory 198536 kb
Host smart-c44976b8-b21d-4c9b-b00a-90f18403710c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925265175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3925265175
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.976058233
Short name T773
Test name
Test status
Simulation time 169367479 ps
CPU time 0.87 seconds
Started Aug 13 06:42:44 PM PDT 24
Finished Aug 13 06:42:45 PM PDT 24
Peak memory 197460 kb
Host smart-ac77da64-c9f9-42b8-8865-e4b4e90a16a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976058233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.976058233
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.4190294053
Short name T832
Test name
Test status
Simulation time 36024369 ps
CPU time 1.6 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:42:55 PM PDT 24
Peak memory 198504 kb
Host smart-253332b2-b36e-4bbd-ab29-92d73d2abecd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190294053 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.4190294053
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2040689311
Short name T82
Test name
Test status
Simulation time 24771490 ps
CPU time 0.59 seconds
Started Aug 13 06:42:43 PM PDT 24
Finished Aug 13 06:42:43 PM PDT 24
Peak memory 195720 kb
Host smart-f9d966aa-a5ca-4d6f-af02-61635d0bb7f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040689311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2040689311
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3150252052
Short name T726
Test name
Test status
Simulation time 29135755 ps
CPU time 0.6 seconds
Started Aug 13 06:42:55 PM PDT 24
Finished Aug 13 06:43:01 PM PDT 24
Peak memory 194268 kb
Host smart-dd9066f7-073d-4366-b73b-448993da32e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150252052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3150252052
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2089176919
Short name T788
Test name
Test status
Simulation time 38076684 ps
CPU time 0.9 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:46 PM PDT 24
Peak memory 196836 kb
Host smart-89b1fd0b-776d-458b-8bb3-df65ff2003ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089176919 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2089176919
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.539746316
Short name T811
Test name
Test status
Simulation time 236639826 ps
CPU time 1.37 seconds
Started Aug 13 06:42:50 PM PDT 24
Finished Aug 13 06:42:51 PM PDT 24
Peak memory 198584 kb
Host smart-ce5c38e5-0900-484f-b912-9385e6f63e39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539746316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.539746316
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.4063207357
Short name T750
Test name
Test status
Simulation time 134616629 ps
CPU time 0.86 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:47 PM PDT 24
Peak memory 197536 kb
Host smart-9b073acd-577d-4360-9f6d-08991351bd99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063207357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.4063207357
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3347132701
Short name T766
Test name
Test status
Simulation time 73715278 ps
CPU time 0.93 seconds
Started Aug 13 06:42:37 PM PDT 24
Finished Aug 13 06:42:38 PM PDT 24
Peak memory 198376 kb
Host smart-0b9019fe-cdd4-46a4-908c-901c5f69a14e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347132701 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3347132701
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3203711294
Short name T83
Test name
Test status
Simulation time 59699633 ps
CPU time 0.58 seconds
Started Aug 13 06:42:47 PM PDT 24
Finished Aug 13 06:42:48 PM PDT 24
Peak memory 195240 kb
Host smart-2518c5b8-93ae-4538-8345-26614d0363f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203711294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3203711294
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2767208233
Short name T787
Test name
Test status
Simulation time 47881556 ps
CPU time 0.58 seconds
Started Aug 13 06:42:50 PM PDT 24
Finished Aug 13 06:42:50 PM PDT 24
Peak memory 194820 kb
Host smart-eefc27d7-91a8-4a08-9d8d-db6d00acc0f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767208233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2767208233
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2222739773
Short name T104
Test name
Test status
Simulation time 110712013 ps
CPU time 0.86 seconds
Started Aug 13 06:43:07 PM PDT 24
Finished Aug 13 06:43:08 PM PDT 24
Peak memory 196652 kb
Host smart-858dc019-a088-4de8-8766-b0d64edbd2e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222739773 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2222739773
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3885638010
Short name T759
Test name
Test status
Simulation time 257014489 ps
CPU time 1.59 seconds
Started Aug 13 06:42:48 PM PDT 24
Finished Aug 13 06:42:50 PM PDT 24
Peak memory 198580 kb
Host smart-a631d7e0-4d5a-4f20-81c8-c512527e5e22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885638010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3885638010
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1402783492
Short name T752
Test name
Test status
Simulation time 116322356 ps
CPU time 0.87 seconds
Started Aug 13 06:42:44 PM PDT 24
Finished Aug 13 06:42:45 PM PDT 24
Peak memory 198364 kb
Host smart-9b95398e-9647-430d-ac18-5436c27e9596
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402783492 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1402783492
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1046671123
Short name T91
Test name
Test status
Simulation time 12171609 ps
CPU time 0.6 seconds
Started Aug 13 06:42:47 PM PDT 24
Finished Aug 13 06:42:48 PM PDT 24
Peak memory 194856 kb
Host smart-80ee6613-5bef-4208-ba5b-279d0115a26c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046671123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1046671123
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2188115279
Short name T815
Test name
Test status
Simulation time 11553819 ps
CPU time 0.61 seconds
Started Aug 13 06:43:07 PM PDT 24
Finished Aug 13 06:43:08 PM PDT 24
Peak memory 194268 kb
Host smart-1f81fadd-130c-4ef8-ab16-cdc156990c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188115279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2188115279
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.394411953
Short name T785
Test name
Test status
Simulation time 117880512 ps
CPU time 0.83 seconds
Started Aug 13 06:42:48 PM PDT 24
Finished Aug 13 06:42:49 PM PDT 24
Peak memory 196464 kb
Host smart-a0effb5e-f242-4be8-9c70-baa43cfcd62a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394411953 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.394411953
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2666265252
Short name T723
Test name
Test status
Simulation time 191992559 ps
CPU time 1.86 seconds
Started Aug 13 06:42:47 PM PDT 24
Finished Aug 13 06:42:49 PM PDT 24
Peak memory 198572 kb
Host smart-e2689b38-bd31-4e04-82a7-4b8a5d6e0513
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666265252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2666265252
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1564853029
Short name T48
Test name
Test status
Simulation time 451658867 ps
CPU time 1.38 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:47 PM PDT 24
Peak memory 198520 kb
Host smart-0a6d3c6a-fac3-4842-8f21-86d8a7ab4723
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564853029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1564853029
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4263610328
Short name T89
Test name
Test status
Simulation time 30326234 ps
CPU time 0.8 seconds
Started Aug 13 06:42:40 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 196292 kb
Host smart-ab6bb56b-0774-4562-b1cc-d158aa9f33c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263610328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.4263610328
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3431347253
Short name T107
Test name
Test status
Simulation time 36806146 ps
CPU time 1.4 seconds
Started Aug 13 06:42:37 PM PDT 24
Finished Aug 13 06:42:38 PM PDT 24
Peak memory 198448 kb
Host smart-e94844f1-5f34-4a17-94e6-2f4bc0302463
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431347253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3431347253
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2795415393
Short name T92
Test name
Test status
Simulation time 18821685 ps
CPU time 0.64 seconds
Started Aug 13 06:42:35 PM PDT 24
Finished Aug 13 06:42:36 PM PDT 24
Peak memory 195156 kb
Host smart-20b98709-0ec9-4002-a0e9-0fee16d85e69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795415393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2795415393
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2604203926
Short name T721
Test name
Test status
Simulation time 28353792 ps
CPU time 0.67 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:47 PM PDT 24
Peak memory 198136 kb
Host smart-b2e15d61-8fe9-4c44-92b7-acdd90453912
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604203926 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2604203926
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.967689683
Short name T86
Test name
Test status
Simulation time 91696718 ps
CPU time 0.59 seconds
Started Aug 13 06:42:42 PM PDT 24
Finished Aug 13 06:42:43 PM PDT 24
Peak memory 194132 kb
Host smart-88021403-fdae-454e-94a9-359c70fcf14c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967689683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.967689683
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1118381434
Short name T729
Test name
Test status
Simulation time 21644370 ps
CPU time 0.56 seconds
Started Aug 13 06:42:36 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 194184 kb
Host smart-eedb5a2d-0916-4249-afc9-ae5c7162d268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118381434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1118381434
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.266744570
Short name T98
Test name
Test status
Simulation time 49740931 ps
CPU time 0.75 seconds
Started Aug 13 06:42:23 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 196644 kb
Host smart-7b0d14ca-6672-4779-9688-8e737f4abac2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266744570 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.266744570
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1575239367
Short name T770
Test name
Test status
Simulation time 103365500 ps
CPU time 2.01 seconds
Started Aug 13 06:42:41 PM PDT 24
Finished Aug 13 06:42:43 PM PDT 24
Peak memory 198604 kb
Host smart-2fbcfe87-e5ed-40ec-a7ff-9eda55860091
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575239367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1575239367
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1056870331
Short name T826
Test name
Test status
Simulation time 163469437 ps
CPU time 0.86 seconds
Started Aug 13 06:42:44 PM PDT 24
Finished Aug 13 06:42:45 PM PDT 24
Peak memory 197648 kb
Host smart-9f35027c-8892-4a0d-8f38-f0d8406a0859
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056870331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1056870331
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3789218599
Short name T762
Test name
Test status
Simulation time 11736079 ps
CPU time 0.6 seconds
Started Aug 13 06:42:48 PM PDT 24
Finished Aug 13 06:42:48 PM PDT 24
Peak memory 194828 kb
Host smart-3a3ec449-ce42-43c7-b3e2-8be6207390b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789218599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3789218599
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2726560341
Short name T733
Test name
Test status
Simulation time 25755582 ps
CPU time 0.6 seconds
Started Aug 13 06:42:54 PM PDT 24
Finished Aug 13 06:42:54 PM PDT 24
Peak memory 194844 kb
Host smart-c61ed076-573e-41e1-aa38-29c314a8a815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726560341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2726560341
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4120287876
Short name T814
Test name
Test status
Simulation time 81774600 ps
CPU time 0.57 seconds
Started Aug 13 06:42:54 PM PDT 24
Finished Aug 13 06:42:54 PM PDT 24
Peak memory 194576 kb
Host smart-42f93ba7-f6db-4c3f-a652-a8cb6e71741b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120287876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4120287876
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2257795091
Short name T743
Test name
Test status
Simulation time 55461960 ps
CPU time 0.64 seconds
Started Aug 13 06:42:43 PM PDT 24
Finished Aug 13 06:42:44 PM PDT 24
Peak memory 194900 kb
Host smart-cc09e6cb-41ac-455f-9e13-4ebc0972f25f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257795091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2257795091
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.319416098
Short name T761
Test name
Test status
Simulation time 43100939 ps
CPU time 0.58 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:47 PM PDT 24
Peak memory 194240 kb
Host smart-38c5006a-d13a-49f8-8a4a-95eb8132857a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319416098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.319416098
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3160539460
Short name T724
Test name
Test status
Simulation time 47562603 ps
CPU time 0.62 seconds
Started Aug 13 06:42:49 PM PDT 24
Finished Aug 13 06:42:49 PM PDT 24
Peak memory 194204 kb
Host smart-e02e668d-7f0a-404b-8b51-b5a05702699c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160539460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3160539460
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2245672361
Short name T795
Test name
Test status
Simulation time 12347657 ps
CPU time 0.57 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:42:53 PM PDT 24
Peak memory 194188 kb
Host smart-79d23e93-c75b-4a07-b14e-a8b5cc8df963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245672361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2245672361
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3660974815
Short name T771
Test name
Test status
Simulation time 22856269 ps
CPU time 0.64 seconds
Started Aug 13 06:43:16 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 194276 kb
Host smart-b48a5ee8-21fb-4b43-abe8-cb629dbbe215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660974815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3660974815
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.728210328
Short name T833
Test name
Test status
Simulation time 63484455 ps
CPU time 0.6 seconds
Started Aug 13 06:42:54 PM PDT 24
Finished Aug 13 06:42:55 PM PDT 24
Peak memory 194928 kb
Host smart-36c21e92-ea68-4e88-a3a6-a8c135e0843e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728210328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.728210328
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2529552712
Short name T747
Test name
Test status
Simulation time 26935813 ps
CPU time 0.59 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:42:54 PM PDT 24
Peak memory 194160 kb
Host smart-406611b6-e4c3-4f71-bd2a-e454cdf392d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529552712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2529552712
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3238714751
Short name T90
Test name
Test status
Simulation time 58482817 ps
CPU time 0.67 seconds
Started Aug 13 06:42:39 PM PDT 24
Finished Aug 13 06:42:39 PM PDT 24
Peak memory 194868 kb
Host smart-9dd11025-c6a1-4a65-ad3d-2b3e0ccba0c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238714751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3238714751
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.394023826
Short name T80
Test name
Test status
Simulation time 262324491 ps
CPU time 3.19 seconds
Started Aug 13 06:42:30 PM PDT 24
Finished Aug 13 06:42:34 PM PDT 24
Peak memory 197600 kb
Host smart-54ed565e-ce1b-45b2-89fa-0408fd075b91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394023826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.394023826
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1381984654
Short name T822
Test name
Test status
Simulation time 31539744 ps
CPU time 0.64 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:25 PM PDT 24
Peak memory 195376 kb
Host smart-af52eaf0-d6fe-4f66-ac52-9b9a583b6c12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381984654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1381984654
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1272486539
Short name T808
Test name
Test status
Simulation time 27592971 ps
CPU time 0.9 seconds
Started Aug 13 06:42:23 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 198412 kb
Host smart-0788ad48-03fd-48a9-99f8-3aa875eb3055
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272486539 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1272486539
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1360118423
Short name T829
Test name
Test status
Simulation time 39076791 ps
CPU time 0.62 seconds
Started Aug 13 06:42:33 PM PDT 24
Finished Aug 13 06:42:34 PM PDT 24
Peak memory 193792 kb
Host smart-13b066ad-51bf-48c3-9f27-bd7119facb6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360118423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1360118423
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3878006905
Short name T755
Test name
Test status
Simulation time 42942473 ps
CPU time 0.61 seconds
Started Aug 13 06:42:17 PM PDT 24
Finished Aug 13 06:42:18 PM PDT 24
Peak memory 194168 kb
Host smart-b148e313-9d17-45c1-9b0b-1c0d8dd1f06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878006905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3878006905
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1119939126
Short name T105
Test name
Test status
Simulation time 17229582 ps
CPU time 0.85 seconds
Started Aug 13 06:42:20 PM PDT 24
Finished Aug 13 06:42:21 PM PDT 24
Peak memory 197416 kb
Host smart-6b87b2df-29f4-427e-9f54-ae66403eb380
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119939126 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1119939126
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.51200270
Short name T725
Test name
Test status
Simulation time 146555785 ps
CPU time 3.01 seconds
Started Aug 13 06:42:40 PM PDT 24
Finished Aug 13 06:42:43 PM PDT 24
Peak memory 198548 kb
Host smart-0323a40a-2abe-47e2-8420-8e4cd15882d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51200270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.51200270
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1387282878
Short name T52
Test name
Test status
Simulation time 186606364 ps
CPU time 0.85 seconds
Started Aug 13 06:42:21 PM PDT 24
Finished Aug 13 06:42:22 PM PDT 24
Peak memory 197740 kb
Host smart-3337e017-8122-4231-936f-776dc6e4400a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387282878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1387282878
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3077366641
Short name T728
Test name
Test status
Simulation time 10708349 ps
CPU time 0.55 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:42:52 PM PDT 24
Peak memory 194232 kb
Host smart-5021af12-159d-4114-97bf-7d7c1fb3fdd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077366641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3077366641
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.295106811
Short name T809
Test name
Test status
Simulation time 28701944 ps
CPU time 0.65 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:42:54 PM PDT 24
Peak memory 194276 kb
Host smart-60d5c07a-00c9-4f90-91b7-bd2ab8206fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295106811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.295106811
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1640766699
Short name T757
Test name
Test status
Simulation time 41174721 ps
CPU time 0.62 seconds
Started Aug 13 06:43:13 PM PDT 24
Finished Aug 13 06:43:14 PM PDT 24
Peak memory 194312 kb
Host smart-16b9ee5c-99c5-492b-a908-c5b71c360a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640766699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1640766699
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2058998133
Short name T775
Test name
Test status
Simulation time 25809688 ps
CPU time 0.56 seconds
Started Aug 13 06:42:54 PM PDT 24
Finished Aug 13 06:42:54 PM PDT 24
Peak memory 193812 kb
Host smart-7dfdb019-4dcf-4465-b21f-27f6a98c9bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058998133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2058998133
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.315154687
Short name T765
Test name
Test status
Simulation time 17283032 ps
CPU time 0.62 seconds
Started Aug 13 06:43:10 PM PDT 24
Finished Aug 13 06:43:11 PM PDT 24
Peak memory 194288 kb
Host smart-292bc086-7d02-4ec6-925c-1459fb6f08b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315154687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.315154687
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3220788664
Short name T760
Test name
Test status
Simulation time 31746986 ps
CPU time 0.56 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:18 PM PDT 24
Peak memory 194096 kb
Host smart-4ad9c960-2879-4a4f-8ba7-c6fb0b861c82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220788664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3220788664
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2448596915
Short name T716
Test name
Test status
Simulation time 179201670 ps
CPU time 0.59 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:42:51 PM PDT 24
Peak memory 194876 kb
Host smart-f9e64067-4d15-4595-9603-06c4ca8122a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448596915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2448596915
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.721842609
Short name T734
Test name
Test status
Simulation time 11362156 ps
CPU time 0.57 seconds
Started Aug 13 06:42:59 PM PDT 24
Finished Aug 13 06:42:59 PM PDT 24
Peak memory 194204 kb
Host smart-e6132591-0ed0-4776-a86f-fe78fcd73fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721842609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.721842609
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.545617899
Short name T816
Test name
Test status
Simulation time 19149055 ps
CPU time 0.6 seconds
Started Aug 13 06:42:47 PM PDT 24
Finished Aug 13 06:42:48 PM PDT 24
Peak memory 194220 kb
Host smart-df286470-7675-4914-95b2-b9971df2a9ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545617899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.545617899
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.512519704
Short name T820
Test name
Test status
Simulation time 14811755 ps
CPU time 0.58 seconds
Started Aug 13 06:42:47 PM PDT 24
Finished Aug 13 06:42:48 PM PDT 24
Peak memory 194144 kb
Host smart-fd954b60-3371-468a-b075-0a2a0c594e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512519704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.512519704
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1770208819
Short name T95
Test name
Test status
Simulation time 37860084 ps
CPU time 0.86 seconds
Started Aug 13 06:42:28 PM PDT 24
Finished Aug 13 06:42:29 PM PDT 24
Peak memory 196596 kb
Host smart-df5bcf67-f002-4096-a656-748ce41f662a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770208819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1770208819
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1469299299
Short name T783
Test name
Test status
Simulation time 302903442 ps
CPU time 1.36 seconds
Started Aug 13 06:42:19 PM PDT 24
Finished Aug 13 06:42:20 PM PDT 24
Peak memory 197340 kb
Host smart-d2f487bf-f1a0-4509-a4e5-e3adf29a579c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469299299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1469299299
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3844299301
Short name T81
Test name
Test status
Simulation time 14942225 ps
CPU time 0.6 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:46 PM PDT 24
Peak memory 195056 kb
Host smart-20301119-9f97-4b81-a159-c1a59f486b51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844299301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3844299301
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1653176224
Short name T778
Test name
Test status
Simulation time 36789107 ps
CPU time 1.57 seconds
Started Aug 13 06:42:31 PM PDT 24
Finished Aug 13 06:42:33 PM PDT 24
Peak memory 198532 kb
Host smart-ce0656d0-2d70-4951-982d-1ca73322a852
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653176224 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1653176224
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.789715743
Short name T110
Test name
Test status
Simulation time 18710335 ps
CPU time 0.61 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:25 PM PDT 24
Peak memory 194364 kb
Host smart-96362ca6-af45-4be4-aef3-354e7183bc5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789715743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.789715743
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1127642574
Short name T735
Test name
Test status
Simulation time 22340559 ps
CPU time 0.64 seconds
Started Aug 13 06:42:44 PM PDT 24
Finished Aug 13 06:42:45 PM PDT 24
Peak memory 194908 kb
Host smart-e1d6ced9-05c3-4742-b664-6cda5010fd28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127642574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1127642574
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3103068312
Short name T806
Test name
Test status
Simulation time 25751198 ps
CPU time 0.74 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:46 PM PDT 24
Peak memory 197224 kb
Host smart-9cfdae05-9d16-44e5-96b9-003fa6758403
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103068312 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3103068312
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1727028298
Short name T784
Test name
Test status
Simulation time 905074710 ps
CPU time 2.17 seconds
Started Aug 13 06:42:34 PM PDT 24
Finished Aug 13 06:42:36 PM PDT 24
Peak memory 198596 kb
Host smart-c5e70e68-2ffa-4ab2-a9d2-785d9ae4cee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727028298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1727028298
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2170205913
Short name T800
Test name
Test status
Simulation time 229999671 ps
CPU time 1.41 seconds
Started Aug 13 06:42:43 PM PDT 24
Finished Aug 13 06:42:44 PM PDT 24
Peak memory 198484 kb
Host smart-c434adc2-5c4c-47ce-8ed5-a760a03bc4a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170205913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2170205913
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1525392960
Short name T746
Test name
Test status
Simulation time 30942769 ps
CPU time 0.59 seconds
Started Aug 13 06:42:58 PM PDT 24
Finished Aug 13 06:42:58 PM PDT 24
Peak memory 194212 kb
Host smart-87776c86-f49a-4003-abcb-184d206cd4f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525392960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1525392960
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.4222300035
Short name T807
Test name
Test status
Simulation time 13774375 ps
CPU time 0.64 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:42:51 PM PDT 24
Peak memory 194920 kb
Host smart-4b37558b-238d-4ab3-b09c-2cfaec920d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222300035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.4222300035
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1169244440
Short name T777
Test name
Test status
Simulation time 38292233 ps
CPU time 0.56 seconds
Started Aug 13 06:42:55 PM PDT 24
Finished Aug 13 06:42:55 PM PDT 24
Peak memory 194212 kb
Host smart-dff0de51-2d1f-4476-8496-d3cbb1bba1f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169244440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1169244440
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3931175197
Short name T796
Test name
Test status
Simulation time 17309329 ps
CPU time 0.62 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:42:51 PM PDT 24
Peak memory 194892 kb
Host smart-ffb5c185-3cf5-4917-b477-e25beeb6bba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931175197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3931175197
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1135777087
Short name T819
Test name
Test status
Simulation time 13610921 ps
CPU time 0.6 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:47 PM PDT 24
Peak memory 194232 kb
Host smart-469036ec-6795-479f-a4d8-0872a3fceb58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135777087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1135777087
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2268411012
Short name T793
Test name
Test status
Simulation time 41729155 ps
CPU time 0.6 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:47 PM PDT 24
Peak memory 194268 kb
Host smart-46ed0b06-ad4b-4309-9908-fe0430fa78ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268411012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2268411012
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1248984647
Short name T764
Test name
Test status
Simulation time 12429230 ps
CPU time 0.58 seconds
Started Aug 13 06:42:56 PM PDT 24
Finished Aug 13 06:42:57 PM PDT 24
Peak memory 194088 kb
Host smart-704bdb08-f121-499a-8afb-169d079c6e1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248984647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1248984647
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1699658704
Short name T768
Test name
Test status
Simulation time 33460666 ps
CPU time 0.63 seconds
Started Aug 13 06:42:43 PM PDT 24
Finished Aug 13 06:42:43 PM PDT 24
Peak memory 194252 kb
Host smart-8360e50c-c1e4-4a3c-aebe-7162690c15a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699658704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1699658704
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1896274405
Short name T739
Test name
Test status
Simulation time 70573020 ps
CPU time 0.65 seconds
Started Aug 13 06:42:59 PM PDT 24
Finished Aug 13 06:42:59 PM PDT 24
Peak memory 194260 kb
Host smart-2dc3a2e4-e227-41db-b7d4-01f58dd0e142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896274405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1896274405
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1211376351
Short name T740
Test name
Test status
Simulation time 64214967 ps
CPU time 0.61 seconds
Started Aug 13 06:42:43 PM PDT 24
Finished Aug 13 06:42:44 PM PDT 24
Peak memory 194224 kb
Host smart-40374fe0-8c91-4791-87ad-30ece479e280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211376351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1211376351
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2331296861
Short name T748
Test name
Test status
Simulation time 39806561 ps
CPU time 1.01 seconds
Started Aug 13 06:42:36 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 198312 kb
Host smart-03da9c03-4aaf-42d0-b4a7-20bb6760d75f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331296861 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2331296861
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1868360072
Short name T824
Test name
Test status
Simulation time 12729429 ps
CPU time 0.61 seconds
Started Aug 13 06:42:18 PM PDT 24
Finished Aug 13 06:42:19 PM PDT 24
Peak memory 195744 kb
Host smart-db57ba07-2191-4528-bc40-4ead07856ace
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868360072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1868360072
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3448044734
Short name T769
Test name
Test status
Simulation time 47263071 ps
CPU time 0.6 seconds
Started Aug 13 06:42:33 PM PDT 24
Finished Aug 13 06:42:34 PM PDT 24
Peak memory 194172 kb
Host smart-7188d22d-bba2-49b2-ad73-38915cd0511c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448044734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3448044734
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.503470864
Short name T106
Test name
Test status
Simulation time 129172643 ps
CPU time 0.88 seconds
Started Aug 13 06:42:32 PM PDT 24
Finished Aug 13 06:42:33 PM PDT 24
Peak memory 196656 kb
Host smart-0e92ee3f-eca4-44a0-baa5-f52918bef341
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503470864 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.503470864
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2482531341
Short name T730
Test name
Test status
Simulation time 37768462 ps
CPU time 1.66 seconds
Started Aug 13 06:42:33 PM PDT 24
Finished Aug 13 06:42:35 PM PDT 24
Peak memory 198528 kb
Host smart-961a5476-300c-4701-bf66-2390e353f72b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482531341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2482531341
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2938520422
Short name T49
Test name
Test status
Simulation time 82998900 ps
CPU time 1.17 seconds
Started Aug 13 06:42:40 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 198540 kb
Host smart-8cacb477-a9d4-4e65-b3a8-acb5d116dfea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938520422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2938520422
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1187831124
Short name T802
Test name
Test status
Simulation time 146984501 ps
CPU time 1.75 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:26 PM PDT 24
Peak memory 198616 kb
Host smart-4c0f26a9-c262-4126-88e3-95116193033d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187831124 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1187831124
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3953318650
Short name T817
Test name
Test status
Simulation time 43788516 ps
CPU time 0.6 seconds
Started Aug 13 06:42:43 PM PDT 24
Finished Aug 13 06:42:43 PM PDT 24
Peak memory 195196 kb
Host smart-be93cba2-9b76-42d7-a59a-c1ad743a9b35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953318650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3953318650
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1926559030
Short name T745
Test name
Test status
Simulation time 30820244 ps
CPU time 0.59 seconds
Started Aug 13 06:42:44 PM PDT 24
Finished Aug 13 06:42:45 PM PDT 24
Peak memory 194308 kb
Host smart-ff3b870f-4fe2-45a4-8004-a46acb0553fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926559030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1926559030
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3981665921
Short name T810
Test name
Test status
Simulation time 112499980 ps
CPU time 0.81 seconds
Started Aug 13 06:42:30 PM PDT 24
Finished Aug 13 06:42:31 PM PDT 24
Peak memory 196672 kb
Host smart-271436f6-dc8b-4596-9d0d-97f82a609e65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981665921 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3981665921
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.480576027
Short name T836
Test name
Test status
Simulation time 64019238 ps
CPU time 3.23 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:29 PM PDT 24
Peak memory 198560 kb
Host smart-ffea5732-7a27-40f4-9b1e-b1b19252aad9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480576027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.480576027
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3677197006
Short name T803
Test name
Test status
Simulation time 162214030 ps
CPU time 0.81 seconds
Started Aug 13 06:42:44 PM PDT 24
Finished Aug 13 06:42:45 PM PDT 24
Peak memory 197560 kb
Host smart-340681bc-4cf9-4e49-9469-906db9c5e2fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677197006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3677197006
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.697835524
Short name T751
Test name
Test status
Simulation time 50387262 ps
CPU time 0.71 seconds
Started Aug 13 06:42:36 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 198140 kb
Host smart-96068f71-242d-4461-8d6c-68ee75bd7987
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697835524 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.697835524
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.4161522199
Short name T732
Test name
Test status
Simulation time 24539342 ps
CPU time 0.59 seconds
Started Aug 13 06:42:32 PM PDT 24
Finished Aug 13 06:42:33 PM PDT 24
Peak memory 194992 kb
Host smart-a6b2c3a1-588c-4546-9176-5f69f2f10b7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161522199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.4161522199
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1774429249
Short name T828
Test name
Test status
Simulation time 18973051 ps
CPU time 0.59 seconds
Started Aug 13 06:42:19 PM PDT 24
Finished Aug 13 06:42:19 PM PDT 24
Peak memory 194156 kb
Host smart-a6dfc177-d38c-4580-91d8-3d46a7ee892e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774429249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1774429249
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3130991145
Short name T825
Test name
Test status
Simulation time 32139977 ps
CPU time 0.82 seconds
Started Aug 13 06:42:27 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 196864 kb
Host smart-1f326afc-54b2-43a5-a8ee-5e85c37e837d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130991145 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3130991145
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2827807236
Short name T830
Test name
Test status
Simulation time 162403013 ps
CPU time 3.38 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:49 PM PDT 24
Peak memory 198564 kb
Host smart-33da0c68-fd97-4a06-b97f-6d72eeeb087d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827807236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2827807236
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4237487768
Short name T791
Test name
Test status
Simulation time 92131693 ps
CPU time 1.08 seconds
Started Aug 13 06:42:24 PM PDT 24
Finished Aug 13 06:42:25 PM PDT 24
Peak memory 198508 kb
Host smart-62b7bfec-bf03-49c6-9db1-0d19a695a85c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237487768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.4237487768
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3766051816
Short name T763
Test name
Test status
Simulation time 70298826 ps
CPU time 0.9 seconds
Started Aug 13 06:42:40 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 198436 kb
Host smart-b646dfcd-afe1-4fb6-8258-3ecb8c328520
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766051816 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3766051816
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.806396368
Short name T774
Test name
Test status
Simulation time 41808363 ps
CPU time 0.58 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:47 PM PDT 24
Peak memory 194380 kb
Host smart-3a22373b-1ada-45c8-94c0-d756b84a831d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806396368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.806396368
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3312628929
Short name T831
Test name
Test status
Simulation time 108625472 ps
CPU time 0.57 seconds
Started Aug 13 06:42:41 PM PDT 24
Finished Aug 13 06:42:42 PM PDT 24
Peak memory 194168 kb
Host smart-d5cf8edf-28c7-4045-b807-d1b5fec5ec96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312628929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3312628929
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2177233263
Short name T103
Test name
Test status
Simulation time 56082321 ps
CPU time 0.85 seconds
Started Aug 13 06:42:33 PM PDT 24
Finished Aug 13 06:42:34 PM PDT 24
Peak memory 196828 kb
Host smart-0a854171-ecec-4fbd-8845-3ccf659f929c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177233263 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2177233263
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2996513114
Short name T742
Test name
Test status
Simulation time 117861693 ps
CPU time 1.36 seconds
Started Aug 13 06:42:23 PM PDT 24
Finished Aug 13 06:42:24 PM PDT 24
Peak memory 198524 kb
Host smart-dcc623f7-a5d7-42c6-89ac-ab01befaea2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996513114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2996513114
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1420026694
Short name T55
Test name
Test status
Simulation time 371492482 ps
CPU time 1.36 seconds
Started Aug 13 06:42:26 PM PDT 24
Finished Aug 13 06:42:28 PM PDT 24
Peak memory 198556 kb
Host smart-c7b9a522-02bb-42a4-9d09-ff0dfba7fc31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420026694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1420026694
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.667642931
Short name T798
Test name
Test status
Simulation time 19120522 ps
CPU time 0.7 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:46 PM PDT 24
Peak memory 198328 kb
Host smart-881646dd-b26c-4787-bd90-3d94d36ef0ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667642931 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.667642931
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1379302017
Short name T799
Test name
Test status
Simulation time 18887390 ps
CPU time 0.59 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:45 PM PDT 24
Peak memory 194432 kb
Host smart-6016b51f-f88f-4242-9697-1621cbad0889
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379302017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1379302017
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2987482805
Short name T737
Test name
Test status
Simulation time 14220758 ps
CPU time 0.58 seconds
Started Aug 13 06:42:42 PM PDT 24
Finished Aug 13 06:42:43 PM PDT 24
Peak memory 194892 kb
Host smart-5384f3ca-5011-4666-83f1-461a605b58e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987482805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2987482805
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1518061374
Short name T101
Test name
Test status
Simulation time 172022376 ps
CPU time 0.72 seconds
Started Aug 13 06:42:43 PM PDT 24
Finished Aug 13 06:42:44 PM PDT 24
Peak memory 197292 kb
Host smart-eee4812c-bc40-4306-8f42-bd022f998dba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518061374 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1518061374
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2164243533
Short name T758
Test name
Test status
Simulation time 442150975 ps
CPU time 2.66 seconds
Started Aug 13 06:42:36 PM PDT 24
Finished Aug 13 06:42:39 PM PDT 24
Peak memory 198620 kb
Host smart-305eb051-f435-41b3-913d-0279644d817d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164243533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2164243533
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.792806981
Short name T113
Test name
Test status
Simulation time 48863715 ps
CPU time 0.92 seconds
Started Aug 13 06:42:54 PM PDT 24
Finished Aug 13 06:42:55 PM PDT 24
Peak memory 197596 kb
Host smart-5103e4e3-0ed6-4624-9399-20f0e0a000a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792806981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.792806981
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2540143318
Short name T447
Test name
Test status
Simulation time 147105972 ps
CPU time 0.83 seconds
Started Aug 13 04:59:31 PM PDT 24
Finished Aug 13 04:59:32 PM PDT 24
Peak memory 196968 kb
Host smart-e36ff879-4d45-42a3-b0f6-ef75372f8053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540143318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2540143318
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2720060015
Short name T374
Test name
Test status
Simulation time 619247233 ps
CPU time 16.66 seconds
Started Aug 13 04:59:17 PM PDT 24
Finished Aug 13 04:59:34 PM PDT 24
Peak memory 198184 kb
Host smart-810f43c6-0e69-47b9-9837-e251c8ed94de
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720060015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2720060015
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2589921166
Short name T187
Test name
Test status
Simulation time 252927802 ps
CPU time 0.79 seconds
Started Aug 13 04:59:16 PM PDT 24
Finished Aug 13 04:59:17 PM PDT 24
Peak memory 196584 kb
Host smart-4956d337-f716-4ebb-b0f0-cba147f9cadb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589921166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2589921166
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.307440321
Short name T654
Test name
Test status
Simulation time 46441015 ps
CPU time 1.19 seconds
Started Aug 13 04:59:30 PM PDT 24
Finished Aug 13 04:59:32 PM PDT 24
Peak memory 196608 kb
Host smart-34112702-7fa5-4b1a-97a5-ef5009418c00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307440321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.307440321
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3052831838
Short name T701
Test name
Test status
Simulation time 168287349 ps
CPU time 1.47 seconds
Started Aug 13 04:59:30 PM PDT 24
Finished Aug 13 04:59:32 PM PDT 24
Peak memory 196276 kb
Host smart-cb83a8df-7361-4f62-b140-94b982266ebd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052831838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3052831838
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.181933696
Short name T333
Test name
Test status
Simulation time 34130356 ps
CPU time 1.16 seconds
Started Aug 13 04:59:30 PM PDT 24
Finished Aug 13 04:59:31 PM PDT 24
Peak memory 196704 kb
Host smart-04c990a1-89b1-4558-9575-e8209657bb56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181933696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.181933696
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.234644463
Short name T328
Test name
Test status
Simulation time 124153826 ps
CPU time 0.87 seconds
Started Aug 13 04:59:31 PM PDT 24
Finished Aug 13 04:59:32 PM PDT 24
Peak memory 195788 kb
Host smart-c604f068-a669-40e0-8434-46b99af51936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234644463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.234644463
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.125156143
Short name T189
Test name
Test status
Simulation time 28816267 ps
CPU time 1.07 seconds
Started Aug 13 04:59:11 PM PDT 24
Finished Aug 13 04:59:13 PM PDT 24
Peak memory 197216 kb
Host smart-ec48425f-d50d-4877-819f-1c347b71dcdf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125156143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.125156143
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1192826046
Short name T487
Test name
Test status
Simulation time 114006458 ps
CPU time 1.63 seconds
Started Aug 13 04:59:19 PM PDT 24
Finished Aug 13 04:59:20 PM PDT 24
Peak memory 198016 kb
Host smart-6ecdf764-3e58-4fe4-bdba-608a3369fa3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192826046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1192826046
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1451452876
Short name T54
Test name
Test status
Simulation time 59195526 ps
CPU time 0.85 seconds
Started Aug 13 04:59:17 PM PDT 24
Finished Aug 13 04:59:17 PM PDT 24
Peak memory 212900 kb
Host smart-26797df6-87d4-44e3-91f3-4d7eb258c366
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451452876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1451452876
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.362971809
Short name T372
Test name
Test status
Simulation time 70534354 ps
CPU time 1.2 seconds
Started Aug 13 04:59:16 PM PDT 24
Finished Aug 13 04:59:18 PM PDT 24
Peak memory 196596 kb
Host smart-a33462b9-36da-49c2-b3ca-f7b272160acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362971809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.362971809
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1737333958
Short name T301
Test name
Test status
Simulation time 83904174 ps
CPU time 1.29 seconds
Started Aug 13 04:59:17 PM PDT 24
Finished Aug 13 04:59:18 PM PDT 24
Peak memory 196004 kb
Host smart-2ba44df8-acd4-4975-a94b-67f6eb9e6e50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737333958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1737333958
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3650231738
Short name T481
Test name
Test status
Simulation time 17873818632 ps
CPU time 112.94 seconds
Started Aug 13 04:59:16 PM PDT 24
Finished Aug 13 05:01:09 PM PDT 24
Peak memory 198276 kb
Host smart-5faa27cb-8387-43a3-8545-357a60158e55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650231738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3650231738
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3897987754
Short name T66
Test name
Test status
Simulation time 3762156354 ps
CPU time 53.33 seconds
Started Aug 13 04:59:18 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 198408 kb
Host smart-6f417372-38d7-454f-ba29-3225b56d0bf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3897987754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3897987754
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.768579131
Short name T261
Test name
Test status
Simulation time 21598087 ps
CPU time 0.55 seconds
Started Aug 13 04:59:20 PM PDT 24
Finished Aug 13 04:59:21 PM PDT 24
Peak memory 194028 kb
Host smart-6ece299f-7898-44cf-8b8a-7448d93a4636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768579131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.768579131
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3095375635
Short name T350
Test name
Test status
Simulation time 40041894 ps
CPU time 0.81 seconds
Started Aug 13 04:59:21 PM PDT 24
Finished Aug 13 04:59:22 PM PDT 24
Peak memory 195460 kb
Host smart-1d8023e3-8d19-4bde-a7a9-7fed17674b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095375635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3095375635
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.564290615
Short name T574
Test name
Test status
Simulation time 1772180089 ps
CPU time 19.79 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 04:59:41 PM PDT 24
Peak memory 196976 kb
Host smart-f1040141-baa3-474a-9687-e4a30d3fd9ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564290615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.564290615
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2286375387
Short name T321
Test name
Test status
Simulation time 155420888 ps
CPU time 0.78 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 04:59:23 PM PDT 24
Peak memory 195752 kb
Host smart-45ebdcc4-087f-490e-9339-d10c63be4900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286375387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2286375387
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.502654001
Short name T129
Test name
Test status
Simulation time 80850849 ps
CPU time 1.15 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 04:59:24 PM PDT 24
Peak memory 196328 kb
Host smart-cc8049bd-c71b-4d95-a2f4-2b60864d394a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502654001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.502654001
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1310400746
Short name T368
Test name
Test status
Simulation time 47769042 ps
CPU time 1.92 seconds
Started Aug 13 04:59:21 PM PDT 24
Finished Aug 13 04:59:23 PM PDT 24
Peak memory 198112 kb
Host smart-bb3cc7ed-ea1c-4098-9639-b499dc30116d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310400746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1310400746
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.839956146
Short name T586
Test name
Test status
Simulation time 70201278 ps
CPU time 1.62 seconds
Started Aug 13 04:59:21 PM PDT 24
Finished Aug 13 04:59:23 PM PDT 24
Peak memory 196904 kb
Host smart-c9ce1f65-acc9-4528-a205-de29a961aca7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839956146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.839956146
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.276895102
Short name T552
Test name
Test status
Simulation time 43884743 ps
CPU time 0.89 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 04:59:23 PM PDT 24
Peak memory 196076 kb
Host smart-9df4039b-35e4-4ec5-b565-f34585f88df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276895102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.276895102
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2253581290
Short name T78
Test name
Test status
Simulation time 254862273 ps
CPU time 1.35 seconds
Started Aug 13 04:59:20 PM PDT 24
Finished Aug 13 04:59:22 PM PDT 24
Peak memory 197476 kb
Host smart-bf0cdf94-ebdb-4077-b8c1-990ed1af7d65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253581290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2253581290
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2149072596
Short name T9
Test name
Test status
Simulation time 511600732 ps
CPU time 5.74 seconds
Started Aug 13 04:59:23 PM PDT 24
Finished Aug 13 04:59:29 PM PDT 24
Peak memory 198012 kb
Host smart-91ce3407-3edd-4449-85d8-dd5a343d36c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149072596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2149072596
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.3619717464
Short name T444
Test name
Test status
Simulation time 89478613 ps
CPU time 1.38 seconds
Started Aug 13 04:59:25 PM PDT 24
Finished Aug 13 04:59:26 PM PDT 24
Peak memory 195684 kb
Host smart-7f4f4ba5-4337-4186-92cb-28789fbd7a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619717464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3619717464
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.550562002
Short name T484
Test name
Test status
Simulation time 33635672 ps
CPU time 0.8 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 04:59:23 PM PDT 24
Peak memory 195204 kb
Host smart-7ddc53d0-29dd-4eb7-adaa-6fbd9204ba91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550562002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.550562002
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.4051661065
Short name T622
Test name
Test status
Simulation time 20645313556 ps
CPU time 78.19 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 05:00:40 PM PDT 24
Peak memory 198276 kb
Host smart-25aa2351-f115-4549-b4f0-15f8452abcfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051661065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.4051661065
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3593358660
Short name T493
Test name
Test status
Simulation time 14911451 ps
CPU time 0.6 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:49 PM PDT 24
Peak memory 194004 kb
Host smart-838e0792-32f9-4179-bc46-45891d9ad518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593358660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3593358660
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3063901326
Short name T638
Test name
Test status
Simulation time 41501404 ps
CPU time 0.75 seconds
Started Aug 13 04:59:47 PM PDT 24
Finished Aug 13 04:59:48 PM PDT 24
Peak memory 195184 kb
Host smart-427a7062-b3fe-4313-9994-e7fd61a8dc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063901326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3063901326
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2392910936
Short name T658
Test name
Test status
Simulation time 287156386 ps
CPU time 10.67 seconds
Started Aug 13 04:59:47 PM PDT 24
Finished Aug 13 04:59:58 PM PDT 24
Peak memory 197032 kb
Host smart-ba12a900-7463-498a-967b-473ae49f9b02
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392910936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2392910936
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3683937276
Short name T547
Test name
Test status
Simulation time 92960797 ps
CPU time 1.05 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 196644 kb
Host smart-cb0cf199-dad3-45dc-adc0-97031ea6ef09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683937276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3683937276
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.468174845
Short name T174
Test name
Test status
Simulation time 91879718 ps
CPU time 1.53 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:51 PM PDT 24
Peak memory 197444 kb
Host smart-06014862-3407-49d2-b95a-bf7bd073d9d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468174845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.468174845
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3999127178
Short name T399
Test name
Test status
Simulation time 253933703 ps
CPU time 2.22 seconds
Started Aug 13 04:59:51 PM PDT 24
Finished Aug 13 04:59:54 PM PDT 24
Peak memory 196480 kb
Host smart-ae47c584-1230-4d24-b3cd-69475a16c648
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999127178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3999127178
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2409477738
Short name T272
Test name
Test status
Simulation time 223334501 ps
CPU time 1.58 seconds
Started Aug 13 04:59:46 PM PDT 24
Finished Aug 13 04:59:47 PM PDT 24
Peak memory 196124 kb
Host smart-0dd786e4-6c4b-4303-b15b-327867e1aa18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409477738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2409477738
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3964969727
Short name T185
Test name
Test status
Simulation time 105096087 ps
CPU time 0.88 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 196660 kb
Host smart-faa781c3-3f07-4d68-84ee-30038c4c1623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964969727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3964969727
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3651872607
Short name T363
Test name
Test status
Simulation time 27200238 ps
CPU time 1.03 seconds
Started Aug 13 04:59:50 PM PDT 24
Finished Aug 13 04:59:51 PM PDT 24
Peak memory 196104 kb
Host smart-5d10690c-cd83-4252-a47e-bac97d85628a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651872607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3651872607
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3474045610
Short name T691
Test name
Test status
Simulation time 45835517 ps
CPU time 1.17 seconds
Started Aug 13 04:59:46 PM PDT 24
Finished Aug 13 04:59:48 PM PDT 24
Peak memory 197336 kb
Host smart-98d20df3-c50a-41e0-8c80-e3eef13ba391
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474045610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3474045610
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1143188818
Short name T132
Test name
Test status
Simulation time 258447105 ps
CPU time 1.29 seconds
Started Aug 13 04:59:47 PM PDT 24
Finished Aug 13 04:59:49 PM PDT 24
Peak memory 196380 kb
Host smart-b70bd5f6-dcd0-41ad-8920-125f83fb57e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143188818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1143188818
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1345852635
Short name T76
Test name
Test status
Simulation time 46855084 ps
CPU time 1.04 seconds
Started Aug 13 04:59:48 PM PDT 24
Finished Aug 13 04:59:49 PM PDT 24
Peak memory 195808 kb
Host smart-2c716710-cefc-4870-b4c0-b92adf98a05d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345852635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1345852635
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1525438586
Short name T404
Test name
Test status
Simulation time 8562114145 ps
CPU time 101.16 seconds
Started Aug 13 04:59:47 PM PDT 24
Finished Aug 13 05:01:28 PM PDT 24
Peak memory 198352 kb
Host smart-b002d527-564b-4320-9209-8557f5cfc11b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525438586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1525438586
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.2373251394
Short name T46
Test name
Test status
Simulation time 2400822058 ps
CPU time 42.81 seconds
Started Aug 13 04:59:48 PM PDT 24
Finished Aug 13 05:00:31 PM PDT 24
Peak memory 198404 kb
Host smart-6fb3e1c8-aec0-4534-ae8c-489b49fd5a23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2373251394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.2373251394
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2379583656
Short name T656
Test name
Test status
Simulation time 17087433 ps
CPU time 0.59 seconds
Started Aug 13 04:59:48 PM PDT 24
Finished Aug 13 04:59:48 PM PDT 24
Peak memory 194148 kb
Host smart-1dbb480a-0281-4ae1-90a5-927adb891efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379583656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2379583656
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2131906449
Short name T358
Test name
Test status
Simulation time 36855831 ps
CPU time 0.86 seconds
Started Aug 13 04:59:51 PM PDT 24
Finished Aug 13 04:59:52 PM PDT 24
Peak memory 196056 kb
Host smart-2cfe3da7-0ce0-40ee-aa12-c2dcf8d815f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131906449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2131906449
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.315839312
Short name T431
Test name
Test status
Simulation time 535894872 ps
CPU time 4.63 seconds
Started Aug 13 04:59:51 PM PDT 24
Finished Aug 13 04:59:56 PM PDT 24
Peak memory 196720 kb
Host smart-48fee66d-0766-4b78-9629-d2e5cc83cf42
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315839312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.315839312
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3193201867
Short name T539
Test name
Test status
Simulation time 351257648 ps
CPU time 0.93 seconds
Started Aug 13 04:59:48 PM PDT 24
Finished Aug 13 04:59:49 PM PDT 24
Peak memory 197016 kb
Host smart-72a1a813-ec1b-4f43-89a1-d2decb8be5cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193201867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3193201867
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3404839500
Short name T571
Test name
Test status
Simulation time 256772181 ps
CPU time 1.25 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:51 PM PDT 24
Peak memory 196124 kb
Host smart-09b7873d-d7c3-4c39-8246-ec198c4fb49f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404839500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3404839500
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3500525318
Short name T676
Test name
Test status
Simulation time 348988476 ps
CPU time 1.94 seconds
Started Aug 13 04:59:51 PM PDT 24
Finished Aug 13 04:59:53 PM PDT 24
Peak memory 196100 kb
Host smart-d28cf72d-df96-4646-afb9-0343b399e0cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500525318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3500525318
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2444798465
Short name T216
Test name
Test status
Simulation time 475057338 ps
CPU time 1.41 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:51 PM PDT 24
Peak memory 195936 kb
Host smart-08f6450f-450c-47b1-a4a1-1c862a932ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444798465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2444798465
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3961990945
Short name T154
Test name
Test status
Simulation time 17741664 ps
CPU time 0.77 seconds
Started Aug 13 04:59:47 PM PDT 24
Finished Aug 13 04:59:48 PM PDT 24
Peak memory 196260 kb
Host smart-85bb7bb3-1955-4a7c-a022-8176a43590a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961990945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3961990945
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3058679822
Short name T651
Test name
Test status
Simulation time 1376113530 ps
CPU time 1.75 seconds
Started Aug 13 04:59:54 PM PDT 24
Finished Aug 13 04:59:56 PM PDT 24
Peak memory 197964 kb
Host smart-350d6272-b237-420c-bd79-cc4a5343676f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058679822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3058679822
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2013255589
Short name T575
Test name
Test status
Simulation time 445637791 ps
CPU time 0.99 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 195916 kb
Host smart-ca704686-aac6-481a-8ef8-3f52e2d79782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013255589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2013255589
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.138912803
Short name T317
Test name
Test status
Simulation time 239107349 ps
CPU time 1.25 seconds
Started Aug 13 04:59:52 PM PDT 24
Finished Aug 13 04:59:53 PM PDT 24
Peak memory 195576 kb
Host smart-d2efa8df-c19c-4236-a6af-0bfe87346d6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138912803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.138912803
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.610968310
Short name T692
Test name
Test status
Simulation time 27324026658 ps
CPU time 191.71 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 05:03:01 PM PDT 24
Peak memory 198212 kb
Host smart-a32618cc-4d44-4c1f-9a4b-5f7e9ba10ce7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610968310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.610968310
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.650121277
Short name T702
Test name
Test status
Simulation time 8556723214 ps
CPU time 69.41 seconds
Started Aug 13 04:59:51 PM PDT 24
Finished Aug 13 05:01:00 PM PDT 24
Peak memory 198424 kb
Host smart-f4574047-e80c-4d8a-8f22-47f47bd3aed5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=650121277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.650121277
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1437739579
Short name T153
Test name
Test status
Simulation time 11980275 ps
CPU time 0.58 seconds
Started Aug 13 04:59:57 PM PDT 24
Finished Aug 13 04:59:58 PM PDT 24
Peak memory 194016 kb
Host smart-62e0ea65-5e56-4168-9874-cb3dcedb21f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437739579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1437739579
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.991694111
Short name T558
Test name
Test status
Simulation time 49994250 ps
CPU time 0.67 seconds
Started Aug 13 04:59:55 PM PDT 24
Finished Aug 13 04:59:56 PM PDT 24
Peak memory 194132 kb
Host smart-228a84f5-b7a2-4b98-8b97-7c7ab92c9fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991694111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.991694111
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1687280417
Short name T389
Test name
Test status
Simulation time 2018882332 ps
CPU time 27.91 seconds
Started Aug 13 04:59:57 PM PDT 24
Finished Aug 13 05:00:25 PM PDT 24
Peak memory 196816 kb
Host smart-8ca1cc6b-58fc-42ae-8331-d51586abf742
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687280417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1687280417
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1437531919
Short name T608
Test name
Test status
Simulation time 56742839 ps
CPU time 0.68 seconds
Started Aug 13 04:59:57 PM PDT 24
Finished Aug 13 04:59:58 PM PDT 24
Peak memory 194596 kb
Host smart-727c5aad-4ea4-4a08-be57-3851a8eee6ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437531919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1437531919
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1323935805
Short name T19
Test name
Test status
Simulation time 164769002 ps
CPU time 0.91 seconds
Started Aug 13 04:59:50 PM PDT 24
Finished Aug 13 04:59:51 PM PDT 24
Peak memory 196504 kb
Host smart-2f56c129-1947-4c74-9b97-afe9cc9c0dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323935805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1323935805
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1388022826
Short name T278
Test name
Test status
Simulation time 191420012 ps
CPU time 2.1 seconds
Started Aug 13 04:59:58 PM PDT 24
Finished Aug 13 05:00:01 PM PDT 24
Peak memory 198168 kb
Host smart-4d6a7922-4f9a-4664-839e-723e929cf9dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388022826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1388022826
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2740974350
Short name T159
Test name
Test status
Simulation time 644662035 ps
CPU time 3.26 seconds
Started Aug 13 04:59:55 PM PDT 24
Finished Aug 13 04:59:59 PM PDT 24
Peak memory 196612 kb
Host smart-9ffc86f1-0769-4663-ba03-7452ef2fb035
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740974350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2740974350
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1583966921
Short name T135
Test name
Test status
Simulation time 40385326 ps
CPU time 0.79 seconds
Started Aug 13 04:59:56 PM PDT 24
Finished Aug 13 04:59:57 PM PDT 24
Peak memory 195516 kb
Host smart-baca618f-d401-4e16-a1e6-f6f9b46d6ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583966921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1583966921
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.4240122466
Short name T170
Test name
Test status
Simulation time 45620626 ps
CPU time 0.68 seconds
Started Aug 13 04:59:50 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 194428 kb
Host smart-00243a2e-6ed6-4d8a-945f-6330c9f4daed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240122466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.4240122466
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3763176688
Short name T429
Test name
Test status
Simulation time 1431785079 ps
CPU time 6.14 seconds
Started Aug 13 04:59:58 PM PDT 24
Finished Aug 13 05:00:04 PM PDT 24
Peak memory 198084 kb
Host smart-83fce6f5-0205-4353-9897-a597a58df9b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763176688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3763176688
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1138785433
Short name T181
Test name
Test status
Simulation time 42294224 ps
CPU time 0.86 seconds
Started Aug 13 04:59:51 PM PDT 24
Finished Aug 13 04:59:52 PM PDT 24
Peak memory 195248 kb
Host smart-07d410d9-cb97-4cfa-a99b-b9360ab37a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138785433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1138785433
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3800944122
Short name T569
Test name
Test status
Simulation time 155832769 ps
CPU time 0.92 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 195328 kb
Host smart-000db15d-593d-4ef0-b4bd-f5af87da2ba2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800944122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3800944122
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2877093410
Short name T466
Test name
Test status
Simulation time 37281597168 ps
CPU time 149.4 seconds
Started Aug 13 05:00:00 PM PDT 24
Finished Aug 13 05:02:30 PM PDT 24
Peak memory 198308 kb
Host smart-16d79d6f-250e-4b92-8d36-42689b462149
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877093410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2877093410
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1653252380
Short name T650
Test name
Test status
Simulation time 97259114 ps
CPU time 0.58 seconds
Started Aug 13 04:59:58 PM PDT 24
Finished Aug 13 04:59:59 PM PDT 24
Peak memory 193532 kb
Host smart-47786e75-e854-4218-ba0b-3254cdbee30f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653252380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1653252380
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.73329470
Short name T145
Test name
Test status
Simulation time 71080659 ps
CPU time 0.63 seconds
Started Aug 13 04:59:58 PM PDT 24
Finished Aug 13 04:59:58 PM PDT 24
Peak memory 194028 kb
Host smart-b31df7cd-4e9a-4d15-8c1a-cbe7e396baad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73329470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.73329470
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.725220917
Short name T535
Test name
Test status
Simulation time 376237021 ps
CPU time 19.5 seconds
Started Aug 13 04:59:59 PM PDT 24
Finished Aug 13 05:00:18 PM PDT 24
Peak memory 196352 kb
Host smart-bf2dc8d7-11cb-4f7a-bfd5-c0869a647801
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725220917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.725220917
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1577913999
Short name T433
Test name
Test status
Simulation time 546176875 ps
CPU time 0.95 seconds
Started Aug 13 04:59:56 PM PDT 24
Finished Aug 13 04:59:57 PM PDT 24
Peak memory 197304 kb
Host smart-cc68080e-20c5-42ed-9b07-8677719d44bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577913999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1577913999
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3382783685
Short name T532
Test name
Test status
Simulation time 151873795 ps
CPU time 0.85 seconds
Started Aug 13 04:59:56 PM PDT 24
Finished Aug 13 04:59:57 PM PDT 24
Peak memory 196600 kb
Host smart-bea2bb91-63e6-4625-a9bd-cf3021b5db54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382783685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3382783685
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1296053750
Short name T151
Test name
Test status
Simulation time 48308379 ps
CPU time 1.93 seconds
Started Aug 13 04:59:58 PM PDT 24
Finished Aug 13 05:00:00 PM PDT 24
Peak memory 196484 kb
Host smart-2ecb5334-bdae-4822-b3dc-b379f9da76d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296053750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1296053750
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3628946759
Short name T124
Test name
Test status
Simulation time 129426944 ps
CPU time 1.53 seconds
Started Aug 13 04:59:58 PM PDT 24
Finished Aug 13 05:00:00 PM PDT 24
Peak memory 196156 kb
Host smart-eb3d5d45-397b-42ee-8462-25e413399c63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628946759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3628946759
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.808836377
Short name T561
Test name
Test status
Simulation time 161662575 ps
CPU time 1.01 seconds
Started Aug 13 04:59:57 PM PDT 24
Finished Aug 13 04:59:58 PM PDT 24
Peak memory 196780 kb
Host smart-0d944afd-581a-46ba-b32c-d2d3ca79da35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808836377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.808836377
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2880721547
Short name T511
Test name
Test status
Simulation time 48935662 ps
CPU time 1.05 seconds
Started Aug 13 04:59:56 PM PDT 24
Finished Aug 13 04:59:57 PM PDT 24
Peak memory 196052 kb
Host smart-0bcd8b8c-37d1-4c75-84e1-c2c70fb83828
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880721547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2880721547
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4218722284
Short name T599
Test name
Test status
Simulation time 434810995 ps
CPU time 5.63 seconds
Started Aug 13 05:00:01 PM PDT 24
Finished Aug 13 05:00:11 PM PDT 24
Peak memory 198164 kb
Host smart-c0a9bc48-165a-46df-980f-a2b3bf4af88d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218722284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4218722284
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2580603541
Short name T352
Test name
Test status
Simulation time 331688193 ps
CPU time 1.24 seconds
Started Aug 13 04:59:56 PM PDT 24
Finished Aug 13 04:59:57 PM PDT 24
Peak memory 195844 kb
Host smart-18311e31-ea33-4908-8280-38f32f385618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580603541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2580603541
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1333005900
Short name T471
Test name
Test status
Simulation time 32949352 ps
CPU time 0.9 seconds
Started Aug 13 04:59:59 PM PDT 24
Finished Aug 13 05:00:00 PM PDT 24
Peak memory 196040 kb
Host smart-bf090b86-776d-437d-ac2c-52743d5058f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333005900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1333005900
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.565241168
Short name T343
Test name
Test status
Simulation time 37208548574 ps
CPU time 83.65 seconds
Started Aug 13 04:59:57 PM PDT 24
Finished Aug 13 05:01:21 PM PDT 24
Peak memory 198280 kb
Host smart-c2ae6c43-f315-4b41-87fd-6972ead85232
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565241168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.565241168
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1601710934
Short name T150
Test name
Test status
Simulation time 40271935 ps
CPU time 0.57 seconds
Started Aug 13 05:00:00 PM PDT 24
Finished Aug 13 05:00:00 PM PDT 24
Peak memory 194688 kb
Host smart-7cfc6bc8-bc92-4bba-bda2-0ae823fee8c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601710934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1601710934
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.27842266
Short name T376
Test name
Test status
Simulation time 166391921 ps
CPU time 0.97 seconds
Started Aug 13 04:59:59 PM PDT 24
Finished Aug 13 05:00:01 PM PDT 24
Peak memory 197368 kb
Host smart-65265109-bb61-4a7f-81c8-42f22610d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27842266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.27842266
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3503091494
Short name T249
Test name
Test status
Simulation time 525020130 ps
CPU time 18.01 seconds
Started Aug 13 05:00:01 PM PDT 24
Finished Aug 13 05:00:23 PM PDT 24
Peak memory 196516 kb
Host smart-49b32628-94d2-4865-8bf2-b065be89405e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503091494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3503091494
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.785108261
Short name T568
Test name
Test status
Simulation time 41907780 ps
CPU time 0.77 seconds
Started Aug 13 04:59:58 PM PDT 24
Finished Aug 13 04:59:59 PM PDT 24
Peak memory 194752 kb
Host smart-fdc9735b-4bbb-4e42-9f54-243dc703c179
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785108261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.785108261
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1319333199
Short name T74
Test name
Test status
Simulation time 62483429 ps
CPU time 1.15 seconds
Started Aug 13 05:00:02 PM PDT 24
Finished Aug 13 05:00:06 PM PDT 24
Peak memory 196296 kb
Host smart-6e0bdb71-5b2b-49d9-b32c-9f854576345a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319333199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1319333199
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3103571204
Short name T306
Test name
Test status
Simulation time 90275350 ps
CPU time 3.66 seconds
Started Aug 13 05:00:02 PM PDT 24
Finished Aug 13 05:00:09 PM PDT 24
Peak memory 198264 kb
Host smart-b65354eb-e15b-470c-97e6-d23cfe7832ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103571204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3103571204
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2933604402
Short name T576
Test name
Test status
Simulation time 454157983 ps
CPU time 3.21 seconds
Started Aug 13 05:00:01 PM PDT 24
Finished Aug 13 05:00:04 PM PDT 24
Peak memory 197192 kb
Host smart-9a5dcd4f-7a4d-4608-8d15-b2849c1e9f22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933604402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2933604402
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2116899683
Short name T370
Test name
Test status
Simulation time 40906968 ps
CPU time 1.05 seconds
Started Aug 13 05:00:02 PM PDT 24
Finished Aug 13 05:00:06 PM PDT 24
Peak memory 196180 kb
Host smart-fc51cd4b-79a4-48e7-a7ee-db4d344ed1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116899683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2116899683
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2867653837
Short name T497
Test name
Test status
Simulation time 97469073 ps
CPU time 1.02 seconds
Started Aug 13 04:59:56 PM PDT 24
Finished Aug 13 04:59:57 PM PDT 24
Peak memory 195976 kb
Host smart-a503baa4-9793-44de-ac44-f4b12258ac4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867653837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2867653837
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3315241464
Short name T614
Test name
Test status
Simulation time 2718239381 ps
CPU time 3.97 seconds
Started Aug 13 04:59:58 PM PDT 24
Finished Aug 13 05:00:02 PM PDT 24
Peak memory 198252 kb
Host smart-aa5d98fe-bfb2-4967-b001-26fa2651d8b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315241464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3315241464
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3440889936
Short name T407
Test name
Test status
Simulation time 69003291 ps
CPU time 1.07 seconds
Started Aug 13 05:00:00 PM PDT 24
Finished Aug 13 05:00:01 PM PDT 24
Peak memory 195988 kb
Host smart-5d2946a1-c344-433b-8cdc-fc18c7767009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440889936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3440889936
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2913066164
Short name T690
Test name
Test status
Simulation time 70318900 ps
CPU time 1.17 seconds
Started Aug 13 05:00:00 PM PDT 24
Finished Aug 13 05:00:01 PM PDT 24
Peak memory 195944 kb
Host smart-0edc6433-8d55-4878-9a7a-8efd44e438fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913066164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2913066164
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3404288717
Short name T613
Test name
Test status
Simulation time 10922378819 ps
CPU time 84.01 seconds
Started Aug 13 05:00:01 PM PDT 24
Finished Aug 13 05:01:29 PM PDT 24
Peak memory 198364 kb
Host smart-30f0cf25-1a57-4f53-83f5-fb26ed037159
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404288717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3404288717
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.4221678456
Short name T606
Test name
Test status
Simulation time 25945352 ps
CPU time 0.59 seconds
Started Aug 13 05:00:00 PM PDT 24
Finished Aug 13 05:00:00 PM PDT 24
Peak memory 194144 kb
Host smart-28440fe9-6e74-438d-b6a8-e79f1992ae8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221678456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.4221678456
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1665864701
Short name T595
Test name
Test status
Simulation time 29517696 ps
CPU time 0.72 seconds
Started Aug 13 05:00:01 PM PDT 24
Finished Aug 13 05:00:01 PM PDT 24
Peak memory 195240 kb
Host smart-98cb710e-f3bc-470a-94c6-d71aa725ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665864701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1665864701
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.522556186
Short name T22
Test name
Test status
Simulation time 456028175 ps
CPU time 22.59 seconds
Started Aug 13 05:00:03 PM PDT 24
Finished Aug 13 05:00:28 PM PDT 24
Peak memory 197076 kb
Host smart-4698b967-fe07-488f-88e8-63a46715f370
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522556186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.522556186
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1691863611
Short name T325
Test name
Test status
Simulation time 129612426 ps
CPU time 1.12 seconds
Started Aug 13 05:00:04 PM PDT 24
Finished Aug 13 05:00:06 PM PDT 24
Peak memory 196676 kb
Host smart-afdd5446-051e-46b6-8bca-a810feba5371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691863611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1691863611
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3851401446
Short name T490
Test name
Test status
Simulation time 127989092 ps
CPU time 1.2 seconds
Started Aug 13 05:00:03 PM PDT 24
Finished Aug 13 05:00:06 PM PDT 24
Peak memory 196200 kb
Host smart-f969ef6f-ac01-44e2-a965-19170048965c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851401446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3851401446
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1780333136
Short name T418
Test name
Test status
Simulation time 208359918 ps
CPU time 1.7 seconds
Started Aug 13 05:00:00 PM PDT 24
Finished Aug 13 05:00:02 PM PDT 24
Peak memory 196504 kb
Host smart-75dbf92c-33b7-4e80-ae43-45a64e594a14
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780333136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1780333136
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.762839250
Short name T437
Test name
Test status
Simulation time 71915629 ps
CPU time 2.22 seconds
Started Aug 13 05:00:05 PM PDT 24
Finished Aug 13 05:00:07 PM PDT 24
Peak memory 197336 kb
Host smart-cc063e51-f1b1-4df9-abf1-c38806fa6055
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762839250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
762839250
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3543411818
Short name T123
Test name
Test status
Simulation time 14089294 ps
CPU time 0.68 seconds
Started Aug 13 05:00:01 PM PDT 24
Finished Aug 13 05:00:06 PM PDT 24
Peak memory 194312 kb
Host smart-2c657b95-069b-44d3-82c4-72a0f0311bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543411818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3543411818
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.357802265
Short name T582
Test name
Test status
Simulation time 68593698 ps
CPU time 1.29 seconds
Started Aug 13 05:00:03 PM PDT 24
Finished Aug 13 05:00:07 PM PDT 24
Peak memory 197148 kb
Host smart-ec67402b-83ea-4dc3-a4b3-779db635f3ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357802265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.357802265
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2406693852
Short name T601
Test name
Test status
Simulation time 1844376393 ps
CPU time 6.27 seconds
Started Aug 13 05:00:04 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 198172 kb
Host smart-b1726612-a8d2-4a4b-a8f3-8dc40e74cc45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406693852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2406693852
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1907242960
Short name T347
Test name
Test status
Simulation time 34935806 ps
CPU time 0.85 seconds
Started Aug 13 05:00:02 PM PDT 24
Finished Aug 13 05:00:06 PM PDT 24
Peak memory 195460 kb
Host smart-368bd784-7c52-4a24-856d-ce4f2a3a55b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907242960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1907242960
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.300114504
Short name T143
Test name
Test status
Simulation time 208148094 ps
CPU time 1.03 seconds
Started Aug 13 04:59:59 PM PDT 24
Finished Aug 13 05:00:00 PM PDT 24
Peak memory 195624 kb
Host smart-170653c2-66a6-457f-b7d0-1bee7ac7d460
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300114504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.300114504
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3303215522
Short name T570
Test name
Test status
Simulation time 7944581781 ps
CPU time 60.47 seconds
Started Aug 13 05:00:05 PM PDT 24
Finished Aug 13 05:01:06 PM PDT 24
Peak memory 198304 kb
Host smart-551edd4c-514b-412e-9c79-2904eec47c74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303215522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3303215522
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3060535502
Short name T212
Test name
Test status
Simulation time 24318911 ps
CPU time 0.58 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 193932 kb
Host smart-ba86b380-4605-46c1-b1cf-da5de7259465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060535502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3060535502
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1538398987
Short name T250
Test name
Test status
Simulation time 63037535 ps
CPU time 0.69 seconds
Started Aug 13 05:00:12 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 194212 kb
Host smart-b48fb72a-3d49-4288-92d6-ed86e9758066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538398987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1538398987
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1249661339
Short name T452
Test name
Test status
Simulation time 6052045198 ps
CPU time 21.95 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:33 PM PDT 24
Peak memory 196792 kb
Host smart-119cfff1-699f-4535-992e-0c215bb7c84e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249661339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1249661339
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3346335647
Short name T31
Test name
Test status
Simulation time 110379123 ps
CPU time 0.83 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 196020 kb
Host smart-20821e5e-3658-401e-b566-27c0d5b49bad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346335647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3346335647
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1247501209
Short name T367
Test name
Test status
Simulation time 84744743 ps
CPU time 1.41 seconds
Started Aug 13 05:00:12 PM PDT 24
Finished Aug 13 05:00:14 PM PDT 24
Peak memory 198180 kb
Host smart-b473fdca-ef96-4f2e-af71-3a626da5835b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247501209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1247501209
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2565547058
Short name T61
Test name
Test status
Simulation time 63071107 ps
CPU time 2.55 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 198076 kb
Host smart-9b67f535-8255-443d-a0ca-d0e007a9c87a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565547058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2565547058
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.284794206
Short name T64
Test name
Test status
Simulation time 132631407 ps
CPU time 1.99 seconds
Started Aug 13 05:00:13 PM PDT 24
Finished Aug 13 05:00:15 PM PDT 24
Peak memory 197224 kb
Host smart-dd719f23-9279-4652-9ee4-6fb6cc9056b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284794206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
284794206
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.340529425
Short name T305
Test name
Test status
Simulation time 37581915 ps
CPU time 1.28 seconds
Started Aug 13 05:00:04 PM PDT 24
Finished Aug 13 05:00:07 PM PDT 24
Peak memory 197144 kb
Host smart-714b8aed-d52e-43b9-9a30-771db05ebd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340529425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.340529425
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2561964301
Short name T258
Test name
Test status
Simulation time 49058043 ps
CPU time 0.8 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 195544 kb
Host smart-6e9e5110-43bc-4f28-bc5f-6b2793f69e8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561964301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2561964301
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2163050487
Short name T526
Test name
Test status
Simulation time 454881063 ps
CPU time 5.02 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:16 PM PDT 24
Peak memory 198036 kb
Host smart-67792d11-3325-4913-9060-9f8220390dea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163050487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2163050487
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.256436982
Short name T245
Test name
Test status
Simulation time 822478801 ps
CPU time 1.26 seconds
Started Aug 13 05:00:03 PM PDT 24
Finished Aug 13 05:00:07 PM PDT 24
Peak memory 196868 kb
Host smart-675500e7-10fc-4c73-95c6-837a59dc5a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256436982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.256436982
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2872764584
Short name T330
Test name
Test status
Simulation time 68079841 ps
CPU time 1.19 seconds
Started Aug 13 05:00:03 PM PDT 24
Finished Aug 13 05:00:06 PM PDT 24
Peak memory 196440 kb
Host smart-62434cf3-6751-40eb-b8c0-344ba279d340
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872764584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2872764584
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2927868560
Short name T573
Test name
Test status
Simulation time 33063721013 ps
CPU time 206.07 seconds
Started Aug 13 05:00:10 PM PDT 24
Finished Aug 13 05:03:37 PM PDT 24
Peak memory 198492 kb
Host smart-2675dd90-fc78-4d23-a138-2afb7b26f85b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927868560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2927868560
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3603325687
Short name T268
Test name
Test status
Simulation time 21441692 ps
CPU time 0.62 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:11 PM PDT 24
Peak memory 194688 kb
Host smart-fb75167d-7ed4-4d30-9b56-a5d0aee2d47e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603325687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3603325687
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2824956128
Short name T131
Test name
Test status
Simulation time 65410373 ps
CPU time 0.77 seconds
Started Aug 13 05:00:12 PM PDT 24
Finished Aug 13 05:00:13 PM PDT 24
Peak memory 195364 kb
Host smart-19de7274-a79e-481e-9f3e-fc8a0b208a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824956128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2824956128
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1627262966
Short name T382
Test name
Test status
Simulation time 616112478 ps
CPU time 8.26 seconds
Started Aug 13 05:00:12 PM PDT 24
Finished Aug 13 05:00:21 PM PDT 24
Peak memory 196668 kb
Host smart-677a5eaa-d599-4ad3-a1d1-8d96fa38ef9a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627262966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1627262966
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1667426588
Short name T700
Test name
Test status
Simulation time 220336656 ps
CPU time 0.97 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 198228 kb
Host smart-27210428-7271-4257-8e91-16962e6b0dfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667426588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1667426588
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.343677179
Short name T501
Test name
Test status
Simulation time 740617000 ps
CPU time 1.08 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:00:10 PM PDT 24
Peak memory 196624 kb
Host smart-2e94ffd6-b758-40f2-99be-ee803bbda99b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343677179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.343677179
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.307060722
Short name T217
Test name
Test status
Simulation time 52241919 ps
CPU time 2.06 seconds
Started Aug 13 05:00:10 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 196464 kb
Host smart-0fce3bb3-a983-4feb-8b70-1037363280a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307060722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.307060722
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3554406856
Short name T171
Test name
Test status
Simulation time 295838910 ps
CPU time 1.89 seconds
Started Aug 13 05:00:10 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 196000 kb
Host smart-12f97472-d594-47de-b4f1-8ae57f3288b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554406856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3554406856
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2744937641
Short name T674
Test name
Test status
Simulation time 283043968 ps
CPU time 0.86 seconds
Started Aug 13 05:00:08 PM PDT 24
Finished Aug 13 05:00:09 PM PDT 24
Peak memory 196740 kb
Host smart-647d38b8-791e-44d4-8bbe-83c772b5d4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744937641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2744937641
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1067932889
Short name T309
Test name
Test status
Simulation time 23592836 ps
CPU time 0.91 seconds
Started Aug 13 05:00:06 PM PDT 24
Finished Aug 13 05:00:07 PM PDT 24
Peak memory 196148 kb
Host smart-e56ecc53-09b7-4b36-90c9-05f6dec1baaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067932889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1067932889
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3831909920
Short name T510
Test name
Test status
Simulation time 359793132 ps
CPU time 3.72 seconds
Started Aug 13 05:00:12 PM PDT 24
Finished Aug 13 05:00:16 PM PDT 24
Peak memory 198144 kb
Host smart-fda31608-f1a8-470a-99e7-31b1209d1679
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831909920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3831909920
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1930700670
Short name T262
Test name
Test status
Simulation time 60761878 ps
CPU time 1.23 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 196928 kb
Host smart-accd713a-3097-4ebb-a35a-fa88b44a51ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930700670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1930700670
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1212825607
Short name T393
Test name
Test status
Simulation time 63583535 ps
CPU time 1.1 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 195968 kb
Host smart-1e512d36-2692-4e6b-970e-60391f387e01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212825607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1212825607
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1797306312
Short name T402
Test name
Test status
Simulation time 15051358621 ps
CPU time 171.15 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:03:00 PM PDT 24
Peak memory 198280 kb
Host smart-756cc050-ebbc-4df6-8f86-3a077da713bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797306312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1797306312
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.4194457623
Short name T366
Test name
Test status
Simulation time 169253010 ps
CPU time 0.56 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 193992 kb
Host smart-441b47f4-5d28-42ec-b1b9-3b18befa68b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194457623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.4194457623
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3806086537
Short name T197
Test name
Test status
Simulation time 17828029 ps
CPU time 0.64 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:00:10 PM PDT 24
Peak memory 194008 kb
Host smart-e80c3432-c0bf-497c-8386-d060824e8c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806086537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3806086537
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.665699817
Short name T546
Test name
Test status
Simulation time 229625992 ps
CPU time 5.72 seconds
Started Aug 13 05:00:12 PM PDT 24
Finished Aug 13 05:00:18 PM PDT 24
Peak memory 196424 kb
Host smart-647d2af4-0683-49c3-8241-a97d3dd00c60
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665699817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.665699817
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2593817198
Short name T362
Test name
Test status
Simulation time 80928682 ps
CPU time 1.02 seconds
Started Aug 13 05:00:19 PM PDT 24
Finished Aug 13 05:00:20 PM PDT 24
Peak memory 196732 kb
Host smart-7e46041b-9ee5-4f58-beaa-ed7fd5e369f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593817198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2593817198
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2447347145
Short name T666
Test name
Test status
Simulation time 250578448 ps
CPU time 1.14 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:00:10 PM PDT 24
Peak memory 196236 kb
Host smart-8823ffb3-152d-4b58-a421-faea0bdccd14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447347145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2447347145
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.4133041075
Short name T381
Test name
Test status
Simulation time 37809437 ps
CPU time 1.18 seconds
Started Aug 13 05:00:07 PM PDT 24
Finished Aug 13 05:00:09 PM PDT 24
Peak memory 197968 kb
Host smart-3741543f-d799-464a-9fa7-9856e00fea93
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133041075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.4133041075
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3202075267
Short name T149
Test name
Test status
Simulation time 186885004 ps
CPU time 2.14 seconds
Started Aug 13 05:00:16 PM PDT 24
Finished Aug 13 05:00:19 PM PDT 24
Peak memory 196104 kb
Host smart-f5c1941d-583e-4dcb-8a29-cd496f2784b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202075267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3202075267
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1932993235
Short name T247
Test name
Test status
Simulation time 275174183 ps
CPU time 0.94 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:00:10 PM PDT 24
Peak memory 195920 kb
Host smart-84230d4f-a8a6-4777-a3a1-71c1bba6dbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932993235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1932993235
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2472419509
Short name T486
Test name
Test status
Simulation time 229971847 ps
CPU time 1.2 seconds
Started Aug 13 05:00:19 PM PDT 24
Finished Aug 13 05:00:21 PM PDT 24
Peak memory 197220 kb
Host smart-f9099518-a5c6-4cd9-b57d-09133351b5d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472419509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2472419509
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1000106057
Short name T25
Test name
Test status
Simulation time 568168234 ps
CPU time 2.88 seconds
Started Aug 13 05:00:10 PM PDT 24
Finished Aug 13 05:00:13 PM PDT 24
Peak memory 197308 kb
Host smart-d3586778-5bd1-494d-b6d2-960de729ef4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000106057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1000106057
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.629851308
Short name T385
Test name
Test status
Simulation time 650952345 ps
CPU time 1.03 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:00:10 PM PDT 24
Peak memory 196312 kb
Host smart-a9176b3a-2386-4664-bb6d-c321f1f3ae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629851308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.629851308
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.132851448
Short name T221
Test name
Test status
Simulation time 53075318 ps
CPU time 0.87 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 195480 kb
Host smart-5e3ec4f4-33a5-4ca6-a04a-26308d4c0b51
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132851448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.132851448
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1548141497
Short name T589
Test name
Test status
Simulation time 9043188871 ps
CPU time 130.22 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:02:20 PM PDT 24
Peak memory 198356 kb
Host smart-94969eb7-cb20-4891-9727-58234cec75ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548141497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1548141497
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.259696550
Short name T23
Test name
Test status
Simulation time 13962278 ps
CPU time 0.59 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 193992 kb
Host smart-9bd5f6fa-e55e-4c21-b0c7-097d660119d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259696550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.259696550
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3715213247
Short name T142
Test name
Test status
Simulation time 30779468 ps
CPU time 0.65 seconds
Started Aug 13 05:00:12 PM PDT 24
Finished Aug 13 05:00:13 PM PDT 24
Peak memory 193992 kb
Host smart-14542c96-63ba-4ff9-bae2-0454166b2aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715213247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3715213247
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3249180009
Short name T630
Test name
Test status
Simulation time 243710583 ps
CPU time 4.55 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:00:13 PM PDT 24
Peak memory 196788 kb
Host smart-6ce62be1-464c-469b-b5d1-2ff8c42e5aeb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249180009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3249180009
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3080852055
Short name T173
Test name
Test status
Simulation time 287967297 ps
CPU time 0.86 seconds
Started Aug 13 05:00:12 PM PDT 24
Finished Aug 13 05:00:13 PM PDT 24
Peak memory 196288 kb
Host smart-2f1ef4a4-004e-4539-8bf4-c1b7a7353e98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080852055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3080852055
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2825079047
Short name T241
Test name
Test status
Simulation time 22662033 ps
CPU time 0.79 seconds
Started Aug 13 05:00:17 PM PDT 24
Finished Aug 13 05:00:18 PM PDT 24
Peak memory 196224 kb
Host smart-f3d78f34-8da3-46eb-a78a-64e3bb58663d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825079047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2825079047
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1788145775
Short name T401
Test name
Test status
Simulation time 26690617 ps
CPU time 1.21 seconds
Started Aug 13 05:00:17 PM PDT 24
Finished Aug 13 05:00:18 PM PDT 24
Peak memory 197344 kb
Host smart-22fc10b6-0dd6-47ba-84af-aeb442d78d73
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788145775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1788145775
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.689951134
Short name T291
Test name
Test status
Simulation time 142806035 ps
CPU time 3.47 seconds
Started Aug 13 05:00:10 PM PDT 24
Finished Aug 13 05:00:14 PM PDT 24
Peak memory 197188 kb
Host smart-c0a5f405-87e5-44a1-837e-2eb0c00ebe54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689951134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
689951134
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3509052378
Short name T72
Test name
Test status
Simulation time 499377638 ps
CPU time 1.18 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:13 PM PDT 24
Peak memory 198196 kb
Host smart-99414956-21b9-488b-b4c2-32ec278e5044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509052378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3509052378
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.378823046
Short name T26
Test name
Test status
Simulation time 39019176 ps
CPU time 1.28 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:13 PM PDT 24
Peak memory 197196 kb
Host smart-580ead45-bdf8-4761-8d40-c87d251e50d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378823046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.378823046
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.565960569
Short name T334
Test name
Test status
Simulation time 645652493 ps
CPU time 2.34 seconds
Started Aug 13 05:00:15 PM PDT 24
Finished Aug 13 05:00:18 PM PDT 24
Peak memory 198004 kb
Host smart-59bedeb4-490f-48cd-9d8f-5827d0ec7e79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565960569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.565960569
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1517123524
Short name T298
Test name
Test status
Simulation time 122736765 ps
CPU time 1.14 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:00:10 PM PDT 24
Peak memory 196956 kb
Host smart-c8e31f44-a32a-42a9-b698-cf46228603e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517123524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1517123524
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2292904386
Short name T383
Test name
Test status
Simulation time 60185140 ps
CPU time 1.19 seconds
Started Aug 13 05:00:08 PM PDT 24
Finished Aug 13 05:00:10 PM PDT 24
Peak memory 195936 kb
Host smart-97a4615e-db4f-493c-b7b5-a6ca64384d89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292904386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2292904386
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1762455537
Short name T545
Test name
Test status
Simulation time 50646181677 ps
CPU time 119.35 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:02:08 PM PDT 24
Peak memory 198264 kb
Host smart-b6fa6c03-82f4-4a2c-8c2e-eeb71a644069
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762455537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1762455537
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.4018176226
Short name T643
Test name
Test status
Simulation time 14201402 ps
CPU time 0.55 seconds
Started Aug 13 04:59:23 PM PDT 24
Finished Aug 13 04:59:24 PM PDT 24
Peak memory 194064 kb
Host smart-8da6d2ff-f63e-42ba-8fe3-3eba950cf922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018176226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.4018176226
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2073592117
Short name T669
Test name
Test status
Simulation time 35433720 ps
CPU time 0.85 seconds
Started Aug 13 04:59:25 PM PDT 24
Finished Aug 13 04:59:26 PM PDT 24
Peak memory 196436 kb
Host smart-12c6a0b1-a340-4149-b799-28273befee0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073592117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2073592117
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1417323637
Short name T384
Test name
Test status
Simulation time 344562232 ps
CPU time 17.59 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 04:59:40 PM PDT 24
Peak memory 198100 kb
Host smart-f11178f3-2ec4-471c-8750-92df904c0563
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417323637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1417323637
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1778902213
Short name T509
Test name
Test status
Simulation time 73762297 ps
CPU time 0.98 seconds
Started Aug 13 04:59:20 PM PDT 24
Finished Aug 13 04:59:21 PM PDT 24
Peak memory 197976 kb
Host smart-cc7b62ee-9261-4e12-9c71-21e11884d991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778902213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1778902213
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.818948097
Short name T182
Test name
Test status
Simulation time 281574455 ps
CPU time 1.11 seconds
Started Aug 13 04:59:21 PM PDT 24
Finished Aug 13 04:59:22 PM PDT 24
Peak memory 196040 kb
Host smart-cc9f09dc-af74-4e8b-a771-66a8f9eb403b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818948097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.818948097
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2651386577
Short name T685
Test name
Test status
Simulation time 73078892 ps
CPU time 1.75 seconds
Started Aug 13 04:59:21 PM PDT 24
Finished Aug 13 04:59:23 PM PDT 24
Peak memory 198048 kb
Host smart-021e7de9-1a08-47a6-ad76-165de3b0ef69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651386577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2651386577
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.496517440
Short name T495
Test name
Test status
Simulation time 160096769 ps
CPU time 2.89 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 04:59:25 PM PDT 24
Peak memory 196880 kb
Host smart-a650c984-bbad-40c0-9542-069813194fec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496517440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.496517440
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.125266467
Short name T210
Test name
Test status
Simulation time 951567058 ps
CPU time 1.5 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 04:59:24 PM PDT 24
Peak memory 196016 kb
Host smart-278864c3-c54e-416a-8541-23c58498dc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125266467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.125266467
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3489021423
Short name T266
Test name
Test status
Simulation time 22394714 ps
CPU time 0.68 seconds
Started Aug 13 04:59:21 PM PDT 24
Finished Aug 13 04:59:22 PM PDT 24
Peak memory 195096 kb
Host smart-7f4cb848-e37c-4980-8569-72ab047d410f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489021423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3489021423
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.790008657
Short name T598
Test name
Test status
Simulation time 1359913098 ps
CPU time 6.04 seconds
Started Aug 13 04:59:23 PM PDT 24
Finished Aug 13 04:59:29 PM PDT 24
Peak memory 198004 kb
Host smart-6b490771-4220-4542-9b96-d46f6f7376a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790008657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.790008657
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2311658664
Short name T58
Test name
Test status
Simulation time 57644390 ps
CPU time 0.88 seconds
Started Aug 13 04:59:21 PM PDT 24
Finished Aug 13 04:59:22 PM PDT 24
Peak memory 214044 kb
Host smart-48c1f14f-e1a9-4544-8ae1-cdfa0c93e433
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311658664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2311658664
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2469007429
Short name T428
Test name
Test status
Simulation time 144394256 ps
CPU time 0.99 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 04:59:23 PM PDT 24
Peak memory 195876 kb
Host smart-95bfb59a-9885-43a1-a9f0-4c022a5351fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469007429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2469007429
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3708140365
Short name T507
Test name
Test status
Simulation time 257913255 ps
CPU time 1.24 seconds
Started Aug 13 04:59:24 PM PDT 24
Finished Aug 13 04:59:25 PM PDT 24
Peak memory 195860 kb
Host smart-72518c94-cc99-49a2-b175-1abdc3f69437
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708140365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3708140365
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1272612065
Short name T5
Test name
Test status
Simulation time 14033322104 ps
CPU time 83.61 seconds
Started Aug 13 04:59:21 PM PDT 24
Finished Aug 13 05:00:45 PM PDT 24
Peak memory 198316 kb
Host smart-89999b28-61c5-4932-8ae7-8e9d4afdf455
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272612065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1272612065
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1154388393
Short name T47
Test name
Test status
Simulation time 17414077401 ps
CPU time 143.94 seconds
Started Aug 13 04:59:21 PM PDT 24
Finished Aug 13 05:01:45 PM PDT 24
Peak memory 198488 kb
Host smart-0fe7bf35-e585-468e-aff5-cfd4368d7078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1154388393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1154388393
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.276523695
Short name T611
Test name
Test status
Simulation time 42694803 ps
CPU time 0.58 seconds
Started Aug 13 05:00:18 PM PDT 24
Finished Aug 13 05:00:19 PM PDT 24
Peak memory 194060 kb
Host smart-1ef0ab7a-9233-45ff-b15a-0f6f28b77095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276523695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.276523695
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3709917918
Short name T326
Test name
Test status
Simulation time 27530645 ps
CPU time 0.86 seconds
Started Aug 13 05:00:11 PM PDT 24
Finished Aug 13 05:00:12 PM PDT 24
Peak memory 196568 kb
Host smart-bae212a0-433e-4387-9673-6703977ed128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709917918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3709917918
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2762958282
Short name T257
Test name
Test status
Simulation time 495937228 ps
CPU time 14.1 seconds
Started Aug 13 05:00:22 PM PDT 24
Finished Aug 13 05:00:36 PM PDT 24
Peak memory 195676 kb
Host smart-e90aa3d1-7763-4e95-978e-d10eec016be2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762958282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2762958282
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.134443393
Short name T287
Test name
Test status
Simulation time 367325974 ps
CPU time 1.16 seconds
Started Aug 13 05:00:19 PM PDT 24
Finished Aug 13 05:00:21 PM PDT 24
Peak memory 198208 kb
Host smart-67453f9f-3998-4825-a108-9716ba879d19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134443393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.134443393
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.854585448
Short name T597
Test name
Test status
Simulation time 43196034 ps
CPU time 0.81 seconds
Started Aug 13 05:00:17 PM PDT 24
Finished Aug 13 05:00:18 PM PDT 24
Peak memory 195724 kb
Host smart-00db75c2-ff33-4dab-82ba-a0d72900ca88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854585448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.854585448
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1047337335
Short name T645
Test name
Test status
Simulation time 337400905 ps
CPU time 2.11 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 197952 kb
Host smart-921c39b1-dcc9-4ee0-bbaf-d778eaca4efd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047337335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1047337335
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1910090673
Short name T634
Test name
Test status
Simulation time 401469104 ps
CPU time 2.96 seconds
Started Aug 13 05:00:19 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 197104 kb
Host smart-94c050f2-68b9-46ab-a707-56d62943ccdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910090673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1910090673
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3062849768
Short name T578
Test name
Test status
Simulation time 58641863 ps
CPU time 1.33 seconds
Started Aug 13 05:00:17 PM PDT 24
Finished Aug 13 05:00:18 PM PDT 24
Peak memory 197152 kb
Host smart-fc3d81e7-668a-4a5d-91a1-39db4bd3d1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062849768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3062849768
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.161880222
Short name T636
Test name
Test status
Simulation time 32805090 ps
CPU time 0.98 seconds
Started Aug 13 05:00:09 PM PDT 24
Finished Aug 13 05:00:10 PM PDT 24
Peak memory 196880 kb
Host smart-fb2f7c8b-aac9-4c25-8704-1d46b4e6437f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161880222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.161880222
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2737562007
Short name T357
Test name
Test status
Simulation time 1563141911 ps
CPU time 2.94 seconds
Started Aug 13 05:00:23 PM PDT 24
Finished Aug 13 05:00:26 PM PDT 24
Peak memory 198080 kb
Host smart-1ecaeb7b-7566-489f-b342-ab78875d6426
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737562007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2737562007
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.168712140
Short name T665
Test name
Test status
Simulation time 44267760 ps
CPU time 1.15 seconds
Started Aug 13 05:00:10 PM PDT 24
Finished Aug 13 05:00:11 PM PDT 24
Peak memory 195648 kb
Host smart-554272d0-5591-49ba-b79f-92824d2e1e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168712140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.168712140
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2654595990
Short name T310
Test name
Test status
Simulation time 194372917 ps
CPU time 1.37 seconds
Started Aug 13 05:00:10 PM PDT 24
Finished Aug 13 05:00:11 PM PDT 24
Peak memory 196920 kb
Host smart-b7c72556-c5f3-4cdf-a5cd-fe228d2030c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654595990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2654595990
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1801145015
Short name T256
Test name
Test status
Simulation time 4715483295 ps
CPU time 109.2 seconds
Started Aug 13 05:00:19 PM PDT 24
Finished Aug 13 05:02:09 PM PDT 24
Peak memory 198292 kb
Host smart-dfe8ac56-7000-4905-8ecd-2e5c7891653c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801145015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1801145015
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2505288371
Short name T70
Test name
Test status
Simulation time 3875741897 ps
CPU time 66.7 seconds
Started Aug 13 05:00:17 PM PDT 24
Finished Aug 13 05:01:24 PM PDT 24
Peak memory 198396 kb
Host smart-2008ba27-ab5c-4fd5-8bb6-9194166a04df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2505288371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2505288371
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2943170912
Short name T492
Test name
Test status
Simulation time 31784360 ps
CPU time 0.57 seconds
Started Aug 13 05:00:18 PM PDT 24
Finished Aug 13 05:00:19 PM PDT 24
Peak memory 194044 kb
Host smart-2ad3c9f2-7c85-487a-987c-f4be11bd94dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943170912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2943170912
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1845614554
Short name T438
Test name
Test status
Simulation time 39700426 ps
CPU time 0.75 seconds
Started Aug 13 05:00:22 PM PDT 24
Finished Aug 13 05:00:23 PM PDT 24
Peak memory 196180 kb
Host smart-6731a58b-75bf-4775-82ce-b8cc1616693d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845614554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1845614554
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1655756638
Short name T502
Test name
Test status
Simulation time 944750425 ps
CPU time 26.41 seconds
Started Aug 13 05:00:21 PM PDT 24
Finished Aug 13 05:00:48 PM PDT 24
Peak memory 196796 kb
Host smart-f6f9fe5b-53f6-451d-bc66-0487dfc906ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655756638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1655756638
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.4115797450
Short name T518
Test name
Test status
Simulation time 816554752 ps
CPU time 1.03 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 196736 kb
Host smart-f4a5f2d8-69f6-4b2e-8c4c-ba9e58ba72fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115797450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.4115797450
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2689858777
Short name T479
Test name
Test status
Simulation time 143061401 ps
CPU time 1.13 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 195972 kb
Host smart-0fa24b35-8289-489b-bf39-9948fa3f4db9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689858777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2689858777
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1465361543
Short name T127
Test name
Test status
Simulation time 1249791600 ps
CPU time 3.57 seconds
Started Aug 13 05:00:24 PM PDT 24
Finished Aug 13 05:00:28 PM PDT 24
Peak memory 198056 kb
Host smart-da737ca9-cf0f-470d-9efe-4b9730c4817a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465361543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1465361543
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.47314367
Short name T336
Test name
Test status
Simulation time 180024284 ps
CPU time 2.15 seconds
Started Aug 13 05:00:16 PM PDT 24
Finished Aug 13 05:00:18 PM PDT 24
Peak memory 196100 kb
Host smart-f96a4f10-0b58-4032-a7df-7690743fb8bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47314367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.47314367
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.441274193
Short name T17
Test name
Test status
Simulation time 134339876 ps
CPU time 1.15 seconds
Started Aug 13 05:00:23 PM PDT 24
Finished Aug 13 05:00:24 PM PDT 24
Peak memory 195896 kb
Host smart-cce67fdd-2a21-4d97-9496-a2138e6a8f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441274193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.441274193
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2504461608
Short name T412
Test name
Test status
Simulation time 177774680 ps
CPU time 1.21 seconds
Started Aug 13 05:00:21 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 198148 kb
Host smart-48ec0b25-c850-4be7-907a-0930d41a457a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504461608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2504461608
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1038030036
Short name T696
Test name
Test status
Simulation time 470732379 ps
CPU time 5.53 seconds
Started Aug 13 05:00:18 PM PDT 24
Finished Aug 13 05:00:24 PM PDT 24
Peak memory 198156 kb
Host smart-1a058319-db04-4771-b8db-b51eb4b163a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038030036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1038030036
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2404902956
Short name T684
Test name
Test status
Simulation time 93401826 ps
CPU time 1.37 seconds
Started Aug 13 05:00:25 PM PDT 24
Finished Aug 13 05:00:26 PM PDT 24
Peak memory 198084 kb
Host smart-0463ec30-ac54-45b5-8ba9-414ba94470fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404902956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2404902956
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1472415380
Short name T195
Test name
Test status
Simulation time 502338018 ps
CPU time 1.04 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:21 PM PDT 24
Peak memory 195820 kb
Host smart-a6fb5462-198f-4c1f-9de2-d2484dde9def
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472415380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1472415380
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.735189994
Short name T420
Test name
Test status
Simulation time 6290100845 ps
CPU time 158.45 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:02:59 PM PDT 24
Peak memory 198284 kb
Host smart-b8e67529-a4b1-49de-91e9-29b0c0e1c3f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735189994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.735189994
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1261907356
Short name T442
Test name
Test status
Simulation time 1608295395 ps
CPU time 23.41 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:44 PM PDT 24
Peak memory 198364 kb
Host smart-d0e09435-de3e-4891-9802-0b9466636c84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1261907356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1261907356
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3069375404
Short name T564
Test name
Test status
Simulation time 23850135 ps
CPU time 0.61 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:21 PM PDT 24
Peak memory 194056 kb
Host smart-7bdf25ff-4e79-442e-885b-ccfd50e44994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069375404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3069375404
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.4164761155
Short name T508
Test name
Test status
Simulation time 24766148 ps
CPU time 0.64 seconds
Started Aug 13 05:00:19 PM PDT 24
Finished Aug 13 05:00:20 PM PDT 24
Peak memory 194068 kb
Host smart-a6509313-830b-4f2d-8576-4e859e999c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164761155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.4164761155
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2086121558
Short name T236
Test name
Test status
Simulation time 896875257 ps
CPU time 6.53 seconds
Started Aug 13 05:00:17 PM PDT 24
Finished Aug 13 05:00:23 PM PDT 24
Peak memory 196368 kb
Host smart-bfc0164b-a2e0-4fb3-8999-ec649b96802a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086121558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2086121558
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.4118978555
Short name T222
Test name
Test status
Simulation time 53660275 ps
CPU time 0.91 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 197296 kb
Host smart-31d90b80-9705-4a66-b542-43e146b02a2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118978555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.4118978555
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.865294509
Short name T530
Test name
Test status
Simulation time 40970604 ps
CPU time 1.14 seconds
Started Aug 13 05:00:18 PM PDT 24
Finished Aug 13 05:00:19 PM PDT 24
Peak memory 195884 kb
Host smart-622bdda7-20fc-4c39-891a-f963e2aae07e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865294509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.865294509
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1299816627
Short name T584
Test name
Test status
Simulation time 139459498 ps
CPU time 3.15 seconds
Started Aug 13 05:00:19 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 198256 kb
Host smart-5f8937f8-455d-4754-9260-ec1079f658f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299816627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1299816627
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2455573214
Short name T626
Test name
Test status
Simulation time 121425544 ps
CPU time 1.29 seconds
Started Aug 13 05:00:19 PM PDT 24
Finished Aug 13 05:00:21 PM PDT 24
Peak memory 197136 kb
Host smart-80a35ea5-bb5c-4b35-ac6b-2e0d513c3a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455573214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2455573214
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3941638163
Short name T43
Test name
Test status
Simulation time 45491760 ps
CPU time 0.73 seconds
Started Aug 13 05:00:21 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 195456 kb
Host smart-d4db9798-27b8-4172-ac3f-705c249ef55e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941638163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3941638163
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.196177315
Short name T482
Test name
Test status
Simulation time 233102926 ps
CPU time 2.81 seconds
Started Aug 13 05:00:21 PM PDT 24
Finished Aug 13 05:00:24 PM PDT 24
Peak memory 198044 kb
Host smart-fe64d9f4-5fe5-493c-9323-dcb9db1cd7e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196177315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.196177315
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.38097178
Short name T542
Test name
Test status
Simulation time 83216881 ps
CPU time 1.31 seconds
Started Aug 13 05:00:21 PM PDT 24
Finished Aug 13 05:00:23 PM PDT 24
Peak memory 196840 kb
Host smart-7b65177e-3777-461c-a320-114582d7bc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38097178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.38097178
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1016807317
Short name T555
Test name
Test status
Simulation time 85512897 ps
CPU time 0.98 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 195884 kb
Host smart-7a3842a6-af0f-42d2-a60a-359e8a8257fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016807317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1016807317
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.889810026
Short name T165
Test name
Test status
Simulation time 6393180055 ps
CPU time 113.68 seconds
Started Aug 13 05:00:25 PM PDT 24
Finished Aug 13 05:02:18 PM PDT 24
Peak memory 198232 kb
Host smart-79b73d2e-9459-4c35-aae3-1a131917da23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889810026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.889810026
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.173237845
Short name T635
Test name
Test status
Simulation time 7674594069 ps
CPU time 139.64 seconds
Started Aug 13 05:00:17 PM PDT 24
Finished Aug 13 05:02:36 PM PDT 24
Peak memory 198540 kb
Host smart-dcb96667-4090-4690-9b96-cc294808fb8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=173237845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.173237845
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3261695173
Short name T344
Test name
Test status
Simulation time 11812499 ps
CPU time 0.6 seconds
Started Aug 13 05:00:22 PM PDT 24
Finished Aug 13 05:00:23 PM PDT 24
Peak memory 193972 kb
Host smart-c0e87305-904b-4268-b23e-c53126aacd06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261695173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3261695173
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3191979032
Short name T12
Test name
Test status
Simulation time 42668561 ps
CPU time 0.75 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:21 PM PDT 24
Peak memory 195328 kb
Host smart-051d614b-1b3a-4a62-931b-2bc22ff80bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191979032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3191979032
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1808535121
Short name T237
Test name
Test status
Simulation time 727821375 ps
CPU time 21.76 seconds
Started Aug 13 05:00:24 PM PDT 24
Finished Aug 13 05:00:46 PM PDT 24
Peak memory 198056 kb
Host smart-de3d88b6-7388-4a4a-966c-ccb7cf77831a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808535121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1808535121
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3573635166
Short name T176
Test name
Test status
Simulation time 111998875 ps
CPU time 0.95 seconds
Started Aug 13 05:00:25 PM PDT 24
Finished Aug 13 05:00:26 PM PDT 24
Peak memory 197716 kb
Host smart-3fb387fc-39d5-41a1-9604-140a4a63fc32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573635166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3573635166
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1293553182
Short name T134
Test name
Test status
Simulation time 71048732 ps
CPU time 1.1 seconds
Started Aug 13 05:00:21 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 196712 kb
Host smart-8f7a9352-27bb-47d2-81e8-bfbe83101d05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293553182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1293553182
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1331516879
Short name T579
Test name
Test status
Simulation time 235713877 ps
CPU time 2.51 seconds
Started Aug 13 05:00:23 PM PDT 24
Finished Aug 13 05:00:26 PM PDT 24
Peak memory 198124 kb
Host smart-cfc61068-74e3-48d2-870a-1ef3dbaacf5b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331516879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1331516879
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.802791048
Short name T414
Test name
Test status
Simulation time 160560839 ps
CPU time 3.75 seconds
Started Aug 13 05:00:18 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 198208 kb
Host smart-7411ed9c-4d15-4b14-a465-5be1f730e5fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802791048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
802791048
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3454355668
Short name T485
Test name
Test status
Simulation time 55059592 ps
CPU time 1.22 seconds
Started Aug 13 05:00:22 PM PDT 24
Finished Aug 13 05:00:23 PM PDT 24
Peak memory 198240 kb
Host smart-662b261f-f14b-4015-9930-d5a3cc878610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454355668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3454355668
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1144407868
Short name T327
Test name
Test status
Simulation time 83163954 ps
CPU time 0.92 seconds
Started Aug 13 05:00:23 PM PDT 24
Finished Aug 13 05:00:24 PM PDT 24
Peak memory 196108 kb
Host smart-290a2533-b1d7-4f7f-9f5c-1cfdf584f3c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144407868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1144407868
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.726087624
Short name T454
Test name
Test status
Simulation time 84989058 ps
CPU time 4.17 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:24 PM PDT 24
Peak memory 198084 kb
Host smart-22e6ebc9-0438-487e-bef9-d1b42c42415a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726087624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.726087624
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1967329367
Short name T581
Test name
Test status
Simulation time 56844068 ps
CPU time 1.56 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:23 PM PDT 24
Peak memory 196796 kb
Host smart-c0bec00d-5c9e-4911-aee5-ad16b66af997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967329367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1967329367
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3771276614
Short name T543
Test name
Test status
Simulation time 212418022 ps
CPU time 1.12 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 195908 kb
Host smart-c81b9ce4-c44f-4b0f-aef1-cfc03d19c091
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771276614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3771276614
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2574829664
Short name T440
Test name
Test status
Simulation time 3535364033 ps
CPU time 75.41 seconds
Started Aug 13 05:00:21 PM PDT 24
Finished Aug 13 05:01:37 PM PDT 24
Peak memory 198236 kb
Host smart-b018fa47-be2c-495e-9fac-7e36fc7ab0b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574829664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2574829664
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.796884901
Short name T644
Test name
Test status
Simulation time 24522905 ps
CPU time 0.58 seconds
Started Aug 13 05:00:24 PM PDT 24
Finished Aug 13 05:00:25 PM PDT 24
Peak memory 194708 kb
Host smart-7eb8d0dc-a16a-4bd7-9725-dae6684df243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796884901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.796884901
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1709488216
Short name T464
Test name
Test status
Simulation time 45545770 ps
CPU time 0.9 seconds
Started Aug 13 05:00:22 PM PDT 24
Finished Aug 13 05:00:23 PM PDT 24
Peak memory 196460 kb
Host smart-d372af49-721e-4486-a8e3-0296fd8c3b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709488216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1709488216
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1634213264
Short name T294
Test name
Test status
Simulation time 797327618 ps
CPU time 20.62 seconds
Started Aug 13 05:00:24 PM PDT 24
Finished Aug 13 05:00:45 PM PDT 24
Peak memory 196880 kb
Host smart-1aff91ec-409f-4083-93b1-f4b1f3b47f55
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634213264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1634213264
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.427079388
Short name T687
Test name
Test status
Simulation time 309892991 ps
CPU time 0.94 seconds
Started Aug 13 05:00:25 PM PDT 24
Finished Aug 13 05:00:26 PM PDT 24
Peak memory 197120 kb
Host smart-f31305af-a579-456a-bd97-d10a8bb80df4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427079388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.427079388
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2744591005
Short name T591
Test name
Test status
Simulation time 153708844 ps
CPU time 1.35 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:21 PM PDT 24
Peak memory 196792 kb
Host smart-6d1c8f82-992c-4e5e-91a3-a0cbf46fac83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744591005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2744591005
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.457548528
Short name T300
Test name
Test status
Simulation time 415258020 ps
CPU time 1.77 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:23 PM PDT 24
Peak memory 196556 kb
Host smart-a0b05e8a-cf8e-429d-bcc8-df653537c581
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457548528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.457548528
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3965553366
Short name T592
Test name
Test status
Simulation time 463228623 ps
CPU time 2.61 seconds
Started Aug 13 05:00:25 PM PDT 24
Finished Aug 13 05:00:28 PM PDT 24
Peak memory 197236 kb
Host smart-effa20de-1b88-449d-b656-7507140d1859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965553366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3965553366
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1983093311
Short name T218
Test name
Test status
Simulation time 282969068 ps
CPU time 1.27 seconds
Started Aug 13 05:00:24 PM PDT 24
Finished Aug 13 05:00:25 PM PDT 24
Peak memory 197084 kb
Host smart-112983e4-993e-437c-a957-6d8b45d0edb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983093311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1983093311
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.466349409
Short name T271
Test name
Test status
Simulation time 244380528 ps
CPU time 1.07 seconds
Started Aug 13 05:00:22 PM PDT 24
Finished Aug 13 05:00:23 PM PDT 24
Peak memory 196844 kb
Host smart-3ae13f3b-659b-449c-a72a-f71dc8dcd6f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466349409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.466349409
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.968484122
Short name T455
Test name
Test status
Simulation time 484626639 ps
CPU time 1.91 seconds
Started Aug 13 05:00:22 PM PDT 24
Finished Aug 13 05:00:25 PM PDT 24
Peak memory 198160 kb
Host smart-3925f935-bed5-4296-86eb-3905d5403ca7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968484122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.968484122
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1813761935
Short name T641
Test name
Test status
Simulation time 68389043 ps
CPU time 1.07 seconds
Started Aug 13 05:00:21 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 195864 kb
Host smart-2b8f7f84-11a4-4279-9169-6363259f47f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813761935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1813761935
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1542941390
Short name T204
Test name
Test status
Simulation time 77293941 ps
CPU time 0.88 seconds
Started Aug 13 05:00:19 PM PDT 24
Finished Aug 13 05:00:20 PM PDT 24
Peak memory 197076 kb
Host smart-72d38e51-9d62-48a1-bb2a-b3bbfaaaa6b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542941390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1542941390
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3667287937
Short name T693
Test name
Test status
Simulation time 228179445249 ps
CPU time 164.76 seconds
Started Aug 13 05:00:25 PM PDT 24
Finished Aug 13 05:03:10 PM PDT 24
Peak memory 198208 kb
Host smart-af123f4a-5c1a-4028-a155-1389557e01dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667287937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3667287937
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2892028947
Short name T34
Test name
Test status
Simulation time 15688675 ps
CPU time 0.62 seconds
Started Aug 13 05:00:29 PM PDT 24
Finished Aug 13 05:00:30 PM PDT 24
Peak memory 194232 kb
Host smart-dc18f72c-2b75-4b77-9e94-6d0df80d21f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892028947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2892028947
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2201132108
Short name T239
Test name
Test status
Simulation time 74881111 ps
CPU time 0.83 seconds
Started Aug 13 05:00:23 PM PDT 24
Finished Aug 13 05:00:24 PM PDT 24
Peak memory 195448 kb
Host smart-c3eef462-c0cd-400a-85f5-097b93d7a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201132108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2201132108
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1708189782
Short name T652
Test name
Test status
Simulation time 1431467079 ps
CPU time 23.07 seconds
Started Aug 13 05:00:26 PM PDT 24
Finished Aug 13 05:00:50 PM PDT 24
Peak memory 197048 kb
Host smart-01f43888-8a13-464a-8d3e-20ca89496364
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708189782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1708189782
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2917288193
Short name T16
Test name
Test status
Simulation time 74829151 ps
CPU time 1.07 seconds
Started Aug 13 05:00:30 PM PDT 24
Finished Aug 13 05:00:31 PM PDT 24
Peak memory 196640 kb
Host smart-5bdcf44a-a7d0-4a40-b1e7-5bb79c83c578
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917288193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2917288193
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.772924076
Short name T15
Test name
Test status
Simulation time 42793842 ps
CPU time 1.23 seconds
Started Aug 13 05:00:32 PM PDT 24
Finished Aug 13 05:00:33 PM PDT 24
Peak memory 197420 kb
Host smart-8e8eb2e0-18fe-4375-a44b-517a9d3c5c7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772924076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.772924076
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1910264481
Short name T424
Test name
Test status
Simulation time 94403177 ps
CPU time 3.86 seconds
Started Aug 13 05:00:32 PM PDT 24
Finished Aug 13 05:00:36 PM PDT 24
Peak memory 198156 kb
Host smart-fddd639b-dc5c-41da-a5e1-4e18225782b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910264481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1910264481
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3865924965
Short name T304
Test name
Test status
Simulation time 171960689 ps
CPU time 2.76 seconds
Started Aug 13 05:00:31 PM PDT 24
Finished Aug 13 05:00:34 PM PDT 24
Peak memory 195912 kb
Host smart-ecb04af8-012a-49ae-9e56-cab0e999a52a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865924965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3865924965
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1619991245
Short name T178
Test name
Test status
Simulation time 111941636 ps
CPU time 1.07 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:21 PM PDT 24
Peak memory 196064 kb
Host smart-74b59d3a-8525-48e1-91ee-1115fba12c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619991245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1619991245
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3892762492
Short name T63
Test name
Test status
Simulation time 34213580 ps
CPU time 0.95 seconds
Started Aug 13 05:00:19 PM PDT 24
Finished Aug 13 05:00:20 PM PDT 24
Peak memory 196492 kb
Host smart-9adac792-cc3f-4dc9-af4b-81765092529e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892762492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3892762492
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1882675266
Short name T567
Test name
Test status
Simulation time 398432411 ps
CPU time 1.71 seconds
Started Aug 13 05:00:35 PM PDT 24
Finished Aug 13 05:00:36 PM PDT 24
Peak memory 198112 kb
Host smart-fa3c5d73-4508-45b7-9912-05ef370e422e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882675266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1882675266
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3249329083
Short name T400
Test name
Test status
Simulation time 856627945 ps
CPU time 1.45 seconds
Started Aug 13 05:00:20 PM PDT 24
Finished Aug 13 05:00:22 PM PDT 24
Peak memory 196860 kb
Host smart-f4ca0377-1846-4013-8e6d-add6003328aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249329083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3249329083
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.187641641
Short name T520
Test name
Test status
Simulation time 33225323 ps
CPU time 0.78 seconds
Started Aug 13 05:00:25 PM PDT 24
Finished Aug 13 05:00:26 PM PDT 24
Peak memory 195208 kb
Host smart-17195f5d-94e6-4ac2-b53a-ef3a3978e9a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187641641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.187641641
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1062406737
Short name T534
Test name
Test status
Simulation time 21664358802 ps
CPU time 123.47 seconds
Started Aug 13 05:00:27 PM PDT 24
Finished Aug 13 05:02:31 PM PDT 24
Peak memory 198360 kb
Host smart-93e5ff49-015e-4415-87c4-5e6d287cafe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062406737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1062406737
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1414142430
Short name T242
Test name
Test status
Simulation time 41368073 ps
CPU time 0.58 seconds
Started Aug 13 05:00:32 PM PDT 24
Finished Aug 13 05:00:33 PM PDT 24
Peak memory 193980 kb
Host smart-232ab838-5480-4dd0-a5ae-a448e28d16ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414142430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1414142430
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3831001415
Short name T75
Test name
Test status
Simulation time 60305249 ps
CPU time 0.92 seconds
Started Aug 13 05:00:29 PM PDT 24
Finished Aug 13 05:00:31 PM PDT 24
Peak memory 196164 kb
Host smart-49c4c3ef-f5a4-48ff-aa3a-530512a3b9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831001415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3831001415
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3446591083
Short name T417
Test name
Test status
Simulation time 1117949028 ps
CPU time 11.24 seconds
Started Aug 13 05:00:29 PM PDT 24
Finished Aug 13 05:00:41 PM PDT 24
Peak memory 197096 kb
Host smart-7105b478-c31a-45de-ae4b-3b5c375b56ed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446591083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3446591083
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1176829069
Short name T224
Test name
Test status
Simulation time 132035755 ps
CPU time 0.67 seconds
Started Aug 13 05:00:30 PM PDT 24
Finished Aug 13 05:00:31 PM PDT 24
Peak memory 195392 kb
Host smart-a1009c19-dd93-47cc-9f8f-14063a4a0e08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176829069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1176829069
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3979412383
Short name T219
Test name
Test status
Simulation time 68406354 ps
CPU time 1.06 seconds
Started Aug 13 05:00:32 PM PDT 24
Finished Aug 13 05:00:33 PM PDT 24
Peak memory 196140 kb
Host smart-0d7cc578-3b95-46f6-8e82-c06b6f3f2aef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979412383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3979412383
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3749862625
Short name T267
Test name
Test status
Simulation time 155883862 ps
CPU time 3.39 seconds
Started Aug 13 05:00:28 PM PDT 24
Finished Aug 13 05:00:32 PM PDT 24
Peak memory 197964 kb
Host smart-c2f6fddc-8d2a-4ae5-8244-8339699ea82b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749862625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3749862625
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1119125468
Short name T167
Test name
Test status
Simulation time 402873012 ps
CPU time 2.4 seconds
Started Aug 13 05:00:32 PM PDT 24
Finished Aug 13 05:00:34 PM PDT 24
Peak memory 195888 kb
Host smart-969597db-b9ba-4ad2-9ded-b7185a8e6479
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119125468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1119125468
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2195661997
Short name T120
Test name
Test status
Simulation time 20345579 ps
CPU time 0.94 seconds
Started Aug 13 05:00:29 PM PDT 24
Finished Aug 13 05:00:31 PM PDT 24
Peak memory 197388 kb
Host smart-cf57c4f3-b74a-4c12-b579-b345b3fb6792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195661997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2195661997
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3119639964
Short name T593
Test name
Test status
Simulation time 34232737 ps
CPU time 1.17 seconds
Started Aug 13 05:00:30 PM PDT 24
Finished Aug 13 05:00:31 PM PDT 24
Peak memory 196016 kb
Host smart-61690a49-7b2c-4774-a660-5fd3a8a80983
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119639964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3119639964
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_smoke.3013755372
Short name T209
Test name
Test status
Simulation time 98670750 ps
CPU time 0.92 seconds
Started Aug 13 05:00:30 PM PDT 24
Finished Aug 13 05:00:31 PM PDT 24
Peak memory 195392 kb
Host smart-5cec58b4-411f-420b-b7f7-91c73be321fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013755372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3013755372
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3627036449
Short name T680
Test name
Test status
Simulation time 215496933 ps
CPU time 1.29 seconds
Started Aug 13 05:00:27 PM PDT 24
Finished Aug 13 05:00:29 PM PDT 24
Peak memory 196504 kb
Host smart-7a7a2b62-f873-43d0-983d-8c2200c2886c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627036449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3627036449
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1680893001
Short name T156
Test name
Test status
Simulation time 9401591640 ps
CPU time 120.91 seconds
Started Aug 13 05:00:34 PM PDT 24
Finished Aug 13 05:02:35 PM PDT 24
Peak memory 198364 kb
Host smart-e8871b69-ca49-4c77-9a95-35f3d3d8573c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680893001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1680893001
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.1541318480
Short name T467
Test name
Test status
Simulation time 2909898144 ps
CPU time 16.51 seconds
Started Aug 13 05:00:29 PM PDT 24
Finished Aug 13 05:00:46 PM PDT 24
Peak memory 197772 kb
Host smart-e2bc39f3-b8cb-4fbb-9e84-d67577db0878
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1541318480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.1541318480
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2672497979
Short name T544
Test name
Test status
Simulation time 14455187 ps
CPU time 0.6 seconds
Started Aug 13 05:00:34 PM PDT 24
Finished Aug 13 05:00:35 PM PDT 24
Peak memory 193952 kb
Host smart-aec4e715-1f27-42be-8015-3191219b7578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672497979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2672497979
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2364463780
Short name T365
Test name
Test status
Simulation time 80614669 ps
CPU time 0.68 seconds
Started Aug 13 05:00:36 PM PDT 24
Finished Aug 13 05:00:37 PM PDT 24
Peak memory 195036 kb
Host smart-809d341f-ef95-4de9-92b0-31ca8a87d6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364463780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2364463780
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1769194789
Short name T77
Test name
Test status
Simulation time 739603784 ps
CPU time 24.89 seconds
Started Aug 13 05:00:34 PM PDT 24
Finished Aug 13 05:00:59 PM PDT 24
Peak memory 197040 kb
Host smart-603d57ce-fb9d-44be-a0d2-0531cbfc3e67
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769194789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1769194789
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1720902195
Short name T252
Test name
Test status
Simulation time 74591420 ps
CPU time 0.66 seconds
Started Aug 13 05:00:34 PM PDT 24
Finished Aug 13 05:00:34 PM PDT 24
Peak memory 194552 kb
Host smart-1bac6521-26f4-4a25-a2a5-c6bf4aed7a93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720902195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1720902195
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1769949728
Short name T677
Test name
Test status
Simulation time 822940972 ps
CPU time 1.4 seconds
Started Aug 13 05:00:35 PM PDT 24
Finished Aug 13 05:00:37 PM PDT 24
Peak memory 196108 kb
Host smart-8f71f8bd-75ff-4540-9c79-69a6d297d69a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769949728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1769949728
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2224067720
Short name T639
Test name
Test status
Simulation time 105615880 ps
CPU time 3.39 seconds
Started Aug 13 05:00:32 PM PDT 24
Finished Aug 13 05:00:35 PM PDT 24
Peak memory 198096 kb
Host smart-7cb82466-f2f3-4fbf-8a68-edb6b0576e2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224067720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2224067720
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.366104711
Short name T473
Test name
Test status
Simulation time 239380424 ps
CPU time 2.69 seconds
Started Aug 13 05:00:38 PM PDT 24
Finished Aug 13 05:00:41 PM PDT 24
Peak memory 197032 kb
Host smart-9143b304-f45b-42a0-a09d-8e34aefba682
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366104711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
366104711
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.533025124
Short name T647
Test name
Test status
Simulation time 62295701 ps
CPU time 1.23 seconds
Started Aug 13 05:00:32 PM PDT 24
Finished Aug 13 05:00:33 PM PDT 24
Peak memory 195932 kb
Host smart-0d4d3a65-c96e-42cf-8ec6-00ddd77b1279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533025124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.533025124
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2725377634
Short name T531
Test name
Test status
Simulation time 319695145 ps
CPU time 1.32 seconds
Started Aug 13 05:00:31 PM PDT 24
Finished Aug 13 05:00:32 PM PDT 24
Peak memory 195984 kb
Host smart-6bbed8a8-eb3b-41ce-b575-b5e00161cdcf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725377634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2725377634
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2577402051
Short name T560
Test name
Test status
Simulation time 77208046 ps
CPU time 1.48 seconds
Started Aug 13 05:00:38 PM PDT 24
Finished Aug 13 05:00:40 PM PDT 24
Peak memory 197904 kb
Host smart-2cb46fb7-9b1d-4e5f-af7b-d413198b001e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577402051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2577402051
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.775041796
Short name T661
Test name
Test status
Simulation time 436391279 ps
CPU time 0.9 seconds
Started Aug 13 05:00:32 PM PDT 24
Finished Aug 13 05:00:33 PM PDT 24
Peak memory 195364 kb
Host smart-30d93084-0872-4664-809e-3cab50a95d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775041796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.775041796
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1632088846
Short name T475
Test name
Test status
Simulation time 91969331 ps
CPU time 1.46 seconds
Started Aug 13 05:00:33 PM PDT 24
Finished Aug 13 05:00:35 PM PDT 24
Peak memory 195780 kb
Host smart-01e0cfd3-f4fe-4c37-978c-eb7aa34468d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632088846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1632088846
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3083749290
Short name T196
Test name
Test status
Simulation time 23475998578 ps
CPU time 151.18 seconds
Started Aug 13 05:00:32 PM PDT 24
Finished Aug 13 05:03:03 PM PDT 24
Peak memory 198300 kb
Host smart-466eeccc-c994-4a26-acc8-51fd67c6e6f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083749290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3083749290
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.85460826
Short name T394
Test name
Test status
Simulation time 77689059 ps
CPU time 0.59 seconds
Started Aug 13 05:00:38 PM PDT 24
Finished Aug 13 05:00:39 PM PDT 24
Peak memory 194952 kb
Host smart-5ad60e3c-eec1-46d8-8a56-45c64fcc0e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85460826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.85460826
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1574686191
Short name T453
Test name
Test status
Simulation time 43349806 ps
CPU time 0.94 seconds
Started Aug 13 05:00:33 PM PDT 24
Finished Aug 13 05:00:34 PM PDT 24
Peak memory 196068 kb
Host smart-5e4d321e-79f0-457c-8a3f-156cb22ae3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574686191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1574686191
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2426779498
Short name T528
Test name
Test status
Simulation time 170260247 ps
CPU time 9.23 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:56 PM PDT 24
Peak memory 198056 kb
Host smart-bae0d51f-34c1-4b84-a9ff-f15eab408bcc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426779498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2426779498
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3805956378
Short name T320
Test name
Test status
Simulation time 88147389 ps
CPU time 0.65 seconds
Started Aug 13 05:00:38 PM PDT 24
Finished Aug 13 05:00:39 PM PDT 24
Peak memory 195244 kb
Host smart-5b7fc6e6-2c19-4a0b-a227-d97ba7d23436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805956378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3805956378
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1084502790
Short name T235
Test name
Test status
Simulation time 88148669 ps
CPU time 1.24 seconds
Started Aug 13 05:00:32 PM PDT 24
Finished Aug 13 05:00:34 PM PDT 24
Peak memory 195944 kb
Host smart-e2f4ce11-a18c-44dc-a59b-82f31322a968
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084502790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1084502790
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2425459894
Short name T572
Test name
Test status
Simulation time 383613271 ps
CPU time 3.64 seconds
Started Aug 13 05:00:39 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 198248 kb
Host smart-9547c4e5-d1b3-4f51-8162-91df62396d26
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425459894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2425459894
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.106094802
Short name T430
Test name
Test status
Simulation time 82311525 ps
CPU time 1.44 seconds
Started Aug 13 05:00:34 PM PDT 24
Finished Aug 13 05:00:36 PM PDT 24
Peak memory 196160 kb
Host smart-6d831baa-427f-44b7-b1a3-1d10346d5bc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106094802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
106094802
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3602960321
Short name T441
Test name
Test status
Simulation time 94064472 ps
CPU time 1.04 seconds
Started Aug 13 05:00:36 PM PDT 24
Finished Aug 13 05:00:38 PM PDT 24
Peak memory 196764 kb
Host smart-b38507cc-8317-4777-b8bc-aac774f7098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602960321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3602960321
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2776667863
Short name T494
Test name
Test status
Simulation time 35888894 ps
CPU time 0.97 seconds
Started Aug 13 05:00:37 PM PDT 24
Finished Aug 13 05:00:38 PM PDT 24
Peak memory 196784 kb
Host smart-036c42ec-137d-425e-9788-0f8f529e9450
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776667863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2776667863
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1579733197
Short name T186
Test name
Test status
Simulation time 317855492 ps
CPU time 5.15 seconds
Started Aug 13 05:00:37 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 198152 kb
Host smart-7b288bc3-830f-4623-a8a7-d64b5c4a3813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579733197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1579733197
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.210021804
Short name T392
Test name
Test status
Simulation time 225039377 ps
CPU time 1.13 seconds
Started Aug 13 05:00:32 PM PDT 24
Finished Aug 13 05:00:33 PM PDT 24
Peak memory 196604 kb
Host smart-32ee8937-36a7-4595-867d-a258962f4248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210021804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.210021804
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2768045395
Short name T536
Test name
Test status
Simulation time 53853586 ps
CPU time 1.07 seconds
Started Aug 13 05:00:33 PM PDT 24
Finished Aug 13 05:00:34 PM PDT 24
Peak memory 195884 kb
Host smart-008dfb3e-66ec-4899-9437-c04257f4330e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768045395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2768045395
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2943847086
Short name T323
Test name
Test status
Simulation time 26644185216 ps
CPU time 62.88 seconds
Started Aug 13 05:00:39 PM PDT 24
Finished Aug 13 05:01:43 PM PDT 24
Peak memory 198224 kb
Host smart-bb855065-26a5-4f1b-8486-be49d290bb39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943847086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2943847086
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1617422186
Short name T449
Test name
Test status
Simulation time 20739887 ps
CPU time 0.56 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:42 PM PDT 24
Peak memory 194192 kb
Host smart-4c63b2dd-331d-49e1-a0a6-e141a4fba6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617422186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1617422186
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4098458947
Short name T403
Test name
Test status
Simulation time 83169872 ps
CPU time 0.68 seconds
Started Aug 13 05:00:38 PM PDT 24
Finished Aug 13 05:00:39 PM PDT 24
Peak memory 194236 kb
Host smart-d3a1f67c-694f-4017-89f0-8bf22ef63dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098458947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4098458947
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3292556711
Short name T498
Test name
Test status
Simulation time 2563481071 ps
CPU time 12.12 seconds
Started Aug 13 05:00:39 PM PDT 24
Finished Aug 13 05:00:51 PM PDT 24
Peak memory 197576 kb
Host smart-0d2aa1a3-ffc6-439f-9acf-183897220550
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292556711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3292556711
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3151464168
Short name T686
Test name
Test status
Simulation time 194830432 ps
CPU time 0.76 seconds
Started Aug 13 05:00:39 PM PDT 24
Finished Aug 13 05:00:40 PM PDT 24
Peak memory 195952 kb
Host smart-ad268b3d-3e19-4944-a5aa-9f60c653bec7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151464168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3151464168
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2212599431
Short name T678
Test name
Test status
Simulation time 90360775 ps
CPU time 1.53 seconds
Started Aug 13 05:00:39 PM PDT 24
Finished Aug 13 05:00:41 PM PDT 24
Peak memory 198152 kb
Host smart-40dbb03b-9884-4d98-9f0d-ea4354b4bbce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212599431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2212599431
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2698451847
Short name T477
Test name
Test status
Simulation time 23504145 ps
CPU time 1.09 seconds
Started Aug 13 05:00:42 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 196520 kb
Host smart-da7763b2-ec1b-4eda-acab-4fe97e66dc36
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698451847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2698451847
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3268576488
Short name T164
Test name
Test status
Simulation time 35923013 ps
CPU time 1.09 seconds
Started Aug 13 05:00:37 PM PDT 24
Finished Aug 13 05:00:39 PM PDT 24
Peak memory 195684 kb
Host smart-d8040370-9880-41a7-bff3-12a084e84766
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268576488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3268576488
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2599873470
Short name T566
Test name
Test status
Simulation time 20725335 ps
CPU time 0.83 seconds
Started Aug 13 05:00:39 PM PDT 24
Finished Aug 13 05:00:40 PM PDT 24
Peak memory 196616 kb
Host smart-8848daa8-0090-41fa-bfe7-214796138b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599873470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2599873470
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.4192619907
Short name T637
Test name
Test status
Simulation time 43066376 ps
CPU time 0.68 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:42 PM PDT 24
Peak memory 195044 kb
Host smart-3e41df12-29d0-44ad-80c9-f294340120fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192619907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.4192619907
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1278371796
Short name T594
Test name
Test status
Simulation time 1198102075 ps
CPU time 3.6 seconds
Started Aug 13 05:00:38 PM PDT 24
Finished Aug 13 05:00:42 PM PDT 24
Peak memory 198064 kb
Host smart-d7682b7f-582e-4ad4-9fd1-a3c003efd87c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278371796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1278371796
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.57650896
Short name T703
Test name
Test status
Simulation time 92404380 ps
CPU time 0.94 seconds
Started Aug 13 05:00:40 PM PDT 24
Finished Aug 13 05:00:41 PM PDT 24
Peak memory 197104 kb
Host smart-500505c3-b973-4060-8be6-0784adf82d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57650896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.57650896
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2531643730
Short name T234
Test name
Test status
Simulation time 62648917 ps
CPU time 0.8 seconds
Started Aug 13 05:00:38 PM PDT 24
Finished Aug 13 05:00:39 PM PDT 24
Peak memory 196084 kb
Host smart-a154422c-0c0c-4de4-b5ba-e8c205f9d672
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531643730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2531643730
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2572730694
Short name T194
Test name
Test status
Simulation time 10598165058 ps
CPU time 68.96 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:01:50 PM PDT 24
Peak memory 198216 kb
Host smart-dc411961-0537-412e-a488-13332f95344a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572730694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2572730694
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3693972603
Short name T712
Test name
Test status
Simulation time 13828370 ps
CPU time 0.59 seconds
Started Aug 13 04:59:31 PM PDT 24
Finished Aug 13 04:59:32 PM PDT 24
Peak memory 194744 kb
Host smart-360ba6da-7135-4152-b2f3-41d57d1bd1a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693972603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3693972603
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.641054923
Short name T462
Test name
Test status
Simulation time 27662060 ps
CPU time 0.93 seconds
Started Aug 13 04:59:21 PM PDT 24
Finished Aug 13 04:59:22 PM PDT 24
Peak memory 196396 kb
Host smart-438e31a3-6878-4176-96a4-56833a9130dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641054923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.641054923
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2097350473
Short name T139
Test name
Test status
Simulation time 653591034 ps
CPU time 5.65 seconds
Started Aug 13 04:59:28 PM PDT 24
Finished Aug 13 04:59:34 PM PDT 24
Peak memory 198188 kb
Host smart-59845f00-9ac8-4310-b491-e39b5bcf07f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097350473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2097350473
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2256705369
Short name T79
Test name
Test status
Simulation time 70284107 ps
CPU time 0.98 seconds
Started Aug 13 04:59:30 PM PDT 24
Finished Aug 13 04:59:31 PM PDT 24
Peak memory 195952 kb
Host smart-73b5c863-df4d-443f-9e93-54c59c041d62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256705369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2256705369
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3421506803
Short name T29
Test name
Test status
Simulation time 69213688 ps
CPU time 1 seconds
Started Aug 13 04:59:23 PM PDT 24
Finished Aug 13 04:59:24 PM PDT 24
Peak memory 196128 kb
Host smart-5dcd058a-5ec4-4978-bd2a-7b7bd3db97b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421506803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3421506803
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.612794016
Short name T408
Test name
Test status
Simulation time 196168160 ps
CPU time 2.16 seconds
Started Aug 13 04:59:31 PM PDT 24
Finished Aug 13 04:59:33 PM PDT 24
Peak memory 198260 kb
Host smart-c48a4748-82fc-467d-a819-c648077cd905
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612794016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.612794016
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2150894227
Short name T220
Test name
Test status
Simulation time 306494193 ps
CPU time 1.71 seconds
Started Aug 13 04:59:33 PM PDT 24
Finished Aug 13 04:59:35 PM PDT 24
Peak memory 196136 kb
Host smart-5085b36b-cd1a-4972-ac02-153a899f7d87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150894227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2150894227
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3405216861
Short name T513
Test name
Test status
Simulation time 78301127 ps
CPU time 1.24 seconds
Started Aug 13 04:59:23 PM PDT 24
Finished Aug 13 04:59:24 PM PDT 24
Peak memory 197128 kb
Host smart-c8696c0e-cfb5-4b8c-a363-e3e71fcb1822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405216861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3405216861
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2403656930
Short name T260
Test name
Test status
Simulation time 148483516 ps
CPU time 0.92 seconds
Started Aug 13 04:59:23 PM PDT 24
Finished Aug 13 04:59:24 PM PDT 24
Peak memory 195920 kb
Host smart-a767eafd-1ca5-4c63-b12f-d983e7ca861d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403656930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2403656930
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3203635196
Short name T480
Test name
Test status
Simulation time 63013051 ps
CPU time 1.59 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:34 PM PDT 24
Peak memory 198040 kb
Host smart-9eceb455-398b-4ece-9171-3763351f728d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203635196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3203635196
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3311500505
Short name T53
Test name
Test status
Simulation time 75818634 ps
CPU time 0.82 seconds
Started Aug 13 04:59:33 PM PDT 24
Finished Aug 13 04:59:34 PM PDT 24
Peak memory 213884 kb
Host smart-5a983406-634a-43a3-8a3c-545e5a376d21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311500505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3311500505
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3071042981
Short name T646
Test name
Test status
Simulation time 107416574 ps
CPU time 0.93 seconds
Started Aug 13 04:59:22 PM PDT 24
Finished Aug 13 04:59:23 PM PDT 24
Peak memory 195608 kb
Host smart-a2ec6146-073e-4d09-b1dc-90f335ed081c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071042981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3071042981
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3714292179
Short name T610
Test name
Test status
Simulation time 50707525 ps
CPU time 1.04 seconds
Started Aug 13 04:59:21 PM PDT 24
Finished Aug 13 04:59:22 PM PDT 24
Peak memory 195856 kb
Host smart-e7216ac5-1f89-4f81-8864-6410bab3c0f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714292179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3714292179
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2101861224
Short name T553
Test name
Test status
Simulation time 75238596521 ps
CPU time 198.44 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 05:02:50 PM PDT 24
Peak memory 198260 kb
Host smart-4a2a83bd-1542-4ce5-9b8c-193bc75d051d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101861224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2101861224
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2115417405
Short name T179
Test name
Test status
Simulation time 12339665 ps
CPU time 0.62 seconds
Started Aug 13 05:00:43 PM PDT 24
Finished Aug 13 05:00:44 PM PDT 24
Peak memory 194044 kb
Host smart-ee624ada-b8cb-4f81-b4c3-331bee74a84f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115417405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2115417405
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2275466823
Short name T373
Test name
Test status
Simulation time 90013880 ps
CPU time 0.8 seconds
Started Aug 13 05:00:40 PM PDT 24
Finished Aug 13 05:00:41 PM PDT 24
Peak memory 195552 kb
Host smart-e8f163d8-a4f6-4e46-94c6-241eb57aaba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275466823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2275466823
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1830852839
Short name T554
Test name
Test status
Simulation time 2085636395 ps
CPU time 28.21 seconds
Started Aug 13 05:00:40 PM PDT 24
Finished Aug 13 05:01:09 PM PDT 24
Peak memory 196892 kb
Host smart-55ab8632-a2cd-4396-876e-d78b9328c900
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830852839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1830852839
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.824062291
Short name T670
Test name
Test status
Simulation time 394001883 ps
CPU time 0.96 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 197972 kb
Host smart-8f1d7214-ff07-4924-880f-d965e6e185ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824062291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.824062291
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3555863946
Short name T565
Test name
Test status
Simulation time 74132491 ps
CPU time 1.11 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:42 PM PDT 24
Peak memory 196284 kb
Host smart-cd77ffd1-3096-4152-b43e-9cea67458356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555863946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3555863946
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2096034078
Short name T263
Test name
Test status
Simulation time 282335580 ps
CPU time 2.74 seconds
Started Aug 13 05:00:42 PM PDT 24
Finished Aug 13 05:00:45 PM PDT 24
Peak memory 198196 kb
Host smart-59b99673-1fbd-4a7f-8414-e2355fe78fb3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096034078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2096034078
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2027977949
Short name T118
Test name
Test status
Simulation time 806538110 ps
CPU time 3.51 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:45 PM PDT 24
Peak memory 197340 kb
Host smart-9bd57c74-eb07-4a97-b80a-cef05b6ddbd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027977949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2027977949
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.352923206
Short name T314
Test name
Test status
Simulation time 29506140 ps
CPU time 0.8 seconds
Started Aug 13 05:00:38 PM PDT 24
Finished Aug 13 05:00:39 PM PDT 24
Peak memory 195564 kb
Host smart-aa359c9d-786f-448b-8577-4d933390636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352923206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.352923206
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.188672563
Short name T705
Test name
Test status
Simulation time 209072097 ps
CPU time 1.21 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 197436 kb
Host smart-1d4abf26-227e-4b8f-a21a-c4986a3aebcc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188672563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.188672563
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.472652797
Short name T354
Test name
Test status
Simulation time 339586586 ps
CPU time 2.28 seconds
Started Aug 13 05:00:40 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 198096 kb
Host smart-d15e494d-f7eb-4d59-9c1f-2f14f7a16753
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472652797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.472652797
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.889378239
Short name T243
Test name
Test status
Simulation time 791489799 ps
CPU time 1.2 seconds
Started Aug 13 05:00:39 PM PDT 24
Finished Aug 13 05:00:41 PM PDT 24
Peak memory 195912 kb
Host smart-72f3f5db-ce6c-4632-93cb-160adb815717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889378239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.889378239
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.440501472
Short name T191
Test name
Test status
Simulation time 96627415 ps
CPU time 0.89 seconds
Started Aug 13 05:00:42 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 195280 kb
Host smart-c12a1204-9cfc-45b5-b03f-096c6fe0c6eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440501472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.440501472
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2770796518
Short name T379
Test name
Test status
Simulation time 23764722595 ps
CPU time 186.42 seconds
Started Aug 13 05:00:45 PM PDT 24
Finished Aug 13 05:03:51 PM PDT 24
Peak memory 198296 kb
Host smart-e452c70f-07ad-47f4-a2e7-f67f1aa84175
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770796518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2770796518
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.345243359
Short name T24
Test name
Test status
Simulation time 58877779 ps
CPU time 0.58 seconds
Started Aug 13 05:00:42 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 194680 kb
Host smart-d2d64597-2e89-4e42-a0ee-ea0842c9613a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345243359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.345243359
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3838692602
Short name T147
Test name
Test status
Simulation time 101519104 ps
CPU time 0.89 seconds
Started Aug 13 05:00:43 PM PDT 24
Finished Aug 13 05:00:45 PM PDT 24
Peak memory 196620 kb
Host smart-61db6e6e-7633-423a-b405-6f26436ddc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838692602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3838692602
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1745155062
Short name T519
Test name
Test status
Simulation time 381010208 ps
CPU time 16.6 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:58 PM PDT 24
Peak memory 198152 kb
Host smart-b7e904f3-e452-485d-9ce1-e16935182d03
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745155062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1745155062
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.566620921
Short name T659
Test name
Test status
Simulation time 111912197 ps
CPU time 0.71 seconds
Started Aug 13 05:00:43 PM PDT 24
Finished Aug 13 05:00:44 PM PDT 24
Peak memory 194704 kb
Host smart-c22a51a7-39da-4f9c-8fff-7f7ad2272fbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566620921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.566620921
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2760325895
Short name T39
Test name
Test status
Simulation time 308995015 ps
CPU time 1.05 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:42 PM PDT 24
Peak memory 195884 kb
Host smart-e00481fc-5ece-4552-af4c-ce3cba31e896
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760325895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2760325895
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.744680983
Short name T360
Test name
Test status
Simulation time 214071111 ps
CPU time 2.21 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:44 PM PDT 24
Peak memory 198208 kb
Host smart-6176a9e9-2b72-48b8-90e3-f49866a3a7b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744680983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.744680983
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.10658664
Short name T297
Test name
Test status
Simulation time 29404096 ps
CPU time 0.93 seconds
Started Aug 13 05:00:42 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 195292 kb
Host smart-942cd914-fb92-4663-84b6-4c809504c236
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10658664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.10658664
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3405417741
Short name T533
Test name
Test status
Simulation time 71488955 ps
CPU time 1.28 seconds
Started Aug 13 05:00:43 PM PDT 24
Finished Aug 13 05:00:44 PM PDT 24
Peak memory 195936 kb
Host smart-1ca53c6f-1b1e-4ca1-9159-a83b45b87a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405417741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3405417741
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2219744154
Short name T246
Test name
Test status
Simulation time 81646320 ps
CPU time 0.96 seconds
Started Aug 13 05:00:43 PM PDT 24
Finished Aug 13 05:00:44 PM PDT 24
Peak memory 196848 kb
Host smart-da59754f-9d38-45a4-a312-e3db0c280bff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219744154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2219744154
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2763452698
Short name T621
Test name
Test status
Simulation time 55720225 ps
CPU time 2.66 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:50 PM PDT 24
Peak memory 198056 kb
Host smart-7bace399-cfa6-44fb-8b9b-207ddb08baee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763452698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2763452698
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2316069942
Short name T282
Test name
Test status
Simulation time 167904688 ps
CPU time 1.08 seconds
Started Aug 13 05:00:39 PM PDT 24
Finished Aug 13 05:00:40 PM PDT 24
Peak memory 195876 kb
Host smart-ce98dde6-d115-47a8-9eb4-e017c265e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316069942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2316069942
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2524536428
Short name T229
Test name
Test status
Simulation time 233006684 ps
CPU time 1.17 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:42 PM PDT 24
Peak memory 195628 kb
Host smart-607977c3-5cd5-419d-b73e-c74025d2e1f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524536428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2524536428
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.745458270
Short name T711
Test name
Test status
Simulation time 36013241224 ps
CPU time 85.38 seconds
Started Aug 13 05:00:43 PM PDT 24
Finished Aug 13 05:02:08 PM PDT 24
Peak memory 198188 kb
Host smart-c28caad7-b057-4a19-a6e4-6ccbe38686b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745458270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.745458270
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3825106146
Short name T36
Test name
Test status
Simulation time 12517434 ps
CPU time 0.62 seconds
Started Aug 13 05:00:45 PM PDT 24
Finished Aug 13 05:00:45 PM PDT 24
Peak memory 194768 kb
Host smart-89b047cf-c156-484f-a2f6-c1d4cbf0b7b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825106146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3825106146
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2192498872
Short name T125
Test name
Test status
Simulation time 108021459 ps
CPU time 0.82 seconds
Started Aug 13 05:00:43 PM PDT 24
Finished Aug 13 05:00:44 PM PDT 24
Peak memory 195284 kb
Host smart-63e5a07f-b354-46d4-b5ba-f301961f4678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192498872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2192498872
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.464600072
Short name T302
Test name
Test status
Simulation time 810975746 ps
CPU time 26.03 seconds
Started Aug 13 05:00:43 PM PDT 24
Finished Aug 13 05:01:09 PM PDT 24
Peak memory 198116 kb
Host smart-fcfd6a71-e629-4059-833c-29b17ab83085
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464600072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.464600072
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3197673108
Short name T415
Test name
Test status
Simulation time 137042518 ps
CPU time 1.09 seconds
Started Aug 13 05:00:45 PM PDT 24
Finished Aug 13 05:00:47 PM PDT 24
Peak memory 196512 kb
Host smart-c49b9546-108a-4912-969f-e7c30ed41155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197673108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3197673108
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.419766034
Short name T188
Test name
Test status
Simulation time 109329176 ps
CPU time 1.65 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:49 PM PDT 24
Peak memory 197112 kb
Host smart-38ead936-b8b1-447f-b16d-5feac1b32a27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419766034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.419766034
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.210698710
Short name T280
Test name
Test status
Simulation time 68098881 ps
CPU time 2.75 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:45 PM PDT 24
Peak memory 196364 kb
Host smart-c4215a07-59e0-439a-acee-4b538af0f3fa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210698710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.210698710
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1422080290
Short name T488
Test name
Test status
Simulation time 113151965 ps
CPU time 3.14 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:45 PM PDT 24
Peak memory 198208 kb
Host smart-90420408-7548-4b46-b2ac-9cafe408e8a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422080290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1422080290
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3759806444
Short name T624
Test name
Test status
Simulation time 33678786 ps
CPU time 0.91 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:48 PM PDT 24
Peak memory 196460 kb
Host smart-e34907f6-5041-47c6-97f1-53aed67bd57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759806444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3759806444
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.4020773403
Short name T474
Test name
Test status
Simulation time 103392839 ps
CPU time 1.08 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 196980 kb
Host smart-3c5ea166-4222-4228-ac86-4e8ed9beec45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020773403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.4020773403
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2683435646
Short name T168
Test name
Test status
Simulation time 7375893713 ps
CPU time 6.01 seconds
Started Aug 13 05:00:43 PM PDT 24
Finished Aug 13 05:00:49 PM PDT 24
Peak memory 198244 kb
Host smart-7a207e5d-c36d-40b9-99dd-689716a1fcc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683435646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2683435646
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1535319290
Short name T322
Test name
Test status
Simulation time 64452952 ps
CPU time 1.29 seconds
Started Aug 13 05:00:42 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 196892 kb
Host smart-4f393b29-f047-4468-8d33-e5bfafe3291d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535319290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1535319290
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3029388091
Short name T175
Test name
Test status
Simulation time 159926401 ps
CPU time 0.87 seconds
Started Aug 13 05:00:44 PM PDT 24
Finished Aug 13 05:00:45 PM PDT 24
Peak memory 195968 kb
Host smart-bb286d26-3e4f-4815-ab90-91e6231fabd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029388091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3029388091
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4166104469
Short name T426
Test name
Test status
Simulation time 6158078826 ps
CPU time 175.82 seconds
Started Aug 13 05:00:45 PM PDT 24
Finished Aug 13 05:03:41 PM PDT 24
Peak memory 192124 kb
Host smart-c9c5b604-49c1-44b8-9df2-3e3e9924575f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166104469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4166104469
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3415400985
Short name T694
Test name
Test status
Simulation time 17399231 ps
CPU time 0.59 seconds
Started Aug 13 05:00:39 PM PDT 24
Finished Aug 13 05:00:40 PM PDT 24
Peak memory 193996 kb
Host smart-f83b6b62-ec08-4712-b718-5bf81c020abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415400985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3415400985
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3542067918
Short name T311
Test name
Test status
Simulation time 93796277 ps
CPU time 0.61 seconds
Started Aug 13 05:00:45 PM PDT 24
Finished Aug 13 05:00:46 PM PDT 24
Peak memory 193992 kb
Host smart-e5762b09-6b57-4e6c-8603-6be6c0713533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542067918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3542067918
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.719600525
Short name T459
Test name
Test status
Simulation time 382366093 ps
CPU time 9.88 seconds
Started Aug 13 05:00:46 PM PDT 24
Finished Aug 13 05:00:56 PM PDT 24
Peak memory 197176 kb
Host smart-65455dc5-8354-4b0b-a4f5-53bb9b1053cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719600525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.719600525
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3249146609
Short name T662
Test name
Test status
Simulation time 159084876 ps
CPU time 1.05 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 196644 kb
Host smart-7b637ad8-e0f7-41e6-94bb-69b2e3eed59c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249146609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3249146609
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2483967846
Short name T387
Test name
Test status
Simulation time 46947591 ps
CPU time 0.95 seconds
Started Aug 13 05:00:45 PM PDT 24
Finished Aug 13 05:00:46 PM PDT 24
Peak memory 197356 kb
Host smart-0d446859-95b9-4718-81c9-00431e88177b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483967846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2483967846
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3177651924
Short name T436
Test name
Test status
Simulation time 1169612129 ps
CPU time 3.44 seconds
Started Aug 13 05:00:48 PM PDT 24
Finished Aug 13 05:00:51 PM PDT 24
Peak memory 198300 kb
Host smart-95bb7424-e9a4-4e29-82ea-1b73a00038e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177651924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3177651924
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2260368357
Short name T289
Test name
Test status
Simulation time 105724262 ps
CPU time 3.13 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:50 PM PDT 24
Peak memory 197144 kb
Host smart-03f559a2-aea4-4d85-9d6c-f00be1ed668c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260368357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2260368357
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2378791189
Short name T413
Test name
Test status
Simulation time 67103570 ps
CPU time 0.86 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 196516 kb
Host smart-698b03cf-f5b5-48bf-8e6a-b508dd416615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378791189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2378791189
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2587363986
Short name T227
Test name
Test status
Simulation time 33600771 ps
CPU time 1.19 seconds
Started Aug 13 05:00:44 PM PDT 24
Finished Aug 13 05:00:45 PM PDT 24
Peak memory 196980 kb
Host smart-aa3f35ef-3ff4-411f-acff-eddd5508d044
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587363986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2587363986
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2264382966
Short name T603
Test name
Test status
Simulation time 865952146 ps
CPU time 2.44 seconds
Started Aug 13 05:00:45 PM PDT 24
Finished Aug 13 05:00:47 PM PDT 24
Peak memory 198124 kb
Host smart-70b47265-5d9f-46b9-ac06-7766d55933b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264382966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2264382966
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3341171837
Short name T681
Test name
Test status
Simulation time 54030926 ps
CPU time 1.43 seconds
Started Aug 13 05:00:45 PM PDT 24
Finished Aug 13 05:00:46 PM PDT 24
Peak memory 196824 kb
Host smart-b598749a-d0cc-4f1e-875c-f38126c12026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341171837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3341171837
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2706941020
Short name T557
Test name
Test status
Simulation time 167912281 ps
CPU time 1.25 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:48 PM PDT 24
Peak memory 195672 kb
Host smart-c2965834-26cb-4893-81ea-3232168ca6d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706941020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2706941020
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.599138404
Short name T688
Test name
Test status
Simulation time 16974271747 ps
CPU time 233.82 seconds
Started Aug 13 05:00:45 PM PDT 24
Finished Aug 13 05:04:39 PM PDT 24
Peak memory 198260 kb
Host smart-78efde00-ead3-4cfd-9a2d-55c857f1b809
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599138404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.599138404
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2498248679
Short name T293
Test name
Test status
Simulation time 23610769 ps
CPU time 0.63 seconds
Started Aug 13 05:00:46 PM PDT 24
Finished Aug 13 05:00:46 PM PDT 24
Peak memory 194180 kb
Host smart-443e60aa-f06a-452b-945c-44091e8c7512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498248679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2498248679
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3887012385
Short name T211
Test name
Test status
Simulation time 101106582 ps
CPU time 0.72 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:48 PM PDT 24
Peak memory 195380 kb
Host smart-f11f37d3-31f5-428e-a2cb-c26fc61e03a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887012385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3887012385
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2632828844
Short name T226
Test name
Test status
Simulation time 218314662 ps
CPU time 4.7 seconds
Started Aug 13 05:00:50 PM PDT 24
Finished Aug 13 05:00:54 PM PDT 24
Peak memory 196976 kb
Host smart-6a09b632-09a3-4468-8f9d-5d443a66ea6f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632828844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2632828844
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3825095892
Short name T619
Test name
Test status
Simulation time 53584079 ps
CPU time 0.84 seconds
Started Aug 13 05:00:46 PM PDT 24
Finished Aug 13 05:00:48 PM PDT 24
Peak memory 196552 kb
Host smart-7555cb8c-540c-41f3-89d0-0d0e8ed9d0b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825095892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3825095892
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2964652736
Short name T667
Test name
Test status
Simulation time 20140945 ps
CPU time 0.69 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:47 PM PDT 24
Peak memory 194308 kb
Host smart-85afeb45-5f80-4d5c-b7a9-23fee8dc77b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964652736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2964652736
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1274748411
Short name T62
Test name
Test status
Simulation time 53985746 ps
CPU time 2.11 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:49 PM PDT 24
Peak memory 198192 kb
Host smart-4928ba1e-0def-4890-8e29-e562ce9b2939
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274748411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1274748411
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2875988219
Short name T332
Test name
Test status
Simulation time 78143055 ps
CPU time 2.21 seconds
Started Aug 13 05:00:49 PM PDT 24
Finished Aug 13 05:00:51 PM PDT 24
Peak memory 197052 kb
Host smart-ce0150f0-09ea-45f9-8500-2788f7b5c9c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875988219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2875988219
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.4019570430
Short name T342
Test name
Test status
Simulation time 76284440 ps
CPU time 1 seconds
Started Aug 13 05:00:39 PM PDT 24
Finished Aug 13 05:00:41 PM PDT 24
Peak memory 196832 kb
Host smart-aa360e7d-24a5-409f-a139-4d64979a2237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019570430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.4019570430
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1868709980
Short name T296
Test name
Test status
Simulation time 78123208 ps
CPU time 0.91 seconds
Started Aug 13 05:00:40 PM PDT 24
Finished Aug 13 05:00:41 PM PDT 24
Peak memory 196848 kb
Host smart-31f83509-9914-491d-9601-b859d93f3313
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868709980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1868709980
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2666090168
Short name T2
Test name
Test status
Simulation time 7309788758 ps
CPU time 6.33 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:54 PM PDT 24
Peak memory 198172 kb
Host smart-5477f4c6-6aea-465f-a33f-818bf845b52b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666090168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2666090168
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.826081688
Short name T264
Test name
Test status
Simulation time 188326777 ps
CPU time 0.98 seconds
Started Aug 13 05:00:41 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 195876 kb
Host smart-d564216e-ed81-4349-bbac-910931442623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826081688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.826081688
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1359893412
Short name T585
Test name
Test status
Simulation time 261434077 ps
CPU time 1.06 seconds
Started Aug 13 05:00:42 PM PDT 24
Finished Aug 13 05:00:43 PM PDT 24
Peak memory 195868 kb
Host smart-0e49f34b-d1cc-4de7-b843-655524d8f8dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359893412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1359893412
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.784666500
Short name T398
Test name
Test status
Simulation time 3737611852 ps
CPU time 50.78 seconds
Started Aug 13 05:00:51 PM PDT 24
Finished Aug 13 05:01:42 PM PDT 24
Peak memory 198324 kb
Host smart-b11c0f3f-d776-46eb-a514-1a9170a339d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784666500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.784666500
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2905500530
Short name T203
Test name
Test status
Simulation time 26681755 ps
CPU time 0.6 seconds
Started Aug 13 05:00:50 PM PDT 24
Finished Aug 13 05:00:51 PM PDT 24
Peak memory 194908 kb
Host smart-9341b688-ff01-48f9-902e-dda29da9a4e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905500530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2905500530
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.977330873
Short name T625
Test name
Test status
Simulation time 25868583 ps
CPU time 0.79 seconds
Started Aug 13 05:00:46 PM PDT 24
Finished Aug 13 05:00:47 PM PDT 24
Peak memory 195488 kb
Host smart-9a7f7253-f313-4f87-953b-4475888b6ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977330873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.977330873
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.381146582
Short name T160
Test name
Test status
Simulation time 601922571 ps
CPU time 17.44 seconds
Started Aug 13 05:00:54 PM PDT 24
Finished Aug 13 05:01:11 PM PDT 24
Peak memory 198056 kb
Host smart-06b63dcb-ed0f-4459-8ed3-1379f3f343ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381146582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.381146582
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2099367502
Short name T33
Test name
Test status
Simulation time 45156095 ps
CPU time 0.78 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:48 PM PDT 24
Peak memory 195940 kb
Host smart-0768d312-9b0d-4c7e-969a-6a732ed4920e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099367502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2099367502
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2821153074
Short name T423
Test name
Test status
Simulation time 1028084225 ps
CPU time 1.29 seconds
Started Aug 13 05:00:54 PM PDT 24
Finished Aug 13 05:00:56 PM PDT 24
Peak memory 195832 kb
Host smart-261bb377-8a96-465d-b1b4-56fdd0fd99de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821153074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2821153074
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1554610370
Short name T202
Test name
Test status
Simulation time 171878017 ps
CPU time 3.46 seconds
Started Aug 13 05:00:45 PM PDT 24
Finished Aug 13 05:00:49 PM PDT 24
Peak memory 198152 kb
Host smart-608af4c5-c419-4087-b34e-5ff1bbeb78bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554610370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1554610370
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.367753090
Short name T609
Test name
Test status
Simulation time 91004838 ps
CPU time 1.92 seconds
Started Aug 13 05:00:49 PM PDT 24
Finished Aug 13 05:00:51 PM PDT 24
Peak memory 195964 kb
Host smart-72c7c034-e912-4304-a748-12cc0bb7b950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367753090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
367753090
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2155255603
Short name T137
Test name
Test status
Simulation time 345929833 ps
CPU time 1.36 seconds
Started Aug 13 05:00:52 PM PDT 24
Finished Aug 13 05:00:53 PM PDT 24
Peak memory 198176 kb
Host smart-0a020fef-4d86-46f4-a64c-71addda05f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155255603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2155255603
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3329917256
Short name T653
Test name
Test status
Simulation time 40362111 ps
CPU time 0.73 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:48 PM PDT 24
Peak memory 195564 kb
Host smart-5e02b75e-f226-4ff4-a787-53bafbf1582a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329917256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3329917256
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1003175578
Short name T422
Test name
Test status
Simulation time 2451763984 ps
CPU time 3.79 seconds
Started Aug 13 05:00:53 PM PDT 24
Finished Aug 13 05:00:56 PM PDT 24
Peak memory 198180 kb
Host smart-398e86d9-6b7d-4c2d-93be-24e9a45c1e6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003175578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1003175578
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2690291237
Short name T521
Test name
Test status
Simulation time 53373784 ps
CPU time 1.08 seconds
Started Aug 13 05:00:49 PM PDT 24
Finished Aug 13 05:00:50 PM PDT 24
Peak memory 196336 kb
Host smart-16044b93-1546-485f-9742-f31770229ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690291237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2690291237
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1645292348
Short name T351
Test name
Test status
Simulation time 166690502 ps
CPU time 0.86 seconds
Started Aug 13 05:00:49 PM PDT 24
Finished Aug 13 05:00:50 PM PDT 24
Peak memory 196136 kb
Host smart-0660571a-887d-407f-9448-7dcd9791b502
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645292348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1645292348
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2801044241
Short name T128
Test name
Test status
Simulation time 5433837993 ps
CPU time 72.99 seconds
Started Aug 13 05:00:50 PM PDT 24
Finished Aug 13 05:02:03 PM PDT 24
Peak memory 198228 kb
Host smart-e92d77e0-d337-496a-9c79-e664cd45d1d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801044241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2801044241
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4015387256
Short name T290
Test name
Test status
Simulation time 27085022 ps
CPU time 0.59 seconds
Started Aug 13 05:00:51 PM PDT 24
Finished Aug 13 05:00:51 PM PDT 24
Peak memory 194912 kb
Host smart-ac20a8bf-79c9-412a-823b-ece0a3631356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015387256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4015387256
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3156556601
Short name T660
Test name
Test status
Simulation time 66652029 ps
CPU time 0.67 seconds
Started Aug 13 05:00:47 PM PDT 24
Finished Aug 13 05:00:48 PM PDT 24
Peak memory 194084 kb
Host smart-1ee43c5b-2b0f-41e4-bf52-69a5b947cfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156556601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3156556601
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3957486940
Short name T672
Test name
Test status
Simulation time 268352372 ps
CPU time 9.88 seconds
Started Aug 13 05:00:54 PM PDT 24
Finished Aug 13 05:01:04 PM PDT 24
Peak memory 196952 kb
Host smart-e722f74f-1fa5-4fad-a74a-011b698055e6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957486940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3957486940
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1692252748
Short name T119
Test name
Test status
Simulation time 348511853 ps
CPU time 0.91 seconds
Started Aug 13 05:00:50 PM PDT 24
Finished Aug 13 05:00:52 PM PDT 24
Peak memory 196132 kb
Host smart-592c673c-b9e5-442b-ad2b-568ee33c4994
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692252748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1692252748
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.4096682019
Short name T707
Test name
Test status
Simulation time 254301103 ps
CPU time 1.08 seconds
Started Aug 13 05:00:49 PM PDT 24
Finished Aug 13 05:00:50 PM PDT 24
Peak memory 195956 kb
Host smart-ebf697ca-27e6-4266-83ca-b516e5eb666b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096682019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.4096682019
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2437712755
Short name T446
Test name
Test status
Simulation time 118055439 ps
CPU time 2.49 seconds
Started Aug 13 05:00:49 PM PDT 24
Finished Aug 13 05:00:51 PM PDT 24
Peak memory 198204 kb
Host smart-2f75bda2-3406-46b5-b2a3-8d622ded8776
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437712755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2437712755
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3948788223
Short name T255
Test name
Test status
Simulation time 176679672 ps
CPU time 1.54 seconds
Started Aug 13 05:00:49 PM PDT 24
Finished Aug 13 05:00:50 PM PDT 24
Peak memory 196888 kb
Host smart-f4b7cf4a-40f6-4e61-826d-568161062afd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948788223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3948788223
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1273773958
Short name T213
Test name
Test status
Simulation time 32967183 ps
CPU time 0.89 seconds
Started Aug 13 05:00:48 PM PDT 24
Finished Aug 13 05:00:49 PM PDT 24
Peak memory 197412 kb
Host smart-f85ae6ed-84ce-402d-87d9-9b1d75a47a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273773958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1273773958
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3332610074
Short name T525
Test name
Test status
Simulation time 719502323 ps
CPU time 1 seconds
Started Aug 13 05:00:51 PM PDT 24
Finished Aug 13 05:00:52 PM PDT 24
Peak memory 196116 kb
Host smart-3b53e7d7-ccee-4ec0-bf42-92c5f428c617
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332610074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3332610074
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2127358580
Short name T286
Test name
Test status
Simulation time 730168126 ps
CPU time 5.77 seconds
Started Aug 13 05:00:50 PM PDT 24
Finished Aug 13 05:00:56 PM PDT 24
Peak memory 198160 kb
Host smart-ff282b6b-e796-48f7-85fa-4bdf950370b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127358580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2127358580
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.4229149534
Short name T157
Test name
Test status
Simulation time 76540972 ps
CPU time 1.27 seconds
Started Aug 13 05:00:50 PM PDT 24
Finished Aug 13 05:00:51 PM PDT 24
Peak memory 196656 kb
Host smart-e8f2d987-433a-4105-8f0a-3c2f85d68b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229149534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.4229149534
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1148074130
Short name T274
Test name
Test status
Simulation time 59541265 ps
CPU time 0.99 seconds
Started Aug 13 05:00:50 PM PDT 24
Finished Aug 13 05:00:51 PM PDT 24
Peak memory 195664 kb
Host smart-f16ae690-d085-4d25-8a9c-37dd4b248a7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148074130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1148074130
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.4023965016
Short name T6
Test name
Test status
Simulation time 17330904475 ps
CPU time 212.18 seconds
Started Aug 13 05:00:50 PM PDT 24
Finished Aug 13 05:04:22 PM PDT 24
Peak memory 198372 kb
Host smart-141c2988-c2b3-482d-a999-98cea2d6eafb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023965016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.4023965016
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1693744924
Short name T559
Test name
Test status
Simulation time 17585842 ps
CPU time 0.54 seconds
Started Aug 13 05:00:55 PM PDT 24
Finished Aug 13 05:00:55 PM PDT 24
Peak memory 194008 kb
Host smart-ae277f1a-29c3-4b4d-bc62-f9cb5120e7bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693744924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1693744924
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.410894822
Short name T361
Test name
Test status
Simulation time 110223499 ps
CPU time 0.93 seconds
Started Aug 13 05:01:01 PM PDT 24
Finished Aug 13 05:01:02 PM PDT 24
Peak memory 195904 kb
Host smart-d418ee91-af26-4b30-af77-b91e588f8677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410894822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.410894822
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.656016214
Short name T448
Test name
Test status
Simulation time 1245368008 ps
CPU time 16.03 seconds
Started Aug 13 05:00:54 PM PDT 24
Finished Aug 13 05:01:10 PM PDT 24
Peak memory 198112 kb
Host smart-ccd6535e-bdbc-47ac-9c4a-03a91a1ef0ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656016214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.656016214
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1073040890
Short name T496
Test name
Test status
Simulation time 147094100 ps
CPU time 0.73 seconds
Started Aug 13 05:00:54 PM PDT 24
Finished Aug 13 05:00:55 PM PDT 24
Peak memory 195892 kb
Host smart-1664267e-3a3c-4f97-aacd-73d418af8e86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073040890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1073040890
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.763297270
Short name T698
Test name
Test status
Simulation time 57520321 ps
CPU time 0.97 seconds
Started Aug 13 05:00:56 PM PDT 24
Finished Aug 13 05:00:57 PM PDT 24
Peak memory 196120 kb
Host smart-61fd1e57-4b84-4019-a78d-cae1af282ebc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763297270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.763297270
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2975075637
Short name T331
Test name
Test status
Simulation time 43859632 ps
CPU time 1.8 seconds
Started Aug 13 05:00:57 PM PDT 24
Finished Aug 13 05:00:58 PM PDT 24
Peak memory 198260 kb
Host smart-6a44469a-bb1f-4c51-9e2f-c2d41dda03a1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975075637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2975075637
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.858243434
Short name T183
Test name
Test status
Simulation time 91794483 ps
CPU time 1.63 seconds
Started Aug 13 05:00:58 PM PDT 24
Finished Aug 13 05:00:59 PM PDT 24
Peak memory 196932 kb
Host smart-e498263d-887f-42ce-a413-16c2f9427b28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858243434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
858243434
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1435240027
Short name T714
Test name
Test status
Simulation time 34571479 ps
CPU time 1.31 seconds
Started Aug 13 05:00:50 PM PDT 24
Finished Aug 13 05:00:51 PM PDT 24
Peak memory 197032 kb
Host smart-d5150581-e80f-40df-aea2-dc6949304449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435240027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1435240027
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.4156713054
Short name T285
Test name
Test status
Simulation time 20889738 ps
CPU time 0.74 seconds
Started Aug 13 05:00:50 PM PDT 24
Finished Aug 13 05:00:51 PM PDT 24
Peak memory 195364 kb
Host smart-856e8161-081c-45ed-a417-cb34568e40f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156713054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.4156713054
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.4098694913
Short name T673
Test name
Test status
Simulation time 178754899 ps
CPU time 2.71 seconds
Started Aug 13 05:00:59 PM PDT 24
Finished Aug 13 05:01:02 PM PDT 24
Peak memory 198016 kb
Host smart-fd613f16-2580-4fcf-a0a6-b2b172c8f49a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098694913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.4098694913
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2948828683
Short name T138
Test name
Test status
Simulation time 40262094 ps
CPU time 0.91 seconds
Started Aug 13 05:00:54 PM PDT 24
Finished Aug 13 05:00:55 PM PDT 24
Peak memory 196368 kb
Host smart-cb983e02-bf66-4c68-a3e7-59a1e59b0521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948828683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2948828683
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3708188116
Short name T590
Test name
Test status
Simulation time 117063749 ps
CPU time 1.15 seconds
Started Aug 13 05:00:53 PM PDT 24
Finished Aug 13 05:00:54 PM PDT 24
Peak memory 195788 kb
Host smart-c4083826-bc1e-454e-a10c-95620b6aece8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708188116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3708188116
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1774284104
Short name T439
Test name
Test status
Simulation time 20781520306 ps
CPU time 53.59 seconds
Started Aug 13 05:01:03 PM PDT 24
Finished Aug 13 05:01:57 PM PDT 24
Peak memory 191964 kb
Host smart-9a880ebc-e38f-41b4-b839-9db224e61057
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774284104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1774284104
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2297898451
Short name T443
Test name
Test status
Simulation time 12047127 ps
CPU time 0.59 seconds
Started Aug 13 05:00:53 PM PDT 24
Finished Aug 13 05:00:53 PM PDT 24
Peak memory 193980 kb
Host smart-0cd89787-dcae-4ebb-be36-046a2ae2167d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297898451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2297898451
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2807280386
Short name T450
Test name
Test status
Simulation time 90424175 ps
CPU time 0.7 seconds
Started Aug 13 05:01:01 PM PDT 24
Finished Aug 13 05:01:02 PM PDT 24
Peak memory 194256 kb
Host smart-45528663-1e9b-43be-bf69-7eda9f0c5fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807280386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2807280386
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1509512992
Short name T193
Test name
Test status
Simulation time 853005997 ps
CPU time 24.94 seconds
Started Aug 13 05:00:59 PM PDT 24
Finished Aug 13 05:01:24 PM PDT 24
Peak memory 196936 kb
Host smart-dd5ca2c9-3c71-4a94-acbd-e6040e83404a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509512992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1509512992
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3418575339
Short name T45
Test name
Test status
Simulation time 1534232180 ps
CPU time 1.02 seconds
Started Aug 13 05:00:54 PM PDT 24
Finished Aug 13 05:00:56 PM PDT 24
Peak memory 196788 kb
Host smart-7a469056-5c5e-4a88-b05a-f75c04d5dad2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418575339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3418575339
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3479709313
Short name T457
Test name
Test status
Simulation time 445695551 ps
CPU time 1.28 seconds
Started Aug 13 05:00:53 PM PDT 24
Finished Aug 13 05:00:54 PM PDT 24
Peak memory 197104 kb
Host smart-9d282ffe-8c87-482d-b8da-2c8e4b7a280c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479709313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3479709313
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3741111226
Short name T503
Test name
Test status
Simulation time 32873562 ps
CPU time 1.3 seconds
Started Aug 13 05:00:57 PM PDT 24
Finished Aug 13 05:00:58 PM PDT 24
Peak memory 196880 kb
Host smart-c9faee7a-42cb-4467-b84f-66168ac3333c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741111226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3741111226
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2190627415
Short name T512
Test name
Test status
Simulation time 590417773 ps
CPU time 1.96 seconds
Started Aug 13 05:00:58 PM PDT 24
Finished Aug 13 05:01:00 PM PDT 24
Peak memory 196052 kb
Host smart-e83ce0e6-eb9b-414c-8c4f-73884d859dc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190627415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2190627415
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.119295349
Short name T148
Test name
Test status
Simulation time 19752824 ps
CPU time 0.72 seconds
Started Aug 13 05:00:57 PM PDT 24
Finished Aug 13 05:00:58 PM PDT 24
Peak memory 195364 kb
Host smart-ae8f2858-4420-4524-8ea2-400d709cefab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119295349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.119295349
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3029591853
Short name T588
Test name
Test status
Simulation time 26961608 ps
CPU time 0.82 seconds
Started Aug 13 05:01:03 PM PDT 24
Finished Aug 13 05:01:04 PM PDT 24
Peak memory 195488 kb
Host smart-34ff94cd-653c-4c86-a4dc-0732da12e8bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029591853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3029591853
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1290416881
Short name T642
Test name
Test status
Simulation time 97078381 ps
CPU time 4.42 seconds
Started Aug 13 05:01:03 PM PDT 24
Finished Aug 13 05:01:07 PM PDT 24
Peak memory 197988 kb
Host smart-eb329f16-d578-41ab-9d72-a997ef6f2011
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290416881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1290416881
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3511819450
Short name T225
Test name
Test status
Simulation time 84048577 ps
CPU time 1.28 seconds
Started Aug 13 05:01:01 PM PDT 24
Finished Aug 13 05:01:02 PM PDT 24
Peak memory 196052 kb
Host smart-e9d81980-4433-42e4-bd11-39d6ae44d249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511819450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3511819450
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3287074509
Short name T14
Test name
Test status
Simulation time 50363957 ps
CPU time 0.93 seconds
Started Aug 13 05:00:54 PM PDT 24
Finished Aug 13 05:00:55 PM PDT 24
Peak memory 196424 kb
Host smart-c7d3aa1d-34b6-4d6f-999b-7a2195a8e573
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287074509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3287074509
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.885502977
Short name T273
Test name
Test status
Simulation time 4866100100 ps
CPU time 123.42 seconds
Started Aug 13 05:00:54 PM PDT 24
Finished Aug 13 05:02:58 PM PDT 24
Peak memory 198296 kb
Host smart-8e857774-d27e-42b7-b9c5-ab579618c834
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885502977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.885502977
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.4234879327
Short name T65
Test name
Test status
Simulation time 4398016064 ps
CPU time 92.6 seconds
Started Aug 13 05:00:56 PM PDT 24
Finished Aug 13 05:02:28 PM PDT 24
Peak memory 198456 kb
Host smart-38409e6a-7cf7-4783-85d9-903f6c877884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4234879327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.4234879327
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1479899333
Short name T240
Test name
Test status
Simulation time 20773553 ps
CPU time 0.62 seconds
Started Aug 13 05:01:00 PM PDT 24
Finished Aug 13 05:01:00 PM PDT 24
Peak memory 194244 kb
Host smart-182c3519-c39e-4e3e-b282-7457bb34a238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479899333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1479899333
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1426725061
Short name T253
Test name
Test status
Simulation time 48924738 ps
CPU time 0.88 seconds
Started Aug 13 05:01:04 PM PDT 24
Finished Aug 13 05:01:04 PM PDT 24
Peak memory 195460 kb
Host smart-b91b7a8c-6e72-4815-8b4e-927b2625d010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426725061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1426725061
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1518789882
Short name T472
Test name
Test status
Simulation time 926666879 ps
CPU time 6.33 seconds
Started Aug 13 05:00:57 PM PDT 24
Finished Aug 13 05:01:04 PM PDT 24
Peak memory 195704 kb
Host smart-475576f1-baaa-4399-8c34-ece2a01257af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518789882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1518789882
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.609272705
Short name T633
Test name
Test status
Simulation time 97422335 ps
CPU time 0.66 seconds
Started Aug 13 05:00:57 PM PDT 24
Finished Aug 13 05:00:57 PM PDT 24
Peak memory 194596 kb
Host smart-adb6138e-893e-4899-8051-f56e05750a83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609272705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.609272705
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3126645288
Short name T38
Test name
Test status
Simulation time 37017771 ps
CPU time 1.04 seconds
Started Aug 13 05:00:56 PM PDT 24
Finished Aug 13 05:00:58 PM PDT 24
Peak memory 196216 kb
Host smart-a37d608b-2716-4c2c-867e-e928a4a55036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126645288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3126645288
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.85173657
Short name T451
Test name
Test status
Simulation time 48904097 ps
CPU time 2.04 seconds
Started Aug 13 05:00:55 PM PDT 24
Finished Aug 13 05:00:57 PM PDT 24
Peak memory 198124 kb
Host smart-907a7132-e6e6-41d5-87ac-f078d9c88ace
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85173657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.gpio_intr_with_filter_rand_intr_event.85173657
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.634366849
Short name T540
Test name
Test status
Simulation time 640601747 ps
CPU time 2.23 seconds
Started Aug 13 05:00:59 PM PDT 24
Finished Aug 13 05:01:01 PM PDT 24
Peak memory 197136 kb
Host smart-b3080227-5fd9-4b6c-827e-d510db2e6bdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634366849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
634366849
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1068468310
Short name T396
Test name
Test status
Simulation time 57506140 ps
CPU time 0.93 seconds
Started Aug 13 05:00:56 PM PDT 24
Finished Aug 13 05:00:57 PM PDT 24
Peak memory 196016 kb
Host smart-0a600838-bf1a-47d0-bfb2-6cdd832211eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068468310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1068468310
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2652211840
Short name T704
Test name
Test status
Simulation time 34603585 ps
CPU time 0.98 seconds
Started Aug 13 05:00:56 PM PDT 24
Finished Aug 13 05:00:57 PM PDT 24
Peak memory 196728 kb
Host smart-4ff9a449-3af9-4f64-a41b-d269f953e9eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652211840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2652211840
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3274314531
Short name T461
Test name
Test status
Simulation time 311002714 ps
CPU time 5.36 seconds
Started Aug 13 05:00:52 PM PDT 24
Finished Aug 13 05:00:58 PM PDT 24
Peak memory 198096 kb
Host smart-cefe7d43-15e8-4afd-a936-593a701191b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274314531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3274314531
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.766840447
Short name T121
Test name
Test status
Simulation time 241518180 ps
CPU time 1.21 seconds
Started Aug 13 05:00:55 PM PDT 24
Finished Aug 13 05:00:57 PM PDT 24
Peak memory 195912 kb
Host smart-11e89a9e-6c21-4784-b6fe-9fe427b56b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766840447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.766840447
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.387218760
Short name T689
Test name
Test status
Simulation time 33341218 ps
CPU time 1.01 seconds
Started Aug 13 05:00:58 PM PDT 24
Finished Aug 13 05:00:59 PM PDT 24
Peak memory 195900 kb
Host smart-9e2e52a6-1d13-4fd3-b26f-87fa213b2b2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387218760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.387218760
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.848696470
Short name T18
Test name
Test status
Simulation time 18570280666 ps
CPU time 74.42 seconds
Started Aug 13 05:00:59 PM PDT 24
Finished Aug 13 05:02:14 PM PDT 24
Peak memory 198296 kb
Host smart-5cd6ba99-cfc8-4697-b788-3678de9ebc38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848696470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.848696470
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2690710189
Short name T10
Test name
Test status
Simulation time 1218804451 ps
CPU time 19.28 seconds
Started Aug 13 05:00:54 PM PDT 24
Finished Aug 13 05:01:14 PM PDT 24
Peak memory 198272 kb
Host smart-b5de1561-10b1-4581-ba68-20417e4cb9ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2690710189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2690710189
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3158728020
Short name T664
Test name
Test status
Simulation time 14325441 ps
CPU time 0.59 seconds
Started Aug 13 04:59:34 PM PDT 24
Finished Aug 13 04:59:35 PM PDT 24
Peak memory 194200 kb
Host smart-143a96fc-5559-4228-8d94-e6856c15181a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158728020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3158728020
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.604162257
Short name T269
Test name
Test status
Simulation time 47069452 ps
CPU time 0.95 seconds
Started Aug 13 04:59:33 PM PDT 24
Finished Aug 13 04:59:34 PM PDT 24
Peak memory 196612 kb
Host smart-abd88726-105e-4e32-a6e6-abd09f5d0b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604162257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.604162257
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2156598431
Short name T190
Test name
Test status
Simulation time 3686393072 ps
CPU time 16.7 seconds
Started Aug 13 04:59:36 PM PDT 24
Finished Aug 13 04:59:53 PM PDT 24
Peak memory 196048 kb
Host smart-dd2f59cc-5e0a-493c-8660-0167020cebe7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156598431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2156598431
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1560018076
Short name T405
Test name
Test status
Simulation time 67160631 ps
CPU time 0.7 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:32 PM PDT 24
Peak memory 194636 kb
Host smart-8e7f49f0-da47-453a-959f-7fc4097e231b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560018076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1560018076
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1414375636
Short name T42
Test name
Test status
Simulation time 59230700 ps
CPU time 0.69 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:33 PM PDT 24
Peak memory 194424 kb
Host smart-5ae3ab7d-8659-4da6-85bf-e2a55192dd8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414375636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1414375636
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1340453553
Short name T468
Test name
Test status
Simulation time 121683769 ps
CPU time 2.61 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:35 PM PDT 24
Peak memory 198088 kb
Host smart-42cd3025-0351-4264-abfe-c168534c2b97
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340453553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1340453553
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2242971936
Short name T506
Test name
Test status
Simulation time 71881464 ps
CPU time 1.66 seconds
Started Aug 13 04:59:31 PM PDT 24
Finished Aug 13 04:59:33 PM PDT 24
Peak memory 196116 kb
Host smart-86fc1781-decf-4d3f-874f-cb4e2045fa14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242971936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2242971936
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3368200190
Short name T679
Test name
Test status
Simulation time 22015201 ps
CPU time 0.89 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:33 PM PDT 24
Peak memory 196820 kb
Host smart-145b1936-5ffc-45ad-9f00-abbd1dd23aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368200190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3368200190
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2013552365
Short name T386
Test name
Test status
Simulation time 26108303 ps
CPU time 0.84 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:33 PM PDT 24
Peak memory 195540 kb
Host smart-8eef0a3c-b47e-4339-8365-6d8128a0f958
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013552365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2013552365
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3573500292
Short name T126
Test name
Test status
Simulation time 196326162 ps
CPU time 1.42 seconds
Started Aug 13 04:59:36 PM PDT 24
Finished Aug 13 04:59:38 PM PDT 24
Peak memory 198088 kb
Host smart-0f763081-5a88-4692-891f-13a3f5efff4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573500292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3573500292
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2152909679
Short name T59
Test name
Test status
Simulation time 296600422 ps
CPU time 0.8 seconds
Started Aug 13 04:59:34 PM PDT 24
Finished Aug 13 04:59:34 PM PDT 24
Peak memory 213944 kb
Host smart-94575c2c-c2a2-40ed-91b0-360e1833c59c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152909679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2152909679
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2804190532
Short name T710
Test name
Test status
Simulation time 35258355 ps
CPU time 1 seconds
Started Aug 13 04:59:31 PM PDT 24
Finished Aug 13 04:59:32 PM PDT 24
Peak memory 195812 kb
Host smart-b0ec663c-b5e0-4f14-8ff8-0b666d26c8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804190532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2804190532
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.4042765397
Short name T380
Test name
Test status
Simulation time 59119559 ps
CPU time 1.03 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:33 PM PDT 24
Peak memory 196632 kb
Host smart-843b2a05-6905-40cb-a894-e779d1baefee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042765397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.4042765397
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2110150018
Short name T549
Test name
Test status
Simulation time 7633700462 ps
CPU time 88.66 seconds
Started Aug 13 04:59:30 PM PDT 24
Finished Aug 13 05:00:59 PM PDT 24
Peak memory 198356 kb
Host smart-dff6508c-a346-4120-8f3e-6f2ce824ce84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110150018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2110150018
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3525472346
Short name T67
Test name
Test status
Simulation time 11643505366 ps
CPU time 198.32 seconds
Started Aug 13 04:59:37 PM PDT 24
Finished Aug 13 05:02:55 PM PDT 24
Peak memory 198456 kb
Host smart-ca6659cb-3f0a-402c-8862-7cad1edeac7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3525472346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3525472346
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.165596547
Short name T299
Test name
Test status
Simulation time 21639263 ps
CPU time 0.56 seconds
Started Aug 13 05:01:00 PM PDT 24
Finished Aug 13 05:01:01 PM PDT 24
Peak memory 194000 kb
Host smart-dd5b0db9-7f8f-4e47-93c9-9d4f01e7be04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165596547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.165596547
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2279933241
Short name T144
Test name
Test status
Simulation time 17655335 ps
CPU time 0.65 seconds
Started Aug 13 05:01:03 PM PDT 24
Finished Aug 13 05:01:04 PM PDT 24
Peak memory 194008 kb
Host smart-a7d69244-1be0-4b89-a684-5838257df62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279933241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2279933241
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2314826551
Short name T177
Test name
Test status
Simulation time 892402645 ps
CPU time 13.4 seconds
Started Aug 13 05:01:02 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 196904 kb
Host smart-ecdfd838-2d76-4af8-837b-c98e7f90f54b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314826551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2314826551
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2208429020
Short name T313
Test name
Test status
Simulation time 65009363 ps
CPU time 0.91 seconds
Started Aug 13 05:01:00 PM PDT 24
Finished Aug 13 05:01:01 PM PDT 24
Peak memory 195992 kb
Host smart-cd97a52a-bff3-46c0-8795-7d44190eb492
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208429020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2208429020
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3001155337
Short name T117
Test name
Test status
Simulation time 54210520 ps
CPU time 0.91 seconds
Started Aug 13 05:01:03 PM PDT 24
Finished Aug 13 05:01:04 PM PDT 24
Peak memory 196852 kb
Host smart-ee83daa0-9ea5-490e-adeb-6830f694f0dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001155337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3001155337
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.368869560
Short name T577
Test name
Test status
Simulation time 215374548 ps
CPU time 2.27 seconds
Started Aug 13 05:00:56 PM PDT 24
Finished Aug 13 05:00:58 PM PDT 24
Peak memory 198060 kb
Host smart-65c6ac70-dbf9-49f0-ace3-89cb7db3486b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368869560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.368869560
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.142366915
Short name T276
Test name
Test status
Simulation time 123869263 ps
CPU time 1.05 seconds
Started Aug 13 05:00:59 PM PDT 24
Finished Aug 13 05:01:00 PM PDT 24
Peak memory 195412 kb
Host smart-7db70dc6-5a06-43bf-880e-7fa3d376179d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142366915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
142366915
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3666416378
Short name T228
Test name
Test status
Simulation time 55898143 ps
CPU time 0.79 seconds
Started Aug 13 05:00:56 PM PDT 24
Finished Aug 13 05:00:57 PM PDT 24
Peak memory 195448 kb
Host smart-c0ad6064-7514-4e8b-a9db-1f877b8c0167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666416378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3666416378
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1491403309
Short name T397
Test name
Test status
Simulation time 42078890 ps
CPU time 1.32 seconds
Started Aug 13 05:00:53 PM PDT 24
Finished Aug 13 05:00:54 PM PDT 24
Peak memory 198120 kb
Host smart-5ac52b31-6f55-4097-834d-09c634f70d20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491403309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1491403309
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3961088121
Short name T617
Test name
Test status
Simulation time 3648440828 ps
CPU time 4.75 seconds
Started Aug 13 05:01:01 PM PDT 24
Finished Aug 13 05:01:05 PM PDT 24
Peak memory 198296 kb
Host smart-260c4a52-0696-47e3-966b-f2a5e6c410f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961088121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3961088121
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1877180800
Short name T524
Test name
Test status
Simulation time 34558349 ps
CPU time 1.13 seconds
Started Aug 13 05:01:01 PM PDT 24
Finished Aug 13 05:01:02 PM PDT 24
Peak memory 195772 kb
Host smart-80273b79-7159-41db-9715-6a25968f4102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877180800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1877180800
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.675569199
Short name T596
Test name
Test status
Simulation time 599810703 ps
CPU time 1.27 seconds
Started Aug 13 05:00:59 PM PDT 24
Finished Aug 13 05:01:00 PM PDT 24
Peak memory 197248 kb
Host smart-c1432a72-dffc-4cf5-8009-fec9bd3744b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675569199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.675569199
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3539572974
Short name T427
Test name
Test status
Simulation time 76627716349 ps
CPU time 219.55 seconds
Started Aug 13 05:01:03 PM PDT 24
Finished Aug 13 05:04:43 PM PDT 24
Peak memory 198260 kb
Host smart-01c53ac2-4cc1-4eb7-8284-03ce136cbed9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539572974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3539572974
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.2902456386
Short name T71
Test name
Test status
Simulation time 5089133337 ps
CPU time 179.11 seconds
Started Aug 13 05:00:59 PM PDT 24
Finished Aug 13 05:03:58 PM PDT 24
Peak memory 198572 kb
Host smart-6ef86e54-e756-4077-ba6e-30680021ca11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2902456386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.2902456386
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2151638950
Short name T556
Test name
Test status
Simulation time 35154442 ps
CPU time 0.56 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:14 PM PDT 24
Peak memory 194708 kb
Host smart-b034bb8e-5e91-413a-ae2f-0f1e7141b7e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151638950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2151638950
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.4085748947
Short name T259
Test name
Test status
Simulation time 11829846 ps
CPU time 0.64 seconds
Started Aug 13 05:01:04 PM PDT 24
Finished Aug 13 05:01:04 PM PDT 24
Peak memory 193976 kb
Host smart-3508a510-3f7b-4913-85b7-7dcd008feaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085748947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.4085748947
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1322443453
Short name T40
Test name
Test status
Simulation time 1333964636 ps
CPU time 4.83 seconds
Started Aug 13 05:01:12 PM PDT 24
Finished Aug 13 05:01:17 PM PDT 24
Peak memory 195676 kb
Host smart-139619f7-f741-4355-b274-4adad86c32cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322443453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1322443453
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3341371123
Short name T32
Test name
Test status
Simulation time 43998009 ps
CPU time 0.72 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 194836 kb
Host smart-1993102a-5105-491f-8d46-fe71644a9557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341371123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3341371123
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3924742247
Short name T364
Test name
Test status
Simulation time 150639684 ps
CPU time 1.4 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 198168 kb
Host smart-601dbafb-1cf4-4d4f-ae3f-8279a45883ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924742247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3924742247
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2626888343
Short name T632
Test name
Test status
Simulation time 72640407 ps
CPU time 2.79 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:16 PM PDT 24
Peak memory 198092 kb
Host smart-13dd687c-10ff-42bd-8e75-4578684a1721
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626888343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2626888343
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2983156496
Short name T335
Test name
Test status
Simulation time 333856031 ps
CPU time 1.86 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:01:16 PM PDT 24
Peak memory 196088 kb
Host smart-5179be18-62a7-47e7-8b30-fc86f549bf5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983156496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2983156496
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1246668115
Short name T169
Test name
Test status
Simulation time 18801208 ps
CPU time 0.87 seconds
Started Aug 13 05:00:59 PM PDT 24
Finished Aug 13 05:01:00 PM PDT 24
Peak memory 196580 kb
Host smart-9e6d0c85-5f82-42ad-b2d1-e8ab56863ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246668115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1246668115
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3517563098
Short name T161
Test name
Test status
Simulation time 68176479 ps
CPU time 0.79 seconds
Started Aug 13 05:01:03 PM PDT 24
Finished Aug 13 05:01:04 PM PDT 24
Peak memory 196444 kb
Host smart-332a6cab-aec4-4d38-9f1e-37b14c2306b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517563098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3517563098
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2784884280
Short name T3
Test name
Test status
Simulation time 790510934 ps
CPU time 2.54 seconds
Started Aug 13 05:01:16 PM PDT 24
Finished Aug 13 05:01:18 PM PDT 24
Peak memory 198052 kb
Host smart-56ef4612-4039-426e-8e51-201113fa212e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784884280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2784884280
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3811104350
Short name T435
Test name
Test status
Simulation time 95397144 ps
CPU time 0.95 seconds
Started Aug 13 05:00:59 PM PDT 24
Finished Aug 13 05:01:00 PM PDT 24
Peak memory 196416 kb
Host smart-3efe5a2f-f1ab-4e0a-918b-2028b68123da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811104350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3811104350
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.4212886738
Short name T615
Test name
Test status
Simulation time 253136575 ps
CPU time 1.27 seconds
Started Aug 13 05:00:56 PM PDT 24
Finished Aug 13 05:00:57 PM PDT 24
Peak memory 196876 kb
Host smart-01160120-71a8-485f-a4ff-54ab8761a0c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212886738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.4212886738
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3087532721
Short name T7
Test name
Test status
Simulation time 25931351362 ps
CPU time 152.38 seconds
Started Aug 13 05:01:10 PM PDT 24
Finished Aug 13 05:03:43 PM PDT 24
Peak memory 198292 kb
Host smart-424ddb2d-3658-4888-bd54-346f53f0a867
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087532721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3087532721
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1959538941
Short name T265
Test name
Test status
Simulation time 14878208 ps
CPU time 0.58 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 194632 kb
Host smart-d7779967-a085-4e4e-a68d-10b764b84173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959538941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1959538941
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.653628148
Short name T463
Test name
Test status
Simulation time 30325033 ps
CPU time 0.9 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:14 PM PDT 24
Peak memory 195996 kb
Host smart-1893ed36-16a4-4bc2-981e-e2cdc858ce7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653628148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.653628148
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2534758693
Short name T13
Test name
Test status
Simulation time 543466453 ps
CPU time 13.87 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:27 PM PDT 24
Peak memory 197092 kb
Host smart-5b0ff7e7-5679-4652-8859-2d4bea44d2cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534758693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2534758693
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2386046391
Short name T30
Test name
Test status
Simulation time 181142886 ps
CPU time 0.83 seconds
Started Aug 13 05:01:12 PM PDT 24
Finished Aug 13 05:01:13 PM PDT 24
Peak memory 196656 kb
Host smart-acac0eae-0ca2-4126-9b5d-13119ce27a8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386046391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2386046391
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1526552217
Short name T419
Test name
Test status
Simulation time 30533635 ps
CPU time 0.71 seconds
Started Aug 13 05:01:08 PM PDT 24
Finished Aug 13 05:01:09 PM PDT 24
Peak memory 196144 kb
Host smart-0117f082-c95d-4e5f-90b5-77e5eb6b1e4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526552217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1526552217
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1120997344
Short name T312
Test name
Test status
Simulation time 255048027 ps
CPU time 1.87 seconds
Started Aug 13 05:01:15 PM PDT 24
Finished Aug 13 05:01:17 PM PDT 24
Peak memory 198116 kb
Host smart-8c5db6a5-d6f4-4e29-87dc-6d0735e78ae4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120997344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1120997344
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3027646326
Short name T340
Test name
Test status
Simulation time 815731613 ps
CPU time 3.25 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:01:17 PM PDT 24
Peak memory 198108 kb
Host smart-7c5a87cb-a692-4776-a62e-c13000afd85e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027646326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3027646326
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2516993169
Short name T537
Test name
Test status
Simulation time 67415547 ps
CPU time 1.35 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 198184 kb
Host smart-721e87a0-bdf2-4a02-8c87-08626f6d54da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516993169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2516993169
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1023528462
Short name T587
Test name
Test status
Simulation time 107091036 ps
CPU time 1.25 seconds
Started Aug 13 05:01:16 PM PDT 24
Finished Aug 13 05:01:17 PM PDT 24
Peak memory 196108 kb
Host smart-b0cd136a-fe83-4e69-ba58-d6e91eab9fc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023528462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1023528462
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.58958736
Short name T371
Test name
Test status
Simulation time 240104295 ps
CPU time 2.36 seconds
Started Aug 13 05:01:16 PM PDT 24
Finished Aug 13 05:01:18 PM PDT 24
Peak memory 198084 kb
Host smart-5d1690cf-521d-473e-a2a4-b93ef8caaa1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58958736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand
om_long_reg_writes_reg_reads.58958736
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.810311291
Short name T395
Test name
Test status
Simulation time 219161321 ps
CPU time 1.19 seconds
Started Aug 13 05:01:12 PM PDT 24
Finished Aug 13 05:01:13 PM PDT 24
Peak memory 196668 kb
Host smart-e789cec2-4b4a-4724-b4b1-2eeec6bdfc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810311291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.810311291
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2336056800
Short name T248
Test name
Test status
Simulation time 86422850 ps
CPU time 1.44 seconds
Started Aug 13 05:01:11 PM PDT 24
Finished Aug 13 05:01:13 PM PDT 24
Peak memory 198072 kb
Host smart-dcece2c6-8c1d-480c-9c18-19ee4a4c339f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336056800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2336056800
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3835543979
Short name T434
Test name
Test status
Simulation time 20290437095 ps
CPU time 57.88 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:02:12 PM PDT 24
Peak memory 191876 kb
Host smart-2b26a03f-33f2-4365-a5df-4f51aeece87b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835543979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3835543979
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.472278491
Short name T504
Test name
Test status
Simulation time 87088686 ps
CPU time 0.61 seconds
Started Aug 13 05:01:11 PM PDT 24
Finished Aug 13 05:01:12 PM PDT 24
Peak memory 194192 kb
Host smart-dca89ca9-0203-4592-90f1-84d496ebbaaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472278491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.472278491
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1631213652
Short name T356
Test name
Test status
Simulation time 71744041 ps
CPU time 0.69 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:13 PM PDT 24
Peak memory 194224 kb
Host smart-e04d9169-5103-4824-9e5e-258f62967355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631213652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1631213652
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.4229547299
Short name T346
Test name
Test status
Simulation time 172478984 ps
CPU time 9.21 seconds
Started Aug 13 05:01:16 PM PDT 24
Finished Aug 13 05:01:25 PM PDT 24
Peak memory 197032 kb
Host smart-0ea9232a-347c-4cfd-bb91-8d847252388d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229547299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.4229547299
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3989490711
Short name T275
Test name
Test status
Simulation time 154389147 ps
CPU time 0.86 seconds
Started Aug 13 05:01:16 PM PDT 24
Finished Aug 13 05:01:17 PM PDT 24
Peak memory 196636 kb
Host smart-63fe8bd2-731d-4191-b9ea-f963939ceeee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989490711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3989490711
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.274335469
Short name T657
Test name
Test status
Simulation time 62631046 ps
CPU time 1.15 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 196184 kb
Host smart-60c221a9-0b39-4e36-b42f-82a2a4566d35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274335469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.274335469
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2427256516
Short name T338
Test name
Test status
Simulation time 98413136 ps
CPU time 3.12 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:01:17 PM PDT 24
Peak memory 198192 kb
Host smart-66245b2b-b7b7-43ea-85b0-14c77535dc36
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427256516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2427256516
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1970497176
Short name T695
Test name
Test status
Simulation time 306963457 ps
CPU time 2.62 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:16 PM PDT 24
Peak memory 198268 kb
Host smart-f8988d17-2700-45f1-b3ed-72be3ee99259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970497176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1970497176
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1053595826
Short name T284
Test name
Test status
Simulation time 109912054 ps
CPU time 1 seconds
Started Aug 13 05:01:11 PM PDT 24
Finished Aug 13 05:01:12 PM PDT 24
Peak memory 196548 kb
Host smart-6ed81358-6822-492f-b063-9ff582f77e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053595826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1053595826
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2740281130
Short name T359
Test name
Test status
Simulation time 25461486 ps
CPU time 0.79 seconds
Started Aug 13 05:01:16 PM PDT 24
Finished Aug 13 05:01:17 PM PDT 24
Peak memory 196304 kb
Host smart-a27d47f8-97cb-4873-8afa-57df5937668f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740281130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2740281130
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2460266619
Short name T604
Test name
Test status
Simulation time 356291781 ps
CPU time 6.08 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:19 PM PDT 24
Peak memory 198028 kb
Host smart-7b3bb2e0-21aa-4314-881c-640ce525d685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460266619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2460266619
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3663908741
Short name T655
Test name
Test status
Simulation time 69364597 ps
CPU time 1.26 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 196548 kb
Host smart-bea535df-02a8-432b-9b48-93249a97bba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663908741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3663908741
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3774048906
Short name T411
Test name
Test status
Simulation time 49570933 ps
CPU time 1.42 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 196900 kb
Host smart-9555079c-ab63-42e3-ac9b-c9187fec6857
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774048906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3774048906
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2869066336
Short name T349
Test name
Test status
Simulation time 5876542441 ps
CPU time 43.14 seconds
Started Aug 13 05:01:11 PM PDT 24
Finished Aug 13 05:01:54 PM PDT 24
Peak memory 198288 kb
Host smart-f8822a30-de8b-44fb-a24c-58a286810f89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869066336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2869066336
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2686192557
Short name T207
Test name
Test status
Simulation time 45202323 ps
CPU time 0.6 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:14 PM PDT 24
Peak memory 194728 kb
Host smart-902c3b6b-a4a6-4bb1-bfae-32ec33e547ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686192557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2686192557
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.253773625
Short name T163
Test name
Test status
Simulation time 153889358 ps
CPU time 0.93 seconds
Started Aug 13 05:01:15 PM PDT 24
Finished Aug 13 05:01:16 PM PDT 24
Peak memory 197256 kb
Host smart-8d7c14e8-0a7a-41cf-b50e-ea2a789c193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253773625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.253773625
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2081556636
Short name T663
Test name
Test status
Simulation time 272524300 ps
CPU time 13.62 seconds
Started Aug 13 05:01:12 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 198192 kb
Host smart-a77853a9-ed9c-49ca-8970-03f87669a2bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081556636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2081556636
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3388683742
Short name T277
Test name
Test status
Simulation time 72742625 ps
CPU time 1.01 seconds
Started Aug 13 05:01:11 PM PDT 24
Finished Aug 13 05:01:12 PM PDT 24
Peak memory 197856 kb
Host smart-31d32af7-35c3-4d65-8e4c-a1f7147eda03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388683742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3388683742
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2498340068
Short name T329
Test name
Test status
Simulation time 177236558 ps
CPU time 1.05 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 196948 kb
Host smart-9421abc9-c2cb-4d30-a345-6c634e11b9dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498340068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2498340068
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1309922908
Short name T133
Test name
Test status
Simulation time 163805232 ps
CPU time 1.67 seconds
Started Aug 13 05:01:17 PM PDT 24
Finished Aug 13 05:01:18 PM PDT 24
Peak memory 196800 kb
Host smart-7d5d55e7-218e-40f6-ab29-d47dfb464544
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309922908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1309922908
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.4243570201
Short name T514
Test name
Test status
Simulation time 37755866 ps
CPU time 1.03 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 196140 kb
Host smart-5ada36a4-d450-461a-9ec8-0fb5dfdd714c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243570201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.4243570201
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1063472088
Short name T192
Test name
Test status
Simulation time 137832742 ps
CPU time 0.98 seconds
Started Aug 13 05:01:12 PM PDT 24
Finished Aug 13 05:01:13 PM PDT 24
Peak memory 196748 kb
Host smart-4d91b820-e55c-4c9d-a89f-ce3e28e570b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063472088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1063472088
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1093621229
Short name T682
Test name
Test status
Simulation time 28392147 ps
CPU time 1.07 seconds
Started Aug 13 05:01:16 PM PDT 24
Finished Aug 13 05:01:17 PM PDT 24
Peak memory 196132 kb
Host smart-fe8778e3-5080-4371-9a3f-8fb949ab4a0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093621229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1093621229
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2291534667
Short name T369
Test name
Test status
Simulation time 434633489 ps
CPU time 2.14 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:01:16 PM PDT 24
Peak memory 198084 kb
Host smart-5f98f367-9d40-441f-bdae-bf95626f3ace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291534667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2291534667
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3540860722
Short name T668
Test name
Test status
Simulation time 241620085 ps
CPU time 1.34 seconds
Started Aug 13 05:01:11 PM PDT 24
Finished Aug 13 05:01:12 PM PDT 24
Peak memory 196712 kb
Host smart-8fdd61b9-cd38-439c-960e-ddc2d2693e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540860722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3540860722
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.916758567
Short name T406
Test name
Test status
Simulation time 82544078 ps
CPU time 0.75 seconds
Started Aug 13 05:01:15 PM PDT 24
Finished Aug 13 05:01:16 PM PDT 24
Peak memory 195284 kb
Host smart-ea768a24-93a7-48d1-ba9b-40042878d898
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916758567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.916758567
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3645134162
Short name T391
Test name
Test status
Simulation time 84109563635 ps
CPU time 217.81 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:04:51 PM PDT 24
Peak memory 198252 kb
Host smart-f5dd6bf3-2da1-4f50-b2a2-e6cfa039361e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645134162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3645134162
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2664322189
Short name T377
Test name
Test status
Simulation time 14124533 ps
CPU time 0.61 seconds
Started Aug 13 05:01:25 PM PDT 24
Finished Aug 13 05:01:25 PM PDT 24
Peak memory 194180 kb
Host smart-9a761245-5ae9-4849-b2b1-a3d949b46a29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664322189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2664322189
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2774113763
Short name T37
Test name
Test status
Simulation time 153161277 ps
CPU time 0.89 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:14 PM PDT 24
Peak memory 196652 kb
Host smart-4f94b3fe-0d46-440a-96e9-90791e78cfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774113763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2774113763
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.953728313
Short name T281
Test name
Test status
Simulation time 166194640 ps
CPU time 9.11 seconds
Started Aug 13 05:01:12 PM PDT 24
Finished Aug 13 05:01:21 PM PDT 24
Peak memory 196876 kb
Host smart-6856201f-ed88-4387-8974-e10454cf38cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953728313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.953728313
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.510454100
Short name T292
Test name
Test status
Simulation time 38008114 ps
CPU time 0.76 seconds
Started Aug 13 05:01:13 PM PDT 24
Finished Aug 13 05:01:14 PM PDT 24
Peak memory 195740 kb
Host smart-88b176c3-8f77-4e6e-be27-4311cd4a8515
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510454100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.510454100
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.89054532
Short name T683
Test name
Test status
Simulation time 78994172 ps
CPU time 0.75 seconds
Started Aug 13 05:01:15 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 195116 kb
Host smart-644130b1-9b19-44bf-963d-c77bc81ee47e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89054532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.89054532
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.546109379
Short name T244
Test name
Test status
Simulation time 27063192 ps
CPU time 1.19 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:01:15 PM PDT 24
Peak memory 197392 kb
Host smart-50d40ace-b3eb-493d-b2a8-bbb1b928eef8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546109379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.546109379
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3786188048
Short name T279
Test name
Test status
Simulation time 1002302938 ps
CPU time 3.81 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:01:18 PM PDT 24
Peak memory 197032 kb
Host smart-dccfbd59-35cb-408c-bfd4-ffab71724205
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786188048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3786188048
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1110236703
Short name T318
Test name
Test status
Simulation time 47145063 ps
CPU time 1.14 seconds
Started Aug 13 05:01:12 PM PDT 24
Finished Aug 13 05:01:13 PM PDT 24
Peak memory 196972 kb
Host smart-06ba28fa-dfb0-4af5-b7f3-f10c1bbce8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110236703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1110236703
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3810564070
Short name T516
Test name
Test status
Simulation time 22611350 ps
CPU time 0.89 seconds
Started Aug 13 05:01:12 PM PDT 24
Finished Aug 13 05:01:13 PM PDT 24
Peak memory 196244 kb
Host smart-b727fd1a-5ad7-4296-a1f1-b8fb8eae4d77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810564070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3810564070
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2116306041
Short name T538
Test name
Test status
Simulation time 405634638 ps
CPU time 4.83 seconds
Started Aug 13 05:01:11 PM PDT 24
Finished Aug 13 05:01:16 PM PDT 24
Peak memory 198060 kb
Host smart-b7761e3a-c3bd-48e7-aaaf-cd9948b16271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116306041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2116306041
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.983660013
Short name T548
Test name
Test status
Simulation time 40390071 ps
CPU time 1.2 seconds
Started Aug 13 05:01:15 PM PDT 24
Finished Aug 13 05:01:16 PM PDT 24
Peak memory 196628 kb
Host smart-51c56992-9b27-4dd7-8b45-62f673d36300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983660013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.983660013
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.784256582
Short name T605
Test name
Test status
Simulation time 153708797 ps
CPU time 1.01 seconds
Started Aug 13 05:01:15 PM PDT 24
Finished Aug 13 05:01:16 PM PDT 24
Peak memory 195748 kb
Host smart-53a43beb-c68f-4926-b36d-eab306346dee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784256582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.784256582
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3210470841
Short name T456
Test name
Test status
Simulation time 8966862073 ps
CPU time 90.68 seconds
Started Aug 13 05:01:14 PM PDT 24
Finished Aug 13 05:02:44 PM PDT 24
Peak memory 191904 kb
Host smart-422b79a1-c831-4acc-890d-5cc1b74877f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210470841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3210470841
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.327413166
Short name T140
Test name
Test status
Simulation time 12696428 ps
CPU time 0.6 seconds
Started Aug 13 05:01:24 PM PDT 24
Finished Aug 13 05:01:25 PM PDT 24
Peak memory 193996 kb
Host smart-2cfbdb6c-dbae-49e2-8428-cbf93fb5dc1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327413166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.327413166
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3469339862
Short name T500
Test name
Test status
Simulation time 76627165 ps
CPU time 0.83 seconds
Started Aug 13 05:01:26 PM PDT 24
Finished Aug 13 05:01:27 PM PDT 24
Peak memory 196124 kb
Host smart-d5c11734-6dab-42c0-a732-93c8df104caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469339862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3469339862
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2342610631
Short name T607
Test name
Test status
Simulation time 493781119 ps
CPU time 12 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:45 PM PDT 24
Peak memory 196944 kb
Host smart-5bedcebd-6f16-4a8e-be02-d13acfd6db00
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342610631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2342610631
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.721072633
Short name T529
Test name
Test status
Simulation time 69839047 ps
CPU time 0.92 seconds
Started Aug 13 05:01:25 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 196140 kb
Host smart-e489b0c0-53d0-4fd7-8bdf-b02153d268b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721072633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.721072633
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2710123361
Short name T223
Test name
Test status
Simulation time 96742550 ps
CPU time 0.81 seconds
Started Aug 13 05:01:26 PM PDT 24
Finished Aug 13 05:01:27 PM PDT 24
Peak memory 195576 kb
Host smart-ecf5c80a-1b6c-4c3b-bc87-b14d8159881c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710123361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2710123361
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3391320215
Short name T288
Test name
Test status
Simulation time 149963623 ps
CPU time 3.07 seconds
Started Aug 13 05:01:24 PM PDT 24
Finished Aug 13 05:01:27 PM PDT 24
Peak memory 198180 kb
Host smart-4f685042-7b56-49ad-a03d-7a10de33f685
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391320215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3391320215
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.20931104
Short name T115
Test name
Test status
Simulation time 60170546 ps
CPU time 1.82 seconds
Started Aug 13 05:01:24 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 195960 kb
Host smart-0fe33ff8-12e9-40a4-a9dc-a74ab6a06e4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20931104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.20931104
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.464719943
Short name T230
Test name
Test status
Simulation time 217483268 ps
CPU time 1.43 seconds
Started Aug 13 05:01:25 PM PDT 24
Finished Aug 13 05:01:27 PM PDT 24
Peak memory 197116 kb
Host smart-c646cf5c-ca4f-4161-b516-b5716416bf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464719943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.464719943
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3917523058
Short name T390
Test name
Test status
Simulation time 70926076 ps
CPU time 0.69 seconds
Started Aug 13 05:01:24 PM PDT 24
Finished Aug 13 05:01:24 PM PDT 24
Peak memory 195064 kb
Host smart-3bccc9d0-0c0a-431f-9f33-e1137c1c9681
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917523058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3917523058
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.409814906
Short name T640
Test name
Test status
Simulation time 320216431 ps
CPU time 1.61 seconds
Started Aug 13 05:01:25 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 198052 kb
Host smart-ee8c086c-4c09-49ff-b749-5933244591e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409814906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.409814906
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.738041427
Short name T146
Test name
Test status
Simulation time 65530778 ps
CPU time 1.3 seconds
Started Aug 13 05:01:25 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 196888 kb
Host smart-72577aa6-509b-4f4f-8f8e-01962fe7b931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738041427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.738041427
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1342159148
Short name T21
Test name
Test status
Simulation time 309006632 ps
CPU time 1.09 seconds
Started Aug 13 05:01:25 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 196492 kb
Host smart-eb1f6cc8-ae64-4162-9427-e36eb3b5b39c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342159148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1342159148
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1492154269
Short name T172
Test name
Test status
Simulation time 2409078312 ps
CPU time 61.86 seconds
Started Aug 13 05:01:27 PM PDT 24
Finished Aug 13 05:02:29 PM PDT 24
Peak memory 198368 kb
Host smart-ac3cde82-4c02-40e7-be28-3fa58b3ba6fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492154269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1492154269
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2512732459
Short name T476
Test name
Test status
Simulation time 13965320 ps
CPU time 0.59 seconds
Started Aug 13 05:01:26 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 193924 kb
Host smart-58f8cb5c-6127-484e-8661-5b472a370b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512732459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2512732459
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1692221275
Short name T158
Test name
Test status
Simulation time 70973877 ps
CPU time 0.88 seconds
Started Aug 13 05:01:25 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 197144 kb
Host smart-934cf302-c5f7-4d4f-b081-6851590ccbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692221275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1692221275
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.996575509
Short name T671
Test name
Test status
Simulation time 553145846 ps
CPU time 28.05 seconds
Started Aug 13 05:01:26 PM PDT 24
Finished Aug 13 05:01:54 PM PDT 24
Peak memory 197192 kb
Host smart-650e5c52-d2d1-4687-a29c-b00494bd328e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996575509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.996575509
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.4029327631
Short name T432
Test name
Test status
Simulation time 105703885 ps
CPU time 0.74 seconds
Started Aug 13 05:01:30 PM PDT 24
Finished Aug 13 05:01:31 PM PDT 24
Peak memory 194772 kb
Host smart-66b492c8-0a15-42c0-8d85-21d44eba3b45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029327631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.4029327631
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3604647963
Short name T73
Test name
Test status
Simulation time 62900333 ps
CPU time 1.06 seconds
Started Aug 13 05:01:29 PM PDT 24
Finished Aug 13 05:01:30 PM PDT 24
Peak memory 196188 kb
Host smart-5bacf781-9072-463a-9188-4f9be028ed25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604647963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3604647963
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3284376003
Short name T378
Test name
Test status
Simulation time 50970761 ps
CPU time 1.99 seconds
Started Aug 13 05:01:26 PM PDT 24
Finished Aug 13 05:01:28 PM PDT 24
Peak memory 198168 kb
Host smart-f21db2b8-4edb-42bc-8217-f561c7791343
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284376003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3284376003
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3991219415
Short name T184
Test name
Test status
Simulation time 472968640 ps
CPU time 3.92 seconds
Started Aug 13 05:01:29 PM PDT 24
Finished Aug 13 05:01:33 PM PDT 24
Peak memory 197292 kb
Host smart-f4933134-74a8-4c96-b3fc-4426cb2b119c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991219415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3991219415
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.628999607
Short name T491
Test name
Test status
Simulation time 95929227 ps
CPU time 0.76 seconds
Started Aug 13 05:01:25 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 195460 kb
Host smart-13ff644a-edb0-4635-84b0-6d6312c4b89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628999607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.628999607
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2371770592
Short name T60
Test name
Test status
Simulation time 30671739 ps
CPU time 0.82 seconds
Started Aug 13 05:01:28 PM PDT 24
Finished Aug 13 05:01:29 PM PDT 24
Peak memory 196632 kb
Host smart-f6acaefc-290e-42b2-8fbe-5af26f463285
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371770592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2371770592
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.61707176
Short name T8
Test name
Test status
Simulation time 470528775 ps
CPU time 5.84 seconds
Started Aug 13 05:01:31 PM PDT 24
Finished Aug 13 05:01:37 PM PDT 24
Peak memory 198300 kb
Host smart-78ac427c-1639-4609-804c-613a6fc8b4f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61707176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand
om_long_reg_writes_reg_reads.61707176
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4292205959
Short name T445
Test name
Test status
Simulation time 40924332 ps
CPU time 1.05 seconds
Started Aug 13 05:01:26 PM PDT 24
Finished Aug 13 05:01:27 PM PDT 24
Peak memory 196640 kb
Host smart-685523cf-8505-49ac-a07e-38d132ee38fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292205959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4292205959
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3513361068
Short name T337
Test name
Test status
Simulation time 284641305 ps
CPU time 1.41 seconds
Started Aug 13 05:01:26 PM PDT 24
Finished Aug 13 05:01:28 PM PDT 24
Peak memory 196772 kb
Host smart-baf3b081-5898-4d9e-aa85-b9d33d4acdb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513361068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3513361068
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.511958979
Short name T709
Test name
Test status
Simulation time 1840426301 ps
CPU time 45.88 seconds
Started Aug 13 05:01:29 PM PDT 24
Finished Aug 13 05:02:15 PM PDT 24
Peak memory 198216 kb
Host smart-7dea8d41-4c0f-4b31-bc44-38b45a36d1f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511958979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.511958979
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2078255506
Short name T283
Test name
Test status
Simulation time 12027495 ps
CPU time 0.57 seconds
Started Aug 13 05:01:30 PM PDT 24
Finished Aug 13 05:01:30 PM PDT 24
Peak memory 193984 kb
Host smart-9141351c-5c05-4184-88f4-49b5618f272c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078255506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2078255506
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1449739518
Short name T232
Test name
Test status
Simulation time 62442780 ps
CPU time 0.6 seconds
Started Aug 13 05:01:28 PM PDT 24
Finished Aug 13 05:01:29 PM PDT 24
Peak memory 194764 kb
Host smart-7ab8c678-89ae-447c-9a01-5088e4ffa8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449739518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1449739518
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1833805785
Short name T166
Test name
Test status
Simulation time 1112406956 ps
CPU time 14.72 seconds
Started Aug 13 05:01:29 PM PDT 24
Finished Aug 13 05:01:43 PM PDT 24
Peak memory 198160 kb
Host smart-af1de74a-80e1-46e3-82ea-f017d0ae7b97
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833805785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1833805785
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.960268484
Short name T319
Test name
Test status
Simulation time 28080025 ps
CPU time 0.74 seconds
Started Aug 13 05:01:28 PM PDT 24
Finished Aug 13 05:01:29 PM PDT 24
Peak memory 194820 kb
Host smart-8b527fdf-bcab-40d7-baef-b38201c8cef1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960268484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.960268484
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.359761602
Short name T388
Test name
Test status
Simulation time 97427126 ps
CPU time 1.63 seconds
Started Aug 13 05:01:30 PM PDT 24
Finished Aug 13 05:01:31 PM PDT 24
Peak memory 198152 kb
Host smart-3cd1da37-b440-4f94-b454-2683cc9953fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359761602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.359761602
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.770517575
Short name T198
Test name
Test status
Simulation time 283975536 ps
CPU time 2.05 seconds
Started Aug 13 05:01:29 PM PDT 24
Finished Aug 13 05:01:31 PM PDT 24
Peak memory 198136 kb
Host smart-5eb44b07-be12-4772-bc80-de4f55583752
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770517575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.770517575
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.762003995
Short name T214
Test name
Test status
Simulation time 30298762 ps
CPU time 1.02 seconds
Started Aug 13 05:01:29 PM PDT 24
Finished Aug 13 05:01:31 PM PDT 24
Peak memory 195520 kb
Host smart-d9c9b035-c6c5-4864-bfb6-570769aa737f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762003995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
762003995
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1006064101
Short name T499
Test name
Test status
Simulation time 70426847 ps
CPU time 0.8 seconds
Started Aug 13 05:01:28 PM PDT 24
Finished Aug 13 05:01:29 PM PDT 24
Peak memory 195572 kb
Host smart-fefaefb4-82a8-4ef3-9ae0-1a351291b63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006064101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1006064101
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2243379064
Short name T308
Test name
Test status
Simulation time 47271490 ps
CPU time 1.18 seconds
Started Aug 13 05:01:30 PM PDT 24
Finished Aug 13 05:01:31 PM PDT 24
Peak memory 196164 kb
Host smart-c540a935-622d-4ff2-abb5-5b43719ba4b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243379064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2243379064
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.283830190
Short name T324
Test name
Test status
Simulation time 700515934 ps
CPU time 4.26 seconds
Started Aug 13 05:01:28 PM PDT 24
Finished Aug 13 05:01:32 PM PDT 24
Peak memory 198040 kb
Host smart-3837448d-0cb1-4ec4-b9ff-13229b408417
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283830190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.283830190
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1935110206
Short name T136
Test name
Test status
Simulation time 64625748 ps
CPU time 1.04 seconds
Started Aug 13 05:01:31 PM PDT 24
Finished Aug 13 05:01:32 PM PDT 24
Peak memory 196812 kb
Host smart-5c5cce04-a5d9-4298-a1ed-412624e66370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935110206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1935110206
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2737907467
Short name T649
Test name
Test status
Simulation time 82422514 ps
CPU time 1.36 seconds
Started Aug 13 05:01:31 PM PDT 24
Finished Aug 13 05:01:33 PM PDT 24
Peak memory 195628 kb
Host smart-33ec7f16-ec58-4562-9f37-3a8a84e00496
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737907467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2737907467
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3407275653
Short name T4
Test name
Test status
Simulation time 4064584313 ps
CPU time 22.38 seconds
Started Aug 13 05:01:28 PM PDT 24
Finished Aug 13 05:01:50 PM PDT 24
Peak memory 198368 kb
Host smart-8e2aea18-06c0-45da-b01e-b660bfa174bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407275653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3407275653
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1312060364
Short name T69
Test name
Test status
Simulation time 1036999061 ps
CPU time 34.29 seconds
Started Aug 13 05:01:29 PM PDT 24
Finished Aug 13 05:02:03 PM PDT 24
Peak memory 197616 kb
Host smart-40794583-15e6-49cd-b4ef-488c28ab7efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1312060364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1312060364
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2718740128
Short name T307
Test name
Test status
Simulation time 20133559 ps
CPU time 0.59 seconds
Started Aug 13 05:01:28 PM PDT 24
Finished Aug 13 05:01:28 PM PDT 24
Peak memory 193976 kb
Host smart-14651933-63e7-4877-adfb-0dc15db00c83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718740128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2718740128
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2910952017
Short name T648
Test name
Test status
Simulation time 49488652 ps
CPU time 0.64 seconds
Started Aug 13 05:01:30 PM PDT 24
Finished Aug 13 05:01:31 PM PDT 24
Peak memory 194720 kb
Host smart-f10fed5e-f28e-4788-8c99-d941beae05fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910952017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2910952017
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3504017455
Short name T315
Test name
Test status
Simulation time 878328757 ps
CPU time 6.56 seconds
Started Aug 13 05:01:28 PM PDT 24
Finished Aug 13 05:01:34 PM PDT 24
Peak memory 197144 kb
Host smart-16b0cc90-ae3c-40f8-8743-7355f621f550
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504017455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3504017455
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3405690055
Short name T478
Test name
Test status
Simulation time 17697596 ps
CPU time 0.62 seconds
Started Aug 13 05:01:25 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 194472 kb
Host smart-148a33c7-7514-448c-a577-ab57358b257b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405690055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3405690055
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3619479392
Short name T41
Test name
Test status
Simulation time 71761597 ps
CPU time 0.72 seconds
Started Aug 13 05:01:30 PM PDT 24
Finished Aug 13 05:01:31 PM PDT 24
Peak memory 194396 kb
Host smart-c7c0b2e3-8849-4a89-abdf-de0ce0c8de66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619479392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3619479392
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.427010853
Short name T618
Test name
Test status
Simulation time 123776138 ps
CPU time 0.97 seconds
Started Aug 13 05:01:26 PM PDT 24
Finished Aug 13 05:01:27 PM PDT 24
Peak memory 196404 kb
Host smart-b04f549c-298e-457c-981c-5bafabfc453f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427010853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.427010853
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.615643408
Short name T116
Test name
Test status
Simulation time 75977274 ps
CPU time 2.35 seconds
Started Aug 13 05:01:33 PM PDT 24
Finished Aug 13 05:01:35 PM PDT 24
Peak memory 197100 kb
Host smart-230b2d4b-05a7-4fad-9223-aac38469cbaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615643408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
615643408
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.838382988
Short name T303
Test name
Test status
Simulation time 48885163 ps
CPU time 1.01 seconds
Started Aug 13 05:01:28 PM PDT 24
Finished Aug 13 05:01:29 PM PDT 24
Peak memory 195944 kb
Host smart-6975c238-b5ac-4301-87a4-f070d1c9cf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838382988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.838382988
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3979000874
Short name T421
Test name
Test status
Simulation time 23311924 ps
CPU time 0.9 seconds
Started Aug 13 05:01:28 PM PDT 24
Finished Aug 13 05:01:29 PM PDT 24
Peak memory 195988 kb
Host smart-1e9ca725-d475-4423-a721-4a8a5780fe6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979000874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3979000874
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3881387780
Short name T627
Test name
Test status
Simulation time 225232975 ps
CPU time 3.58 seconds
Started Aug 13 05:01:23 PM PDT 24
Finished Aug 13 05:01:26 PM PDT 24
Peak memory 198096 kb
Host smart-b26bbbc8-88ee-4212-a425-1a7f62418f25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881387780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3881387780
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1596725807
Short name T551
Test name
Test status
Simulation time 128864147 ps
CPU time 1.07 seconds
Started Aug 13 05:01:30 PM PDT 24
Finished Aug 13 05:01:31 PM PDT 24
Peak memory 195904 kb
Host smart-788f1eae-4251-413e-a1bf-3aa1564d601d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596725807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1596725807
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1081667796
Short name T583
Test name
Test status
Simulation time 98396547 ps
CPU time 1.16 seconds
Started Aug 13 05:01:29 PM PDT 24
Finished Aug 13 05:01:30 PM PDT 24
Peak memory 195656 kb
Host smart-8836ff87-3967-4934-aa89-e16ea8b8d832
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081667796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1081667796
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.4194253497
Short name T580
Test name
Test status
Simulation time 6346828352 ps
CPU time 167.49 seconds
Started Aug 13 05:01:23 PM PDT 24
Finished Aug 13 05:04:11 PM PDT 24
Peak memory 198304 kb
Host smart-fe6763b9-24d6-486e-9730-3538251adfb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194253497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.4194253497
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1629601208
Short name T631
Test name
Test status
Simulation time 37379851 ps
CPU time 0.57 seconds
Started Aug 13 04:59:34 PM PDT 24
Finished Aug 13 04:59:35 PM PDT 24
Peak memory 192752 kb
Host smart-38ad1dce-3f5b-4d10-be3d-fd345f25fec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629601208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1629601208
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2434346069
Short name T517
Test name
Test status
Simulation time 24374903 ps
CPU time 0.84 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:33 PM PDT 24
Peak memory 195300 kb
Host smart-c83fa331-e939-463a-8219-a661d8ab8834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434346069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2434346069
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1488706162
Short name T295
Test name
Test status
Simulation time 550463382 ps
CPU time 8.95 seconds
Started Aug 13 04:59:33 PM PDT 24
Finished Aug 13 04:59:42 PM PDT 24
Peak memory 196832 kb
Host smart-2f60f45e-a0a0-4ecf-b6ff-f26f9c94c484
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488706162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1488706162
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3406874370
Short name T541
Test name
Test status
Simulation time 210487719 ps
CPU time 0.77 seconds
Started Aug 13 04:59:36 PM PDT 24
Finished Aug 13 04:59:37 PM PDT 24
Peak memory 196560 kb
Host smart-e9d06eef-4a09-403c-bc17-ac097d067608
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406874370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3406874370
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3161613460
Short name T489
Test name
Test status
Simulation time 47947847 ps
CPU time 1.36 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:34 PM PDT 24
Peak memory 198112 kb
Host smart-7b0e9229-f1be-4bdb-933e-58e15f18066d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161613460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3161613460
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1687940365
Short name T122
Test name
Test status
Simulation time 77518999 ps
CPU time 3.06 seconds
Started Aug 13 04:59:34 PM PDT 24
Finished Aug 13 04:59:37 PM PDT 24
Peak memory 198196 kb
Host smart-baac8631-7eac-47c2-8429-5ff96a784d76
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687940365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1687940365
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1770863763
Short name T713
Test name
Test status
Simulation time 282253611 ps
CPU time 1.76 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:34 PM PDT 24
Peak memory 196784 kb
Host smart-ab08027c-9aca-473b-a810-c5731fe0ec9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770863763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1770863763
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2822442098
Short name T527
Test name
Test status
Simulation time 446422010 ps
CPU time 1.15 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:33 PM PDT 24
Peak memory 196092 kb
Host smart-8318f7c1-1859-410a-b0de-336b8e684255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822442098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2822442098
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.678580250
Short name T505
Test name
Test status
Simulation time 57566448 ps
CPU time 0.78 seconds
Started Aug 13 04:59:33 PM PDT 24
Finished Aug 13 04:59:34 PM PDT 24
Peak memory 195380 kb
Host smart-8d5dafe9-94d2-4f96-8366-8fbb114de10b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678580250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.678580250
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1830603027
Short name T469
Test name
Test status
Simulation time 430853604 ps
CPU time 4.8 seconds
Started Aug 13 04:59:33 PM PDT 24
Finished Aug 13 04:59:38 PM PDT 24
Peak memory 198160 kb
Host smart-6599464a-8373-42fe-920b-654d773eeb74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830603027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1830603027
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3297920573
Short name T152
Test name
Test status
Simulation time 43837902 ps
CPU time 1.21 seconds
Started Aug 13 04:59:32 PM PDT 24
Finished Aug 13 04:59:33 PM PDT 24
Peak memory 196860 kb
Host smart-45100b0b-16ce-44bf-b678-1aaef1285435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297920573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3297920573
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2763113388
Short name T231
Test name
Test status
Simulation time 80703660 ps
CPU time 0.92 seconds
Started Aug 13 04:59:33 PM PDT 24
Finished Aug 13 04:59:34 PM PDT 24
Peak memory 195352 kb
Host smart-ad14902b-1ef1-4800-ae94-40910a1c26b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763113388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2763113388
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3977568080
Short name T628
Test name
Test status
Simulation time 73699408413 ps
CPU time 133.74 seconds
Started Aug 13 04:59:35 PM PDT 24
Finished Aug 13 05:01:49 PM PDT 24
Peak memory 198376 kb
Host smart-6b08eae0-b736-470f-91e6-d8fec6a49163
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977568080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3977568080
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1630626625
Short name T708
Test name
Test status
Simulation time 1063766012 ps
CPU time 18.52 seconds
Started Aug 13 04:59:35 PM PDT 24
Finished Aug 13 04:59:54 PM PDT 24
Peak memory 198324 kb
Host smart-96a3d872-b7fb-44cd-b6d2-7252cf10e96a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1630626625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1630626625
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.783480289
Short name T200
Test name
Test status
Simulation time 38498992 ps
CPU time 0.61 seconds
Started Aug 13 04:59:46 PM PDT 24
Finished Aug 13 04:59:47 PM PDT 24
Peak memory 194000 kb
Host smart-05434840-604a-403d-89ff-cbc82ab6f5e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783480289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.783480289
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3733822487
Short name T353
Test name
Test status
Simulation time 126120313 ps
CPU time 0.79 seconds
Started Aug 13 04:59:43 PM PDT 24
Finished Aug 13 04:59:44 PM PDT 24
Peak memory 195376 kb
Host smart-6f38d4f5-3950-481f-a1fb-ba0d1c3077e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733822487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3733822487
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2135490078
Short name T162
Test name
Test status
Simulation time 1077681739 ps
CPU time 8.68 seconds
Started Aug 13 04:59:41 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 198084 kb
Host smart-a16b804b-bdbe-4678-9d79-fee7de96d0b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135490078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2135490078
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3123015361
Short name T339
Test name
Test status
Simulation time 29354847 ps
CPU time 0.71 seconds
Started Aug 13 04:59:38 PM PDT 24
Finished Aug 13 04:59:39 PM PDT 24
Peak memory 194876 kb
Host smart-8793ec83-6f9c-4674-914a-91b15055b0fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123015361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3123015361
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2430697082
Short name T410
Test name
Test status
Simulation time 18076760 ps
CPU time 0.68 seconds
Started Aug 13 04:59:44 PM PDT 24
Finished Aug 13 04:59:45 PM PDT 24
Peak memory 195100 kb
Host smart-5197bdee-6d8c-4f7c-a979-4f5be01e6330
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430697082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2430697082
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.540879827
Short name T616
Test name
Test status
Simulation time 73908081 ps
CPU time 3.04 seconds
Started Aug 13 04:59:43 PM PDT 24
Finished Aug 13 04:59:46 PM PDT 24
Peak memory 198224 kb
Host smart-ff703e27-2738-40b3-b391-d673a0334a9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540879827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.540879827
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3595539645
Short name T201
Test name
Test status
Simulation time 113600888 ps
CPU time 1.1 seconds
Started Aug 13 04:59:45 PM PDT 24
Finished Aug 13 04:59:46 PM PDT 24
Peak memory 195604 kb
Host smart-1bbf862f-36da-4671-b048-9f8a1760e778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595539645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3595539645
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1287186220
Short name T208
Test name
Test status
Simulation time 58650137 ps
CPU time 1.14 seconds
Started Aug 13 04:59:35 PM PDT 24
Finished Aug 13 04:59:37 PM PDT 24
Peak memory 198224 kb
Host smart-c31d8136-d083-47c8-8f2f-93c5707cc9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287186220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1287186220
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2631215444
Short name T416
Test name
Test status
Simulation time 245304660 ps
CPU time 1.26 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 195896 kb
Host smart-52afb404-07ef-478e-91db-ecd51fd1fdf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631215444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2631215444
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3175230403
Short name T706
Test name
Test status
Simulation time 553039547 ps
CPU time 6.29 seconds
Started Aug 13 04:59:45 PM PDT 24
Finished Aug 13 04:59:51 PM PDT 24
Peak memory 198092 kb
Host smart-8c7f988a-888e-4395-b129-e55a86f883ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175230403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3175230403
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.20943775
Short name T612
Test name
Test status
Simulation time 319746132 ps
CPU time 0.96 seconds
Started Aug 13 04:59:35 PM PDT 24
Finished Aug 13 04:59:36 PM PDT 24
Peak memory 196628 kb
Host smart-562ceced-d2c4-4f5f-a84b-559129e503b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20943775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.20943775
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3045152862
Short name T697
Test name
Test status
Simulation time 55688204 ps
CPU time 1.18 seconds
Started Aug 13 04:59:33 PM PDT 24
Finished Aug 13 04:59:34 PM PDT 24
Peak memory 195672 kb
Host smart-f6b6aee9-b9e6-4c47-b3a5-90b38de666e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045152862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3045152862
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.11986459
Short name T206
Test name
Test status
Simulation time 6941348847 ps
CPU time 148.94 seconds
Started Aug 13 04:59:42 PM PDT 24
Finished Aug 13 05:02:11 PM PDT 24
Peak memory 198364 kb
Host smart-46d049f2-14bf-4d0f-a834-25b455c7fdc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpi
o_stress_all.11986459
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.2644259939
Short name T563
Test name
Test status
Simulation time 5077747405 ps
CPU time 86.51 seconds
Started Aug 13 04:59:41 PM PDT 24
Finished Aug 13 05:01:08 PM PDT 24
Peak memory 198428 kb
Host smart-375183a9-2173-48d0-9fd8-687100391c58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2644259939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.2644259939
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3593937435
Short name T458
Test name
Test status
Simulation time 16935876 ps
CPU time 0.6 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 194156 kb
Host smart-3754600d-99e5-4138-adff-44aaf27ecb49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593937435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3593937435
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3031246754
Short name T562
Test name
Test status
Simulation time 91088103 ps
CPU time 0.78 seconds
Started Aug 13 04:59:47 PM PDT 24
Finished Aug 13 04:59:48 PM PDT 24
Peak memory 195360 kb
Host smart-9293eda1-85a9-48ac-a0f6-b57e29038423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031246754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3031246754
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3988283570
Short name T675
Test name
Test status
Simulation time 667832757 ps
CPU time 15.04 seconds
Started Aug 13 04:59:45 PM PDT 24
Finished Aug 13 05:00:00 PM PDT 24
Peak memory 198160 kb
Host smart-e54dce70-242d-4637-8d69-cacaf8701db9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988283570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3988283570
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3581093809
Short name T355
Test name
Test status
Simulation time 34985868 ps
CPU time 0.75 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 195768 kb
Host smart-1fbd4c20-0a26-4b8e-ba88-6c04e6d10cfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581093809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3581093809
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1919921061
Short name T515
Test name
Test status
Simulation time 134650380 ps
CPU time 1.04 seconds
Started Aug 13 04:59:46 PM PDT 24
Finished Aug 13 04:59:47 PM PDT 24
Peak memory 196960 kb
Host smart-e945532e-6a8d-4a03-81e4-614e8b63cc45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919921061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1919921061
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2464326222
Short name T375
Test name
Test status
Simulation time 293172285 ps
CPU time 3.1 seconds
Started Aug 13 04:59:48 PM PDT 24
Finished Aug 13 04:59:51 PM PDT 24
Peak memory 198176 kb
Host smart-50961bdb-3d7d-491c-b033-4a7baa1f9081
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464326222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2464326222
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2441377310
Short name T205
Test name
Test status
Simulation time 412730561 ps
CPU time 3.01 seconds
Started Aug 13 04:59:46 PM PDT 24
Finished Aug 13 04:59:49 PM PDT 24
Peak memory 198208 kb
Host smart-7a6f6875-1dc7-456c-9728-b2520eb30f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441377310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2441377310
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.930040530
Short name T141
Test name
Test status
Simulation time 194562302 ps
CPU time 0.91 seconds
Started Aug 13 04:59:43 PM PDT 24
Finished Aug 13 04:59:44 PM PDT 24
Peak memory 195996 kb
Host smart-84d84b4b-aa73-49e3-8584-b572a0d148ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930040530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.930040530
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2450388581
Short name T270
Test name
Test status
Simulation time 286783529 ps
CPU time 1.01 seconds
Started Aug 13 04:59:47 PM PDT 24
Finished Aug 13 04:59:48 PM PDT 24
Peak memory 196796 kb
Host smart-9e7c9852-5e78-4ebc-a0a4-02e5af90498d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450388581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2450388581
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2173331068
Short name T233
Test name
Test status
Simulation time 110434480 ps
CPU time 2.2 seconds
Started Aug 13 04:59:46 PM PDT 24
Finished Aug 13 04:59:49 PM PDT 24
Peak memory 198096 kb
Host smart-63e45ee4-a2b8-429e-9bfe-80ff5e79e719
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173331068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2173331068
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2212886477
Short name T348
Test name
Test status
Simulation time 729373174 ps
CPU time 1.35 seconds
Started Aug 13 04:59:44 PM PDT 24
Finished Aug 13 04:59:46 PM PDT 24
Peak memory 196868 kb
Host smart-f87ea231-05a8-430b-b737-6db375f25291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212886477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2212886477
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2196350914
Short name T345
Test name
Test status
Simulation time 479913917 ps
CPU time 1.06 seconds
Started Aug 13 04:59:45 PM PDT 24
Finished Aug 13 04:59:46 PM PDT 24
Peak memory 195708 kb
Host smart-2c9b2e74-606b-4fd6-9992-35f1567a86b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196350914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2196350914
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.839768522
Short name T629
Test name
Test status
Simulation time 16124137916 ps
CPU time 171.28 seconds
Started Aug 13 04:59:47 PM PDT 24
Finished Aug 13 05:02:38 PM PDT 24
Peak memory 198300 kb
Host smart-5946724c-4640-4564-a045-d4108458b6cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839768522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.839768522
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1039756016
Short name T68
Test name
Test status
Simulation time 1150883171 ps
CPU time 39.88 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 05:00:29 PM PDT 24
Peak memory 197576 kb
Host smart-3a427bd0-7eef-4043-979f-56f13756e456
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1039756016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1039756016
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.529244896
Short name T215
Test name
Test status
Simulation time 45606216 ps
CPU time 0.58 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 194768 kb
Host smart-8192ef12-67a7-4cca-a2e6-a9bb3704bcb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529244896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.529244896
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2170052159
Short name T130
Test name
Test status
Simulation time 322940548 ps
CPU time 0.81 seconds
Started Aug 13 04:59:50 PM PDT 24
Finished Aug 13 04:59:51 PM PDT 24
Peak memory 196096 kb
Host smart-254b737a-1b0f-456e-8bcf-492a67f027d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170052159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2170052159
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1776723279
Short name T341
Test name
Test status
Simulation time 347305071 ps
CPU time 12.68 seconds
Started Aug 13 04:59:50 PM PDT 24
Finished Aug 13 05:00:02 PM PDT 24
Peak memory 196892 kb
Host smart-180255e7-19b6-4815-acae-220116249639
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776723279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1776723279
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2558365623
Short name T20
Test name
Test status
Simulation time 304683511 ps
CPU time 0.91 seconds
Started Aug 13 04:59:56 PM PDT 24
Finished Aug 13 04:59:57 PM PDT 24
Peak memory 196140 kb
Host smart-1a9851c3-21a1-4c04-b0e6-fedb8d722ef5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558365623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2558365623
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.177114050
Short name T11
Test name
Test status
Simulation time 213128590 ps
CPU time 1.45 seconds
Started Aug 13 04:59:51 PM PDT 24
Finished Aug 13 04:59:52 PM PDT 24
Peak memory 197052 kb
Host smart-fe0c4e91-a6a0-49c9-bd62-720fa16fb04f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177114050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.177114050
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.825987395
Short name T465
Test name
Test status
Simulation time 77490926 ps
CPU time 2.82 seconds
Started Aug 13 04:59:51 PM PDT 24
Finished Aug 13 04:59:54 PM PDT 24
Peak memory 196508 kb
Host smart-e412ee93-2b9e-4234-8ce0-0aef56435b16
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825987395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.825987395
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.755645902
Short name T550
Test name
Test status
Simulation time 187688547 ps
CPU time 2.4 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:52 PM PDT 24
Peak memory 196664 kb
Host smart-d7b42604-5d91-40f1-8aa6-6a2058de246d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755645902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.755645902
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1301712156
Short name T238
Test name
Test status
Simulation time 807695939 ps
CPU time 1.1 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 196124 kb
Host smart-2b19dac0-491c-4773-b439-09cadd7568d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301712156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1301712156
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3833708929
Short name T522
Test name
Test status
Simulation time 210600306 ps
CPU time 1.21 seconds
Started Aug 13 04:59:51 PM PDT 24
Finished Aug 13 04:59:52 PM PDT 24
Peak memory 197372 kb
Host smart-db98754d-3804-44cc-bab8-c9daf02bdf64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833708929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3833708929
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.4167661286
Short name T620
Test name
Test status
Simulation time 48971312 ps
CPU time 2.28 seconds
Started Aug 13 04:59:47 PM PDT 24
Finished Aug 13 04:59:49 PM PDT 24
Peak memory 198064 kb
Host smart-06f17077-70eb-4030-906e-4870f9de64d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167661286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.4167661286
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.4289640572
Short name T199
Test name
Test status
Simulation time 72635126 ps
CPU time 0.95 seconds
Started Aug 13 04:59:48 PM PDT 24
Finished Aug 13 04:59:49 PM PDT 24
Peak memory 195856 kb
Host smart-ccf23491-06ef-43ec-92fa-b0437df19f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289640572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.4289640572
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1750309231
Short name T470
Test name
Test status
Simulation time 177924276 ps
CPU time 1.32 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:51 PM PDT 24
Peak memory 196904 kb
Host smart-08708961-6139-45d0-bcab-0709f781a367
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750309231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1750309231
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.872356685
Short name T316
Test name
Test status
Simulation time 52037413195 ps
CPU time 180.56 seconds
Started Aug 13 04:59:51 PM PDT 24
Finished Aug 13 05:02:51 PM PDT 24
Peak memory 198260 kb
Host smart-12e649dc-4507-4908-b53f-5bde03f4d1ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872356685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.872356685
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.29554801
Short name T254
Test name
Test status
Simulation time 15635129 ps
CPU time 0.61 seconds
Started Aug 13 04:59:50 PM PDT 24
Finished Aug 13 04:59:51 PM PDT 24
Peak memory 194220 kb
Host smart-5fd0562a-5e14-4bc1-87e1-ee2f0616e43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29554801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.29554801
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.980084901
Short name T483
Test name
Test status
Simulation time 433453383 ps
CPU time 0.81 seconds
Started Aug 13 04:59:54 PM PDT 24
Finished Aug 13 04:59:55 PM PDT 24
Peak memory 196092 kb
Host smart-d32bea0b-7c19-4ef0-ac4b-e9e036a2a2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980084901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.980084901
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.147906305
Short name T523
Test name
Test status
Simulation time 303919232 ps
CPU time 11.04 seconds
Started Aug 13 04:59:56 PM PDT 24
Finished Aug 13 05:00:07 PM PDT 24
Peak memory 195612 kb
Host smart-bfbfd7ef-afbc-4d16-b399-588d850eece5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147906305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.147906305
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3336231316
Short name T623
Test name
Test status
Simulation time 311773806 ps
CPU time 1.07 seconds
Started Aug 13 04:59:52 PM PDT 24
Finished Aug 13 04:59:54 PM PDT 24
Peak memory 196528 kb
Host smart-c3896dc3-9acc-4739-9724-b6fb2f315d1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336231316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3336231316
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2688531633
Short name T600
Test name
Test status
Simulation time 37302679 ps
CPU time 1.03 seconds
Started Aug 13 04:59:54 PM PDT 24
Finished Aug 13 04:59:55 PM PDT 24
Peak memory 196292 kb
Host smart-bb84a432-0214-414d-9e41-3fe380c920c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688531633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2688531633
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1655508515
Short name T425
Test name
Test status
Simulation time 125173011 ps
CPU time 1.42 seconds
Started Aug 13 04:59:53 PM PDT 24
Finished Aug 13 04:59:54 PM PDT 24
Peak memory 196456 kb
Host smart-e02724cf-6779-491f-a2d1-35705b741335
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655508515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1655508515
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3697063521
Short name T699
Test name
Test status
Simulation time 125370497 ps
CPU time 2.19 seconds
Started Aug 13 04:59:53 PM PDT 24
Finished Aug 13 04:59:56 PM PDT 24
Peak memory 196572 kb
Host smart-42f0a360-2cac-495e-b9ed-49eb82dff1c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697063521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3697063521
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.952477236
Short name T155
Test name
Test status
Simulation time 84800902 ps
CPU time 0.79 seconds
Started Aug 13 04:59:55 PM PDT 24
Finished Aug 13 04:59:56 PM PDT 24
Peak memory 196284 kb
Host smart-99c851f0-0ae7-47f2-be3b-8941875c49b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952477236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.952477236
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.259046837
Short name T602
Test name
Test status
Simulation time 119371192 ps
CPU time 0.77 seconds
Started Aug 13 04:59:49 PM PDT 24
Finished Aug 13 04:59:50 PM PDT 24
Peak memory 196152 kb
Host smart-61d42185-0c0a-43aa-8f87-5c6470eacceb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259046837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.259046837
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.435827536
Short name T409
Test name
Test status
Simulation time 160713932 ps
CPU time 4.03 seconds
Started Aug 13 04:59:56 PM PDT 24
Finished Aug 13 05:00:00 PM PDT 24
Peak memory 198080 kb
Host smart-5e378379-d721-4212-834d-279375f06720
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435827536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.435827536
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2557939902
Short name T251
Test name
Test status
Simulation time 653764254 ps
CPU time 1.25 seconds
Started Aug 13 04:59:55 PM PDT 24
Finished Aug 13 04:59:57 PM PDT 24
Peak memory 196352 kb
Host smart-cbf6fa4d-3cca-49aa-bbd4-9982ed11a9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557939902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2557939902
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3754667175
Short name T460
Test name
Test status
Simulation time 70985656 ps
CPU time 1.39 seconds
Started Aug 13 04:59:55 PM PDT 24
Finished Aug 13 04:59:56 PM PDT 24
Peak memory 196844 kb
Host smart-deb72a1b-ef89-466b-b0b8-ab4a19a895a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754667175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3754667175
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.428060126
Short name T846
Test name
Test status
Simulation time 64173822 ps
CPU time 1.05 seconds
Started Aug 13 06:31:13 PM PDT 24
Finished Aug 13 06:31:14 PM PDT 24
Peak memory 190780 kb
Host smart-7eba4100-61d9-40b2-be73-6331d5929514
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=428060126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.428060126
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.774521941
Short name T863
Test name
Test status
Simulation time 129129033 ps
CPU time 0.94 seconds
Started Aug 13 06:31:01 PM PDT 24
Finished Aug 13 06:31:02 PM PDT 24
Peak memory 191148 kb
Host smart-f5cd8c56-49ba-437d-8e2f-d43eb7a747eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774521941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.774521941
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.910461521
Short name T887
Test name
Test status
Simulation time 63226888 ps
CPU time 1.19 seconds
Started Aug 13 06:30:59 PM PDT 24
Finished Aug 13 06:31:01 PM PDT 24
Peak memory 196408 kb
Host smart-31834913-0246-449b-8fd5-6d39f46e61d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=910461521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.910461521
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466368302
Short name T918
Test name
Test status
Simulation time 245043611 ps
CPU time 1.27 seconds
Started Aug 13 06:30:52 PM PDT 24
Finished Aug 13 06:30:53 PM PDT 24
Peak memory 191392 kb
Host smart-c32399b4-1398-47d4-82e2-4e9077c8bd3a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466368302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2466368302
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.82097137
Short name T904
Test name
Test status
Simulation time 70663109 ps
CPU time 0.79 seconds
Started Aug 13 06:31:05 PM PDT 24
Finished Aug 13 06:31:06 PM PDT 24
Peak memory 191124 kb
Host smart-3340d92b-9d2e-411a-af61-6dced838e45f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=82097137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.82097137
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2719434874
Short name T865
Test name
Test status
Simulation time 26772246 ps
CPU time 0.78 seconds
Started Aug 13 06:31:06 PM PDT 24
Finished Aug 13 06:31:07 PM PDT 24
Peak memory 195708 kb
Host smart-80aa6d36-fb29-4791-8b6a-8ca769f659f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719434874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2719434874
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.465588893
Short name T925
Test name
Test status
Simulation time 37320751 ps
CPU time 0.95 seconds
Started Aug 13 06:31:09 PM PDT 24
Finished Aug 13 06:31:10 PM PDT 24
Peak memory 191360 kb
Host smart-e5d1c139-6a34-488e-86b4-8b3f47cabe9e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=465588893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.465588893
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4153360301
Short name T935
Test name
Test status
Simulation time 160434919 ps
CPU time 1.38 seconds
Started Aug 13 06:31:10 PM PDT 24
Finished Aug 13 06:31:12 PM PDT 24
Peak memory 191424 kb
Host smart-3bac6647-222a-4319-9e04-3da9e0b503d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153360301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4153360301
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2835302363
Short name T843
Test name
Test status
Simulation time 79042425 ps
CPU time 1.23 seconds
Started Aug 13 06:31:06 PM PDT 24
Finished Aug 13 06:31:07 PM PDT 24
Peak memory 191340 kb
Host smart-53958dbc-337a-46ee-960d-b956bd1d81f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2835302363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2835302363
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1347519411
Short name T896
Test name
Test status
Simulation time 202031540 ps
CPU time 1.01 seconds
Started Aug 13 06:31:08 PM PDT 24
Finished Aug 13 06:31:09 PM PDT 24
Peak memory 191428 kb
Host smart-69a197aa-1a21-4570-aff6-27a03a05ecbe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347519411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1347519411
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.864245162
Short name T894
Test name
Test status
Simulation time 32066767 ps
CPU time 0.9 seconds
Started Aug 13 06:31:12 PM PDT 24
Finished Aug 13 06:31:13 PM PDT 24
Peak memory 191100 kb
Host smart-a44e00da-3593-4854-8d21-93d8c0880174
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=864245162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.864245162
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.162247906
Short name T849
Test name
Test status
Simulation time 111321977 ps
CPU time 0.83 seconds
Started Aug 13 06:31:21 PM PDT 24
Finished Aug 13 06:31:22 PM PDT 24
Peak memory 195724 kb
Host smart-8162d867-b6e7-438f-bfaa-c72633c5e1d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162247906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.162247906
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1555012778
Short name T913
Test name
Test status
Simulation time 53199910 ps
CPU time 1.31 seconds
Started Aug 13 06:31:00 PM PDT 24
Finished Aug 13 06:31:01 PM PDT 24
Peak memory 191344 kb
Host smart-241a3c4b-1fc9-46d4-bc49-0cfef6b4e7b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1555012778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1555012778
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.169845592
Short name T916
Test name
Test status
Simulation time 36736447 ps
CPU time 0.91 seconds
Started Aug 13 06:31:10 PM PDT 24
Finished Aug 13 06:31:11 PM PDT 24
Peak memory 191160 kb
Host smart-f1dc4df4-5fdc-429d-885e-d2294a180ce4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169845592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.169845592
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1737724539
Short name T880
Test name
Test status
Simulation time 132694162 ps
CPU time 0.78 seconds
Started Aug 13 06:31:04 PM PDT 24
Finished Aug 13 06:31:05 PM PDT 24
Peak memory 191112 kb
Host smart-5a63e52a-43a4-4a02-b32d-77f667b420b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1737724539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1737724539
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4114764414
Short name T864
Test name
Test status
Simulation time 77377518 ps
CPU time 1.36 seconds
Started Aug 13 06:31:19 PM PDT 24
Finished Aug 13 06:31:21 PM PDT 24
Peak memory 191316 kb
Host smart-9078a484-2d7a-47e9-b92a-12e4230544d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114764414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4114764414
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1063264671
Short name T909
Test name
Test status
Simulation time 173473321 ps
CPU time 0.8 seconds
Started Aug 13 06:31:21 PM PDT 24
Finished Aug 13 06:31:22 PM PDT 24
Peak memory 191112 kb
Host smart-dc50c4be-8bdc-47fe-aaed-190a426900dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1063264671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1063264671
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3312003401
Short name T893
Test name
Test status
Simulation time 456199100 ps
CPU time 0.97 seconds
Started Aug 13 06:31:05 PM PDT 24
Finished Aug 13 06:31:06 PM PDT 24
Peak memory 191428 kb
Host smart-bd23d77b-7df1-4efa-96ea-318c1196cb76
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312003401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3312003401
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1030685072
Short name T881
Test name
Test status
Simulation time 64985955 ps
CPU time 0.97 seconds
Started Aug 13 06:31:12 PM PDT 24
Finished Aug 13 06:31:13 PM PDT 24
Peak memory 197644 kb
Host smart-e468e0bb-905f-4082-8431-408b46e87144
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1030685072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1030685072
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3257710104
Short name T895
Test name
Test status
Simulation time 567593385 ps
CPU time 1.11 seconds
Started Aug 13 06:31:23 PM PDT 24
Finished Aug 13 06:31:29 PM PDT 24
Peak memory 191284 kb
Host smart-eeff37d3-bca6-4891-abb4-de2bcb9e11be
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257710104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3257710104
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.4126827989
Short name T885
Test name
Test status
Simulation time 26082351 ps
CPU time 0.87 seconds
Started Aug 13 06:31:18 PM PDT 24
Finished Aug 13 06:31:19 PM PDT 24
Peak memory 190080 kb
Host smart-773f1182-ae71-44a4-b4f2-6cc0fe04e4bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4126827989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.4126827989
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2108833553
Short name T841
Test name
Test status
Simulation time 45087415 ps
CPU time 0.94 seconds
Started Aug 13 06:31:13 PM PDT 24
Finished Aug 13 06:31:14 PM PDT 24
Peak memory 196952 kb
Host smart-53211b0a-e574-4659-bb2f-ea071adfa6dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108833553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2108833553
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1530443437
Short name T856
Test name
Test status
Simulation time 74816421 ps
CPU time 0.95 seconds
Started Aug 13 06:31:21 PM PDT 24
Finished Aug 13 06:31:22 PM PDT 24
Peak memory 191340 kb
Host smart-3c864b90-df6d-4e1c-a392-e7ee70bfc3d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1530443437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1530443437
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.242471157
Short name T888
Test name
Test status
Simulation time 52809485 ps
CPU time 0.97 seconds
Started Aug 13 06:31:09 PM PDT 24
Finished Aug 13 06:31:11 PM PDT 24
Peak memory 190280 kb
Host smart-526261b5-bac1-491c-b4ef-1cdd1cd34ef4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242471157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.242471157
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2680197231
Short name T850
Test name
Test status
Simulation time 33351715 ps
CPU time 0.91 seconds
Started Aug 13 06:31:15 PM PDT 24
Finished Aug 13 06:31:16 PM PDT 24
Peak memory 191204 kb
Host smart-5580117d-dcf9-41ee-a02c-7a5c4559a4b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2680197231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2680197231
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1729103919
Short name T936
Test name
Test status
Simulation time 1142990564 ps
CPU time 1.42 seconds
Started Aug 13 06:30:52 PM PDT 24
Finished Aug 13 06:30:54 PM PDT 24
Peak memory 191368 kb
Host smart-d0681ac6-f5d8-4c47-a36b-7f681100d980
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729103919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1729103919
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1131345373
Short name T873
Test name
Test status
Simulation time 30875029 ps
CPU time 0.9 seconds
Started Aug 13 06:31:06 PM PDT 24
Finished Aug 13 06:31:07 PM PDT 24
Peak memory 191224 kb
Host smart-c41b3549-c856-4a56-8f8a-1e4005f13ffe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1131345373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1131345373
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1905764030
Short name T890
Test name
Test status
Simulation time 49710378 ps
CPU time 0.95 seconds
Started Aug 13 06:31:20 PM PDT 24
Finished Aug 13 06:31:22 PM PDT 24
Peak memory 196732 kb
Host smart-bc2953a6-6ba3-426a-a9c9-f1bfc718f013
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905764030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1905764030
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1609814763
Short name T868
Test name
Test status
Simulation time 32567177 ps
CPU time 0.79 seconds
Started Aug 13 06:31:21 PM PDT 24
Finished Aug 13 06:31:22 PM PDT 24
Peak memory 191108 kb
Host smart-0b773c00-ab1a-4ea6-a871-044e018b6edb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1609814763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1609814763
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3855859871
Short name T926
Test name
Test status
Simulation time 311540910 ps
CPU time 1.33 seconds
Started Aug 13 06:31:13 PM PDT 24
Finished Aug 13 06:31:14 PM PDT 24
Peak memory 197644 kb
Host smart-de845455-732d-4779-b5e6-6216b356a8ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855859871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3855859871
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.407075155
Short name T839
Test name
Test status
Simulation time 600997715 ps
CPU time 1.45 seconds
Started Aug 13 06:31:05 PM PDT 24
Finished Aug 13 06:31:06 PM PDT 24
Peak memory 197688 kb
Host smart-495cb020-6b13-4192-95c1-e275ba2a290c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=407075155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.407075155
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2998288970
Short name T883
Test name
Test status
Simulation time 94127044 ps
CPU time 1.03 seconds
Started Aug 13 06:31:05 PM PDT 24
Finished Aug 13 06:31:06 PM PDT 24
Peak memory 196208 kb
Host smart-1c1e4c91-b6bd-4add-9f08-d130d8f02980
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998288970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2998288970
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1910858034
Short name T844
Test name
Test status
Simulation time 42353248 ps
CPU time 1.24 seconds
Started Aug 13 06:31:15 PM PDT 24
Finished Aug 13 06:31:16 PM PDT 24
Peak memory 196924 kb
Host smart-0c61f3aa-d705-471c-b3b1-2293cfec0b52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1910858034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1910858034
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.24029635
Short name T901
Test name
Test status
Simulation time 45247280 ps
CPU time 1.22 seconds
Started Aug 13 06:31:17 PM PDT 24
Finished Aug 13 06:31:18 PM PDT 24
Peak memory 191428 kb
Host smart-f5f31199-05b6-4c72-a7bd-ec1625e14c87
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24029635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.24029635
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1497233158
Short name T848
Test name
Test status
Simulation time 57696915 ps
CPU time 1.17 seconds
Started Aug 13 06:31:14 PM PDT 24
Finished Aug 13 06:31:16 PM PDT 24
Peak memory 197620 kb
Host smart-42ebe0e6-f7f6-4bbb-a0bd-d2c91a22b50a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1497233158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1497233158
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3783697919
Short name T871
Test name
Test status
Simulation time 208257290 ps
CPU time 1.12 seconds
Started Aug 13 06:31:17 PM PDT 24
Finished Aug 13 06:31:19 PM PDT 24
Peak memory 191348 kb
Host smart-03f15613-651e-441f-8136-427e22fd3175
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783697919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3783697919
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2578461363
Short name T855
Test name
Test status
Simulation time 32766677 ps
CPU time 0.91 seconds
Started Aug 13 06:31:22 PM PDT 24
Finished Aug 13 06:31:23 PM PDT 24
Peak memory 195608 kb
Host smart-86a92aaf-f9c6-4838-a72b-685eb2175dde
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2578461363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2578461363
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1639928742
Short name T897
Test name
Test status
Simulation time 101175407 ps
CPU time 0.85 seconds
Started Aug 13 06:31:16 PM PDT 24
Finished Aug 13 06:31:17 PM PDT 24
Peak memory 191196 kb
Host smart-8307045f-2c6e-49a2-bc1d-479a0ef49a32
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639928742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1639928742
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1816610431
Short name T845
Test name
Test status
Simulation time 228858593 ps
CPU time 1.1 seconds
Started Aug 13 06:31:18 PM PDT 24
Finished Aug 13 06:31:20 PM PDT 24
Peak memory 191432 kb
Host smart-68c6d008-f4a2-409a-bea5-94669dde7b6b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1816610431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1816610431
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.690534102
Short name T857
Test name
Test status
Simulation time 292830931 ps
CPU time 1.42 seconds
Started Aug 13 06:31:19 PM PDT 24
Finished Aug 13 06:31:20 PM PDT 24
Peak memory 191376 kb
Host smart-b182a49f-84f5-464f-8834-316ba0c3ae03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690534102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.690534102
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.783183263
Short name T923
Test name
Test status
Simulation time 170430420 ps
CPU time 1.42 seconds
Started Aug 13 06:31:17 PM PDT 24
Finished Aug 13 06:31:19 PM PDT 24
Peak memory 191344 kb
Host smart-d47230af-f8c7-412e-aa08-9a8b4b9f3433
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=783183263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.783183263
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2634029325
Short name T862
Test name
Test status
Simulation time 47240680 ps
CPU time 1.4 seconds
Started Aug 13 06:31:22 PM PDT 24
Finished Aug 13 06:31:23 PM PDT 24
Peak memory 191404 kb
Host smart-9bbdd946-93f9-451c-a204-a8381296593b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634029325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2634029325
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3991830366
Short name T886
Test name
Test status
Simulation time 38436312 ps
CPU time 1.09 seconds
Started Aug 13 06:31:16 PM PDT 24
Finished Aug 13 06:31:17 PM PDT 24
Peak memory 196216 kb
Host smart-d19f149e-bce8-484d-a740-8d2b92c43868
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3991830366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3991830366
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2880972033
Short name T907
Test name
Test status
Simulation time 254848923 ps
CPU time 1.24 seconds
Started Aug 13 06:31:16 PM PDT 24
Finished Aug 13 06:31:17 PM PDT 24
Peak memory 191392 kb
Host smart-4d25894b-2bb0-4e5e-b962-985dd88ab0a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880972033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2880972033
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4208269716
Short name T877
Test name
Test status
Simulation time 213939404 ps
CPU time 0.99 seconds
Started Aug 13 06:31:18 PM PDT 24
Finished Aug 13 06:31:19 PM PDT 24
Peak memory 191360 kb
Host smart-553c9251-58f5-4741-a0da-559d8b868c12
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4208269716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.4208269716
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1339439121
Short name T853
Test name
Test status
Simulation time 45774411 ps
CPU time 1.39 seconds
Started Aug 13 06:31:19 PM PDT 24
Finished Aug 13 06:31:21 PM PDT 24
Peak memory 191356 kb
Host smart-9e8b4def-0581-4933-8ed2-6801ae69e5b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339439121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1339439121
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2863377081
Short name T920
Test name
Test status
Simulation time 47862474 ps
CPU time 1.31 seconds
Started Aug 13 06:31:13 PM PDT 24
Finished Aug 13 06:31:14 PM PDT 24
Peak memory 197168 kb
Host smart-151209ce-5225-4d53-abb7-1dd370302491
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2863377081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2863377081
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4068000010
Short name T908
Test name
Test status
Simulation time 32989636 ps
CPU time 0.95 seconds
Started Aug 13 06:31:13 PM PDT 24
Finished Aug 13 06:31:14 PM PDT 24
Peak memory 195216 kb
Host smart-afb77398-ba90-42b7-b76f-d8fcaca14d1e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068000010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4068000010
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3880472709
Short name T851
Test name
Test status
Simulation time 65163349 ps
CPU time 1.22 seconds
Started Aug 13 06:31:15 PM PDT 24
Finished Aug 13 06:31:16 PM PDT 24
Peak memory 197748 kb
Host smart-09d7f998-d8f8-4d66-91d7-abf87b1d3b34
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3880472709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3880472709
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.665232709
Short name T937
Test name
Test status
Simulation time 321690624 ps
CPU time 1.26 seconds
Started Aug 13 06:31:17 PM PDT 24
Finished Aug 13 06:31:19 PM PDT 24
Peak memory 191452 kb
Host smart-f27d3924-05c9-4d25-8d2f-7336d659a098
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665232709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.665232709
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4275665162
Short name T929
Test name
Test status
Simulation time 143265664 ps
CPU time 1.1 seconds
Started Aug 13 06:31:18 PM PDT 24
Finished Aug 13 06:31:19 PM PDT 24
Peak memory 191316 kb
Host smart-bf16f636-ee2d-4579-a87b-2bbd12576e7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4275665162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.4275665162
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2419209898
Short name T874
Test name
Test status
Simulation time 108319951 ps
CPU time 1.03 seconds
Started Aug 13 06:31:20 PM PDT 24
Finished Aug 13 06:31:22 PM PDT 24
Peak memory 191428 kb
Host smart-69b83a31-60ef-4858-b506-ab38c8001703
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419209898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2419209898
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1641640168
Short name T905
Test name
Test status
Simulation time 73876715 ps
CPU time 1.08 seconds
Started Aug 13 06:31:19 PM PDT 24
Finished Aug 13 06:31:21 PM PDT 24
Peak memory 197732 kb
Host smart-8a767af9-d755-4e55-9654-df7f9196d4f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1641640168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1641640168
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3354840059
Short name T921
Test name
Test status
Simulation time 42937115 ps
CPU time 0.92 seconds
Started Aug 13 06:31:14 PM PDT 24
Finished Aug 13 06:31:15 PM PDT 24
Peak memory 191400 kb
Host smart-d13272f4-7f41-48b0-9509-5444b51600ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354840059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3354840059
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3276300021
Short name T914
Test name
Test status
Simulation time 326543648 ps
CPU time 0.72 seconds
Started Aug 13 06:31:42 PM PDT 24
Finished Aug 13 06:31:43 PM PDT 24
Peak memory 191228 kb
Host smart-528642a5-1dcc-4ede-96c7-68923c584ede
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3276300021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3276300021
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2330212240
Short name T928
Test name
Test status
Simulation time 75638992 ps
CPU time 1.2 seconds
Started Aug 13 06:31:15 PM PDT 24
Finished Aug 13 06:31:16 PM PDT 24
Peak memory 191408 kb
Host smart-0b3db8e9-ca5d-4a77-8528-1b2ac14d98b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330212240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2330212240
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2385974003
Short name T867
Test name
Test status
Simulation time 54038336 ps
CPU time 0.9 seconds
Started Aug 13 06:31:20 PM PDT 24
Finished Aug 13 06:31:21 PM PDT 24
Peak memory 197708 kb
Host smart-5d2b751b-f884-4b8c-8331-e1160a001803
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2385974003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2385974003
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.114865450
Short name T861
Test name
Test status
Simulation time 57411375 ps
CPU time 0.87 seconds
Started Aug 13 06:31:17 PM PDT 24
Finished Aug 13 06:31:18 PM PDT 24
Peak memory 191188 kb
Host smart-a4ee27ee-5a95-4a26-99b8-debd61301ce0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114865450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.114865450
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.535214667
Short name T866
Test name
Test status
Simulation time 300405201 ps
CPU time 1.08 seconds
Started Aug 13 06:31:21 PM PDT 24
Finished Aug 13 06:31:22 PM PDT 24
Peak memory 191356 kb
Host smart-d4d4ae72-c1e1-41ce-a71c-a4564afadff7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=535214667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.535214667
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.306748314
Short name T859
Test name
Test status
Simulation time 86510455 ps
CPU time 0.93 seconds
Started Aug 13 06:31:18 PM PDT 24
Finished Aug 13 06:31:19 PM PDT 24
Peak memory 191136 kb
Host smart-05a13c28-7177-47a9-a83f-f37c658449ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306748314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.306748314
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2283331437
Short name T882
Test name
Test status
Simulation time 109802254 ps
CPU time 1.25 seconds
Started Aug 13 06:31:21 PM PDT 24
Finished Aug 13 06:31:22 PM PDT 24
Peak memory 191380 kb
Host smart-8476b1fa-aaa2-4afd-8e61-009f13a59045
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2283331437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2283331437
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.834944611
Short name T910
Test name
Test status
Simulation time 43682584 ps
CPU time 1.15 seconds
Started Aug 13 06:31:19 PM PDT 24
Finished Aug 13 06:31:21 PM PDT 24
Peak memory 191332 kb
Host smart-13997c2f-24ff-4487-9465-92d0a64524dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834944611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.834944611
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1549529418
Short name T917
Test name
Test status
Simulation time 732790712 ps
CPU time 1.35 seconds
Started Aug 13 06:31:18 PM PDT 24
Finished Aug 13 06:31:20 PM PDT 24
Peak memory 191404 kb
Host smart-59b97f13-5ea1-45ae-adf7-d8ae6655fdfa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1549529418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1549529418
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2867418641
Short name T898
Test name
Test status
Simulation time 325588168 ps
CPU time 1.14 seconds
Started Aug 13 06:31:18 PM PDT 24
Finished Aug 13 06:31:20 PM PDT 24
Peak memory 196244 kb
Host smart-ce39fa4f-3615-4b2b-afc9-3e1bc7265364
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867418641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2867418641
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1436575283
Short name T840
Test name
Test status
Simulation time 146347884 ps
CPU time 1.45 seconds
Started Aug 13 06:31:20 PM PDT 24
Finished Aug 13 06:31:22 PM PDT 24
Peak memory 197716 kb
Host smart-8658c59e-b905-4d21-972b-3287fa72bbf4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1436575283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1436575283
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2202322019
Short name T934
Test name
Test status
Simulation time 121563293 ps
CPU time 1.07 seconds
Started Aug 13 06:31:15 PM PDT 24
Finished Aug 13 06:31:16 PM PDT 24
Peak memory 191424 kb
Host smart-0954cd4f-50f1-411b-a267-785dcaf5d226
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202322019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2202322019
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.4042582467
Short name T903
Test name
Test status
Simulation time 219236824 ps
CPU time 1.38 seconds
Started Aug 13 06:31:17 PM PDT 24
Finished Aug 13 06:31:19 PM PDT 24
Peak memory 191380 kb
Host smart-51c16c7b-da35-4be3-a7f3-95f3cb19f29d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4042582467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.4042582467
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2501854027
Short name T933
Test name
Test status
Simulation time 99180799 ps
CPU time 1.32 seconds
Started Aug 13 06:31:18 PM PDT 24
Finished Aug 13 06:31:20 PM PDT 24
Peak memory 191372 kb
Host smart-ffab08ad-73eb-4333-a5a1-52a76b671367
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501854027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2501854027
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3415265288
Short name T852
Test name
Test status
Simulation time 70603829 ps
CPU time 1.24 seconds
Started Aug 13 06:31:04 PM PDT 24
Finished Aug 13 06:31:05 PM PDT 24
Peak memory 191424 kb
Host smart-7c116e1a-9700-4e5e-b581-e5f6a081d10c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3415265288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3415265288
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2990602911
Short name T872
Test name
Test status
Simulation time 205015553 ps
CPU time 0.82 seconds
Started Aug 13 06:31:04 PM PDT 24
Finished Aug 13 06:31:05 PM PDT 24
Peak memory 191200 kb
Host smart-9d67caf7-ddf7-4d41-bb33-c8f704a70976
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990602911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2990602911
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2943696385
Short name T899
Test name
Test status
Simulation time 21554244 ps
CPU time 0.73 seconds
Started Aug 13 06:31:23 PM PDT 24
Finished Aug 13 06:31:24 PM PDT 24
Peak memory 195764 kb
Host smart-d4046bf3-7429-4b98-bda5-62d6cdba6fed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2943696385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2943696385
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3359238540
Short name T869
Test name
Test status
Simulation time 140932047 ps
CPU time 1.4 seconds
Started Aug 13 06:31:13 PM PDT 24
Finished Aug 13 06:31:15 PM PDT 24
Peak memory 197784 kb
Host smart-40e804f5-2cd8-427f-b8dc-56443054338a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359238540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3359238540
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3172614496
Short name T842
Test name
Test status
Simulation time 892463391 ps
CPU time 1.47 seconds
Started Aug 13 06:31:23 PM PDT 24
Finished Aug 13 06:31:25 PM PDT 24
Peak memory 191416 kb
Host smart-bb29e079-558b-449f-b221-39b5c916b750
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3172614496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3172614496
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3710644344
Short name T931
Test name
Test status
Simulation time 41132734 ps
CPU time 1.11 seconds
Started Aug 13 06:31:17 PM PDT 24
Finished Aug 13 06:31:18 PM PDT 24
Peak memory 191292 kb
Host smart-57498c4c-788b-4794-9b02-cfcc57bfaec6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710644344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3710644344
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3044744604
Short name T912
Test name
Test status
Simulation time 85749033 ps
CPU time 1.41 seconds
Started Aug 13 06:31:18 PM PDT 24
Finished Aug 13 06:31:20 PM PDT 24
Peak memory 197756 kb
Host smart-67a5114d-ad2a-4333-b224-f69a5de38a79
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3044744604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3044744604
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2158901380
Short name T854
Test name
Test status
Simulation time 491845726 ps
CPU time 1.51 seconds
Started Aug 13 06:31:17 PM PDT 24
Finished Aug 13 06:31:19 PM PDT 24
Peak memory 197760 kb
Host smart-cf566298-aeba-4b85-9c7e-64187d4b36f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158901380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2158901380
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1983617786
Short name T847
Test name
Test status
Simulation time 68682563 ps
CPU time 1.16 seconds
Started Aug 13 06:31:16 PM PDT 24
Finished Aug 13 06:31:17 PM PDT 24
Peak memory 191352 kb
Host smart-98dd6ff7-c057-474a-910e-23c3e80f533f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1983617786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1983617786
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1639156821
Short name T930
Test name
Test status
Simulation time 51043776 ps
CPU time 1.36 seconds
Started Aug 13 06:31:15 PM PDT 24
Finished Aug 13 06:31:16 PM PDT 24
Peak memory 191396 kb
Host smart-3c7a351d-9ff4-4301-99f1-628d11a3377e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639156821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1639156821
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.286269744
Short name T884
Test name
Test status
Simulation time 129862643 ps
CPU time 0.91 seconds
Started Aug 13 06:31:14 PM PDT 24
Finished Aug 13 06:31:15 PM PDT 24
Peak memory 191220 kb
Host smart-99b413b6-d5b2-4dcd-bbc9-d42092341ecb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=286269744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.286269744
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3474731862
Short name T858
Test name
Test status
Simulation time 110137995 ps
CPU time 0.92 seconds
Started Aug 13 06:31:18 PM PDT 24
Finished Aug 13 06:31:19 PM PDT 24
Peak memory 191232 kb
Host smart-65e727b3-ba0d-46c2-8790-c1c3d6ad3443
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474731862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3474731862
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2281046145
Short name T876
Test name
Test status
Simulation time 246743310 ps
CPU time 1.18 seconds
Started Aug 13 06:31:16 PM PDT 24
Finished Aug 13 06:31:17 PM PDT 24
Peak memory 191336 kb
Host smart-0a25cc90-3543-47c7-950b-8eb53dea3b6a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2281046145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2281046145
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2485950646
Short name T879
Test name
Test status
Simulation time 46716331 ps
CPU time 1.27 seconds
Started Aug 13 06:31:15 PM PDT 24
Finished Aug 13 06:31:16 PM PDT 24
Peak memory 196036 kb
Host smart-ffe922d0-1aaa-40f3-af2a-586127c3655d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485950646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2485950646
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3627390232
Short name T838
Test name
Test status
Simulation time 199440464 ps
CPU time 0.97 seconds
Started Aug 13 06:31:13 PM PDT 24
Finished Aug 13 06:31:15 PM PDT 24
Peak memory 197508 kb
Host smart-c2116b12-1287-4660-871a-c77f440f62f4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3627390232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3627390232
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2707228038
Short name T927
Test name
Test status
Simulation time 185196446 ps
CPU time 1 seconds
Started Aug 13 06:31:22 PM PDT 24
Finished Aug 13 06:31:24 PM PDT 24
Peak memory 197120 kb
Host smart-95bc40a2-3960-48dc-a112-cc593d1f2eff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707228038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2707228038
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1148284382
Short name T915
Test name
Test status
Simulation time 609368298 ps
CPU time 1.37 seconds
Started Aug 13 06:31:20 PM PDT 24
Finished Aug 13 06:31:22 PM PDT 24
Peak memory 191464 kb
Host smart-bc7d6677-36e2-4cb4-ad67-c3e561d2e2dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1148284382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1148284382
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1708456703
Short name T900
Test name
Test status
Simulation time 56025482 ps
CPU time 1 seconds
Started Aug 13 06:31:20 PM PDT 24
Finished Aug 13 06:31:21 PM PDT 24
Peak memory 191408 kb
Host smart-3be6bae0-548f-418a-8084-c6ba14b558a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708456703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1708456703
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2684769589
Short name T924
Test name
Test status
Simulation time 970087882 ps
CPU time 1.4 seconds
Started Aug 13 06:31:15 PM PDT 24
Finished Aug 13 06:31:16 PM PDT 24
Peak memory 191344 kb
Host smart-c5a973ed-5951-42a7-bbf0-0791939a498e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2684769589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2684769589
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2882152037
Short name T911
Test name
Test status
Simulation time 102069157 ps
CPU time 1.43 seconds
Started Aug 13 06:31:19 PM PDT 24
Finished Aug 13 06:31:20 PM PDT 24
Peak memory 191376 kb
Host smart-c4764701-c2f3-4e90-a2be-c7c3be28eafa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882152037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2882152037
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4143258084
Short name T919
Test name
Test status
Simulation time 56151936 ps
CPU time 1.11 seconds
Started Aug 13 06:31:50 PM PDT 24
Finished Aug 13 06:31:51 PM PDT 24
Peak memory 197752 kb
Host smart-f94c356f-ecf2-45bf-81ea-5c179cca4814
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4143258084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.4143258084
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2355158197
Short name T892
Test name
Test status
Simulation time 226764405 ps
CPU time 0.87 seconds
Started Aug 13 06:31:20 PM PDT 24
Finished Aug 13 06:31:21 PM PDT 24
Peak memory 191196 kb
Host smart-9e2f66dd-9bbc-45bb-a56e-846305005121
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355158197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2355158197
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3413940211
Short name T922
Test name
Test status
Simulation time 209024570 ps
CPU time 1.06 seconds
Started Aug 13 06:30:58 PM PDT 24
Finished Aug 13 06:30:59 PM PDT 24
Peak memory 197744 kb
Host smart-0202be19-7fed-445e-a938-255c20e378cc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3413940211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3413940211
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.869017303
Short name T932
Test name
Test status
Simulation time 136108839 ps
CPU time 1.18 seconds
Started Aug 13 06:31:14 PM PDT 24
Finished Aug 13 06:31:15 PM PDT 24
Peak memory 191400 kb
Host smart-efe570a5-a36f-412a-a1d5-719fbc241827
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869017303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.869017303
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1013478605
Short name T870
Test name
Test status
Simulation time 189973728 ps
CPU time 1.36 seconds
Started Aug 13 06:31:03 PM PDT 24
Finished Aug 13 06:31:05 PM PDT 24
Peak memory 196068 kb
Host smart-562e33e0-61bc-418d-896e-d27b25351c51
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1013478605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1013478605
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3918169445
Short name T906
Test name
Test status
Simulation time 138587276 ps
CPU time 1.02 seconds
Started Aug 13 06:31:17 PM PDT 24
Finished Aug 13 06:31:18 PM PDT 24
Peak memory 190308 kb
Host smart-8c731b29-5c87-4a73-b7ad-805557ac39e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918169445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3918169445
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1609125370
Short name T902
Test name
Test status
Simulation time 320871763 ps
CPU time 1.34 seconds
Started Aug 13 06:31:01 PM PDT 24
Finished Aug 13 06:31:02 PM PDT 24
Peak memory 191376 kb
Host smart-da11253f-a487-4903-be26-59a35366e3d2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1609125370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1609125370
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.338622035
Short name T891
Test name
Test status
Simulation time 100319298 ps
CPU time 1.48 seconds
Started Aug 13 06:31:07 PM PDT 24
Finished Aug 13 06:31:09 PM PDT 24
Peak memory 191408 kb
Host smart-fa0df9a1-d9de-402e-9b19-9926789170b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338622035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.338622035
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.438753157
Short name T878
Test name
Test status
Simulation time 89393765 ps
CPU time 1.22 seconds
Started Aug 13 06:30:59 PM PDT 24
Finished Aug 13 06:31:00 PM PDT 24
Peak memory 191400 kb
Host smart-9967ea1b-6233-4c75-9d5a-d0b8c650af11
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=438753157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.438753157
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1226337786
Short name T860
Test name
Test status
Simulation time 22201786 ps
CPU time 0.78 seconds
Started Aug 13 06:31:13 PM PDT 24
Finished Aug 13 06:31:14 PM PDT 24
Peak memory 191108 kb
Host smart-1e5e7604-9cc5-45db-9390-f04cb6b724fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226337786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1226337786
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1341396885
Short name T889
Test name
Test status
Simulation time 291030231 ps
CPU time 1.3 seconds
Started Aug 13 06:31:03 PM PDT 24
Finished Aug 13 06:31:04 PM PDT 24
Peak memory 191348 kb
Host smart-81df0a58-75d7-463b-bd60-f59900c06404
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1341396885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1341396885
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3247907595
Short name T875
Test name
Test status
Simulation time 82010946 ps
CPU time 0.95 seconds
Started Aug 13 06:31:03 PM PDT 24
Finished Aug 13 06:31:04 PM PDT 24
Peak memory 191224 kb
Host smart-78cc8b87-db4c-47a8-afff-7468efcb47ee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247907595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3247907595
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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