Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1501472	1			T21	1		T22	100		T23	1
all_pins[1]	1501472	1			T21	1		T22	100		T23	1
all_pins[2]	1501472	1			T21	1		T22	100		T23	1
all_pins[3]	1501472	1			T21	1		T22	100		T23	1
all_pins[4]	1501472	1			T21	1		T22	100		T23	1
all_pins[5]	1501472	1			T21	1		T22	100		T23	1
all_pins[6]	1501472	1			T21	1		T22	100		T23	1
all_pins[7]	1501472	1			T21	1		T22	100		T23	1
all_pins[8]	1501472	1			T21	1		T22	100		T23	1
all_pins[9]	1501472	1			T21	1		T22	100		T23	1
all_pins[10]	1501472	1			T21	1		T22	100		T23	1
all_pins[11]	1501472	1			T21	1		T22	100		T23	1
all_pins[12]	1501472	1			T21	1		T22	100		T23	1
all_pins[13]	1501472	1			T21	1		T22	100		T23	1
all_pins[14]	1501472	1			T21	1		T22	100		T23	1
all_pins[15]	1501472	1			T21	1		T22	100		T23	1
all_pins[16]	1501472	1			T21	1		T22	100		T23	1
all_pins[17]	1501472	1			T21	1		T22	100		T23	1
all_pins[18]	1501472	1			T21	1		T22	100		T23	1
all_pins[19]	1501472	1			T21	1		T22	100		T23	1
all_pins[20]	1501472	1			T21	1		T22	100		T23	1
all_pins[21]	1501472	1			T21	1		T22	100		T23	1
all_pins[22]	1501472	1			T21	1		T22	100		T23	1
all_pins[23]	1501472	1			T21	1		T22	100		T23	1
all_pins[24]	1501472	1			T21	1		T22	100		T23	1
all_pins[25]	1501472	1			T21	1		T22	100		T23	1
all_pins[26]	1501472	1			T21	1		T22	100		T23	1
all_pins[27]	1501472	1			T21	1		T22	100		T23	1
all_pins[28]	1501472	1			T21	1		T22	100		T23	1
all_pins[29]	1501472	1			T21	1		T22	100		T23	1
all_pins[30]	1501472	1			T21	1		T22	100		T23	1
all_pins[31]	1501472	1			T21	1		T22	100		T23	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	29866545	1			T21	32		T22	1665		T23	32
values[0x1]	18180559	1			T22	1535		T25	1461		T26	1463
transitions[0x0=>0x1]	10890494	1			T22	769		T25	914		T26	787
transitions[0x1=>0x0]	10890366	1			T22	769		T25	914		T26	786

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	933633	1			T21	1		T22	45		T23	1
all_pins[0]	values[0x1]	567839	1			T22	55		T25	35		T26	43
all_pins[0]	transitions[0x0=>0x1]	348909	1			T22	28		T25	9		T26	25
all_pins[0]	transitions[0x1=>0x0]	352907	1			T22	27		T25	47		T26	26
all_pins[1]	values[0x0]	932130	1			T21	1		T22	50		T23	1
all_pins[1]	values[0x1]	569342	1			T22	50		T25	29		T26	47
all_pins[1]	transitions[0x0=>0x1]	341496	1			T22	22		T25	24		T26	26
all_pins[1]	transitions[0x1=>0x0]	339993	1			T22	27		T25	30		T26	22
all_pins[2]	values[0x0]	933621	1			T21	1		T22	54		T23	1
all_pins[2]	values[0x1]	567851	1			T22	46		T25	24		T26	47
all_pins[2]	transitions[0x0=>0x1]	339175	1			T22	25		T25	14		T26	24
all_pins[2]	transitions[0x1=>0x0]	340666	1			T22	29		T25	19		T26	24
all_pins[3]	values[0x0]	931939	1			T21	1		T22	42		T23	1
all_pins[3]	values[0x1]	569533	1			T22	58		T25	70		T26	43
all_pins[3]	transitions[0x0=>0x1]	341138	1			T22	27		T25	58		T26	24
all_pins[3]	transitions[0x1=>0x0]	339456	1			T22	15		T25	12		T26	28
all_pins[4]	values[0x0]	934096	1			T21	1		T22	55		T23	1
all_pins[4]	values[0x1]	567376	1			T22	45		T25	54		T26	47
all_pins[4]	transitions[0x0=>0x1]	339550	1			T22	17		T25	35		T26	26
all_pins[4]	transitions[0x1=>0x0]	341707	1			T22	30		T25	51		T26	22
all_pins[5]	values[0x0]	931975	1			T21	1		T22	58		T23	1
all_pins[5]	values[0x1]	569497	1			T22	42		T25	47		T26	37
all_pins[5]	transitions[0x0=>0x1]	342040	1			T22	21		T25	16		T26	22
all_pins[5]	transitions[0x1=>0x0]	339919	1			T22	24		T25	23		T26	32
all_pins[6]	values[0x0]	931664	1			T21	1		T22	56		T23	1
all_pins[6]	values[0x1]	569808	1			T22	44		T25	48		T26	54
all_pins[6]	transitions[0x0=>0x1]	340114	1			T22	28		T25	30		T26	34
all_pins[6]	transitions[0x1=>0x0]	339803	1			T22	26		T25	29		T26	17
all_pins[7]	values[0x0]	934697	1			T21	1		T22	47		T23	1
all_pins[7]	values[0x1]	566775	1			T22	53		T25	27		T26	58
all_pins[7]	transitions[0x0=>0x1]	337339	1			T22	27		T25	17		T26	25
all_pins[7]	transitions[0x1=>0x0]	340372	1			T22	18		T25	38		T26	21
all_pins[8]	values[0x0]	933673	1			T21	1		T22	51		T23	1
all_pins[8]	values[0x1]	567799	1			T22	49		T25	42		T26	46
all_pins[8]	transitions[0x0=>0x1]	340627	1			T22	21		T25	24		T26	19
all_pins[8]	transitions[0x1=>0x0]	339603	1			T22	25		T25	9		T26	31
all_pins[9]	values[0x0]	934115	1			T21	1		T22	56		T23	1
all_pins[9]	values[0x1]	567357	1			T22	44		T25	39		T26	46
all_pins[9]	transitions[0x0=>0x1]	340394	1			T22	22		T25	25		T26	18
all_pins[9]	transitions[0x1=>0x0]	340836	1			T22	27		T25	28		T26	18
all_pins[10]	values[0x0]	933309	1			T21	1		T22	51		T23	1
all_pins[10]	values[0x1]	568163	1			T22	49		T25	46		T26	39
all_pins[10]	transitions[0x0=>0x1]	338779	1			T22	27		T25	25		T26	23
all_pins[10]	transitions[0x1=>0x0]	337973	1			T22	22		T25	18		T26	30
all_pins[11]	values[0x0]	933443	1			T21	1		T22	43		T23	1
all_pins[11]	values[0x1]	568029	1			T22	57		T25	33		T26	43
all_pins[11]	transitions[0x0=>0x1]	339774	1			T22	31		T25	23		T26	31
all_pins[11]	transitions[0x1=>0x0]	339908	1			T22	23		T25	36		T26	27
all_pins[12]	values[0x0]	934365	1			T21	1		T22	56		T23	1
all_pins[12]	values[0x1]	567107	1			T22	44		T25	42		T26	40
all_pins[12]	transitions[0x0=>0x1]	338986	1			T22	13		T25	33		T26	18
all_pins[12]	transitions[0x1=>0x0]	339908	1			T22	26		T25	24		T26	21
all_pins[13]	values[0x0]	933741	1			T21	1		T22	50		T23	1
all_pins[13]	values[0x1]	567731	1			T22	50		T25	31		T26	46
all_pins[13]	transitions[0x0=>0x1]	340260	1			T22	27		T25	25		T26	28
all_pins[13]	transitions[0x1=>0x0]	339636	1			T22	21		T25	36		T26	22
all_pins[14]	values[0x0]	935510	1			T21	1		T22	54		T23	1
all_pins[14]	values[0x1]	565962	1			T22	46		T25	46		T26	51
all_pins[14]	transitions[0x0=>0x1]	338773	1			T22	26		T25	39		T26	26
all_pins[14]	transitions[0x1=>0x0]	340542	1			T22	30		T25	24		T26	21
all_pins[15]	values[0x0]	931843	1			T21	1		T22	50		T23	1
all_pins[15]	values[0x1]	569629	1			T22	50		T25	28		T26	50
all_pins[15]	transitions[0x0=>0x1]	341516	1			T22	28		T25	17		T26	21
all_pins[15]	transitions[0x1=>0x0]	337849	1			T22	24		T25	35		T26	22
all_pins[16]	values[0x0]	933652	1			T21	1		T22	59		T23	1
all_pins[16]	values[0x1]	567820	1			T22	41		T25	45		T26	46
all_pins[16]	transitions[0x0=>0x1]	340194	1			T22	19		T25	41		T26	25
all_pins[16]	transitions[0x1=>0x0]	342003	1			T22	28		T25	24		T26	29
all_pins[17]	values[0x0]	931298	1			T21	1		T22	55		T23	1
all_pins[17]	values[0x1]	570174	1			T22	45		T25	64		T26	48
all_pins[17]	transitions[0x0=>0x1]	343239	1			T22	20		T25	42		T26	24
all_pins[17]	transitions[0x1=>0x0]	340885	1			T22	16		T25	23		T26	22
all_pins[18]	values[0x0]	934540	1			T21	1		T22	49		T23	1
all_pins[18]	values[0x1]	566932	1			T22	51		T25	34		T26	46
all_pins[18]	transitions[0x0=>0x1]	338243	1			T22	28		T25	24		T26	27
all_pins[18]	transitions[0x1=>0x0]	341485	1			T22	22		T25	54		T26	29
all_pins[19]	values[0x0]	931429	1			T21	1		T22	53		T23	1
all_pins[19]	values[0x1]	570043	1			T22	47		T25	65		T26	41
all_pins[19]	transitions[0x0=>0x1]	341329	1			T22	19		T25	43		T26	20
all_pins[19]	transitions[0x1=>0x0]	338218	1			T22	23		T25	12		T26	25
all_pins[20]	values[0x0]	932443	1			T21	1		T22	58		T23	1
all_pins[20]	values[0x1]	569029	1			T22	42		T25	38		T26	40
all_pins[20]	transitions[0x0=>0x1]	340384	1			T22	22		T25	17		T26	20
all_pins[20]	transitions[0x1=>0x0]	341398	1			T22	27		T25	44		T26	21
all_pins[21]	values[0x0]	931352	1			T21	1		T22	51		T23	1
all_pins[21]	values[0x1]	570120	1			T22	49		T25	77		T26	44
all_pins[21]	transitions[0x0=>0x1]	340784	1			T22	24		T25	53		T26	29
all_pins[21]	transitions[0x1=>0x0]	339693	1			T22	17		T25	14		T26	25
all_pins[22]	values[0x0]	935926	1			T21	1		T22	55		T23	1
all_pins[22]	values[0x1]	565546	1			T22	45		T25	30		T26	53
all_pins[22]	transitions[0x0=>0x1]	336873	1			T22	22		T25	8		T26	32
all_pins[22]	transitions[0x1=>0x0]	341447	1			T22	26		T25	55		T26	23
all_pins[23]	values[0x0]	936222	1			T21	1		T22	50		T23	1
all_pins[23]	values[0x1]	565250	1			T22	50		T25	59		T26	48
all_pins[23]	transitions[0x0=>0x1]	339181	1			T22	28		T25	40		T26	25
all_pins[23]	transitions[0x1=>0x0]	339477	1			T22	23		T25	11		T26	30
all_pins[24]	values[0x0]	929626	1			T21	1		T22	52		T23	1
all_pins[24]	values[0x1]	571846	1			T22	48		T25	51		T26	39
all_pins[24]	transitions[0x0=>0x1]	342537	1			T22	17		T25	23		T26	19
all_pins[24]	transitions[0x1=>0x0]	335941	1			T22	19		T25	31		T26	28
all_pins[25]	values[0x0]	934064	1			T21	1		T22	54		T23	1
all_pins[25]	values[0x1]	567408	1			T22	46		T25	27		T26	41
all_pins[25]	transitions[0x0=>0x1]	337121	1			T22	22		T25	7		T26	25
all_pins[25]	transitions[0x1=>0x0]	341559	1			T22	24		T25	31		T26	23
all_pins[26]	values[0x0]	935421	1			T21	1		T22	60		T23	1
all_pins[26]	values[0x1]	566051	1			T22	40		T25	32		T26	54
all_pins[26]	transitions[0x0=>0x1]	339079	1			T22	22		T25	29		T26	31
all_pins[26]	transitions[0x1=>0x0]	340436	1			T22	28		T25	24		T26	18
all_pins[27]	values[0x0]	934838	1			T21	1		T22	50		T23	1
all_pins[27]	values[0x1]	566634	1			T22	50		T25	77		T26	42
all_pins[27]	transitions[0x0=>0x1]	341329	1			T22	32		T25	53		T26	17
all_pins[27]	transitions[0x1=>0x0]	340746	1			T22	22		T25	8		T26	29
all_pins[28]	values[0x0]	933359	1			T21	1		T22	56		T23	1
all_pins[28]	values[0x1]	568113	1			T22	44		T25	20		T26	47
all_pins[28]	transitions[0x0=>0x1]	341378	1			T22	24		T25	11		T26	30
all_pins[28]	transitions[0x1=>0x0]	339899	1			T22	30		T25	68		T26	25
all_pins[29]	values[0x0]	934607	1			T21	1		T22	55		T23	1
all_pins[29]	values[0x1]	566865	1			T22	45		T25	55		T26	51
all_pins[29]	transitions[0x0=>0x1]	338439	1			T22	24		T25	45		T26	28
all_pins[29]	transitions[0x1=>0x0]	339687	1			T22	23		T25	10		T26	24
all_pins[30]	values[0x0]	934507	1			T21	1		T22	44		T23	1
all_pins[30]	values[0x1]	566965	1			T22	56		T25	73		T26	41
all_pins[30]	transitions[0x0=>0x1]	338882	1			T22	33		T25	46		T26	18
all_pins[30]	transitions[0x1=>0x0]	338782	1			T22	22		T25	28		T26	28
all_pins[31]	values[0x0]	929507	1			T21	1		T22	46		T23	1
all_pins[31]	values[0x1]	571965	1			T22	54		T25	73		T26	45
all_pins[31]	transitions[0x0=>0x1]	342632	1			T22	23		T25	18		T26	27
all_pins[31]	transitions[0x1=>0x0]	337632	1			T22	25		T25	18		T26	23