Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6316724	1			T21	345		T22	1456		T23	386
all_values[1]	6316724	1			T21	345		T22	1456		T23	386
all_values[2]	6316724	1			T21	345		T22	1456		T23	386
all_values[3]	6316724	1			T21	345		T22	1456		T23	386
all_values[4]	6316724	1			T21	345		T22	1456		T23	386
all_values[5]	6316724	1			T21	345		T22	1456		T23	386
all_values[6]	6316724	1			T21	345		T22	1456		T23	386
all_values[7]	6316724	1			T21	345		T22	1456		T23	386
all_values[8]	6316724	1			T21	345		T22	1456		T23	386
all_values[9]	6316724	1			T21	345		T22	1456		T23	386
all_values[10]	6316724	1			T21	345		T22	1456		T23	386
all_values[11]	6316724	1			T21	345		T22	1456		T23	386
all_values[12]	6316724	1			T21	345		T22	1456		T23	386
all_values[13]	6316724	1			T21	345		T22	1456		T23	386
all_values[14]	6316724	1			T21	345		T22	1456		T23	386
all_values[15]	6316724	1			T21	345		T22	1456		T23	386
all_values[16]	6316724	1			T21	345		T22	1456		T23	386
all_values[17]	6316724	1			T21	345		T22	1456		T23	386
all_values[18]	6316724	1			T21	345		T22	1456		T23	386
all_values[19]	6316724	1			T21	345		T22	1456		T23	386
all_values[20]	6316724	1			T21	345		T22	1456		T23	386
all_values[21]	6316724	1			T21	345		T22	1456		T23	386
all_values[22]	6316724	1			T21	345		T22	1456		T23	386
all_values[23]	6316724	1			T21	345		T22	1456		T23	386
all_values[24]	6316724	1			T21	345		T22	1456		T23	386
all_values[25]	6316724	1			T21	345		T22	1456		T23	386
all_values[26]	6316724	1			T21	345		T22	1456		T23	386
all_values[27]	6316724	1			T21	345		T22	1456		T23	386
all_values[28]	6316724	1			T21	345		T22	1456		T23	386
all_values[29]	6316724	1			T21	345		T22	1456		T23	386
all_values[30]	6316724	1			T21	345		T22	1456		T23	386
all_values[31]	6316724	1			T21	345		T22	1456		T23	386

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137420904

1

T21

11040

T22

46592

T23

12352

auto[1]

64714264

1

T25

6499

T27

924

T28

1272

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85285030

1

T21

11040

T22

46592

T23

12352

auto[1]

116850138

1

T25

11563

T27

1166

T28

2345

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200356677

1

T21

11040

T22

46592

T23

12352

auto[1]

1778491

1

T27

145

T1

9060

T2

2160

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2460817	1			T21	345		T22	1456		T23	386
all_values[0]	auto[0]	auto[0]	auto[1]	1814108	1			T25	214		T27	17		T28	38
all_values[0]	auto[0]	auto[1]	auto[0]	202637	1			T25	15		T27	20		T28	3
all_values[0]	auto[0]	auto[1]	auto[1]	1783350	1			T25	148		T27	16		T28	40
all_values[0]	auto[1]	auto[0]	auto[1]	28240	1			T27	2		T1	115		T2	34
all_values[0]	auto[1]	auto[1]	auto[1]	27572	1			T27	3		T1	150		T2	38
all_values[1]	auto[0]	auto[0]	auto[0]	2461702	1			T21	345		T22	1456		T23	386
all_values[1]	auto[0]	auto[0]	auto[1]	1804394	1			T25	214		T27	10		T28	26
all_values[1]	auto[0]	auto[1]	auto[0]	200918	1			T25	39		T27	12		T28	12
all_values[1]	auto[0]	auto[1]	auto[1]	1794124	1			T25	126		T27	21		T28	48
all_values[1]	auto[1]	auto[0]	auto[1]	28076	1			T27	3		T1	133		T2	26
all_values[1]	auto[1]	auto[1]	auto[1]	27510	1			T27	2		T1	126		T2	40
all_values[2]	auto[0]	auto[0]	auto[0]	2461483	1			T21	345		T22	1456		T23	386
all_values[2]	auto[0]	auto[0]	auto[1]	1802767	1			T25	173		T27	20		T28	45
all_values[2]	auto[0]	auto[1]	auto[0]	204300	1			T25	8		T27	11		T97	20
all_values[2]	auto[0]	auto[1]	auto[1]	1792722	1			T25	117		T27	11		T28	29
all_values[2]	auto[1]	auto[0]	auto[1]	28031	1			T27	4		T1	163		T2	29
all_values[2]	auto[1]	auto[1]	auto[1]	27421	1			T1	124		T2	31		T3	17
all_values[3]	auto[0]	auto[0]	auto[0]	2460246	1			T21	345		T22	1456		T23	386
all_values[3]	auto[0]	auto[0]	auto[1]	1797891	1			T25	96		T27	13		T28	29
all_values[3]	auto[0]	auto[1]	auto[0]	205034	1			T25	24		T27	20		T28	8
all_values[3]	auto[0]	auto[1]	auto[1]	1797879	1			T25	272		T27	11		T28	25
all_values[3]	auto[1]	auto[0]	auto[1]	27852	1			T27	5		T1	126		T2	33
all_values[3]	auto[1]	auto[1]	auto[1]	27822	1			T27	2		T1	175		T2	33
all_values[4]	auto[0]	auto[0]	auto[0]	2460544	1			T21	345		T22	1456		T23	386
all_values[4]	auto[0]	auto[0]	auto[1]	1806419	1			T25	192		T27	15		T28	43
all_values[4]	auto[0]	auto[1]	auto[0]	206346	1			T25	5		T27	11		T28	1
all_values[4]	auto[0]	auto[1]	auto[1]	1787937	1			T25	206		T27	11		T28	43
all_values[4]	auto[1]	auto[0]	auto[1]	27904	1			T27	3		T1	130		T2	28
all_values[4]	auto[1]	auto[1]	auto[1]	27574	1			T1	139		T2	37		T3	8
all_values[5]	auto[0]	auto[0]	auto[0]	2458379	1			T21	345		T22	1456		T23	386
all_values[5]	auto[0]	auto[0]	auto[1]	1794345	1			T25	198		T27	27		T28	31
all_values[5]	auto[0]	auto[1]	auto[0]	205405	1			T25	22		T27	14		T28	1
all_values[5]	auto[0]	auto[1]	auto[1]	1802897	1			T25	158		T27	19		T28	57
all_values[5]	auto[1]	auto[0]	auto[1]	28159	1			T27	3		T1	137		T2	30
all_values[5]	auto[1]	auto[1]	auto[1]	27539	1			T27	3		T1	154		T2	33
all_values[6]	auto[0]	auto[0]	auto[0]	2458894	1			T21	345		T22	1456		T23	386
all_values[6]	auto[0]	auto[0]	auto[1]	1801845	1			T25	166		T27	29		T28	51
all_values[6]	auto[0]	auto[1]	auto[0]	205026	1			T25	21		T27	15		T97	8
all_values[6]	auto[0]	auto[1]	auto[1]	1795250	1			T25	216		T27	6		T28	34
all_values[6]	auto[1]	auto[0]	auto[1]	28177	1			T27	6		T1	160		T2	49
all_values[6]	auto[1]	auto[1]	auto[1]	27532	1			T1	129		T2	20		T3	30
all_values[7]	auto[0]	auto[0]	auto[0]	2460186	1			T21	345		T22	1456		T23	386
all_values[7]	auto[0]	auto[0]	auto[1]	1817680	1			T25	242		T27	8		T28	48
all_values[7]	auto[0]	auto[1]	auto[0]	200881	1			T25	10		T27	14		T28	5
all_values[7]	auto[0]	auto[1]	auto[1]	1782675	1			T25	120		T27	30		T28	25
all_values[7]	auto[1]	auto[0]	auto[1]	27929	1			T27	2		T1	143		T2	30
all_values[7]	auto[1]	auto[1]	auto[1]	27373	1			T27	2		T1	140		T2	33
all_values[8]	auto[0]	auto[0]	auto[0]	2460024	1			T21	345		T22	1456		T23	386
all_values[8]	auto[0]	auto[0]	auto[1]	1810141	1			T25	222		T27	33		T28	53
all_values[8]	auto[0]	auto[1]	auto[0]	204788	1			T25	5		T27	11		T28	13
all_values[8]	auto[0]	auto[1]	auto[1]	1786357	1			T25	162		T27	6		T28	14
all_values[8]	auto[1]	auto[0]	auto[1]	27886	1			T27	4		T1	141		T2	38
all_values[8]	auto[1]	auto[1]	auto[1]	27528	1			T1	141		T2	34		T3	28
all_values[9]	auto[0]	auto[0]	auto[0]	2460065	1			T21	345		T22	1456		T23	386
all_values[9]	auto[0]	auto[0]	auto[1]	1804858	1			T25	181		T27	16		T28	44
all_values[9]	auto[0]	auto[1]	auto[0]	204989	1			T25	58		T27	20		T28	9
all_values[9]	auto[0]	auto[1]	auto[1]	1791340	1			T25	134		T27	23		T28	35
all_values[9]	auto[1]	auto[0]	auto[1]	28072	1			T27	2		T1	150		T2	26
all_values[9]	auto[1]	auto[1]	auto[1]	27400	1			T27	2		T1	141		T2	31
all_values[10]	auto[0]	auto[0]	auto[0]	2464694	1			T21	345		T22	1456		T23	386
all_values[10]	auto[0]	auto[0]	auto[1]	1805240	1			T25	208		T27	13		T28	62
all_values[10]	auto[0]	auto[1]	auto[0]	205732	1			T25	27		T27	18		T97	15
all_values[10]	auto[0]	auto[1]	auto[1]	1785426	1			T25	167		T27	19		T28	21
all_values[10]	auto[1]	auto[0]	auto[1]	28194	1			T27	3		T1	128		T2	31
all_values[10]	auto[1]	auto[1]	auto[1]	27438	1			T27	1		T1	145		T2	29
all_values[11]	auto[0]	auto[0]	auto[0]	2463677	1			T21	345		T22	1456		T23	386
all_values[11]	auto[0]	auto[0]	auto[1]	1810780	1			T25	110		T27	14		T28	21
all_values[11]	auto[0]	auto[1]	auto[0]	208024	1			T25	58		T27	17		T28	10
all_values[11]	auto[0]	auto[1]	auto[1]	1778668	1			T25	152		T27	16		T28	49
all_values[11]	auto[1]	auto[0]	auto[1]	27886	1			T27	2		T1	122		T2	22
all_values[11]	auto[1]	auto[1]	auto[1]	27689	1			T27	2		T1	148		T2	47
all_values[12]	auto[0]	auto[0]	auto[0]	2462179	1			T21	345		T22	1456		T23	386
all_values[12]	auto[0]	auto[0]	auto[1]	1819357	1			T25	184		T27	34		T28	40
all_values[12]	auto[0]	auto[1]	auto[0]	204087	1			T25	27		T27	4		T97	21
all_values[12]	auto[0]	auto[1]	auto[1]	1775361	1			T25	192		T27	5		T28	32
all_values[12]	auto[1]	auto[0]	auto[1]	28100	1			T27	6		T1	132		T2	28
all_values[12]	auto[1]	auto[1]	auto[1]	27640	1			T27	1		T1	139		T2	42
all_values[13]	auto[0]	auto[0]	auto[0]	2463328	1			T21	345		T22	1456		T23	386
all_values[13]	auto[0]	auto[0]	auto[1]	1810584	1			T25	264		T27	33		T28	43
all_values[13]	auto[0]	auto[1]	auto[0]	199967	1			T27	10		T97	14		T1	1136
all_values[13]	auto[0]	auto[1]	auto[1]	1787250	1			T25	90		T27	16		T28	33
all_values[13]	auto[1]	auto[0]	auto[1]	27941	1			T27	1		T1	152		T2	34
all_values[13]	auto[1]	auto[1]	auto[1]	27654	1			T27	2		T1	144		T2	39
all_values[14]	auto[0]	auto[0]	auto[0]	2463426	1			T21	345		T22	1456		T23	386
all_values[14]	auto[0]	auto[0]	auto[1]	1798963	1			T25	184		T27	24		T28	51
all_values[14]	auto[0]	auto[1]	auto[0]	204781	1			T25	34		T27	10		T28	3
all_values[14]	auto[0]	auto[1]	auto[1]	1793965	1			T25	141		T27	9		T28	29
all_values[14]	auto[1]	auto[0]	auto[1]	27981	1			T27	3		T1	128		T2	33
all_values[14]	auto[1]	auto[1]	auto[1]	27608	1			T27	2		T1	143		T2	41
all_values[15]	auto[0]	auto[0]	auto[0]	2462386	1			T21	345		T22	1456		T23	386
all_values[15]	auto[0]	auto[0]	auto[1]	1798075	1			T25	235		T27	15		T28	22
all_values[15]	auto[0]	auto[1]	auto[0]	205320	1			T25	30		T27	8		T28	16
all_values[15]	auto[0]	auto[1]	auto[1]	1795134	1			T25	86		T27	1		T28	46
all_values[15]	auto[1]	auto[0]	auto[1]	28073	1			T27	3		T1	154		T2	40
all_values[15]	auto[1]	auto[1]	auto[1]	27736	1			T1	126		T2	30		T3	25
all_values[16]	auto[0]	auto[0]	auto[0]	2462295	1			T21	345		T22	1456		T23	386
all_values[16]	auto[0]	auto[0]	auto[1]	1809841	1			T25	110		T27	14		T28	36
all_values[16]	auto[0]	auto[1]	auto[0]	201863	1			T25	14		T27	14		T97	3
all_values[16]	auto[0]	auto[1]	auto[1]	1787271	1			T25	240		T27	15		T28	17
all_values[16]	auto[1]	auto[0]	auto[1]	27913	1			T27	2		T1	162		T2	39
all_values[16]	auto[1]	auto[1]	auto[1]	27541	1			T27	3		T1	138		T2	34
all_values[17]	auto[0]	auto[0]	auto[0]	2460664	1			T21	345		T22	1456		T23	386
all_values[17]	auto[0]	auto[0]	auto[1]	1796119	1			T25	103		T27	22		T28	48
all_values[17]	auto[0]	auto[1]	auto[0]	205794	1			T25	25		T27	3		T28	5
all_values[17]	auto[0]	auto[1]	auto[1]	1798676	1			T25	269		T27	25		T28	31
all_values[17]	auto[1]	auto[0]	auto[1]	27931	1			T27	3		T1	131		T2	29
all_values[17]	auto[1]	auto[1]	auto[1]	27540	1			T27	3		T1	150		T2	37
all_values[18]	auto[0]	auto[0]	auto[0]	2459993	1			T21	345		T22	1456		T23	386
all_values[18]	auto[0]	auto[0]	auto[1]	1810967	1			T25	262		T27	21		T28	31
all_values[18]	auto[0]	auto[1]	auto[0]	201103	1			T25	1		T27	19		T28	10
all_values[18]	auto[0]	auto[1]	auto[1]	1789021	1			T25	129		T27	7		T28	45
all_values[18]	auto[1]	auto[0]	auto[1]	28183	1			T27	6		T1	146		T2	45
all_values[18]	auto[1]	auto[1]	auto[1]	27457	1			T1	137		T2	32		T3	23
all_values[19]	auto[0]	auto[0]	auto[0]	2459378	1			T21	345		T22	1456		T23	386
all_values[19]	auto[0]	auto[0]	auto[1]	1798134	1			T25	94		T27	14		T28	34
all_values[19]	auto[0]	auto[1]	auto[0]	204915	1			T25	8		T27	10		T28	8
all_values[19]	auto[0]	auto[1]	auto[1]	1798840	1			T25	257		T27	4		T28	23
all_values[19]	auto[1]	auto[0]	auto[1]	27915	1			T27	3		T1	135		T2	33
all_values[19]	auto[1]	auto[1]	auto[1]	27542	1			T27	1		T1	166		T2	29
all_values[20]	auto[0]	auto[0]	auto[0]	2461373	1			T21	345		T22	1456		T23	386
all_values[20]	auto[0]	auto[0]	auto[1]	1801350	1			T25	232		T27	12		T28	39
all_values[20]	auto[0]	auto[1]	auto[0]	207868	1			T25	4		T27	12		T28	5
all_values[20]	auto[0]	auto[1]	auto[1]	1790520	1			T25	158		T27	20		T28	35
all_values[20]	auto[1]	auto[0]	auto[1]	28021	1			T27	1		T1	159		T2	35
all_values[20]	auto[1]	auto[1]	auto[1]	27592	1			T27	1		T1	131		T2	42
all_values[21]	auto[0]	auto[0]	auto[0]	2460039	1			T21	345		T22	1456		T23	386
all_values[21]	auto[0]	auto[0]	auto[1]	1788631	1			T25	133		T27	20		T28	31
all_values[21]	auto[0]	auto[1]	auto[0]	203181	1			T25	10		T27	3		T28	8
all_values[21]	auto[0]	auto[1]	auto[1]	1809167	1			T25	264		T27	12		T28	45
all_values[21]	auto[1]	auto[0]	auto[1]	28295	1			T27	5		T1	166		T2	32
all_values[21]	auto[1]	auto[1]	auto[1]	27411	1			T1	148		T2	35		T3	23
all_values[22]	auto[0]	auto[0]	auto[0]	2460975	1			T21	345		T22	1456		T23	386
all_values[22]	auto[0]	auto[0]	auto[1]	1809707	1			T25	191		T27	13		T28	32
all_values[22]	auto[0]	auto[1]	auto[0]	201339	1			T25	47		T27	10		T97	21
all_values[22]	auto[0]	auto[1]	auto[1]	1789410	1			T25	160		T27	20		T28	43
all_values[22]	auto[1]	auto[0]	auto[1]	28218	1			T27	1		T1	158		T2	34
all_values[22]	auto[1]	auto[1]	auto[1]	27075	1			T27	1		T1	112		T2	31
all_values[23]	auto[0]	auto[0]	auto[0]	2462545	1			T21	345		T22	1456		T23	386
all_values[23]	auto[0]	auto[0]	auto[1]	1809879	1			T25	130		T27	21		T28	45
all_values[23]	auto[0]	auto[1]	auto[0]	205886	1			T25	18		T27	19		T28	9
all_values[23]	auto[0]	auto[1]	auto[1]	1782851	1			T25	252		T27	7		T28	36
all_values[23]	auto[1]	auto[0]	auto[1]	27967	1			T27	3		T1	127		T2	38
all_values[23]	auto[1]	auto[1]	auto[1]	27596	1			T27	2		T1	163		T2	30
all_values[24]	auto[0]	auto[0]	auto[0]	2461928	1			T21	345		T22	1456		T23	386
all_values[24]	auto[0]	auto[0]	auto[1]	1799345	1			T25	106		T27	4		T28	42
all_values[24]	auto[0]	auto[1]	auto[0]	203151	1			T25	17		T27	24		T28	3
all_values[24]	auto[0]	auto[1]	auto[1]	1796684	1			T25	255		T27	19		T28	30
all_values[24]	auto[1]	auto[0]	auto[1]	28008	1			T27	4		T1	124		T2	43
all_values[24]	auto[1]	auto[1]	auto[1]	27608	1			T1	138		T2	32		T3	20
all_values[25]	auto[0]	auto[0]	auto[0]	2459612	1			T21	345		T22	1456		T23	386
all_values[25]	auto[0]	auto[0]	auto[1]	1808754	1			T25	256		T27	15		T28	33
all_values[25]	auto[0]	auto[1]	auto[0]	202796	1			T25	5		T27	19		T28	1
all_values[25]	auto[0]	auto[1]	auto[1]	1790053	1			T25	124		T27	3		T28	44
all_values[25]	auto[1]	auto[0]	auto[1]	28031	1			T27	4		T1	158		T2	39
all_values[25]	auto[1]	auto[1]	auto[1]	27478	1			T27	2		T1	139		T2	27
all_values[26]	auto[0]	auto[0]	auto[0]	2461776	1			T21	345		T22	1456		T23	386
all_values[26]	auto[0]	auto[0]	auto[1]	1808866	1			T25	249		T27	15		T28	29
all_values[26]	auto[0]	auto[1]	auto[0]	203496	1			T27	8		T97	9		T1	1150
all_values[26]	auto[0]	auto[1]	auto[1]	1787124	1			T25	118		T27	21		T28	56
all_values[26]	auto[1]	auto[0]	auto[1]	27946	1			T27	2		T1	139		T2	38
all_values[26]	auto[1]	auto[1]	auto[1]	27516	1			T27	2		T1	130		T2	31
all_values[27]	auto[0]	auto[0]	auto[0]	2457144	1			T21	345		T22	1456		T23	386
all_values[27]	auto[0]	auto[0]	auto[1]	1820882	1			T25	101		T27	24		T28	31
all_values[27]	auto[0]	auto[1]	auto[0]	204732	1			T25	13		T27	15		T28	14
all_values[27]	auto[0]	auto[1]	auto[1]	1778514	1			T25	288		T27	6		T28	5
all_values[27]	auto[1]	auto[0]	auto[1]	27888	1			T27	3		T1	136		T2	33
all_values[27]	auto[1]	auto[1]	auto[1]	27564	1			T27	2		T1	127		T2	36
all_values[28]	auto[0]	auto[0]	auto[0]	2459070	1			T21	345		T22	1456		T23	386
all_values[28]	auto[0]	auto[0]	auto[1]	1799855	1			T25	238		T27	10		T28	28
all_values[28]	auto[0]	auto[1]	auto[0]	203902	1			T25	7		T27	11		T28	10
all_values[28]	auto[0]	auto[1]	auto[1]	1798330	1			T25	107		T27	26		T28	40
all_values[28]	auto[1]	auto[0]	auto[1]	28217	1			T27	3		T1	164		T2	29
all_values[28]	auto[1]	auto[1]	auto[1]	27350	1			T27	2		T1	148		T2	29
all_values[29]	auto[0]	auto[0]	auto[0]	2466752	1			T21	345		T22	1456		T23	386
all_values[29]	auto[0]	auto[0]	auto[1]	1802825	1			T25	144		T27	19		T28	40
all_values[29]	auto[0]	auto[1]	auto[0]	202194	1			T25	4		T27	16		T28	2
all_values[29]	auto[0]	auto[1]	auto[1]	1789224	1			T25	240		T27	12		T28	43
all_values[29]	auto[1]	auto[0]	auto[1]	28049	1			T27	2		T1	135		T2	32
all_values[29]	auto[1]	auto[1]	auto[1]	27680	1			T1	166		T2	33		T3	21
all_values[30]	auto[0]	auto[0]	auto[0]	2460407	1			T21	345		T22	1456		T23	386
all_values[30]	auto[0]	auto[0]	auto[1]	1804923	1			T25	109		T27	22		T28	48
all_values[30]	auto[0]	auto[1]	auto[0]	202964	1			T25	7		T27	20		T28	1
all_values[30]	auto[0]	auto[1]	auto[1]	1792468	1			T25	284		T27	6		T28	36
all_values[30]	auto[1]	auto[0]	auto[1]	28400	1			T27	4		T1	137		T2	29
all_values[30]	auto[1]	auto[1]	auto[1]	27562	1			T27	3		T1	133		T2	36
all_values[31]	auto[0]	auto[0]	auto[0]	2462665	1			T21	345		T22	1456		T23	386
all_values[31]	auto[0]	auto[0]	auto[1]	1797325	1			T25	102		T27	6		T28	55
all_values[31]	auto[0]	auto[1]	auto[0]	202965	1			T25	16		T27	13		T28	19
all_values[31]	auto[0]	auto[1]	auto[1]	1798309	1			T25	288		T27	25		T28	7
all_values[31]	auto[1]	auto[0]	auto[1]	27925	1			T27	2		T1	170		T2	31
all_values[31]	auto[1]	auto[1]	auto[1]	27535	1			T27	1		T1	109		T2	38

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal