Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[1]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[2]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[3]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[4]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[5]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[6]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[7]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[8]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[9]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[10]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[11]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[12]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[13]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[14]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[15]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[16]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[17]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[18]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[19]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[20]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[21]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[22]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[23]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[24]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[25]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[26]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[27]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[28]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[29]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[30]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[31]	6271672	1			T21	675		T22	1456		T23	614

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108718983

1

T21

17018

T22

23304

T23

6163

auto[1]

91974521

1

T21

4582

T22

23288

T23

13485

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168310056

1

T21

16296

T22

46592

T23

12468

auto[1]

32383448

1

T21

5304

T23

7180

T27

534

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158668518

1

T21

10900

T22

46592

T23

12364

auto[1]

42024986

1

T21

10700

T23

7284

T27

1565

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2354127	1			T21	196		T22	667		T23	77
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2093193	1			T21	26		T22	789		T23	198
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	511213	1			T21	50		T23	112		T27	6
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	532206	1			T21	266		T27	33		T29	90
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	276925	1			T21	31		T23	126		T27	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	504008	1			T21	106		T23	101		T29	114
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2348240	1			T21	220		T22	744		T23	89
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2098246	1			T21	38		T22	712		T23	204
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	510724	1			T21	107		T23	98		T27	12
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	532577	1			T21	218		T27	11		T29	124
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	276423	1			T21	19		T23	108		T27	14
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	505462	1			T21	73		T23	115		T27	3
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2354010	1			T21	220		T22	766		T23	81
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2094017	1			T21	28		T22	690		T23	209
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	508606	1			T21	67		T23	88		T27	7
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	532482	1			T21	260		T27	64		T29	108
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	278335	1			T21	31		T23	140		T27	3
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	504222	1			T21	69		T23	96		T27	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2362878	1			T21	293		T22	834		T23	81
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2090239	1			T21	35		T22	622		T23	198
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	508184	1			T21	58		T23	88		T27	6
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	530237	1			T21	184		T27	10		T29	100
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	277905	1			T21	29		T23	143		T27	11
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	502229	1			T21	76		T23	104		T27	35
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2351754	1			T21	189		T22	713		T23	80
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2098533	1			T21	20		T22	743		T23	211
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	509502	1			T21	88		T23	92		T27	5
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	530205	1			T21	259		T27	13		T29	100
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	278230	1			T21	23		T23	138		T27	11
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	503448	1			T21	96		T23	93		T27	2
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2372417	1			T21	147		T22	632		T23	67
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2080525	1			T21	15		T22	824		T23	212
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	509517	1			T21	53		T23	140		T27	14
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	528535	1			T21	288		T27	24		T29	96
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	275339	1			T21	43		T23	115		T27	24
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	505339	1			T21	129		T23	80		T27	14
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2353405	1			T21	355		T22	759		T23	92
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2091609	1			T21	46		T22	697		T23	165
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	508586	1			T21	53		T23	141		T27	8
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	533395	1			T21	155		T27	34		T29	106
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	280601	1			T21	8		T23	88		T27	14
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	504076	1			T21	58		T23	128		T27	2
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2352513	1			T21	283		T22	686		T23	72
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2089109	1			T21	29		T22	770		T23	169
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	509608	1			T21	63		T23	101		T29	106
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	532697	1			T21	187		T27	21		T29	100
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	279614	1			T21	30		T23	136		T27	18
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	508131	1			T21	83		T23	136		T27	20
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2355385	1			T21	230		T22	715		T23	75
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2093711	1			T21	36		T22	741		T23	176
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	507086	1			T21	95		T23	96		T27	7
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	533140	1			T21	222		T27	34		T29	92
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	279059	1			T21	30		T23	138		T27	11
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	503291	1			T21	62		T23	129		T27	4
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2357429	1			T21	222		T22	761		T23	74
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2092426	1			T21	36		T22	695		T23	214
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	510428	1			T21	122		T23	130		T27	6
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	531381	1			T21	196		T27	30		T29	104
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	276839	1			T21	21		T23	106		T27	19
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	503169	1			T21	78		T23	90		T27	31
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2358290	1			T21	229		T22	705		T23	73
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2093062	1			T21	37		T22	751		T23	178
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	510350	1			T21	119		T23	119		T29	102
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	528426	1			T21	176		T27	57		T29	100
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	276782	1			T21	24		T23	126		T27	4
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	504762	1			T21	90		T23	118		T27	13
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2351958	1			T21	217		T22	707		T23	82
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2096511	1			T21	37		T22	749		T23	203
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	508565	1			T21	122		T23	134		T27	14
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	532168	1			T21	175		T27	13		T29	98
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	278437	1			T21	25		T23	85		T27	13
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	504033	1			T21	99		T23	110		T27	12
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2347106	1			T21	248		T22	677		T23	75
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2099901	1			T21	46		T22	779		T23	216
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	508559	1			T21	114		T23	116		T29	126
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	533036	1			T21	179		T27	17		T29	98
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	278055	1			T21	22		T23	95		T27	9
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	505015	1			T21	66		T23	112		T27	15
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2349711	1			T21	239		T22	749		T23	75
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2094793	1			T21	33		T22	707		T23	197
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	509590	1			T21	113		T23	158		T27	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	532505	1			T21	186		T27	19		T29	108
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	278512	1			T21	27		T23	78		T27	11
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	506561	1			T21	77		T23	106		T27	10
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2363298	1			T21	196		T22	783		T23	76
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2082244	1			T21	31		T22	673		T23	230
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	508768	1			T21	98		T23	96		T27	7
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	531735	1			T21	223		T27	23		T29	95
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	279385	1			T21	23		T23	132		T27	2
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	506242	1			T21	104		T23	80		T27	17
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2368187	1			T21	240		T22	719		T23	78
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2085513	1			T21	21		T22	737		T23	174
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	509585	1			T21	62		T23	110		T27	6
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	527548	1			T21	224		T27	29		T29	108
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	277737	1			T21	26		T23	138		T27	27
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	503102	1			T21	102		T23	114		T27	20
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2356173	1			T21	162		T22	709		T23	70
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2095594	1			T21	22		T22	747		T23	173
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	507031	1			T21	70		T23	144		T27	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	529531	1			T21	258		T27	24		T29	74
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	279841	1			T21	37		T23	103		T27	14
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	503502	1			T21	126		T23	124		T27	6
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2352731	1			T21	246		T22	810		T23	71
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2097246	1			T21	33		T22	646		T23	232
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	505869	1			T21	71		T23	136		T29	76
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	535994	1			T21	215		T27	36		T29	124
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	277631	1			T21	27		T23	90		T27	23
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	502201	1			T21	83		T23	85		T27	3
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2360198	1			T21	233		T22	632		T23	80
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2093681	1			T21	29		T22	824		T23	201
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	511622	1			T21	77		T23	101		T27	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	528678	1			T21	208		T27	9		T29	118
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	277401	1			T21	26		T23	144		T27	26
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	500092	1			T21	102		T23	88		T27	18
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2367441	1			T21	265		T22	735		T23	85
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2086473	1			T21	14		T22	721		T23	181
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	507036	1			T21	70		T23	96		T27	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	531081	1			T21	175		T27	18		T29	134
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	278815	1			T21	36		T23	120		T27	20
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	500826	1			T21	115		T23	132		T27	17
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2350870	1			T21	211		T22	747		T23	81
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2100747	1			T21	29		T22	709		T23	192
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	509793	1			T21	54		T23	122		T29	96
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	529844	1			T21	268		T27	6		T29	111
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	277794	1			T21	43		T23	101		T27	14
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	502624	1			T21	70		T23	118		T27	3
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2366051	1			T21	268		T22	815		T23	83
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2082739	1			T21	38		T22	641		T23	185
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	509444	1			T21	99		T23	114		T29	94
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	533801	1			T21	180		T27	18		T29	100
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	277189	1			T21	17		T23	118		T27	28
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	502448	1			T21	73		T23	114		T27	21
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2359533	1			T21	122		T22	795		T23	88
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2092889	1			T21	11		T22	661		T23	196
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	510266	1			T21	48		T23	130		T27	6
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	532452	1			T21	339		T27	4		T29	102
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	277041	1			T21	34		T23	102		T27	10
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	499491	1			T21	121		T23	98		T27	2
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2362632	1			T21	208		T22	682		T23	82
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2089775	1			T21	21		T22	774		T23	195
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	507822	1			T21	64		T23	110		T27	4
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	532045	1			T21	273		T27	26		T29	99
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	277789	1			T21	27		T23	104		T27	13
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	501609	1			T21	82		T23	123		T27	8
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2358483	1			T21	170		T22	651		T23	84
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2092102	1			T21	19		T22	805		T23	193
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	509800	1			T21	56		T23	89		T27	2
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	532871	1			T21	265		T27	8		T29	96
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	278817	1			T21	43		T23	140		T27	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	499599	1			T21	122		T23	108		T27	8
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2359991	1			T21	219		T22	727		T23	93
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2092456	1			T21	25		T22	729		T23	178
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	508391	1			T21	77		T23	88		T27	9
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	531974	1			T21	267		T27	10		T29	134
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	277244	1			T21	27		T23	126		T27	15
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	501616	1			T21	60		T23	129		T27	33
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2350110	1			T21	317		T22	755		T23	86
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2097255	1			T21	49		T22	701		T23	189
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	507771	1			T21	104		T23	140		T27	6
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	533914	1			T21	123		T27	20		T29	116
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	279790	1			T21	17		T23	83		T27	25
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	502832	1			T21	65		T23	116		T27	15
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2353837	1			T21	234		T22	648		T23	74
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2095584	1			T21	31		T22	808		T23	171
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	508204	1			T21	97		T23	101		T29	126
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	531998	1			T21	221		T27	18		T29	100
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	279183	1			T21	22		T23	144		T27	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	502866	1			T21	70		T23	124		T29	111
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2362248	1			T21	257		T22	760		T23	75
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2090734	1			T21	29		T22	696		T23	170
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	505241	1			T21	75		T23	117		T29	104
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	532537	1			T21	218		T27	6		T29	107
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	275857	1			T21	22		T23	116		T27	20
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	505055	1			T21	74		T23	136		T27	24
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2351181	1			T21	267		T22	758		T23	69
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2097283	1			T21	35		T22	698		T23	196
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	506646	1			T21	58		T23	122		T27	9
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	535117	1			T21	216		T27	31		T29	98
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	278965	1			T21	32		T23	112		T27	9
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	502480	1			T21	67		T23	115		T29	110
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2351920	1			T21	289		T22	704		T23	78
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2098445	1			T21	33		T22	752		T23	190
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	506809	1			T21	72		T23	98		T27	5
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	536203	1			T21	197		T27	39		T29	130
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	277518	1			T21	25		T23	134		T27	6
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	500777	1			T21	59		T23	114		T29	114
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2356437	1			T21	200		T22	759		T23	76
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2094707	1			T21	19		T22	697		T23	205
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	506016	1			T21	81		T23	114		T29	122
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	531494	1			T21	248		T27	39		T29	97
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	277310	1			T21	37		T23	116		T27	13
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	505708	1			T21	90		T23	103		T27	23

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal