Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[1]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[2]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[3]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[4]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[5]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[6]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[7]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[8]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[9]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[10]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[11]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[12]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[13]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[14]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[15]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[16]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[17]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[18]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[19]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[20]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[21]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[22]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[23]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[24]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[25]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[26]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[27]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[28]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[29]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[30]	6271672	1			T21	675		T22	1456		T23	614
bins_for_gpio_bits[31]	6271672	1			T21	675		T22	1456		T23	614

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108718983

1

T21

17018

T22

23304

T23

6163

auto[1]

91974521

1

T21

4582

T22

23288

T23

13485

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108710022

1

T21

17018

T22

23304

T23

6170

auto[1]

91983482

1

T21

4582

T22

23288

T23

13478

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3306297	1			T21	495		T22	667		T23	167
bins_for_gpio_bits[0]	auto[0]	auto[1]	90933	1			T21	17		T23	22		T29	22
bins_for_gpio_bits[0]	auto[1]	auto[0]	91249	1			T21	17		T23	22		T29	22
bins_for_gpio_bits[0]	auto[1]	auto[1]	2783193	1			T21	146		T22	789		T23	403
bins_for_gpio_bits[1]	auto[0]	auto[0]	3299742	1			T21	530		T22	744		T23	159
bins_for_gpio_bits[1]	auto[0]	auto[1]	91516	1			T21	15		T23	28		T27	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	91799	1			T21	15		T23	28		T27	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	2788615	1			T21	115		T22	712		T23	399
bins_for_gpio_bits[2]	auto[0]	auto[0]	3303471	1			T21	536		T22	766		T23	143
bins_for_gpio_bits[2]	auto[0]	auto[1]	91317	1			T21	11		T23	26		T29	28
bins_for_gpio_bits[2]	auto[1]	auto[0]	91627	1			T21	11		T23	26		T29	28
bins_for_gpio_bits[2]	auto[1]	auto[1]	2785257	1			T21	117		T22	690		T23	419
bins_for_gpio_bits[3]	auto[0]	auto[0]	3310134	1			T21	520		T22	834		T23	142
bins_for_gpio_bits[3]	auto[0]	auto[1]	90851	1			T21	15		T23	27		T29	24
bins_for_gpio_bits[3]	auto[1]	auto[0]	91165	1			T21	15		T23	27		T29	24
bins_for_gpio_bits[3]	auto[1]	auto[1]	2779522	1			T21	125		T22	622		T23	418
bins_for_gpio_bits[4]	auto[0]	auto[0]	3300087	1			T21	514		T22	713		T23	147
bins_for_gpio_bits[4]	auto[0]	auto[1]	91105	1			T21	22		T23	25		T29	30
bins_for_gpio_bits[4]	auto[1]	auto[0]	91374	1			T21	22		T23	25		T29	30
bins_for_gpio_bits[4]	auto[1]	auto[1]	2789106	1			T21	117		T22	743		T23	417
bins_for_gpio_bits[5]	auto[0]	auto[0]	3319015	1			T21	468		T22	632		T23	180
bins_for_gpio_bits[5]	auto[0]	auto[1]	91153	1			T21	20		T23	27		T29	25
bins_for_gpio_bits[5]	auto[1]	auto[0]	91454	1			T21	20		T23	27		T27	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	2770050	1			T21	167		T22	824		T23	380
bins_for_gpio_bits[6]	auto[0]	auto[0]	3303815	1			T21	554		T22	759		T23	198
bins_for_gpio_bits[6]	auto[0]	auto[1]	91293	1			T21	9		T23	36		T29	29
bins_for_gpio_bits[6]	auto[1]	auto[0]	91571	1			T21	9		T23	35		T29	29
bins_for_gpio_bits[6]	auto[1]	auto[1]	2784993	1			T21	103		T22	697		T23	345
bins_for_gpio_bits[7]	auto[0]	auto[0]	3303018	1			T21	518		T22	686		T23	145
bins_for_gpio_bits[7]	auto[0]	auto[1]	91518	1			T21	15		T23	29		T29	26
bins_for_gpio_bits[7]	auto[1]	auto[0]	91800	1			T21	15		T23	28		T29	27
bins_for_gpio_bits[7]	auto[1]	auto[1]	2785336	1			T21	127		T22	770		T23	412
bins_for_gpio_bits[8]	auto[0]	auto[0]	3304413	1			T21	536		T22	715		T23	142
bins_for_gpio_bits[8]	auto[0]	auto[1]	90963	1			T21	11		T23	29		T29	23
bins_for_gpio_bits[8]	auto[1]	auto[0]	91198	1			T21	11		T23	29		T29	23
bins_for_gpio_bits[8]	auto[1]	auto[1]	2785098	1			T21	117		T22	741		T23	414
bins_for_gpio_bits[9]	auto[0]	auto[0]	3307984	1			T21	526		T22	761		T23	177
bins_for_gpio_bits[9]	auto[0]	auto[1]	90980	1			T21	14		T23	27		T29	37
bins_for_gpio_bits[9]	auto[1]	auto[0]	91254	1			T21	14		T23	27		T29	37
bins_for_gpio_bits[9]	auto[1]	auto[1]	2781454	1			T21	121		T22	695		T23	383
bins_for_gpio_bits[10]	auto[0]	auto[0]	3305727	1			T21	510		T22	705		T23	162
bins_for_gpio_bits[10]	auto[0]	auto[1]	91058	1			T21	14		T23	31		T29	21
bins_for_gpio_bits[10]	auto[1]	auto[0]	91339	1			T21	14		T23	30		T29	22
bins_for_gpio_bits[10]	auto[1]	auto[1]	2783548	1			T21	137		T22	751		T23	391
bins_for_gpio_bits[11]	auto[0]	auto[0]	3301331	1			T21	499		T22	707		T23	185
bins_for_gpio_bits[11]	auto[0]	auto[1]	91070	1			T21	15		T23	31		T29	28
bins_for_gpio_bits[11]	auto[1]	auto[0]	91360	1			T21	15		T23	31		T29	28
bins_for_gpio_bits[11]	auto[1]	auto[1]	2787911	1			T21	146		T22	749		T23	367
bins_for_gpio_bits[12]	auto[0]	auto[0]	3297088	1			T21	529		T22	677		T23	160
bins_for_gpio_bits[12]	auto[0]	auto[1]	91329	1			T21	12		T23	31		T29	32
bins_for_gpio_bits[12]	auto[1]	auto[0]	91613	1			T21	12		T23	31		T29	32
bins_for_gpio_bits[12]	auto[1]	auto[1]	2791642	1			T21	122		T22	779		T23	392
bins_for_gpio_bits[13]	auto[0]	auto[0]	3300646	1			T21	523		T22	749		T23	201
bins_for_gpio_bits[13]	auto[0]	auto[1]	90879	1			T21	15		T23	32		T29	27
bins_for_gpio_bits[13]	auto[1]	auto[0]	91160	1			T21	15		T23	32		T29	27
bins_for_gpio_bits[13]	auto[1]	auto[1]	2788987	1			T21	122		T22	707		T23	349
bins_for_gpio_bits[14]	auto[0]	auto[0]	3312349	1			T21	499		T22	783		T23	149
bins_for_gpio_bits[14]	auto[0]	auto[1]	91202	1			T21	18		T23	23		T29	32
bins_for_gpio_bits[14]	auto[1]	auto[0]	91452	1			T21	18		T23	23		T29	32
bins_for_gpio_bits[14]	auto[1]	auto[1]	2776669	1			T21	140		T22	673		T23	419
bins_for_gpio_bits[15]	auto[0]	auto[0]	3313970	1			T21	512		T22	719		T23	157
bins_for_gpio_bits[15]	auto[0]	auto[1]	91095	1			T21	14		T23	31		T29	31
bins_for_gpio_bits[15]	auto[1]	auto[0]	91350	1			T21	14		T23	31		T29	31
bins_for_gpio_bits[15]	auto[1]	auto[1]	2775257	1			T21	135		T22	737		T23	395
bins_for_gpio_bits[16]	auto[0]	auto[0]	3301519	1			T21	471		T22	709		T23	186
bins_for_gpio_bits[16]	auto[0]	auto[1]	90976	1			T21	19		T23	28		T29	28
bins_for_gpio_bits[16]	auto[1]	auto[0]	91216	1			T21	19		T23	28		T29	28
bins_for_gpio_bits[16]	auto[1]	auto[1]	2787961	1			T21	166		T22	747		T23	372
bins_for_gpio_bits[17]	auto[0]	auto[0]	3303491	1			T21	518		T22	810		T23	176
bins_for_gpio_bits[17]	auto[0]	auto[1]	90837	1			T21	14		T23	31		T29	27
bins_for_gpio_bits[17]	auto[1]	auto[0]	91103	1			T21	14		T23	31		T29	27
bins_for_gpio_bits[17]	auto[1]	auto[1]	2786241	1			T21	129		T22	646		T23	376
bins_for_gpio_bits[18]	auto[0]	auto[0]	3309105	1			T21	503		T22	632		T23	155
bins_for_gpio_bits[18]	auto[0]	auto[1]	91085	1			T21	15		T23	27		T29	28
bins_for_gpio_bits[18]	auto[1]	auto[0]	91393	1			T21	15		T23	26		T29	28
bins_for_gpio_bits[18]	auto[1]	auto[1]	2780089	1			T21	142		T22	824		T23	406
bins_for_gpio_bits[19]	auto[0]	auto[0]	3314459	1			T21	494		T22	735		T23	155
bins_for_gpio_bits[19]	auto[0]	auto[1]	90792	1			T21	16		T23	26		T29	29
bins_for_gpio_bits[19]	auto[1]	auto[0]	91099	1			T21	16		T23	26		T29	30
bins_for_gpio_bits[19]	auto[1]	auto[1]	2775322	1			T21	149		T22	721		T23	407
bins_for_gpio_bits[20]	auto[0]	auto[0]	3299159	1			T21	517		T22	747		T23	171
bins_for_gpio_bits[20]	auto[0]	auto[1]	91077	1			T21	16		T23	32		T29	24
bins_for_gpio_bits[20]	auto[1]	auto[0]	91348	1			T21	16		T23	32		T29	24
bins_for_gpio_bits[20]	auto[1]	auto[1]	2790088	1			T21	126		T22	709		T23	379
bins_for_gpio_bits[21]	auto[0]	auto[0]	3317553	1			T21	533		T22	815		T23	169
bins_for_gpio_bits[21]	auto[0]	auto[1]	91490	1			T21	14		T23	28		T29	25
bins_for_gpio_bits[21]	auto[1]	auto[0]	91743	1			T21	14		T23	28		T29	26
bins_for_gpio_bits[21]	auto[1]	auto[1]	2770886	1			T21	114		T22	641		T23	389
bins_for_gpio_bits[22]	auto[0]	auto[0]	3310892	1			T21	485		T22	795		T23	187
bins_for_gpio_bits[22]	auto[0]	auto[1]	91059	1			T21	24		T23	31		T29	29
bins_for_gpio_bits[22]	auto[1]	auto[0]	91359	1			T21	24		T23	31		T27	1
bins_for_gpio_bits[22]	auto[1]	auto[1]	2778362	1			T21	142		T22	661		T23	365
bins_for_gpio_bits[23]	auto[0]	auto[0]	3311201	1			T21	530		T22	682		T23	161
bins_for_gpio_bits[23]	auto[0]	auto[1]	91001	1			T21	15		T23	31		T29	30
bins_for_gpio_bits[23]	auto[1]	auto[0]	91298	1			T21	15		T23	31		T29	30
bins_for_gpio_bits[23]	auto[1]	auto[1]	2778172	1			T21	115		T22	774		T23	391
bins_for_gpio_bits[24]	auto[0]	auto[0]	3309956	1			T21	470		T22	651		T23	149
bins_for_gpio_bits[24]	auto[0]	auto[1]	90965	1			T21	21		T23	25		T29	27
bins_for_gpio_bits[24]	auto[1]	auto[0]	91198	1			T21	21		T23	24		T29	27
bins_for_gpio_bits[24]	auto[1]	auto[1]	2779553	1			T21	163		T22	805		T23	416
bins_for_gpio_bits[25]	auto[0]	auto[0]	3308858	1			T21	551		T22	727		T23	157
bins_for_gpio_bits[25]	auto[0]	auto[1]	91204	1			T21	12		T23	24		T29	32
bins_for_gpio_bits[25]	auto[1]	auto[0]	91498	1			T21	12		T23	24		T29	32
bins_for_gpio_bits[25]	auto[1]	auto[1]	2780112	1			T21	100		T22	729		T23	409
bins_for_gpio_bits[26]	auto[0]	auto[0]	3300580	1			T21	530		T22	755		T23	191
bins_for_gpio_bits[26]	auto[0]	auto[1]	90947	1			T21	14		T23	35		T29	23
bins_for_gpio_bits[26]	auto[1]	auto[0]	91215	1			T21	14		T23	35		T29	24
bins_for_gpio_bits[26]	auto[1]	auto[1]	2788930	1			T21	117		T22	701		T23	353
bins_for_gpio_bits[27]	auto[0]	auto[0]	3302707	1			T21	537		T22	648		T23	149
bins_for_gpio_bits[27]	auto[0]	auto[1]	91033	1			T21	15		T23	27		T29	31
bins_for_gpio_bits[27]	auto[1]	auto[0]	91332	1			T21	15		T23	26		T29	32
bins_for_gpio_bits[27]	auto[1]	auto[1]	2786600	1			T21	108		T22	808		T23	412
bins_for_gpio_bits[28]	auto[0]	auto[0]	3308480	1			T21	538		T22	760		T23	165
bins_for_gpio_bits[28]	auto[0]	auto[1]	91276	1			T21	12		T23	28		T29	27
bins_for_gpio_bits[28]	auto[1]	auto[0]	91546	1			T21	12		T23	27		T29	27
bins_for_gpio_bits[28]	auto[1]	auto[1]	2780370	1			T21	113		T22	696		T23	394
bins_for_gpio_bits[29]	auto[0]	auto[0]	3301100	1			T21	527		T22	758		T23	156
bins_for_gpio_bits[29]	auto[0]	auto[1]	91528	1			T21	14		T23	35		T29	28
bins_for_gpio_bits[29]	auto[1]	auto[0]	91844	1			T21	14		T23	35		T29	28
bins_for_gpio_bits[29]	auto[1]	auto[1]	2787200	1			T21	120		T22	698		T23	388
bins_for_gpio_bits[30]	auto[0]	auto[0]	3303354	1			T21	546		T22	704		T23	146
bins_for_gpio_bits[30]	auto[0]	auto[1]	91325	1			T21	12		T23	30		T29	25
bins_for_gpio_bits[30]	auto[1]	auto[0]	91578	1			T21	12		T23	30		T29	25
bins_for_gpio_bits[30]	auto[1]	auto[1]	2785415	1			T21	105		T22	752		T23	408
bins_for_gpio_bits[31]	auto[0]	auto[0]	3302601	1			T21	513		T22	759		T23	164
bins_for_gpio_bits[31]	auto[0]	auto[1]	91063	1			T21	16		T23	26		T29	26
bins_for_gpio_bits[31]	auto[1]	auto[0]	91346	1			T21	16		T23	26		T29	26
bins_for_gpio_bits[31]	auto[1]	auto[1]	2786662	1			T21	130		T22	697		T23	398