Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4303165 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
2013559 |
1 |
|
|
T25 |
163 |
|
T27 |
39 |
|
T28 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5385296 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
931428 |
1 |
|
|
T25 |
86 |
|
T28 |
22 |
|
T97 |
54 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4294884 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
2021840 |
1 |
|
|
T25 |
175 |
|
T27 |
8 |
|
T28 |
61 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
553197 |
1 |
|
|
T25 |
68 |
|
T27 |
8 |
|
T28 |
14 |
| auto[1] |
auto[0] |
auto[1] |
470918 |
1 |
|
|
T25 |
57 |
|
T28 |
8 |
|
T97 |
29 |
| auto[1] |
auto[1] |
auto[0] |
537215 |
1 |
|
|
T25 |
21 |
|
T28 |
25 |
|
T97 |
20 |
| auto[1] |
auto[1] |
auto[1] |
460510 |
1 |
|
|
T25 |
29 |
|
T28 |
14 |
|
T97 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |