Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4309636 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
2007088 |
1 |
|
|
T25 |
219 |
|
T27 |
10 |
|
T28 |
32 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5389144 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
927580 |
1 |
|
|
T25 |
94 |
|
T27 |
7 |
|
T28 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4304738 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
2011986 |
1 |
|
|
T25 |
155 |
|
T27 |
7 |
|
T28 |
50 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
548650 |
1 |
|
|
T25 |
24 |
|
T28 |
10 |
|
T97 |
25 |
| auto[1] |
auto[0] |
auto[1] |
467140 |
1 |
|
|
T25 |
42 |
|
T27 |
7 |
|
T28 |
20 |
| auto[1] |
auto[1] |
auto[0] |
535756 |
1 |
|
|
T25 |
37 |
|
T28 |
14 |
|
T97 |
44 |
| auto[1] |
auto[1] |
auto[1] |
460440 |
1 |
|
|
T25 |
52 |
|
T28 |
6 |
|
T97 |
41 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |