Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4305914 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
2010810 |
1 |
|
|
T25 |
301 |
|
T27 |
23 |
|
T28 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6057447 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
259277 |
1 |
|
|
T25 |
8 |
|
T27 |
1 |
|
T28 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4283215 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
2033509 |
1 |
|
|
T25 |
38 |
|
T27 |
38 |
|
T28 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
901585 |
1 |
|
|
T27 |
36 |
|
T28 |
22 |
|
T97 |
46 |
| auto[1] |
auto[0] |
auto[1] |
131951 |
1 |
|
|
T27 |
1 |
|
T28 |
1 |
|
T97 |
1 |
| auto[1] |
auto[1] |
auto[0] |
872647 |
1 |
|
|
T25 |
30 |
|
T27 |
1 |
|
T28 |
7 |
| auto[1] |
auto[1] |
auto[1] |
127326 |
1 |
|
|
T25 |
8 |
|
T97 |
3 |
|
T1 |
718 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |