Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4300391 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
2016333 |
1 |
|
|
T25 |
270 |
|
T27 |
28 |
|
T28 |
45 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5390546 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
926178 |
1 |
|
|
T25 |
75 |
|
T28 |
20 |
|
T97 |
91 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4302886 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
2013838 |
1 |
|
|
T25 |
148 |
|
T27 |
11 |
|
T28 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
545621 |
1 |
|
|
T25 |
26 |
|
T27 |
11 |
|
T28 |
5 |
| auto[1] |
auto[0] |
auto[1] |
465443 |
1 |
|
|
T25 |
24 |
|
T28 |
9 |
|
T97 |
58 |
| auto[1] |
auto[1] |
auto[0] |
542039 |
1 |
|
|
T25 |
47 |
|
T28 |
2 |
|
T97 |
27 |
| auto[1] |
auto[1] |
auto[1] |
460735 |
1 |
|
|
T25 |
51 |
|
T28 |
11 |
|
T97 |
33 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |