Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4293730 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
2022994 |
1 |
|
|
T25 |
291 |
|
T27 |
29 |
|
T28 |
37 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6058525 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
258199 |
1 |
|
|
T25 |
20 |
|
T27 |
1 |
|
T28 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4291163 |
1 |
|
|
T21 |
345 |
|
T22 |
1456 |
|
T23 |
386 |
| auto[1] |
2025561 |
1 |
|
|
T25 |
117 |
|
T27 |
28 |
|
T28 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
890882 |
1 |
|
|
T25 |
21 |
|
T27 |
21 |
|
T28 |
1 |
| auto[1] |
auto[0] |
auto[1] |
130033 |
1 |
|
|
T25 |
3 |
|
T97 |
12 |
|
T1 |
759 |
| auto[1] |
auto[1] |
auto[0] |
876480 |
1 |
|
|
T25 |
76 |
|
T27 |
6 |
|
T28 |
15 |
| auto[1] |
auto[1] |
auto[1] |
128166 |
1 |
|
|
T25 |
17 |
|
T27 |
1 |
|
T28 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |