Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 938
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T760 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2869401848 Aug 14 04:36:46 PM PDT 24 Aug 14 04:36:47 PM PDT 24 191624567 ps
T761 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3684509365 Aug 14 04:36:53 PM PDT 24 Aug 14 04:36:54 PM PDT 24 15416760 ps
T762 /workspace/coverage/cover_reg_top/48.gpio_intr_test.268958695 Aug 14 04:37:09 PM PDT 24 Aug 14 04:37:10 PM PDT 24 19509388 ps
T763 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3726869608 Aug 14 04:36:53 PM PDT 24 Aug 14 04:36:56 PM PDT 24 326696269 ps
T764 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3219867921 Aug 14 04:36:55 PM PDT 24 Aug 14 04:36:56 PM PDT 24 41501188 ps
T49 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2759754321 Aug 14 04:36:36 PM PDT 24 Aug 14 04:36:37 PM PDT 24 307439076 ps
T765 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2501006710 Aug 14 04:36:37 PM PDT 24 Aug 14 04:36:39 PM PDT 24 365029444 ps
T766 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3379466559 Aug 14 04:36:58 PM PDT 24 Aug 14 04:36:58 PM PDT 24 17820635 ps
T767 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3376205479 Aug 14 04:36:32 PM PDT 24 Aug 14 04:36:33 PM PDT 24 16092791 ps
T768 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2913443017 Aug 14 04:37:07 PM PDT 24 Aug 14 04:37:07 PM PDT 24 42689793 ps
T769 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3932707591 Aug 14 04:36:33 PM PDT 24 Aug 14 04:36:34 PM PDT 24 16135659 ps
T770 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1908221104 Aug 14 04:36:55 PM PDT 24 Aug 14 04:36:56 PM PDT 24 114144730 ps
T771 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2428491642 Aug 14 04:36:52 PM PDT 24 Aug 14 04:36:52 PM PDT 24 14563522 ps
T772 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1066722602 Aug 14 04:36:43 PM PDT 24 Aug 14 04:36:44 PM PDT 24 20554071 ps
T773 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1423539598 Aug 14 04:36:49 PM PDT 24 Aug 14 04:36:50 PM PDT 24 15979011 ps
T774 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.972863099 Aug 14 04:36:51 PM PDT 24 Aug 14 04:36:52 PM PDT 24 111749975 ps
T775 /workspace/coverage/cover_reg_top/5.gpio_intr_test.308001753 Aug 14 04:36:56 PM PDT 24 Aug 14 04:36:57 PM PDT 24 14453072 ps
T80 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2474979149 Aug 14 04:36:33 PM PDT 24 Aug 14 04:36:34 PM PDT 24 32111314 ps
T81 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.413877745 Aug 14 04:36:41 PM PDT 24 Aug 14 04:36:42 PM PDT 24 50897427 ps
T776 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1930859241 Aug 14 04:36:48 PM PDT 24 Aug 14 04:36:48 PM PDT 24 14375839 ps
T777 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3894335441 Aug 14 04:36:54 PM PDT 24 Aug 14 04:36:55 PM PDT 24 71154766 ps
T778 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.997947479 Aug 14 04:36:46 PM PDT 24 Aug 14 04:36:48 PM PDT 24 138221201 ps
T779 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.453458232 Aug 14 04:36:50 PM PDT 24 Aug 14 04:36:51 PM PDT 24 44912827 ps
T780 /workspace/coverage/cover_reg_top/30.gpio_intr_test.2415227550 Aug 14 04:36:52 PM PDT 24 Aug 14 04:36:53 PM PDT 24 16512155 ps
T52 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.4138545222 Aug 14 04:37:02 PM PDT 24 Aug 14 04:37:04 PM PDT 24 72580682 ps
T781 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.324769996 Aug 14 04:36:46 PM PDT 24 Aug 14 04:36:47 PM PDT 24 47210162 ps
T782 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.117461345 Aug 14 04:36:42 PM PDT 24 Aug 14 04:36:42 PM PDT 24 50781230 ps
T783 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3453957827 Aug 14 04:36:47 PM PDT 24 Aug 14 04:36:48 PM PDT 24 184381316 ps
T82 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1339807930 Aug 14 04:36:39 PM PDT 24 Aug 14 04:36:40 PM PDT 24 13399851 ps
T784 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3496953318 Aug 14 04:36:40 PM PDT 24 Aug 14 04:36:41 PM PDT 24 14174747 ps
T785 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.4029109041 Aug 14 04:36:53 PM PDT 24 Aug 14 04:36:54 PM PDT 24 84226008 ps
T786 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2450521257 Aug 14 04:36:35 PM PDT 24 Aug 14 04:36:36 PM PDT 24 21164757 ps
T787 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1190310882 Aug 14 04:36:54 PM PDT 24 Aug 14 04:36:55 PM PDT 24 57390061 ps
T788 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2481335764 Aug 14 04:37:10 PM PDT 24 Aug 14 04:37:11 PM PDT 24 15167558 ps
T789 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2569541670 Aug 14 04:37:19 PM PDT 24 Aug 14 04:37:19 PM PDT 24 35679573 ps
T790 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2754708407 Aug 14 04:37:00 PM PDT 24 Aug 14 04:37:01 PM PDT 24 19574901 ps
T791 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1117198252 Aug 14 04:36:46 PM PDT 24 Aug 14 04:36:47 PM PDT 24 223537234 ps
T792 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2744664058 Aug 14 04:36:50 PM PDT 24 Aug 14 04:36:51 PM PDT 24 13656360 ps
T793 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1403551724 Aug 14 04:36:43 PM PDT 24 Aug 14 04:36:43 PM PDT 24 14850345 ps
T50 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2646268432 Aug 14 04:36:54 PM PDT 24 Aug 14 04:36:56 PM PDT 24 843958012 ps
T794 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3675451906 Aug 14 04:37:05 PM PDT 24 Aug 14 04:37:05 PM PDT 24 19960366 ps
T795 /workspace/coverage/cover_reg_top/10.gpio_intr_test.185585670 Aug 14 04:37:03 PM PDT 24 Aug 14 04:37:04 PM PDT 24 30385982 ps
T796 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2811182545 Aug 14 04:36:52 PM PDT 24 Aug 14 04:36:52 PM PDT 24 37630717 ps
T797 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1502313 Aug 14 04:36:46 PM PDT 24 Aug 14 04:36:48 PM PDT 24 88301143 ps
T798 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1485599088 Aug 14 04:36:34 PM PDT 24 Aug 14 04:36:35 PM PDT 24 160837191 ps
T799 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.4065227813 Aug 14 04:36:57 PM PDT 24 Aug 14 04:36:58 PM PDT 24 44371314 ps
T800 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2330382548 Aug 14 04:36:51 PM PDT 24 Aug 14 04:36:51 PM PDT 24 16885973 ps
T801 /workspace/coverage/cover_reg_top/8.gpio_intr_test.990151632 Aug 14 04:36:44 PM PDT 24 Aug 14 04:36:45 PM PDT 24 63784169 ps
T802 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3292184247 Aug 14 04:36:50 PM PDT 24 Aug 14 04:36:51 PM PDT 24 36796178 ps
T803 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3763833008 Aug 14 04:36:58 PM PDT 24 Aug 14 04:36:59 PM PDT 24 34022442 ps
T804 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.549722949 Aug 14 04:36:54 PM PDT 24 Aug 14 04:36:57 PM PDT 24 253336666 ps
T805 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.551055532 Aug 14 04:36:42 PM PDT 24 Aug 14 04:36:43 PM PDT 24 516010161 ps
T806 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3873349437 Aug 14 04:37:07 PM PDT 24 Aug 14 04:37:08 PM PDT 24 41109544 ps
T807 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4098982858 Aug 14 04:36:53 PM PDT 24 Aug 14 04:36:54 PM PDT 24 102975398 ps
T808 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3605266436 Aug 14 04:36:47 PM PDT 24 Aug 14 04:36:48 PM PDT 24 29445787 ps
T809 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2376602413 Aug 14 04:36:49 PM PDT 24 Aug 14 04:36:50 PM PDT 24 15607562 ps
T810 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2083129875 Aug 14 04:36:43 PM PDT 24 Aug 14 04:36:43 PM PDT 24 14921220 ps
T811 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.61599719 Aug 14 04:37:00 PM PDT 24 Aug 14 04:37:02 PM PDT 24 68517587 ps
T812 /workspace/coverage/cover_reg_top/46.gpio_intr_test.689575436 Aug 14 04:36:56 PM PDT 24 Aug 14 04:36:57 PM PDT 24 25515580 ps
T813 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1171370895 Aug 14 04:36:39 PM PDT 24 Aug 14 04:36:40 PM PDT 24 16476699 ps
T814 /workspace/coverage/cover_reg_top/28.gpio_intr_test.2504464691 Aug 14 04:36:57 PM PDT 24 Aug 14 04:36:58 PM PDT 24 119383106 ps
T815 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2576592086 Aug 14 04:36:53 PM PDT 24 Aug 14 04:36:56 PM PDT 24 123023159 ps
T816 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3702657574 Aug 14 04:36:42 PM PDT 24 Aug 14 04:36:43 PM PDT 24 59837074 ps
T817 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1881917446 Aug 14 04:36:31 PM PDT 24 Aug 14 04:36:32 PM PDT 24 116196281 ps
T818 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3595260071 Aug 14 04:36:30 PM PDT 24 Aug 14 04:36:31 PM PDT 24 27507483 ps
T819 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.278580230 Aug 14 04:36:48 PM PDT 24 Aug 14 04:36:49 PM PDT 24 108535732 ps
T820 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.727750916 Aug 14 04:36:52 PM PDT 24 Aug 14 04:36:53 PM PDT 24 50108475 ps
T821 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3280441217 Aug 14 04:36:42 PM PDT 24 Aug 14 04:36:43 PM PDT 24 66302929 ps
T822 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3350201337 Aug 14 04:37:03 PM PDT 24 Aug 14 04:37:03 PM PDT 24 12426762 ps
T823 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1337007619 Aug 14 04:36:38 PM PDT 24 Aug 14 04:36:40 PM PDT 24 311764687 ps
T83 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.566602504 Aug 14 04:36:31 PM PDT 24 Aug 14 04:36:32 PM PDT 24 105995348 ps
T824 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3464707103 Aug 14 04:36:30 PM PDT 24 Aug 14 04:36:31 PM PDT 24 37648476 ps
T84 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1134129325 Aug 14 04:36:36 PM PDT 24 Aug 14 04:36:36 PM PDT 24 13977281 ps
T825 /workspace/coverage/cover_reg_top/16.gpio_intr_test.159643683 Aug 14 04:36:47 PM PDT 24 Aug 14 04:36:48 PM PDT 24 57398297 ps
T826 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2603368088 Aug 14 04:36:41 PM PDT 24 Aug 14 04:36:43 PM PDT 24 185788062 ps
T827 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3182816501 Aug 14 04:36:42 PM PDT 24 Aug 14 04:36:43 PM PDT 24 16217252 ps
T828 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1702919567 Aug 14 04:37:00 PM PDT 24 Aug 14 04:37:01 PM PDT 24 11772127 ps
T829 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2688696247 Aug 14 04:36:54 PM PDT 24 Aug 14 04:36:55 PM PDT 24 17912045 ps
T830 /workspace/coverage/cover_reg_top/4.gpio_intr_test.4087586114 Aug 14 04:36:35 PM PDT 24 Aug 14 04:36:36 PM PDT 24 116801092 ps
T831 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2204787083 Aug 14 04:36:48 PM PDT 24 Aug 14 04:36:49 PM PDT 24 24898787 ps
T832 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2511709842 Aug 14 04:36:52 PM PDT 24 Aug 14 04:36:53 PM PDT 24 40396671 ps
T833 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.4029319731 Aug 14 04:36:44 PM PDT 24 Aug 14 04:36:44 PM PDT 24 33844346 ps
T834 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3664447482 Aug 14 04:36:55 PM PDT 24 Aug 14 04:36:56 PM PDT 24 17750068 ps
T835 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.435586750 Aug 14 04:36:40 PM PDT 24 Aug 14 04:36:42 PM PDT 24 87051464 ps
T836 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1347160200 Aug 14 04:36:44 PM PDT 24 Aug 14 04:36:45 PM PDT 24 141944203 ps
T837 /workspace/coverage/cover_reg_top/9.gpio_intr_test.966896946 Aug 14 04:36:39 PM PDT 24 Aug 14 04:36:40 PM PDT 24 16288466 ps
T838 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.680937568 Aug 14 04:36:58 PM PDT 24 Aug 14 04:36:59 PM PDT 24 12831002 ps
T86 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.700628416 Aug 14 04:36:57 PM PDT 24 Aug 14 04:36:58 PM PDT 24 32036388 ps
T839 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3580985753 Aug 14 04:27:34 PM PDT 24 Aug 14 04:27:35 PM PDT 24 165819150 ps
T840 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2091905452 Aug 14 04:27:32 PM PDT 24 Aug 14 04:27:33 PM PDT 24 170594032 ps
T841 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4165752006 Aug 14 04:27:35 PM PDT 24 Aug 14 04:27:36 PM PDT 24 135761440 ps
T842 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.4178857686 Aug 14 04:27:24 PM PDT 24 Aug 14 04:27:25 PM PDT 24 228761016 ps
T843 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3949876183 Aug 14 04:27:40 PM PDT 24 Aug 14 04:27:42 PM PDT 24 285345060 ps
T844 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1239421692 Aug 14 04:27:34 PM PDT 24 Aug 14 04:27:34 PM PDT 24 78031219 ps
T845 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.685202858 Aug 14 04:27:39 PM PDT 24 Aug 14 04:27:40 PM PDT 24 300231629 ps
T846 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1943866770 Aug 14 04:27:22 PM PDT 24 Aug 14 04:27:24 PM PDT 24 105541552 ps
T847 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.240759556 Aug 14 04:27:37 PM PDT 24 Aug 14 04:27:38 PM PDT 24 271759653 ps
T848 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.896201185 Aug 14 04:27:43 PM PDT 24 Aug 14 04:27:45 PM PDT 24 47348200 ps
T849 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.531215241 Aug 14 04:27:45 PM PDT 24 Aug 14 04:27:46 PM PDT 24 86287608 ps
T850 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.370784570 Aug 14 04:27:50 PM PDT 24 Aug 14 04:27:51 PM PDT 24 69435747 ps
T851 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3172139088 Aug 14 04:27:22 PM PDT 24 Aug 14 04:27:24 PM PDT 24 377725491 ps
T852 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3145904859 Aug 14 04:27:28 PM PDT 24 Aug 14 04:27:34 PM PDT 24 137005113 ps
T853 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4294896484 Aug 14 04:27:45 PM PDT 24 Aug 14 04:27:46 PM PDT 24 51670381 ps
T854 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.934918551 Aug 14 04:28:37 PM PDT 24 Aug 14 04:28:38 PM PDT 24 130245944 ps
T855 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.26660748 Aug 14 04:27:37 PM PDT 24 Aug 14 04:27:38 PM PDT 24 170626823 ps
T856 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4177228531 Aug 14 04:27:27 PM PDT 24 Aug 14 04:27:28 PM PDT 24 55667390 ps
T857 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1678578733 Aug 14 04:28:01 PM PDT 24 Aug 14 04:28:02 PM PDT 24 278774454 ps
T858 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4198143198 Aug 14 04:27:22 PM PDT 24 Aug 14 04:27:23 PM PDT 24 69826044 ps
T859 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.843446663 Aug 14 04:27:29 PM PDT 24 Aug 14 04:27:30 PM PDT 24 131214167 ps
T860 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3235005038 Aug 14 04:27:27 PM PDT 24 Aug 14 04:27:28 PM PDT 24 56067091 ps
T861 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2916472741 Aug 14 04:27:48 PM PDT 24 Aug 14 04:27:49 PM PDT 24 84379603 ps
T862 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.133171745 Aug 14 04:27:30 PM PDT 24 Aug 14 04:27:31 PM PDT 24 35579802 ps
T863 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.380842950 Aug 14 04:27:27 PM PDT 24 Aug 14 04:27:29 PM PDT 24 112914211 ps
T864 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3752993293 Aug 14 04:27:54 PM PDT 24 Aug 14 04:27:55 PM PDT 24 34048764 ps
T865 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2555501686 Aug 14 04:27:37 PM PDT 24 Aug 14 04:27:39 PM PDT 24 287630682 ps
T866 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3950133006 Aug 14 04:27:36 PM PDT 24 Aug 14 04:27:37 PM PDT 24 93051934 ps
T867 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4170879214 Aug 14 04:27:42 PM PDT 24 Aug 14 04:27:44 PM PDT 24 49183440 ps
T868 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1811136128 Aug 14 04:27:54 PM PDT 24 Aug 14 04:27:56 PM PDT 24 289054413 ps
T869 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2874768551 Aug 14 04:27:56 PM PDT 24 Aug 14 04:27:58 PM PDT 24 258981987 ps
T870 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2099551134 Aug 14 04:27:29 PM PDT 24 Aug 14 04:27:30 PM PDT 24 64395588 ps
T871 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2303083184 Aug 14 04:27:56 PM PDT 24 Aug 14 04:27:57 PM PDT 24 67345877 ps
T872 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.517123899 Aug 14 04:27:40 PM PDT 24 Aug 14 04:27:42 PM PDT 24 180896081 ps
T873 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2757140653 Aug 14 04:27:34 PM PDT 24 Aug 14 04:27:41 PM PDT 24 93931964 ps
T874 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2998267501 Aug 14 04:27:31 PM PDT 24 Aug 14 04:27:33 PM PDT 24 101002415 ps
T875 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2698513926 Aug 14 04:28:01 PM PDT 24 Aug 14 04:28:02 PM PDT 24 47118016 ps
T876 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3605597935 Aug 14 04:27:39 PM PDT 24 Aug 14 04:27:40 PM PDT 24 100929838 ps
T877 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.280650135 Aug 14 04:27:34 PM PDT 24 Aug 14 04:27:35 PM PDT 24 152004110 ps
T878 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.104502133 Aug 14 04:27:34 PM PDT 24 Aug 14 04:27:36 PM PDT 24 128967786 ps
T879 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4258504615 Aug 14 04:27:37 PM PDT 24 Aug 14 04:27:38 PM PDT 24 87511557 ps
T880 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.279622311 Aug 14 04:27:37 PM PDT 24 Aug 14 04:27:38 PM PDT 24 174375174 ps
T881 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3299305510 Aug 14 04:27:48 PM PDT 24 Aug 14 04:27:50 PM PDT 24 57172547 ps
T882 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1560193002 Aug 14 04:27:41 PM PDT 24 Aug 14 04:27:42 PM PDT 24 123878408 ps
T883 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3468108739 Aug 14 04:27:41 PM PDT 24 Aug 14 04:27:42 PM PDT 24 33161533 ps
T884 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4060897745 Aug 14 04:27:48 PM PDT 24 Aug 14 04:27:49 PM PDT 24 26146931 ps
T885 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1647753263 Aug 14 04:27:48 PM PDT 24 Aug 14 04:27:50 PM PDT 24 219049462 ps
T886 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2466037851 Aug 14 04:27:41 PM PDT 24 Aug 14 04:27:43 PM PDT 24 48510767 ps
T887 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1573030385 Aug 14 04:27:38 PM PDT 24 Aug 14 04:27:39 PM PDT 24 63447034 ps
T888 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2417146789 Aug 14 04:27:31 PM PDT 24 Aug 14 04:27:32 PM PDT 24 311411900 ps
T889 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.113661602 Aug 14 04:27:41 PM PDT 24 Aug 14 04:27:42 PM PDT 24 77592837 ps
T890 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2758819588 Aug 14 04:27:55 PM PDT 24 Aug 14 04:27:56 PM PDT 24 106817261 ps
T891 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.726453018 Aug 14 04:27:26 PM PDT 24 Aug 14 04:27:28 PM PDT 24 310086354 ps
T892 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1156188371 Aug 14 04:27:41 PM PDT 24 Aug 14 04:27:42 PM PDT 24 64873823 ps
T893 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.323598944 Aug 14 04:27:54 PM PDT 24 Aug 14 04:27:56 PM PDT 24 85061071 ps
T894 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.657378298 Aug 14 04:27:46 PM PDT 24 Aug 14 04:27:47 PM PDT 24 43510730 ps
T895 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4265351777 Aug 14 04:27:31 PM PDT 24 Aug 14 04:27:32 PM PDT 24 54968313 ps
T896 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.76920282 Aug 14 04:27:21 PM PDT 24 Aug 14 04:27:22 PM PDT 24 71143794 ps
T897 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2088839837 Aug 14 04:27:48 PM PDT 24 Aug 14 04:27:49 PM PDT 24 78222032 ps
T898 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3698711313 Aug 14 04:27:47 PM PDT 24 Aug 14 04:27:49 PM PDT 24 232251995 ps
T899 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4067694328 Aug 14 04:27:35 PM PDT 24 Aug 14 04:27:36 PM PDT 24 80394214 ps
T900 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4032084201 Aug 14 04:27:34 PM PDT 24 Aug 14 04:27:35 PM PDT 24 188111364 ps
T901 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1571155069 Aug 14 04:27:31 PM PDT 24 Aug 14 04:27:32 PM PDT 24 57034844 ps
T902 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2926530703 Aug 14 04:27:25 PM PDT 24 Aug 14 04:27:26 PM PDT 24 46779964 ps
T903 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3732926679 Aug 14 04:27:22 PM PDT 24 Aug 14 04:27:23 PM PDT 24 81562451 ps
T904 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2615582860 Aug 14 04:27:50 PM PDT 24 Aug 14 04:27:52 PM PDT 24 226614770 ps
T905 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2208587178 Aug 14 04:27:41 PM PDT 24 Aug 14 04:27:42 PM PDT 24 208513819 ps
T906 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3007071778 Aug 14 04:27:59 PM PDT 24 Aug 14 04:28:01 PM PDT 24 337768020 ps
T907 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3645988154 Aug 14 04:27:22 PM PDT 24 Aug 14 04:27:24 PM PDT 24 241360388 ps
T908 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1839008258 Aug 14 04:27:46 PM PDT 24 Aug 14 04:27:48 PM PDT 24 765183566 ps
T909 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3498505214 Aug 14 04:27:38 PM PDT 24 Aug 14 04:27:39 PM PDT 24 375730408 ps
T910 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1436814067 Aug 14 04:27:27 PM PDT 24 Aug 14 04:27:28 PM PDT 24 135909706 ps
T911 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1356041506 Aug 14 04:27:49 PM PDT 24 Aug 14 04:27:50 PM PDT 24 23076264 ps
T912 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.879250534 Aug 14 04:27:36 PM PDT 24 Aug 14 04:27:37 PM PDT 24 141467536 ps
T913 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1987171833 Aug 14 04:27:19 PM PDT 24 Aug 14 04:27:20 PM PDT 24 37128791 ps
T914 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3524689838 Aug 14 04:27:41 PM PDT 24 Aug 14 04:27:43 PM PDT 24 324923472 ps
T915 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3083162468 Aug 14 04:27:53 PM PDT 24 Aug 14 04:27:54 PM PDT 24 362036415 ps
T916 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.743541256 Aug 14 04:27:42 PM PDT 24 Aug 14 04:27:43 PM PDT 24 47066336 ps
T917 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2227389372 Aug 14 04:27:44 PM PDT 24 Aug 14 04:27:45 PM PDT 24 136003748 ps
T918 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1903122316 Aug 14 04:27:32 PM PDT 24 Aug 14 04:27:33 PM PDT 24 155502952 ps
T919 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1240338705 Aug 14 04:27:34 PM PDT 24 Aug 14 04:27:36 PM PDT 24 230935352 ps
T920 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2617372719 Aug 14 04:27:51 PM PDT 24 Aug 14 04:27:53 PM PDT 24 103070481 ps
T921 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2369498016 Aug 14 04:27:41 PM PDT 24 Aug 14 04:27:42 PM PDT 24 157810146 ps
T922 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1958401213 Aug 14 04:27:34 PM PDT 24 Aug 14 04:27:36 PM PDT 24 103868452 ps
T923 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.641830400 Aug 14 04:27:32 PM PDT 24 Aug 14 04:27:34 PM PDT 24 133680366 ps
T924 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3501564203 Aug 14 04:27:37 PM PDT 24 Aug 14 04:27:38 PM PDT 24 24258789 ps
T925 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3783258754 Aug 14 04:27:47 PM PDT 24 Aug 14 04:27:49 PM PDT 24 186534494 ps
T926 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2756977218 Aug 14 04:27:41 PM PDT 24 Aug 14 04:27:43 PM PDT 24 184851045 ps
T927 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1307576534 Aug 14 04:27:36 PM PDT 24 Aug 14 04:27:37 PM PDT 24 197399950 ps
T928 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2719768983 Aug 14 04:28:00 PM PDT 24 Aug 14 04:28:01 PM PDT 24 34793880 ps
T929 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2066988184 Aug 14 04:27:44 PM PDT 24 Aug 14 04:27:45 PM PDT 24 404491244 ps
T930 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3390603729 Aug 14 04:28:34 PM PDT 24 Aug 14 04:28:36 PM PDT 24 210251730 ps
T931 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1272448626 Aug 14 04:27:38 PM PDT 24 Aug 14 04:27:39 PM PDT 24 263194574 ps
T932 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3303838605 Aug 14 04:27:32 PM PDT 24 Aug 14 04:27:33 PM PDT 24 69197118 ps
T933 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3684793584 Aug 14 04:27:33 PM PDT 24 Aug 14 04:27:34 PM PDT 24 51049180 ps
T934 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3639348758 Aug 14 04:27:31 PM PDT 24 Aug 14 04:27:32 PM PDT 24 36750026 ps
T935 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.829578388 Aug 14 04:27:32 PM PDT 24 Aug 14 04:27:33 PM PDT 24 85125444 ps
T936 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1767364085 Aug 14 04:27:32 PM PDT 24 Aug 14 04:27:33 PM PDT 24 259675469 ps
T937 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.916775920 Aug 14 04:27:36 PM PDT 24 Aug 14 04:27:37 PM PDT 24 135435253 ps
T938 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.565997835 Aug 14 04:27:36 PM PDT 24 Aug 14 04:27:37 PM PDT 24 123234907 ps

Test location /workspace/coverage/default/27.gpio_full_random.2226587053
Short name T27
Test name
Test status
Simulation time 67194053 ps
CPU time 0.94 seconds
Started Aug 14 04:44:23 PM PDT 24
Finished Aug 14 04:44:24 PM PDT 24
Peak memory 197840 kb
Host smart-463c4d66-27d7-45e5-a934-95939aea966b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226587053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2226587053
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1897849807
Short name T26
Test name
Test status
Simulation time 175393561 ps
CPU time 3.26 seconds
Started Aug 14 04:44:34 PM PDT 24
Finished Aug 14 04:44:38 PM PDT 24
Peak memory 198196 kb
Host smart-a316da41-7ad1-4c1c-9fc5-6154b756dd8f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897849807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1897849807
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3679556339
Short name T1
Test name
Test status
Simulation time 85478374422 ps
CPU time 68.57 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:46:13 PM PDT 24
Peak memory 206760 kb
Host smart-d889d1e5-80f2-44a5-a035-46ec4bf38ba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3679556339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3679556339
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1413709875
Short name T36
Test name
Test status
Simulation time 237877741 ps
CPU time 0.89 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 213976 kb
Host smart-8928b372-08dd-4584-9688-9a1dadd4eaa1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413709875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1413709875
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2495976013
Short name T72
Test name
Test status
Simulation time 15358916 ps
CPU time 0.59 seconds
Started Aug 14 04:36:30 PM PDT 24
Finished Aug 14 04:36:31 PM PDT 24
Peak memory 195264 kb
Host smart-da6a37c7-296d-4463-bb7b-60d2a41fb93a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495976013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2495976013
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.263635045
Short name T35
Test name
Test status
Simulation time 274723187 ps
CPU time 1.38 seconds
Started Aug 14 04:36:54 PM PDT 24
Finished Aug 14 04:36:55 PM PDT 24
Peak memory 198468 kb
Host smart-93fe9ffe-e576-45a5-99d1-30b7e81ee8e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263635045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.263635045
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2673214357
Short name T103
Test name
Test status
Simulation time 50405255 ps
CPU time 1.33 seconds
Started Aug 14 04:43:58 PM PDT 24
Finished Aug 14 04:44:00 PM PDT 24
Peak memory 198196 kb
Host smart-a87c39f3-6b25-4a4d-981e-5277fb197f27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673214357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2673214357
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1576974710
Short name T42
Test name
Test status
Simulation time 21146159 ps
CPU time 0.54 seconds
Started Aug 14 04:43:42 PM PDT 24
Finished Aug 14 04:43:43 PM PDT 24
Peak memory 193912 kb
Host smart-aa200913-5083-4373-a39a-6d1f0bd80ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576974710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1576974710
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3259090202
Short name T88
Test name
Test status
Simulation time 16833790 ps
CPU time 0.64 seconds
Started Aug 14 04:36:36 PM PDT 24
Finished Aug 14 04:36:37 PM PDT 24
Peak memory 195088 kb
Host smart-1bf994f1-fe11-4d3e-ad42-9c4610bc32fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259090202 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3259090202
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3842176299
Short name T96
Test name
Test status
Simulation time 44584250 ps
CPU time 0.86 seconds
Started Aug 14 04:36:47 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 197720 kb
Host smart-6c5b60c9-a947-4d24-8444-1058206cbb27
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842176299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3842176299
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2759754321
Short name T49
Test name
Test status
Simulation time 307439076 ps
CPU time 1.08 seconds
Started Aug 14 04:36:36 PM PDT 24
Finished Aug 14 04:36:37 PM PDT 24
Peak memory 198532 kb
Host smart-9368c787-db15-4ae2-ac9f-91dddfebb125
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759754321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2759754321
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.64731520
Short name T95
Test name
Test status
Simulation time 122402742 ps
CPU time 1.1 seconds
Started Aug 14 04:36:43 PM PDT 24
Finished Aug 14 04:36:45 PM PDT 24
Peak memory 198496 kb
Host smart-3158881c-7f15-4227-abee-998e1b13b514
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64731520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_tl_intg_err.64731520
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.566602504
Short name T83
Test name
Test status
Simulation time 105995348 ps
CPU time 0.83 seconds
Started Aug 14 04:36:31 PM PDT 24
Finished Aug 14 04:36:32 PM PDT 24
Peak memory 196452 kb
Host smart-9e1529af-388a-4ec4-8bb4-70611be2025f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566602504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.566602504
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3130825858
Short name T732
Test name
Test status
Simulation time 220340335 ps
CPU time 1.59 seconds
Started Aug 14 04:36:40 PM PDT 24
Finished Aug 14 04:36:42 PM PDT 24
Peak memory 198468 kb
Host smart-ecc73f31-b749-4401-829e-047b1051b699
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130825858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3130825858
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.729168196
Short name T754
Test name
Test status
Simulation time 27651012 ps
CPU time 0.61 seconds
Started Aug 14 04:36:42 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 194864 kb
Host smart-7969e39a-98fc-46e0-b59f-2d87d0d30066
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729168196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.729168196
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1881917446
Short name T817
Test name
Test status
Simulation time 116196281 ps
CPU time 1.38 seconds
Started Aug 14 04:36:31 PM PDT 24
Finished Aug 14 04:36:32 PM PDT 24
Peak memory 198568 kb
Host smart-4d5c3671-cc60-4394-b612-a8c6a3bdfd5c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881917446 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1881917446
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.4029319731
Short name T833
Test name
Test status
Simulation time 33844346 ps
CPU time 0.62 seconds
Started Aug 14 04:36:44 PM PDT 24
Finished Aug 14 04:36:44 PM PDT 24
Peak memory 195996 kb
Host smart-fc57d104-e89b-45ae-827c-43b2fdc4cda2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029319731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.4029319731
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2328469501
Short name T723
Test name
Test status
Simulation time 20449942 ps
CPU time 0.55 seconds
Started Aug 14 04:36:33 PM PDT 24
Finished Aug 14 04:36:34 PM PDT 24
Peak memory 194204 kb
Host smart-ba6f0bbc-2654-4813-a2da-a0f55e6b4bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328469501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2328469501
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.324769996
Short name T781
Test name
Test status
Simulation time 47210162 ps
CPU time 1.13 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:47 PM PDT 24
Peak memory 198552 kb
Host smart-ba78407f-849e-4fca-ba69-7cc56de19f29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324769996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.324769996
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1484613975
Short name T94
Test name
Test status
Simulation time 46700124 ps
CPU time 0.72 seconds
Started Aug 14 04:37:44 PM PDT 24
Finished Aug 14 04:37:44 PM PDT 24
Peak memory 196804 kb
Host smart-a5488360-12e2-446f-ade0-a5973e51acff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484613975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1484613975
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2041747189
Short name T742
Test name
Test status
Simulation time 597761012 ps
CPU time 1.52 seconds
Started Aug 14 04:36:29 PM PDT 24
Finished Aug 14 04:36:30 PM PDT 24
Peak memory 196832 kb
Host smart-540551e3-b53b-4d7e-8cb9-96bb0e4e5096
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041747189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2041747189
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3853564425
Short name T70
Test name
Test status
Simulation time 44653012 ps
CPU time 0.61 seconds
Started Aug 14 04:36:41 PM PDT 24
Finished Aug 14 04:36:42 PM PDT 24
Peak memory 194872 kb
Host smart-62bb2c9e-39d0-4907-b94c-01e0e2f24e82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853564425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3853564425
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3464707103
Short name T824
Test name
Test status
Simulation time 37648476 ps
CPU time 1 seconds
Started Aug 14 04:36:30 PM PDT 24
Finished Aug 14 04:36:31 PM PDT 24
Peak memory 198316 kb
Host smart-c4bd3f89-5be6-4e6f-ad26-45e168563b30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464707103 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3464707103
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.4242859631
Short name T733
Test name
Test status
Simulation time 38707542 ps
CPU time 0.58 seconds
Started Aug 14 04:36:39 PM PDT 24
Finished Aug 14 04:36:40 PM PDT 24
Peak memory 194788 kb
Host smart-a871fe21-c109-4364-bf65-76a4d625a89a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242859631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.4242859631
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3381045841
Short name T89
Test name
Test status
Simulation time 13320444 ps
CPU time 0.63 seconds
Started Aug 14 04:36:51 PM PDT 24
Finished Aug 14 04:36:52 PM PDT 24
Peak memory 194796 kb
Host smart-4d5bf01e-360a-48ae-b05f-5a97ace6cf2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381045841 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3381045841
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.158350911
Short name T737
Test name
Test status
Simulation time 573146043 ps
CPU time 3.1 seconds
Started Aug 14 04:36:22 PM PDT 24
Finished Aug 14 04:36:25 PM PDT 24
Peak memory 198612 kb
Host smart-2b96e2b4-e158-47c3-a150-81c4a7f169ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158350911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.158350911
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1637543028
Short name T743
Test name
Test status
Simulation time 128167672 ps
CPU time 1.17 seconds
Started Aug 14 04:36:22 PM PDT 24
Finished Aug 14 04:36:23 PM PDT 24
Peak memory 198492 kb
Host smart-6a2131e1-c35e-49fd-98ce-f902117d6890
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637543028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1637543028
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1630891718
Short name T716
Test name
Test status
Simulation time 34538499 ps
CPU time 0.97 seconds
Started Aug 14 04:36:53 PM PDT 24
Finished Aug 14 04:36:54 PM PDT 24
Peak memory 198344 kb
Host smart-db80a6b1-f646-4554-895d-144b536baaa2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630891718 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1630891718
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2511709842
Short name T832
Test name
Test status
Simulation time 40396671 ps
CPU time 0.6 seconds
Started Aug 14 04:36:52 PM PDT 24
Finished Aug 14 04:36:53 PM PDT 24
Peak memory 195024 kb
Host smart-a68113b2-af11-4f76-84f3-676075410280
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511709842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2511709842
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.185585670
Short name T795
Test name
Test status
Simulation time 30385982 ps
CPU time 0.61 seconds
Started Aug 14 04:37:03 PM PDT 24
Finished Aug 14 04:37:04 PM PDT 24
Peak memory 194260 kb
Host smart-ce913fb9-1edd-4f27-b154-afd348de46d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185585670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.185585670
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3639277862
Short name T75
Test name
Test status
Simulation time 74885335 ps
CPU time 0.87 seconds
Started Aug 14 04:36:44 PM PDT 24
Finished Aug 14 04:36:45 PM PDT 24
Peak memory 197412 kb
Host smart-09f4a52a-efed-4821-a9cd-416d6a47117c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639277862 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3639277862
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2501006710
Short name T765
Test name
Test status
Simulation time 365029444 ps
CPU time 2.01 seconds
Started Aug 14 04:36:37 PM PDT 24
Finished Aug 14 04:36:39 PM PDT 24
Peak memory 198500 kb
Host smart-8e436a06-0ea6-4666-b753-e2e53189d696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501006710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2501006710
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2579512037
Short name T34
Test name
Test status
Simulation time 74141603 ps
CPU time 0.85 seconds
Started Aug 14 04:36:53 PM PDT 24
Finished Aug 14 04:36:54 PM PDT 24
Peak memory 197664 kb
Host smart-af4879cd-b8e9-49b7-aaab-fa231bf97ddb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579512037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2579512037
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4098982858
Short name T807
Test name
Test status
Simulation time 102975398 ps
CPU time 0.81 seconds
Started Aug 14 04:36:53 PM PDT 24
Finished Aug 14 04:36:54 PM PDT 24
Peak memory 198404 kb
Host smart-548b3320-d052-42b5-9bc3-9e6efcab6f8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098982858 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.4098982858
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.4065227813
Short name T799
Test name
Test status
Simulation time 44371314 ps
CPU time 0.61 seconds
Started Aug 14 04:36:57 PM PDT 24
Finished Aug 14 04:36:58 PM PDT 24
Peak memory 195308 kb
Host smart-265529e3-6baa-4278-bf53-98d4f94fd94b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065227813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.4065227813
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2911816398
Short name T713
Test name
Test status
Simulation time 13445458 ps
CPU time 0.61 seconds
Started Aug 14 04:36:51 PM PDT 24
Finished Aug 14 04:36:52 PM PDT 24
Peak memory 194196 kb
Host smart-e38cf3b5-c31e-4b01-bb7c-0f6660c459f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911816398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2911816398
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4179404146
Short name T71
Test name
Test status
Simulation time 30063604 ps
CPU time 0.76 seconds
Started Aug 14 04:36:50 PM PDT 24
Finished Aug 14 04:36:51 PM PDT 24
Peak memory 196544 kb
Host smart-5a58673f-499d-41be-a27a-c42ce9f8cc08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179404146 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.4179404146
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.524902783
Short name T736
Test name
Test status
Simulation time 45595570 ps
CPU time 2.39 seconds
Started Aug 14 04:36:37 PM PDT 24
Finished Aug 14 04:36:39 PM PDT 24
Peak memory 198488 kb
Host smart-63d229ce-4003-41ed-83a3-b7cf6d19814f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524902783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.524902783
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.551055532
Short name T805
Test name
Test status
Simulation time 516010161 ps
CPU time 1.44 seconds
Started Aug 14 04:36:42 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 198548 kb
Host smart-1e1182c8-cf0a-4194-b081-4eb2f85b3096
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551055532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.551055532
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3605266436
Short name T808
Test name
Test status
Simulation time 29445787 ps
CPU time 1.12 seconds
Started Aug 14 04:36:47 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 198572 kb
Host smart-e4be274b-49dd-406e-b928-5cfe6e55fe45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605266436 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3605266436
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1652018330
Short name T76
Test name
Test status
Simulation time 29175055 ps
CPU time 0.56 seconds
Started Aug 14 04:36:55 PM PDT 24
Finished Aug 14 04:36:56 PM PDT 24
Peak memory 193720 kb
Host smart-a3aa71a2-0442-44e8-9d89-b82461b4a0f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652018330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1652018330
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3763833008
Short name T803
Test name
Test status
Simulation time 34022442 ps
CPU time 0.55 seconds
Started Aug 14 04:36:58 PM PDT 24
Finished Aug 14 04:36:59 PM PDT 24
Peak memory 194196 kb
Host smart-6b2d0ff4-6f23-4dfa-85b6-4e519c8a3625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763833008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3763833008
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3280441217
Short name T821
Test name
Test status
Simulation time 66302929 ps
CPU time 0.79 seconds
Started Aug 14 04:36:42 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 196284 kb
Host smart-b1be1aa5-0d9f-46c7-8f3f-9f82781eabe7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280441217 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3280441217
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1923751633
Short name T722
Test name
Test status
Simulation time 25631812 ps
CPU time 1.29 seconds
Started Aug 14 04:36:50 PM PDT 24
Finished Aug 14 04:36:51 PM PDT 24
Peak memory 198592 kb
Host smart-46635274-8933-4ad3-9b27-7fe8399a88b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923751633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1923751633
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.33266203
Short name T756
Test name
Test status
Simulation time 112942976 ps
CPU time 0.85 seconds
Started Aug 14 04:36:51 PM PDT 24
Finished Aug 14 04:36:52 PM PDT 24
Peak memory 198260 kb
Host smart-ed57a41e-c897-42e8-ae70-2a04aef151e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33266203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.gpio_tl_intg_err.33266203
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1066722602
Short name T772
Test name
Test status
Simulation time 20554071 ps
CPU time 0.92 seconds
Started Aug 14 04:36:43 PM PDT 24
Finished Aug 14 04:36:44 PM PDT 24
Peak memory 198368 kb
Host smart-1d08d6ee-1914-408a-8d88-f0a4158a616e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066722602 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1066722602
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3903139806
Short name T753
Test name
Test status
Simulation time 10912135 ps
CPU time 0.55 seconds
Started Aug 14 04:36:50 PM PDT 24
Finished Aug 14 04:36:51 PM PDT 24
Peak memory 195708 kb
Host smart-edc54031-2a80-40d6-ae72-2110d2c1204e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903139806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3903139806
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3684509365
Short name T761
Test name
Test status
Simulation time 15416760 ps
CPU time 0.58 seconds
Started Aug 14 04:36:53 PM PDT 24
Finished Aug 14 04:36:54 PM PDT 24
Peak memory 194188 kb
Host smart-6f36f453-bb76-4806-8a90-2a362e32f559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684509365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3684509365
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.802800610
Short name T748
Test name
Test status
Simulation time 165190478 ps
CPU time 0.71 seconds
Started Aug 14 04:36:54 PM PDT 24
Finished Aug 14 04:36:55 PM PDT 24
Peak memory 196612 kb
Host smart-64e45a7c-7958-48c6-8087-4b0faec01e16
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802800610 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.802800610
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.49549216
Short name T752
Test name
Test status
Simulation time 61594933 ps
CPU time 1.62 seconds
Started Aug 14 04:36:50 PM PDT 24
Finished Aug 14 04:36:51 PM PDT 24
Peak memory 198568 kb
Host smart-a0fbc81f-8390-4938-9e39-dc9d5c22834e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49549216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.49549216
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1198872757
Short name T33
Test name
Test status
Simulation time 125822352 ps
CPU time 0.85 seconds
Started Aug 14 04:37:00 PM PDT 24
Finished Aug 14 04:37:01 PM PDT 24
Peak memory 197284 kb
Host smart-9dc0c5db-9d4f-4a3d-92d7-4f1739459bd2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198872757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1198872757
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1944711197
Short name T750
Test name
Test status
Simulation time 34664991 ps
CPU time 0.66 seconds
Started Aug 14 04:36:51 PM PDT 24
Finished Aug 14 04:36:52 PM PDT 24
Peak memory 197976 kb
Host smart-4bdca919-7224-47fc-aacd-9f3ebb5d0007
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944711197 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1944711197
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1192545590
Short name T93
Test name
Test status
Simulation time 13790690 ps
CPU time 0.61 seconds
Started Aug 14 04:36:49 PM PDT 24
Finished Aug 14 04:36:50 PM PDT 24
Peak memory 195672 kb
Host smart-3d6a136b-e943-41e0-a794-d2799fdaffbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192545590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1192545590
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.473761350
Short name T714
Test name
Test status
Simulation time 21646755 ps
CPU time 0.58 seconds
Started Aug 14 04:36:50 PM PDT 24
Finished Aug 14 04:36:50 PM PDT 24
Peak memory 194904 kb
Host smart-387997bc-462e-4a95-95b5-00d55842369b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473761350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.473761350
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3654352438
Short name T90
Test name
Test status
Simulation time 44463589 ps
CPU time 0.79 seconds
Started Aug 14 04:36:54 PM PDT 24
Finished Aug 14 04:36:55 PM PDT 24
Peak memory 196716 kb
Host smart-86afafd9-a048-43f5-8e95-259e92e57990
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654352438 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3654352438
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3726869608
Short name T763
Test name
Test status
Simulation time 326696269 ps
CPU time 2.46 seconds
Started Aug 14 04:36:53 PM PDT 24
Finished Aug 14 04:36:56 PM PDT 24
Peak memory 198508 kb
Host smart-67ef95fd-635f-43b5-a4c0-95ceec6566aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726869608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3726869608
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.82226371
Short name T731
Test name
Test status
Simulation time 150671159 ps
CPU time 0.85 seconds
Started Aug 14 04:36:33 PM PDT 24
Finished Aug 14 04:36:34 PM PDT 24
Peak memory 198312 kb
Host smart-c344998b-49f4-4739-965e-9db389c18072
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82226371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.gpio_tl_intg_err.82226371
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.453458232
Short name T779
Test name
Test status
Simulation time 44912827 ps
CPU time 0.77 seconds
Started Aug 14 04:36:50 PM PDT 24
Finished Aug 14 04:36:51 PM PDT 24
Peak memory 198396 kb
Host smart-f43d8a28-c24e-417b-bef2-44990318cb0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453458232 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.453458232
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2811182545
Short name T796
Test name
Test status
Simulation time 37630717 ps
CPU time 0.59 seconds
Started Aug 14 04:36:52 PM PDT 24
Finished Aug 14 04:36:52 PM PDT 24
Peak memory 195340 kb
Host smart-46174dab-5f21-49e3-9bb4-8c217b52818c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811182545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2811182545
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2913443017
Short name T768
Test name
Test status
Simulation time 42689793 ps
CPU time 0.57 seconds
Started Aug 14 04:37:07 PM PDT 24
Finished Aug 14 04:37:07 PM PDT 24
Peak memory 194144 kb
Host smart-5df48e9b-93a7-4328-8727-ce213278dd7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913443017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2913443017
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1456894273
Short name T758
Test name
Test status
Simulation time 37653476 ps
CPU time 0.8 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:47 PM PDT 24
Peak memory 196484 kb
Host smart-92eb8a72-1b6c-4669-b2d8-9bfa2928ef4e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456894273 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1456894273
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.258903705
Short name T747
Test name
Test status
Simulation time 194349411 ps
CPU time 3.09 seconds
Started Aug 14 04:36:52 PM PDT 24
Finished Aug 14 04:36:56 PM PDT 24
Peak memory 198524 kb
Host smart-72c18bf6-7517-404a-945e-0b8a4f21660b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258903705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.258903705
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.854275140
Short name T48
Test name
Test status
Simulation time 274451905 ps
CPU time 1.1 seconds
Started Aug 14 04:36:44 PM PDT 24
Finished Aug 14 04:36:46 PM PDT 24
Peak memory 198524 kb
Host smart-4a66aca8-a7d2-46e7-946a-de1290be682e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854275140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.854275140
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3277059169
Short name T728
Test name
Test status
Simulation time 22932185 ps
CPU time 0.77 seconds
Started Aug 14 04:36:53 PM PDT 24
Finished Aug 14 04:36:54 PM PDT 24
Peak memory 198280 kb
Host smart-e1caafd7-52be-4889-a95d-b7a94078f8ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277059169 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3277059169
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3883630020
Short name T73
Test name
Test status
Simulation time 51848769 ps
CPU time 0.61 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:47 PM PDT 24
Peak memory 195468 kb
Host smart-f1790708-a6d8-48b8-bf60-6cd090ce6a1c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883630020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3883630020
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.159643683
Short name T825
Test name
Test status
Simulation time 57398297 ps
CPU time 0.61 seconds
Started Aug 14 04:36:47 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 194196 kb
Host smart-6b2ba43d-0581-400d-99c2-31ffa9f8049b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159643683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.159643683
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2754708407
Short name T790
Test name
Test status
Simulation time 19574901 ps
CPU time 0.8 seconds
Started Aug 14 04:37:00 PM PDT 24
Finished Aug 14 04:37:01 PM PDT 24
Peak memory 196464 kb
Host smart-7f594b5e-76ac-4da2-9508-be87f7c44a63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754708407 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2754708407
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1502313
Short name T797
Test name
Test status
Simulation time 88301143 ps
CPU time 1.97 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 198572 kb
Host smart-402f4309-4509-4aeb-8f12-0f4304fa0120
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1502313
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.278580230
Short name T819
Test name
Test status
Simulation time 108535732 ps
CPU time 1.29 seconds
Started Aug 14 04:36:48 PM PDT 24
Finished Aug 14 04:36:49 PM PDT 24
Peak memory 194372 kb
Host smart-24bf294f-6d54-4f55-9759-0464e9a40f30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278580230 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.278580230
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.63921006
Short name T79
Test name
Test status
Simulation time 191773789 ps
CPU time 0.62 seconds
Started Aug 14 04:36:51 PM PDT 24
Finished Aug 14 04:36:51 PM PDT 24
Peak memory 195220 kb
Host smart-c1b274e1-2996-41ad-8945-544d5c388aae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63921006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_
csr_rw.63921006
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3379466559
Short name T766
Test name
Test status
Simulation time 17820635 ps
CPU time 0.6 seconds
Started Aug 14 04:36:58 PM PDT 24
Finished Aug 14 04:36:58 PM PDT 24
Peak memory 194288 kb
Host smart-cd554b60-f3a9-442d-a940-a3348fb1357f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379466559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3379466559
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3664447482
Short name T834
Test name
Test status
Simulation time 17750068 ps
CPU time 0.73 seconds
Started Aug 14 04:36:55 PM PDT 24
Finished Aug 14 04:36:56 PM PDT 24
Peak memory 196860 kb
Host smart-23c4f2eb-2825-4944-9ef9-9c35054e7bb2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664447482 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3664447482
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.61599719
Short name T811
Test name
Test status
Simulation time 68517587 ps
CPU time 1.48 seconds
Started Aug 14 04:37:00 PM PDT 24
Finished Aug 14 04:37:02 PM PDT 24
Peak memory 198532 kb
Host smart-b4f5fb1b-b530-474b-82eb-31ebab3f269c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61599719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.61599719
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.4138545222
Short name T52
Test name
Test status
Simulation time 72580682 ps
CPU time 1.15 seconds
Started Aug 14 04:37:02 PM PDT 24
Finished Aug 14 04:37:04 PM PDT 24
Peak memory 198328 kb
Host smart-ee61f7a3-d5c6-4d8e-b261-73aecac57b52
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138545222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.4138545222
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2206860802
Short name T749
Test name
Test status
Simulation time 20193523 ps
CPU time 0.66 seconds
Started Aug 14 04:36:53 PM PDT 24
Finished Aug 14 04:36:54 PM PDT 24
Peak memory 197336 kb
Host smart-3f9ffc47-9685-4aa2-97bc-cd9761e8b304
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206860802 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2206860802
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.680937568
Short name T838
Test name
Test status
Simulation time 12831002 ps
CPU time 0.6 seconds
Started Aug 14 04:36:58 PM PDT 24
Finished Aug 14 04:36:59 PM PDT 24
Peak memory 195124 kb
Host smart-710001eb-4371-45d2-ad8a-5acd0cd8833e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680937568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.680937568
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.642037796
Short name T717
Test name
Test status
Simulation time 29004785 ps
CPU time 0.58 seconds
Started Aug 14 04:36:52 PM PDT 24
Finished Aug 14 04:36:52 PM PDT 24
Peak memory 194932 kb
Host smart-4e381cad-a42d-4316-a7e2-29033cef9c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642037796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.642037796
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1313066072
Short name T87
Test name
Test status
Simulation time 50683393 ps
CPU time 0.74 seconds
Started Aug 14 04:36:52 PM PDT 24
Finished Aug 14 04:36:53 PM PDT 24
Peak memory 196936 kb
Host smart-8b666b41-14d3-489d-8b55-b81062770a50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313066072 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1313066072
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2576592086
Short name T815
Test name
Test status
Simulation time 123023159 ps
CPU time 2.58 seconds
Started Aug 14 04:36:53 PM PDT 24
Finished Aug 14 04:36:56 PM PDT 24
Peak memory 198492 kb
Host smart-617d4825-74fe-4755-a70e-de00cd78bd22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576592086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2576592086
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3894335441
Short name T777
Test name
Test status
Simulation time 71154766 ps
CPU time 0.74 seconds
Started Aug 14 04:36:54 PM PDT 24
Finished Aug 14 04:36:55 PM PDT 24
Peak memory 198436 kb
Host smart-156172ae-b804-4d30-8a1a-81ed626a8ac2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894335441 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3894335441
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.700628416
Short name T86
Test name
Test status
Simulation time 32036388 ps
CPU time 0.59 seconds
Started Aug 14 04:36:57 PM PDT 24
Finished Aug 14 04:36:58 PM PDT 24
Peak memory 195456 kb
Host smart-6a1b139a-3d57-4c8e-993b-2e703831d660
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700628416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.700628416
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2496139957
Short name T735
Test name
Test status
Simulation time 11721997 ps
CPU time 0.57 seconds
Started Aug 14 04:36:53 PM PDT 24
Finished Aug 14 04:36:53 PM PDT 24
Peak memory 194084 kb
Host smart-8aaf27a9-5629-4a1e-9ba4-9cf4f4d22b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496139957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2496139957
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1908221104
Short name T770
Test name
Test status
Simulation time 114144730 ps
CPU time 0.78 seconds
Started Aug 14 04:36:55 PM PDT 24
Finished Aug 14 04:36:56 PM PDT 24
Peak memory 196508 kb
Host smart-29df45a6-4c39-4a14-8bdd-1715d4242eca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908221104 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1908221104
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.4029109041
Short name T785
Test name
Test status
Simulation time 84226008 ps
CPU time 1.15 seconds
Started Aug 14 04:36:53 PM PDT 24
Finished Aug 14 04:36:54 PM PDT 24
Peak memory 198408 kb
Host smart-ef45d8cc-323e-49ed-beb0-db885a05e46f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029109041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.4029109041
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3350541102
Short name T43
Test name
Test status
Simulation time 80781124 ps
CPU time 1.08 seconds
Started Aug 14 04:36:49 PM PDT 24
Finished Aug 14 04:36:50 PM PDT 24
Peak memory 198472 kb
Host smart-2c7e09cb-ab5a-43b4-b508-bcf49d5ce56f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350541102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3350541102
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.727750916
Short name T820
Test name
Test status
Simulation time 50108475 ps
CPU time 0.67 seconds
Started Aug 14 04:36:52 PM PDT 24
Finished Aug 14 04:36:53 PM PDT 24
Peak memory 195444 kb
Host smart-73bc4c18-e108-45d1-93b2-1cb630b61ad7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727750916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.727750916
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.549722949
Short name T804
Test name
Test status
Simulation time 253336666 ps
CPU time 3.25 seconds
Started Aug 14 04:36:54 PM PDT 24
Finished Aug 14 04:36:57 PM PDT 24
Peak memory 197644 kb
Host smart-1b737cbf-7bb3-458b-9baa-97593196b2ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549722949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.549722949
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1134129325
Short name T84
Test name
Test status
Simulation time 13977281 ps
CPU time 0.57 seconds
Started Aug 14 04:36:36 PM PDT 24
Finished Aug 14 04:36:36 PM PDT 24
Peak memory 194692 kb
Host smart-bc657be5-fa90-4e1c-8ba1-5da0902eaa50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134129325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1134129325
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3182816501
Short name T827
Test name
Test status
Simulation time 16217252 ps
CPU time 0.68 seconds
Started Aug 14 04:36:42 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 197488 kb
Host smart-8ac6086c-0b4b-4d99-abd8-f542f70cd964
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182816501 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3182816501
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3966126969
Short name T738
Test name
Test status
Simulation time 37148019 ps
CPU time 0.57 seconds
Started Aug 14 04:36:47 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 195012 kb
Host smart-5448e988-8ba1-495a-a2d9-5161cbb0e1f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966126969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3966126969
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2083129875
Short name T810
Test name
Test status
Simulation time 14921220 ps
CPU time 0.63 seconds
Started Aug 14 04:36:43 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 194192 kb
Host smart-3fe0671d-976e-4bd2-8306-9be544f84c73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083129875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2083129875
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2661429047
Short name T92
Test name
Test status
Simulation time 35412657 ps
CPU time 0.63 seconds
Started Aug 14 04:36:35 PM PDT 24
Finished Aug 14 04:36:36 PM PDT 24
Peak memory 195512 kb
Host smart-877930b9-3c9a-4d28-a7d6-e445a64dddaa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661429047 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2661429047
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.435586750
Short name T835
Test name
Test status
Simulation time 87051464 ps
CPU time 1.85 seconds
Started Aug 14 04:36:40 PM PDT 24
Finished Aug 14 04:36:42 PM PDT 24
Peak memory 198556 kb
Host smart-c8decf40-8f4d-4edf-b473-0271e28e918f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435586750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.435586750
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2646268432
Short name T50
Test name
Test status
Simulation time 843958012 ps
CPU time 1.35 seconds
Started Aug 14 04:36:54 PM PDT 24
Finished Aug 14 04:36:56 PM PDT 24
Peak memory 198448 kb
Host smart-1823ba3d-3384-49a1-8f51-114052f371b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646268432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2646268432
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2330382548
Short name T800
Test name
Test status
Simulation time 16885973 ps
CPU time 0.62 seconds
Started Aug 14 04:36:51 PM PDT 24
Finished Aug 14 04:36:51 PM PDT 24
Peak memory 194224 kb
Host smart-76e2dc9d-2894-4106-bacc-aeb3e19525dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330382548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2330382548
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2428491642
Short name T771
Test name
Test status
Simulation time 14563522 ps
CPU time 0.57 seconds
Started Aug 14 04:36:52 PM PDT 24
Finished Aug 14 04:36:52 PM PDT 24
Peak memory 194176 kb
Host smart-39d890b2-798d-48ed-8e7e-ca19ac899f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428491642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2428491642
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1702919567
Short name T828
Test name
Test status
Simulation time 11772127 ps
CPU time 0.58 seconds
Started Aug 14 04:37:00 PM PDT 24
Finished Aug 14 04:37:01 PM PDT 24
Peak memory 194068 kb
Host smart-adde71e3-0da8-47a9-8312-cac2ec9072fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702919567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1702919567
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3873349437
Short name T806
Test name
Test status
Simulation time 41109544 ps
CPU time 0.61 seconds
Started Aug 14 04:37:07 PM PDT 24
Finished Aug 14 04:37:08 PM PDT 24
Peak memory 194336 kb
Host smart-718f3459-19d5-4569-9cf1-e07b0f5d8250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873349437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3873349437
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2744664058
Short name T792
Test name
Test status
Simulation time 13656360 ps
CPU time 0.61 seconds
Started Aug 14 04:36:50 PM PDT 24
Finished Aug 14 04:36:51 PM PDT 24
Peak memory 194216 kb
Host smart-e44ca489-3dbe-44dd-b7ce-4b4def57a70c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744664058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2744664058
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1423539598
Short name T773
Test name
Test status
Simulation time 15979011 ps
CPU time 0.61 seconds
Started Aug 14 04:36:49 PM PDT 24
Finished Aug 14 04:36:50 PM PDT 24
Peak memory 194192 kb
Host smart-2295ba05-9080-4439-83ed-1286e0e1a6f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423539598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1423539598
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.500673004
Short name T724
Test name
Test status
Simulation time 42279765 ps
CPU time 0.61 seconds
Started Aug 14 04:36:55 PM PDT 24
Finished Aug 14 04:36:55 PM PDT 24
Peak memory 194380 kb
Host smart-802a4ca6-e382-4694-939a-f244d0bd4a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500673004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.500673004
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.532247208
Short name T721
Test name
Test status
Simulation time 22438493 ps
CPU time 0.57 seconds
Started Aug 14 04:37:01 PM PDT 24
Finished Aug 14 04:37:02 PM PDT 24
Peak memory 194176 kb
Host smart-6c2f43ec-3040-49a8-b47f-5be2a5850520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532247208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.532247208
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2504464691
Short name T814
Test name
Test status
Simulation time 119383106 ps
CPU time 0.58 seconds
Started Aug 14 04:36:57 PM PDT 24
Finished Aug 14 04:36:58 PM PDT 24
Peak memory 194156 kb
Host smart-1d3da325-b104-47a1-a781-2d347ea5959d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504464691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2504464691
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3419262785
Short name T715
Test name
Test status
Simulation time 52677203 ps
CPU time 0.56 seconds
Started Aug 14 04:36:51 PM PDT 24
Finished Aug 14 04:36:56 PM PDT 24
Peak memory 194268 kb
Host smart-64b5bacc-9d62-4c3e-b67e-75890de3ad07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419262785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3419262785
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2474979149
Short name T80
Test name
Test status
Simulation time 32111314 ps
CPU time 0.85 seconds
Started Aug 14 04:36:33 PM PDT 24
Finished Aug 14 04:36:34 PM PDT 24
Peak memory 196288 kb
Host smart-6f8fd1d0-ccd3-442d-83e7-263902e78e5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474979149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2474979149
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.997947479
Short name T778
Test name
Test status
Simulation time 138221201 ps
CPU time 1.5 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 197132 kb
Host smart-ec472d71-0f2e-49df-b6c8-c2e69e673322
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997947479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.997947479
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1930859241
Short name T776
Test name
Test status
Simulation time 14375839 ps
CPU time 0.58 seconds
Started Aug 14 04:36:48 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 195040 kb
Host smart-f8dc78e7-c6d7-42eb-8a0e-07b050dc7d48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930859241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1930859241
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1485599088
Short name T798
Test name
Test status
Simulation time 160837191 ps
CPU time 0.98 seconds
Started Aug 14 04:36:34 PM PDT 24
Finished Aug 14 04:36:35 PM PDT 24
Peak memory 198276 kb
Host smart-14c8f9fb-5dd1-47d8-be0e-e8ef19963664
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485599088 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1485599088
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1403551724
Short name T793
Test name
Test status
Simulation time 14850345 ps
CPU time 0.57 seconds
Started Aug 14 04:36:43 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 193764 kb
Host smart-b2b69942-e609-4fd3-b10f-3157a1359849
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403551724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1403551724
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3496953318
Short name T784
Test name
Test status
Simulation time 14174747 ps
CPU time 0.63 seconds
Started Aug 14 04:36:40 PM PDT 24
Finished Aug 14 04:36:41 PM PDT 24
Peak memory 194808 kb
Host smart-82d28b56-eb80-42d5-965a-d3994bcc7f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496953318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3496953318
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1723991014
Short name T78
Test name
Test status
Simulation time 33667954 ps
CPU time 0.84 seconds
Started Aug 14 04:36:42 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 197360 kb
Host smart-ceb70c9b-9aab-47ff-af8a-ccdc683261ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723991014 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1723991014
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1215734797
Short name T744
Test name
Test status
Simulation time 45627201 ps
CPU time 1.35 seconds
Started Aug 14 04:36:47 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 198468 kb
Host smart-204ee876-063e-49e8-ab5d-d1344cab33d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215734797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1215734797
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.110889116
Short name T47
Test name
Test status
Simulation time 191996161 ps
CPU time 1.38 seconds
Started Aug 14 04:37:00 PM PDT 24
Finished Aug 14 04:37:02 PM PDT 24
Peak memory 198336 kb
Host smart-bd228606-486b-420a-b910-ab02c1343597
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110889116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.110889116
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2415227550
Short name T780
Test name
Test status
Simulation time 16512155 ps
CPU time 0.6 seconds
Started Aug 14 04:36:52 PM PDT 24
Finished Aug 14 04:36:53 PM PDT 24
Peak memory 194828 kb
Host smart-f4b3662d-5a93-4a7d-bf68-e33f390f8e68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415227550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2415227550
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2376602413
Short name T809
Test name
Test status
Simulation time 15607562 ps
CPU time 0.63 seconds
Started Aug 14 04:36:49 PM PDT 24
Finished Aug 14 04:36:50 PM PDT 24
Peak memory 194132 kb
Host smart-33cd2fdc-3d6a-4ba7-90e4-e798e3fa05dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376602413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2376602413
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1458650234
Short name T720
Test name
Test status
Simulation time 37821313 ps
CPU time 0.6 seconds
Started Aug 14 04:36:56 PM PDT 24
Finished Aug 14 04:36:57 PM PDT 24
Peak memory 194304 kb
Host smart-46d3db2a-a856-46f4-a6fb-7eb01d018f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458650234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1458650234
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1559314156
Short name T727
Test name
Test status
Simulation time 34052151 ps
CPU time 0.57 seconds
Started Aug 14 04:37:04 PM PDT 24
Finished Aug 14 04:37:04 PM PDT 24
Peak memory 194852 kb
Host smart-322615e0-34fd-48a2-9e73-575b115d7c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559314156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1559314156
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1751886929
Short name T740
Test name
Test status
Simulation time 20758293 ps
CPU time 0.62 seconds
Started Aug 14 04:37:01 PM PDT 24
Finished Aug 14 04:37:02 PM PDT 24
Peak memory 194224 kb
Host smart-9f9e2958-35cd-4666-b554-7a7633093429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751886929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1751886929
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3675451906
Short name T794
Test name
Test status
Simulation time 19960366 ps
CPU time 0.62 seconds
Started Aug 14 04:37:05 PM PDT 24
Finished Aug 14 04:37:05 PM PDT 24
Peak memory 194792 kb
Host smart-38a02de3-b78f-4b80-bc1e-655c33912698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675451906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3675451906
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3032674569
Short name T739
Test name
Test status
Simulation time 79531295 ps
CPU time 0.59 seconds
Started Aug 14 04:36:59 PM PDT 24
Finished Aug 14 04:37:00 PM PDT 24
Peak memory 194000 kb
Host smart-d6f3b85a-f039-449e-a8df-655fb5b5ae3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032674569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3032674569
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.478337406
Short name T741
Test name
Test status
Simulation time 20811699 ps
CPU time 0.61 seconds
Started Aug 14 04:37:00 PM PDT 24
Finished Aug 14 04:37:00 PM PDT 24
Peak memory 194256 kb
Host smart-c657f5fd-6e66-4da3-b5e8-4efa2823a57e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478337406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.478337406
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2569541670
Short name T789
Test name
Test status
Simulation time 35679573 ps
CPU time 0.56 seconds
Started Aug 14 04:37:19 PM PDT 24
Finished Aug 14 04:37:19 PM PDT 24
Peak memory 194188 kb
Host smart-0243f0a4-fcfe-4452-8a5f-4403c9f51393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569541670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2569541670
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1190310882
Short name T787
Test name
Test status
Simulation time 57390061 ps
CPU time 0.56 seconds
Started Aug 14 04:36:54 PM PDT 24
Finished Aug 14 04:36:55 PM PDT 24
Peak memory 194100 kb
Host smart-3c7d65d6-7eee-41ba-a451-a193108274ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190310882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1190310882
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1171370895
Short name T813
Test name
Test status
Simulation time 16476699 ps
CPU time 0.7 seconds
Started Aug 14 04:36:39 PM PDT 24
Finished Aug 14 04:36:40 PM PDT 24
Peak memory 195384 kb
Host smart-83fc2607-e89f-4189-9bed-6a8ef4708a95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171370895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1171370895
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1561890185
Short name T85
Test name
Test status
Simulation time 1787270531 ps
CPU time 3.25 seconds
Started Aug 14 04:36:26 PM PDT 24
Finished Aug 14 04:36:29 PM PDT 24
Peak memory 198404 kb
Host smart-e42a45ac-c603-4f83-bffd-4a25ed286eb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561890185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1561890185
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.413877745
Short name T81
Test name
Test status
Simulation time 50897427 ps
CPU time 0.63 seconds
Started Aug 14 04:36:41 PM PDT 24
Finished Aug 14 04:36:42 PM PDT 24
Peak memory 195200 kb
Host smart-80805bc7-5a49-4390-8d52-6e2de626712d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413877745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.413877745
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1347160200
Short name T836
Test name
Test status
Simulation time 141944203 ps
CPU time 0.71 seconds
Started Aug 14 04:36:44 PM PDT 24
Finished Aug 14 04:36:45 PM PDT 24
Peak memory 198408 kb
Host smart-7ff3e28c-f07d-403e-9638-c46aba62f09e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347160200 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1347160200
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3292184247
Short name T802
Test name
Test status
Simulation time 36796178 ps
CPU time 0.64 seconds
Started Aug 14 04:36:50 PM PDT 24
Finished Aug 14 04:36:51 PM PDT 24
Peak memory 195620 kb
Host smart-a64e781f-eece-4bb3-9594-06168a856a2c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292184247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3292184247
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4087586114
Short name T830
Test name
Test status
Simulation time 116801092 ps
CPU time 0.62 seconds
Started Aug 14 04:36:35 PM PDT 24
Finished Aug 14 04:36:36 PM PDT 24
Peak memory 194176 kb
Host smart-734b7cb3-b8c4-4a44-8ef2-1b7495aec9e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087586114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4087586114
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3975167468
Short name T759
Test name
Test status
Simulation time 59765118 ps
CPU time 0.65 seconds
Started Aug 14 04:36:47 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 195132 kb
Host smart-66a4ed7d-59f6-4ab9-9b67-898079396471
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975167468 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3975167468
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.884400787
Short name T729
Test name
Test status
Simulation time 208044570 ps
CPU time 3.26 seconds
Started Aug 14 04:36:40 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 198552 kb
Host smart-af1598e4-858f-4f64-a125-a27dbe7731cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884400787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.884400787
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.4112428591
Short name T746
Test name
Test status
Simulation time 15779864 ps
CPU time 0.61 seconds
Started Aug 14 04:37:03 PM PDT 24
Finished Aug 14 04:37:09 PM PDT 24
Peak memory 194240 kb
Host smart-ed4c2141-c126-41ee-b226-e45db427b347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112428591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.4112428591
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2688696247
Short name T829
Test name
Test status
Simulation time 17912045 ps
CPU time 0.59 seconds
Started Aug 14 04:36:54 PM PDT 24
Finished Aug 14 04:36:55 PM PDT 24
Peak memory 194936 kb
Host smart-9db097c5-ba3d-4d9c-b833-da87289ba930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688696247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2688696247
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3219867921
Short name T764
Test name
Test status
Simulation time 41501188 ps
CPU time 0.57 seconds
Started Aug 14 04:36:55 PM PDT 24
Finished Aug 14 04:36:56 PM PDT 24
Peak memory 194032 kb
Host smart-137eca82-a029-4c37-9c02-5b3ef2712b44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219867921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3219867921
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2711397122
Short name T719
Test name
Test status
Simulation time 100673377 ps
CPU time 0.61 seconds
Started Aug 14 04:36:56 PM PDT 24
Finished Aug 14 04:36:57 PM PDT 24
Peak memory 195036 kb
Host smart-0067d6f3-36d2-4592-9698-967050bb8a6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711397122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2711397122
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2955427362
Short name T757
Test name
Test status
Simulation time 44124249 ps
CPU time 0.59 seconds
Started Aug 14 04:37:00 PM PDT 24
Finished Aug 14 04:37:01 PM PDT 24
Peak memory 194188 kb
Host smart-c78441da-1b97-4c32-b0a9-f8f689691f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955427362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2955427362
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3350201337
Short name T822
Test name
Test status
Simulation time 12426762 ps
CPU time 0.6 seconds
Started Aug 14 04:37:03 PM PDT 24
Finished Aug 14 04:37:03 PM PDT 24
Peak memory 194116 kb
Host smart-ed6c6027-c32e-4028-9055-ea24a49687b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350201337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3350201337
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.689575436
Short name T812
Test name
Test status
Simulation time 25515580 ps
CPU time 0.57 seconds
Started Aug 14 04:36:56 PM PDT 24
Finished Aug 14 04:36:57 PM PDT 24
Peak memory 194220 kb
Host smart-5b4bc9e7-aaa8-4523-bd96-58d804c55ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689575436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.689575436
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3285142795
Short name T755
Test name
Test status
Simulation time 38323006 ps
CPU time 0.56 seconds
Started Aug 14 04:36:55 PM PDT 24
Finished Aug 14 04:36:55 PM PDT 24
Peak memory 194160 kb
Host smart-1b9dff71-9b9b-4f04-9fc7-bde342a344fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285142795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3285142795
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.268958695
Short name T762
Test name
Test status
Simulation time 19509388 ps
CPU time 0.59 seconds
Started Aug 14 04:37:09 PM PDT 24
Finished Aug 14 04:37:10 PM PDT 24
Peak memory 194804 kb
Host smart-456a4433-4d5f-41bb-8767-cef7063c94fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268958695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.268958695
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2481335764
Short name T788
Test name
Test status
Simulation time 15167558 ps
CPU time 0.59 seconds
Started Aug 14 04:37:10 PM PDT 24
Finished Aug 14 04:37:11 PM PDT 24
Peak memory 194080 kb
Host smart-58762933-380d-4d80-85b9-768fa6a571bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481335764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2481335764
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2445468305
Short name T730
Test name
Test status
Simulation time 63528997 ps
CPU time 0.94 seconds
Started Aug 14 04:36:41 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 198324 kb
Host smart-f9ffa250-04c5-47e0-a387-dc30b25e9148
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445468305 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2445468305
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2517467971
Short name T725
Test name
Test status
Simulation time 57476436 ps
CPU time 0.56 seconds
Started Aug 14 04:36:38 PM PDT 24
Finished Aug 14 04:36:39 PM PDT 24
Peak memory 194396 kb
Host smart-7ccd92aa-84ee-4ab8-b4c4-42a972a9f48f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517467971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2517467971
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.308001753
Short name T775
Test name
Test status
Simulation time 14453072 ps
CPU time 0.61 seconds
Started Aug 14 04:36:56 PM PDT 24
Finished Aug 14 04:36:57 PM PDT 24
Peak memory 194096 kb
Host smart-3467168a-5620-461d-9b70-86d03a9ded07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308001753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.308001753
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1520825423
Short name T77
Test name
Test status
Simulation time 63016933 ps
CPU time 0.64 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:47 PM PDT 24
Peak memory 195332 kb
Host smart-19d5a188-9df4-4566-a405-0af4d8fbbd37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520825423 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1520825423
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1109490940
Short name T718
Test name
Test status
Simulation time 68056007 ps
CPU time 0.99 seconds
Started Aug 14 04:36:29 PM PDT 24
Finished Aug 14 04:36:30 PM PDT 24
Peak memory 198368 kb
Host smart-c129e7b1-c347-4753-a418-68196593922d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109490940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1109490940
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1117198252
Short name T791
Test name
Test status
Simulation time 223537234 ps
CPU time 1.21 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:47 PM PDT 24
Peak memory 198516 kb
Host smart-d95aebb5-fc93-4a57-9324-1a4c5e941ea1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117198252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1117198252
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.972863099
Short name T774
Test name
Test status
Simulation time 111749975 ps
CPU time 0.98 seconds
Started Aug 14 04:36:51 PM PDT 24
Finished Aug 14 04:36:52 PM PDT 24
Peak memory 198356 kb
Host smart-fa146a09-8645-4118-aaf0-ea1fedd662ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972863099 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.972863099
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2632238006
Short name T74
Test name
Test status
Simulation time 35260228 ps
CPU time 0.59 seconds
Started Aug 14 04:36:45 PM PDT 24
Finished Aug 14 04:36:46 PM PDT 24
Peak memory 195904 kb
Host smart-f4a3f786-9169-45ac-9030-0f3d22f688a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632238006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2632238006
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3453957827
Short name T783
Test name
Test status
Simulation time 184381316 ps
CPU time 0.66 seconds
Started Aug 14 04:36:47 PM PDT 24
Finished Aug 14 04:36:48 PM PDT 24
Peak memory 194872 kb
Host smart-fd772e5e-479a-4605-8545-639fc91a1e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453957827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3453957827
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.701374169
Short name T91
Test name
Test status
Simulation time 14719336 ps
CPU time 0.65 seconds
Started Aug 14 04:36:47 PM PDT 24
Finished Aug 14 04:36:47 PM PDT 24
Peak memory 194796 kb
Host smart-c58a0e72-043d-4b25-9ef6-fb327e91e1cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701374169 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.701374169
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1353135849
Short name T751
Test name
Test status
Simulation time 105089852 ps
CPU time 2 seconds
Started Aug 14 04:36:43 PM PDT 24
Finished Aug 14 04:36:46 PM PDT 24
Peak memory 198608 kb
Host smart-537e2cf0-2711-4cda-944f-85563dd15abd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353135849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1353135849
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1534473244
Short name T46
Test name
Test status
Simulation time 124353344 ps
CPU time 1.42 seconds
Started Aug 14 04:36:38 PM PDT 24
Finished Aug 14 04:36:40 PM PDT 24
Peak memory 198424 kb
Host smart-e0ba9478-6634-46e5-95fa-7ec4ebb6ce6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534473244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1534473244
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1337007619
Short name T823
Test name
Test status
Simulation time 311764687 ps
CPU time 1.56 seconds
Started Aug 14 04:36:38 PM PDT 24
Finished Aug 14 04:36:40 PM PDT 24
Peak memory 198644 kb
Host smart-e4c5e9c9-e776-47c9-9014-2bfeaafe48ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337007619 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1337007619
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1339807930
Short name T82
Test name
Test status
Simulation time 13399851 ps
CPU time 0.6 seconds
Started Aug 14 04:36:39 PM PDT 24
Finished Aug 14 04:36:40 PM PDT 24
Peak memory 195048 kb
Host smart-d085c80d-7890-4d37-ab58-8dff984b5477
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339807930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1339807930
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3376205479
Short name T767
Test name
Test status
Simulation time 16092791 ps
CPU time 0.6 seconds
Started Aug 14 04:36:32 PM PDT 24
Finished Aug 14 04:36:33 PM PDT 24
Peak memory 194824 kb
Host smart-0f88ad1e-296e-499e-8c73-d80d2a18fde1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376205479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3376205479
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2204787083
Short name T831
Test name
Test status
Simulation time 24898787 ps
CPU time 0.7 seconds
Started Aug 14 04:36:48 PM PDT 24
Finished Aug 14 04:36:49 PM PDT 24
Peak memory 195340 kb
Host smart-f6ee7a10-d2c9-459a-aaa6-761e0236015f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204787083 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2204787083
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2603368088
Short name T826
Test name
Test status
Simulation time 185788062 ps
CPU time 1.24 seconds
Started Aug 14 04:36:41 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 198464 kb
Host smart-be7e39b6-7013-4281-bc66-ce026131e01f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603368088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2603368088
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3702657574
Short name T816
Test name
Test status
Simulation time 59837074 ps
CPU time 0.87 seconds
Started Aug 14 04:36:42 PM PDT 24
Finished Aug 14 04:36:43 PM PDT 24
Peak memory 197588 kb
Host smart-3f8cd741-f43f-4875-9c04-85010cf5f377
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702657574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3702657574
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2450521257
Short name T786
Test name
Test status
Simulation time 21164757 ps
CPU time 0.75 seconds
Started Aug 14 04:36:35 PM PDT 24
Finished Aug 14 04:36:36 PM PDT 24
Peak memory 197420 kb
Host smart-0505a2de-537c-485c-989d-e01fe9b61d9d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450521257 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2450521257
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.117461345
Short name T782
Test name
Test status
Simulation time 50781230 ps
CPU time 0.6 seconds
Started Aug 14 04:36:42 PM PDT 24
Finished Aug 14 04:36:42 PM PDT 24
Peak memory 195104 kb
Host smart-e780fb9f-7c43-4c1d-a89c-603d418a2800
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117461345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.117461345
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.990151632
Short name T801
Test name
Test status
Simulation time 63784169 ps
CPU time 0.56 seconds
Started Aug 14 04:36:44 PM PDT 24
Finished Aug 14 04:36:45 PM PDT 24
Peak memory 194164 kb
Host smart-a05be008-f6c7-4a71-90ad-014dc2e2b893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990151632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.990151632
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2869401848
Short name T760
Test name
Test status
Simulation time 191624567 ps
CPU time 0.8 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:47 PM PDT 24
Peak memory 196404 kb
Host smart-e5fa6b2e-3495-4c5c-bc15-218f7a4c22df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869401848 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2869401848
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.868224182
Short name T726
Test name
Test status
Simulation time 740032936 ps
CPU time 2.46 seconds
Started Aug 14 04:36:46 PM PDT 24
Finished Aug 14 04:36:49 PM PDT 24
Peak memory 198508 kb
Host smart-ee353387-c9d6-4e77-b95f-b77ba971d2d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868224182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.868224182
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2021598010
Short name T51
Test name
Test status
Simulation time 283428814 ps
CPU time 1.09 seconds
Started Aug 14 04:36:56 PM PDT 24
Finished Aug 14 04:36:57 PM PDT 24
Peak memory 198440 kb
Host smart-01ca65ff-0689-41bd-9552-c7a34c698750
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021598010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2021598010
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1021619851
Short name T745
Test name
Test status
Simulation time 136607342 ps
CPU time 0.92 seconds
Started Aug 14 04:36:30 PM PDT 24
Finished Aug 14 04:36:31 PM PDT 24
Peak memory 198316 kb
Host smart-c41875fa-ab91-40dd-8006-2fc173710ce2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021619851 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1021619851
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3932707591
Short name T769
Test name
Test status
Simulation time 16135659 ps
CPU time 0.62 seconds
Started Aug 14 04:36:33 PM PDT 24
Finished Aug 14 04:36:34 PM PDT 24
Peak memory 194928 kb
Host smart-ab6b3119-90de-4fd3-bbd3-78ed56426231
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932707591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3932707591
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.966896946
Short name T837
Test name
Test status
Simulation time 16288466 ps
CPU time 0.61 seconds
Started Aug 14 04:36:39 PM PDT 24
Finished Aug 14 04:36:40 PM PDT 24
Peak memory 194984 kb
Host smart-fa1d1b86-a710-4d00-9021-3a69a07b4df4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966896946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.966896946
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3595260071
Short name T818
Test name
Test status
Simulation time 27507483 ps
CPU time 0.69 seconds
Started Aug 14 04:36:30 PM PDT 24
Finished Aug 14 04:36:31 PM PDT 24
Peak memory 194820 kb
Host smart-e10f9187-708c-4885-9bac-799c46642110
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595260071 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3595260071
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.737555499
Short name T734
Test name
Test status
Simulation time 62694768 ps
CPU time 1.79 seconds
Started Aug 14 04:36:40 PM PDT 24
Finished Aug 14 04:36:42 PM PDT 24
Peak memory 198516 kb
Host smart-70ecfaa6-90db-4827-a948-05a4110143ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737555499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.737555499
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3141970858
Short name T44
Test name
Test status
Simulation time 68187242 ps
CPU time 0.88 seconds
Started Aug 14 04:36:33 PM PDT 24
Finished Aug 14 04:36:34 PM PDT 24
Peak memory 197456 kb
Host smart-60f6e3c0-09c6-48cf-85bc-41bf421a4520
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141970858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3141970858
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.4005721442
Short name T401
Test name
Test status
Simulation time 19025997 ps
CPU time 0.62 seconds
Started Aug 14 04:43:44 PM PDT 24
Finished Aug 14 04:43:45 PM PDT 24
Peak memory 194116 kb
Host smart-720598d1-60a4-4327-b736-a37af5799d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005721442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4005721442
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3788890352
Short name T195
Test name
Test status
Simulation time 133679048 ps
CPU time 6.68 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:25 PM PDT 24
Peak memory 195660 kb
Host smart-1c0be81a-abef-4fdf-b0a4-8fcedd1d696c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788890352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3788890352
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1710441213
Short name T712
Test name
Test status
Simulation time 60860499 ps
CPU time 0.82 seconds
Started Aug 14 04:43:39 PM PDT 24
Finished Aug 14 04:43:40 PM PDT 24
Peak memory 196828 kb
Host smart-5b7b466b-005f-415a-98bf-852d467cc704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710441213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1710441213
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2845656957
Short name T550
Test name
Test status
Simulation time 58502003 ps
CPU time 0.7 seconds
Started Aug 14 04:43:35 PM PDT 24
Finished Aug 14 04:43:36 PM PDT 24
Peak memory 194552 kb
Host smart-d2f2435d-c103-4b42-8a91-bceaf25c8c08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845656957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2845656957
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2165642072
Short name T520
Test name
Test status
Simulation time 90042077 ps
CPU time 3.32 seconds
Started Aug 14 04:43:23 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 198268 kb
Host smart-e40b18bb-c7a7-4c66-a59e-2dec3348347e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165642072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2165642072
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4126089355
Short name T265
Test name
Test status
Simulation time 340560586 ps
CPU time 1.53 seconds
Started Aug 14 04:43:29 PM PDT 24
Finished Aug 14 04:43:31 PM PDT 24
Peak memory 196184 kb
Host smart-e70992b7-0c38-450e-9639-8b8ed2849b90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126089355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4126089355
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2813759467
Short name T383
Test name
Test status
Simulation time 28145884 ps
CPU time 1 seconds
Started Aug 14 04:43:16 PM PDT 24
Finished Aug 14 04:43:17 PM PDT 24
Peak memory 196008 kb
Host smart-23af92ed-640b-4703-878a-949b664a3013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813759467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2813759467
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3038207516
Short name T651
Test name
Test status
Simulation time 21048835 ps
CPU time 0.68 seconds
Started Aug 14 04:43:26 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 196176 kb
Host smart-5de2ae95-67d2-43e1-a8dd-f03d89871b43
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038207516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3038207516
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.4280688645
Short name T597
Test name
Test status
Simulation time 1478987162 ps
CPU time 2.13 seconds
Started Aug 14 04:43:36 PM PDT 24
Finished Aug 14 04:43:39 PM PDT 24
Peak memory 198184 kb
Host smart-530021a1-6ce1-4e7a-bf14-e89b3ba8a848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280688645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.4280688645
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.4250218319
Short name T37
Test name
Test status
Simulation time 58741800 ps
CPU time 0.87 seconds
Started Aug 14 04:43:36 PM PDT 24
Finished Aug 14 04:43:37 PM PDT 24
Peak memory 213972 kb
Host smart-890e4e65-cc89-435a-8cd8-6071353626be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250218319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.4250218319
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2321107211
Short name T595
Test name
Test status
Simulation time 105650582 ps
CPU time 1.1 seconds
Started Aug 14 04:43:39 PM PDT 24
Finished Aug 14 04:43:40 PM PDT 24
Peak memory 195712 kb
Host smart-a6ff6dac-ac7c-44e6-b061-f7f849728e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321107211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2321107211
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.4050121036
Short name T466
Test name
Test status
Simulation time 66686185 ps
CPU time 1.04 seconds
Started Aug 14 04:43:48 PM PDT 24
Finished Aug 14 04:43:50 PM PDT 24
Peak memory 195976 kb
Host smart-8ab0d51a-6e15-4d8d-b0ac-80ed792d3bd2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050121036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.4050121036
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.688918436
Short name T628
Test name
Test status
Simulation time 8137278794 ps
CPU time 85.06 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:44:44 PM PDT 24
Peak memory 198400 kb
Host smart-baa8b4f9-a8a8-4dda-8bb0-313ee7f153e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688918436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.688918436
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.724439684
Short name T132
Test name
Test status
Simulation time 53363523 ps
CPU time 0.56 seconds
Started Aug 14 04:43:48 PM PDT 24
Finished Aug 14 04:43:49 PM PDT 24
Peak memory 194292 kb
Host smart-6329b5b4-fd11-476d-9ebf-19c145cbbcb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724439684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.724439684
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2843906045
Short name T677
Test name
Test status
Simulation time 416010779 ps
CPU time 0.69 seconds
Started Aug 14 04:43:50 PM PDT 24
Finished Aug 14 04:43:50 PM PDT 24
Peak memory 195900 kb
Host smart-413a1e49-7305-4796-868a-7eb086506c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843906045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2843906045
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1564131934
Short name T231
Test name
Test status
Simulation time 1240474880 ps
CPU time 19.8 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 196856 kb
Host smart-fd0fcd2a-5885-4702-96c8-0f1611b3d2bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564131934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1564131934
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.143160679
Short name T648
Test name
Test status
Simulation time 50558667 ps
CPU time 0.83 seconds
Started Aug 14 04:43:27 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 196816 kb
Host smart-e9b4bf10-1611-4551-9628-b27325b7c5a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143160679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.143160679
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1619830052
Short name T346
Test name
Test status
Simulation time 28053505 ps
CPU time 0.84 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:47 PM PDT 24
Peak memory 196636 kb
Host smart-8a5bf297-b918-4159-9142-58df2caadfcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619830052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1619830052
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.4283769372
Short name T507
Test name
Test status
Simulation time 104156103 ps
CPU time 2.26 seconds
Started Aug 14 04:44:19 PM PDT 24
Finished Aug 14 04:44:22 PM PDT 24
Peak memory 196756 kb
Host smart-c4564ce0-c1d4-4462-b626-c0c097fed81a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283769372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.4283769372
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1644705679
Short name T405
Test name
Test status
Simulation time 177277245 ps
CPU time 1.57 seconds
Started Aug 14 04:43:30 PM PDT 24
Finished Aug 14 04:43:32 PM PDT 24
Peak memory 196248 kb
Host smart-d9385daf-8422-4130-b37f-f8ad88f6bf10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644705679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1644705679
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.4236343227
Short name T702
Test name
Test status
Simulation time 36388208 ps
CPU time 1.16 seconds
Started Aug 14 04:43:36 PM PDT 24
Finished Aug 14 04:43:37 PM PDT 24
Peak memory 197136 kb
Host smart-b676fdcc-337f-4e25-b7a3-046a6fa19145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236343227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.4236343227
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2585300420
Short name T602
Test name
Test status
Simulation time 70462324 ps
CPU time 1.26 seconds
Started Aug 14 04:43:41 PM PDT 24
Finished Aug 14 04:43:42 PM PDT 24
Peak memory 197176 kb
Host smart-dff18b75-d878-4920-b4ae-4a6d53c5d339
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585300420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2585300420
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1039622496
Short name T495
Test name
Test status
Simulation time 416181808 ps
CPU time 4.35 seconds
Started Aug 14 04:43:25 PM PDT 24
Finished Aug 14 04:43:29 PM PDT 24
Peak memory 198160 kb
Host smart-09f6c8be-34f5-42cb-9a96-ddf8f54af48d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039622496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1039622496
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.4088602545
Short name T127
Test name
Test status
Simulation time 164864282 ps
CPU time 1.26 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:05 PM PDT 24
Peak memory 195596 kb
Host smart-7d1c150d-979e-46ed-93d6-d5e97f55d22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088602545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.4088602545
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.308304643
Short name T290
Test name
Test status
Simulation time 269437196 ps
CPU time 1.02 seconds
Started Aug 14 04:43:51 PM PDT 24
Finished Aug 14 04:43:52 PM PDT 24
Peak memory 195744 kb
Host smart-9509289c-5b7f-4a9d-b575-24e1eaab5bb3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308304643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.308304643
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1222466147
Short name T166
Test name
Test status
Simulation time 25136224408 ps
CPU time 138.63 seconds
Started Aug 14 04:43:27 PM PDT 24
Finished Aug 14 04:45:46 PM PDT 24
Peak memory 198296 kb
Host smart-1de6aa5f-b29f-490b-a7d6-4cb5e7d5397e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222466147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1222466147
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.543295859
Short name T327
Test name
Test status
Simulation time 37890161 ps
CPU time 0.57 seconds
Started Aug 14 04:44:17 PM PDT 24
Finished Aug 14 04:44:18 PM PDT 24
Peak memory 194060 kb
Host smart-293b571f-c7da-4a10-86f5-9675e95abe51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543295859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.543295859
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.602470429
Short name T353
Test name
Test status
Simulation time 23945779 ps
CPU time 0.65 seconds
Started Aug 14 04:44:02 PM PDT 24
Finished Aug 14 04:44:02 PM PDT 24
Peak memory 194128 kb
Host smart-a3db1287-44ce-4abc-a2bd-6d8a3d3fbbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602470429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.602470429
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2852702234
Short name T596
Test name
Test status
Simulation time 445567505 ps
CPU time 3.52 seconds
Started Aug 14 04:43:53 PM PDT 24
Finished Aug 14 04:43:57 PM PDT 24
Peak memory 195940 kb
Host smart-d1b29c92-88b2-4e1d-8e68-3810d758653a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852702234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2852702234
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2054905760
Short name T616
Test name
Test status
Simulation time 204188518 ps
CPU time 0.78 seconds
Started Aug 14 04:43:54 PM PDT 24
Finished Aug 14 04:43:55 PM PDT 24
Peak memory 195956 kb
Host smart-b0f32d2e-f100-4f2e-9f7b-9d106a9c77c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054905760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2054905760
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3797284137
Short name T558
Test name
Test status
Simulation time 615773935 ps
CPU time 1.29 seconds
Started Aug 14 04:43:59 PM PDT 24
Finished Aug 14 04:44:00 PM PDT 24
Peak memory 196716 kb
Host smart-00defc0b-dde9-4120-bd49-feb36217fa97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797284137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3797284137
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1875384253
Short name T518
Test name
Test status
Simulation time 159003017 ps
CPU time 3.44 seconds
Started Aug 14 04:43:56 PM PDT 24
Finished Aug 14 04:44:00 PM PDT 24
Peak memory 198152 kb
Host smart-206eb3f9-182c-4059-b40c-4c8f752befef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875384253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1875384253
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1684310726
Short name T141
Test name
Test status
Simulation time 73810452 ps
CPU time 1.62 seconds
Started Aug 14 04:43:48 PM PDT 24
Finished Aug 14 04:43:50 PM PDT 24
Peak memory 196276 kb
Host smart-d066f692-a104-44f6-869e-d184bdc7cbbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684310726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1684310726
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3056280842
Short name T601
Test name
Test status
Simulation time 69688959 ps
CPU time 0.98 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:08 PM PDT 24
Peak memory 196124 kb
Host smart-05a728f7-dd02-4de2-a5dd-34e62bbb9c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056280842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3056280842
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1097259144
Short name T606
Test name
Test status
Simulation time 393006313 ps
CPU time 1.05 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:43:58 PM PDT 24
Peak memory 195988 kb
Host smart-9318d29f-2365-40a8-a330-243ae760ea91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097259144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1097259144
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.4147433994
Short name T562
Test name
Test status
Simulation time 118903313 ps
CPU time 1.32 seconds
Started Aug 14 04:44:03 PM PDT 24
Finished Aug 14 04:44:05 PM PDT 24
Peak memory 197888 kb
Host smart-ec6b33e5-9aec-4525-ab4a-78176a919411
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147433994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.4147433994
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1537115512
Short name T612
Test name
Test status
Simulation time 83869832 ps
CPU time 0.9 seconds
Started Aug 14 04:44:01 PM PDT 24
Finished Aug 14 04:44:02 PM PDT 24
Peak memory 195676 kb
Host smart-0c2e74d5-e286-4fe3-b574-d16d9a077d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537115512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1537115512
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.21345227
Short name T267
Test name
Test status
Simulation time 183902274 ps
CPU time 1.1 seconds
Started Aug 14 04:44:00 PM PDT 24
Finished Aug 14 04:44:01 PM PDT 24
Peak memory 195780 kb
Host smart-1202fe5e-5d2b-457b-8173-a0ca92df2dad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21345227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.21345227
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.165401634
Short name T415
Test name
Test status
Simulation time 5387801562 ps
CPU time 132.51 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:46:28 PM PDT 24
Peak memory 198320 kb
Host smart-be7b0670-ec74-4c28-84c5-527e7cda79ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165401634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.165401634
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1120495588
Short name T583
Test name
Test status
Simulation time 29022660 ps
CPU time 0.57 seconds
Started Aug 14 04:44:00 PM PDT 24
Finished Aug 14 04:44:01 PM PDT 24
Peak memory 194288 kb
Host smart-489ddec2-2f72-455c-9a4c-e11a68879d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120495588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1120495588
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3990220594
Short name T500
Test name
Test status
Simulation time 55387328 ps
CPU time 0.64 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 194900 kb
Host smart-ab7e3402-031d-4c9d-8db4-3e75cd005b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990220594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3990220594
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1231255858
Short name T241
Test name
Test status
Simulation time 228994729 ps
CPU time 6.45 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:44:04 PM PDT 24
Peak memory 196996 kb
Host smart-33513151-d220-4d74-be68-6afd046f574d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231255858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1231255858
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.845925836
Short name T9
Test name
Test status
Simulation time 67151744 ps
CPU time 0.68 seconds
Started Aug 14 04:44:20 PM PDT 24
Finished Aug 14 04:44:21 PM PDT 24
Peak memory 194688 kb
Host smart-2d539398-b84b-4dde-b268-73800b4c4cd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845925836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.845925836
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3858499662
Short name T284
Test name
Test status
Simulation time 452141714 ps
CPU time 1.27 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:08 PM PDT 24
Peak memory 197168 kb
Host smart-66e22241-fff0-4b19-8221-33e4d73573b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858499662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3858499662
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3262981745
Short name T386
Test name
Test status
Simulation time 140329028 ps
CPU time 2.77 seconds
Started Aug 14 04:44:06 PM PDT 24
Finished Aug 14 04:44:09 PM PDT 24
Peak memory 198268 kb
Host smart-a307052e-3e70-4140-84e3-eac08a5d501a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262981745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3262981745
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.453476879
Short name T675
Test name
Test status
Simulation time 139264998 ps
CPU time 1.22 seconds
Started Aug 14 04:44:09 PM PDT 24
Finished Aug 14 04:44:11 PM PDT 24
Peak memory 196056 kb
Host smart-7064ba2b-1a71-40d1-9569-e0f73399c0a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453476879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
453476879
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.722597585
Short name T342
Test name
Test status
Simulation time 131601463 ps
CPU time 1.2 seconds
Started Aug 14 04:43:54 PM PDT 24
Finished Aug 14 04:43:55 PM PDT 24
Peak memory 197044 kb
Host smart-a15c3119-5981-4539-be01-c973cfcd797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722597585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.722597585
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2933940991
Short name T186
Test name
Test status
Simulation time 184128853 ps
CPU time 0.91 seconds
Started Aug 14 04:44:01 PM PDT 24
Finished Aug 14 04:44:02 PM PDT 24
Peak memory 196772 kb
Host smart-1fce2f71-b6dc-437b-88c4-ab2909f94b12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933940991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2933940991
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2263747374
Short name T272
Test name
Test status
Simulation time 320425909 ps
CPU time 2.15 seconds
Started Aug 14 04:44:29 PM PDT 24
Finished Aug 14 04:44:32 PM PDT 24
Peak memory 198060 kb
Host smart-4d017388-9715-4df4-84fa-db58bc59c377
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263747374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2263747374
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1479734343
Short name T376
Test name
Test status
Simulation time 121624802 ps
CPU time 0.97 seconds
Started Aug 14 04:43:50 PM PDT 24
Finished Aug 14 04:43:52 PM PDT 24
Peak memory 195708 kb
Host smart-710fa6f6-2505-4a06-b4cc-db6fdf9e09d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479734343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1479734343
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1193336158
Short name T649
Test name
Test status
Simulation time 43166709 ps
CPU time 1.27 seconds
Started Aug 14 04:43:58 PM PDT 24
Finished Aug 14 04:43:59 PM PDT 24
Peak memory 196928 kb
Host smart-3187d27a-d23f-418b-b1aa-a6e4bd4ca0a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193336158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1193336158
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.548872772
Short name T388
Test name
Test status
Simulation time 16542150377 ps
CPU time 100.2 seconds
Started Aug 14 04:43:55 PM PDT 24
Finished Aug 14 04:45:35 PM PDT 24
Peak memory 198344 kb
Host smart-dc54fb25-f53e-449e-aa42-6e29de6f341c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548872772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.548872772
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.654991178
Short name T468
Test name
Test status
Simulation time 4837552699 ps
CPU time 84.14 seconds
Started Aug 14 04:43:56 PM PDT 24
Finished Aug 14 04:45:20 PM PDT 24
Peak memory 198556 kb
Host smart-c54f0c98-e2db-4bf4-8cb2-20f980579462
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=654991178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.654991178
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3305635349
Short name T693
Test name
Test status
Simulation time 12540348 ps
CPU time 0.66 seconds
Started Aug 14 04:44:01 PM PDT 24
Finished Aug 14 04:44:02 PM PDT 24
Peak memory 194092 kb
Host smart-ad36e066-e65d-4c57-a28e-43a31fa08e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305635349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3305635349
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.751050194
Short name T650
Test name
Test status
Simulation time 24956966 ps
CPU time 0.78 seconds
Started Aug 14 04:43:59 PM PDT 24
Finished Aug 14 04:44:00 PM PDT 24
Peak memory 195316 kb
Host smart-1c0120bc-26ce-480a-b47c-97df2efe7b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751050194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.751050194
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1526740002
Short name T273
Test name
Test status
Simulation time 1193393515 ps
CPU time 20.38 seconds
Started Aug 14 04:43:56 PM PDT 24
Finished Aug 14 04:44:16 PM PDT 24
Peak memory 196860 kb
Host smart-810777ad-330a-482e-ae0e-7f9589d4d8e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526740002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1526740002
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.760831540
Short name T698
Test name
Test status
Simulation time 118989989 ps
CPU time 0.99 seconds
Started Aug 14 04:44:02 PM PDT 24
Finished Aug 14 04:44:03 PM PDT 24
Peak memory 197848 kb
Host smart-dfa1f948-3344-4389-8a8d-d94d5f3a7ecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760831540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.760831540
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3305987041
Short name T673
Test name
Test status
Simulation time 87034973 ps
CPU time 3.42 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 198156 kb
Host smart-92f0ddf3-5f04-45cb-a660-c8b1482d9c4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305987041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3305987041
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1218607983
Short name T257
Test name
Test status
Simulation time 1103625506 ps
CPU time 3.43 seconds
Started Aug 14 04:43:52 PM PDT 24
Finished Aug 14 04:43:56 PM PDT 24
Peak memory 198192 kb
Host smart-e3f14e96-1d04-489a-99b4-622e24d626af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218607983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1218607983
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.729556972
Short name T59
Test name
Test status
Simulation time 121613557 ps
CPU time 0.72 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:43:58 PM PDT 24
Peak memory 194396 kb
Host smart-ffe0d5d0-4822-435f-ac80-e5ae40fabb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729556972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.729556972
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.870440951
Short name T669
Test name
Test status
Simulation time 37541371 ps
CPU time 0.88 seconds
Started Aug 14 04:44:02 PM PDT 24
Finished Aug 14 04:44:03 PM PDT 24
Peak memory 196532 kb
Host smart-7fb0cc71-27be-4503-afbe-0ad5ae95f7f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870440951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.870440951
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2892661781
Short name T503
Test name
Test status
Simulation time 765787635 ps
CPU time 3.35 seconds
Started Aug 14 04:43:56 PM PDT 24
Finished Aug 14 04:43:59 PM PDT 24
Peak memory 198192 kb
Host smart-dac6fda4-53df-4398-9440-6cb0934e4a78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892661781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2892661781
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2251279291
Short name T622
Test name
Test status
Simulation time 82174225 ps
CPU time 1.21 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:05 PM PDT 24
Peak memory 195896 kb
Host smart-c2885300-a4a7-4e05-9d35-19e5818983a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251279291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2251279291
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2025387140
Short name T625
Test name
Test status
Simulation time 190627495 ps
CPU time 0.96 seconds
Started Aug 14 04:44:05 PM PDT 24
Finished Aug 14 04:44:06 PM PDT 24
Peak memory 195720 kb
Host smart-a1d58601-a861-4a8c-99e5-a38c3b354af0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025387140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2025387140
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2045617149
Short name T488
Test name
Test status
Simulation time 41791441295 ps
CPU time 144.13 seconds
Started Aug 14 04:44:01 PM PDT 24
Finished Aug 14 04:46:25 PM PDT 24
Peak memory 198296 kb
Host smart-455572d9-c234-4d3a-94fb-f6216704003c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045617149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2045617149
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1725009880
Short name T68
Test name
Test status
Simulation time 3150775814 ps
CPU time 104.82 seconds
Started Aug 14 04:44:20 PM PDT 24
Finished Aug 14 04:46:05 PM PDT 24
Peak memory 198332 kb
Host smart-1751cae6-89c5-497c-bfbf-d5168e957436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1725009880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1725009880
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1146975198
Short name T472
Test name
Test status
Simulation time 18693889 ps
CPU time 0.56 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:05 PM PDT 24
Peak memory 194772 kb
Host smart-fe25b247-cbd3-4a00-a997-f0c33de42ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146975198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1146975198
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.321913790
Short name T679
Test name
Test status
Simulation time 117457764 ps
CPU time 0.81 seconds
Started Aug 14 04:43:54 PM PDT 24
Finished Aug 14 04:43:55 PM PDT 24
Peak memory 196672 kb
Host smart-48bd7c8a-a8c4-41aa-b6ce-bf4b2ccf4ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321913790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.321913790
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.4084197102
Short name T218
Test name
Test status
Simulation time 1873572442 ps
CPU time 15.85 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 195700 kb
Host smart-603c403e-911b-4616-9dd8-fc2c8fb8e353
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084197102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.4084197102
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1780665739
Short name T631
Test name
Test status
Simulation time 71520236 ps
CPU time 0.95 seconds
Started Aug 14 04:44:31 PM PDT 24
Finished Aug 14 04:44:32 PM PDT 24
Peak memory 198004 kb
Host smart-c91d40c4-960e-4d2d-b7c1-b16321861819
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780665739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1780665739
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3180587307
Short name T594
Test name
Test status
Simulation time 396780693 ps
CPU time 1.04 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:05 PM PDT 24
Peak memory 196008 kb
Host smart-aec5283b-f74c-41cb-8784-28562b1cfb23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180587307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3180587307
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3747041666
Short name T593
Test name
Test status
Simulation time 65529507 ps
CPU time 2.4 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:09 PM PDT 24
Peak memory 197952 kb
Host smart-4472f65b-b30d-470c-bb40-3bc77436e9e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747041666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3747041666
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2393882170
Short name T626
Test name
Test status
Simulation time 97849755 ps
CPU time 3 seconds
Started Aug 14 04:44:08 PM PDT 24
Finished Aug 14 04:44:11 PM PDT 24
Peak memory 197140 kb
Host smart-42f5dddd-d38a-41f9-a01a-3d12af102e21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393882170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2393882170
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1091377779
Short name T552
Test name
Test status
Simulation time 24657740 ps
CPU time 0.93 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:43:58 PM PDT 24
Peak memory 196012 kb
Host smart-3bbb00f6-e4c1-4257-a060-72e1a2b37445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091377779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1091377779
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3842873530
Short name T113
Test name
Test status
Simulation time 43516001 ps
CPU time 0.66 seconds
Started Aug 14 04:44:25 PM PDT 24
Finished Aug 14 04:44:26 PM PDT 24
Peak memory 194468 kb
Host smart-78f091ed-9c8a-4720-9fa0-ff638c8ed991
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842873530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3842873530
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.612908544
Short name T19
Test name
Test status
Simulation time 798301851 ps
CPU time 5.5 seconds
Started Aug 14 04:44:01 PM PDT 24
Finished Aug 14 04:44:06 PM PDT 24
Peak memory 198180 kb
Host smart-00a27df3-ad64-4ee1-9955-16c49841ae64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612908544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.612908544
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3270994065
Short name T202
Test name
Test status
Simulation time 282343878 ps
CPU time 1.05 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:05 PM PDT 24
Peak memory 196424 kb
Host smart-b31ffcf7-3e61-473c-93e6-fc15b57046d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270994065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3270994065
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.663454267
Short name T331
Test name
Test status
Simulation time 207843127 ps
CPU time 0.94 seconds
Started Aug 14 04:44:06 PM PDT 24
Finished Aug 14 04:44:07 PM PDT 24
Peak memory 196556 kb
Host smart-ff6e94a3-5873-4942-92cd-ac37770c97b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663454267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.663454267
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.103309166
Short name T61
Test name
Test status
Simulation time 23049285618 ps
CPU time 151.04 seconds
Started Aug 14 04:44:09 PM PDT 24
Finished Aug 14 04:46:41 PM PDT 24
Peak memory 198428 kb
Host smart-69b785b4-fedc-4956-a1cd-c6a7f7edc897
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103309166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.103309166
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2132128180
Short name T212
Test name
Test status
Simulation time 23570581 ps
CPU time 0.57 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:10 PM PDT 24
Peak memory 194220 kb
Host smart-0479f2da-b632-4a54-8038-38e02088d7fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132128180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2132128180
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.417093961
Short name T323
Test name
Test status
Simulation time 48914634 ps
CPU time 0.75 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:08 PM PDT 24
Peak memory 196220 kb
Host smart-c325d428-4b10-4927-9aa1-cec2c839e1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417093961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.417093961
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.991825945
Short name T256
Test name
Test status
Simulation time 465473670 ps
CPU time 23.71 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:28 PM PDT 24
Peak memory 198220 kb
Host smart-2942dd01-a060-47d8-b69a-c7a4a411ca4c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991825945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.991825945
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3463876387
Short name T53
Test name
Test status
Simulation time 114429625 ps
CPU time 0.96 seconds
Started Aug 14 04:44:06 PM PDT 24
Finished Aug 14 04:44:07 PM PDT 24
Peak memory 196012 kb
Host smart-4ca9377a-71b9-4b61-b5af-262d51cff5b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463876387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3463876387
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2014919105
Short name T565
Test name
Test status
Simulation time 74592863 ps
CPU time 1.18 seconds
Started Aug 14 04:44:00 PM PDT 24
Finished Aug 14 04:44:01 PM PDT 24
Peak memory 196904 kb
Host smart-729aafb9-5689-4f6a-8679-2d650350f45b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014919105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2014919105
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.841711673
Short name T522
Test name
Test status
Simulation time 54845754 ps
CPU time 2.16 seconds
Started Aug 14 04:44:09 PM PDT 24
Finished Aug 14 04:44:12 PM PDT 24
Peak memory 198136 kb
Host smart-0109380b-9032-42f2-8411-b1b5e4a6c5b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841711673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.841711673
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.143832143
Short name T571
Test name
Test status
Simulation time 118596455 ps
CPU time 3.54 seconds
Started Aug 14 04:44:09 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 197372 kb
Host smart-ee4bef21-5c96-41b4-bfc1-58cf69950928
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143832143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
143832143
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2984468991
Short name T635
Test name
Test status
Simulation time 288535691 ps
CPU time 0.84 seconds
Started Aug 14 04:44:08 PM PDT 24
Finished Aug 14 04:44:09 PM PDT 24
Peak memory 196736 kb
Host smart-035a848f-b92b-4d26-ad22-457284fd49aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984468991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2984468991
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2949604337
Short name T201
Test name
Test status
Simulation time 44972994 ps
CPU time 0.97 seconds
Started Aug 14 04:44:01 PM PDT 24
Finished Aug 14 04:44:02 PM PDT 24
Peak memory 196708 kb
Host smart-dab58b5a-0fdb-4bbb-b94b-a034c804cde4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949604337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2949604337
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1113412659
Short name T125
Test name
Test status
Simulation time 356275168 ps
CPU time 3.57 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 198004 kb
Host smart-1bf4a8c3-f01b-4b76-8dbf-9a8ea6eee7b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113412659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1113412659
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.4040932804
Short name T568
Test name
Test status
Simulation time 31039564 ps
CPU time 0.81 seconds
Started Aug 14 04:44:03 PM PDT 24
Finished Aug 14 04:44:04 PM PDT 24
Peak memory 195144 kb
Host smart-320f18fe-12b2-4af8-baa2-eff259e25171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040932804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.4040932804
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2788055089
Short name T275
Test name
Test status
Simulation time 245939424 ps
CPU time 0.96 seconds
Started Aug 14 04:44:13 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 196312 kb
Host smart-c95cd25a-51f5-4843-9a01-3277e1199fbb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788055089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2788055089
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1208745978
Short name T7
Test name
Test status
Simulation time 8881489110 ps
CPU time 94.89 seconds
Started Aug 14 04:44:06 PM PDT 24
Finished Aug 14 04:45:41 PM PDT 24
Peak memory 198272 kb
Host smart-36ab3b93-708e-4f7d-82a2-d6ed73adb7c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208745978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1208745978
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2404732063
Short name T66
Test name
Test status
Simulation time 18401864327 ps
CPU time 146.71 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:46:40 PM PDT 24
Peak memory 198556 kb
Host smart-41721dff-4bc9-49d6-8a85-894c23978f67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2404732063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2404732063
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3649850736
Short name T689
Test name
Test status
Simulation time 39611845 ps
CPU time 0.58 seconds
Started Aug 14 04:44:02 PM PDT 24
Finished Aug 14 04:44:03 PM PDT 24
Peak memory 194084 kb
Host smart-8ba0676f-68ca-4944-8378-2d21e339a815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649850736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3649850736
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.530020890
Short name T211
Test name
Test status
Simulation time 46531480 ps
CPU time 0.94 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 195896 kb
Host smart-a0c42f8f-a51e-4bae-9b8b-b976b367636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530020890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.530020890
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2866116723
Short name T555
Test name
Test status
Simulation time 200828411 ps
CPU time 10.64 seconds
Started Aug 14 04:44:03 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 196900 kb
Host smart-f73b5312-645e-4d48-99aa-289208e16696
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866116723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2866116723
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2987453943
Short name T163
Test name
Test status
Simulation time 102220396 ps
CPU time 0.63 seconds
Started Aug 14 04:44:16 PM PDT 24
Finished Aug 14 04:44:17 PM PDT 24
Peak memory 194316 kb
Host smart-acc27fcf-d4de-4132-9d1a-aee31f29f023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987453943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2987453943
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.72572313
Short name T355
Test name
Test status
Simulation time 166337091 ps
CPU time 1.14 seconds
Started Aug 14 04:44:18 PM PDT 24
Finished Aug 14 04:44:19 PM PDT 24
Peak memory 196988 kb
Host smart-52c9cf05-b2ef-4049-a52a-c090fab95388
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72572313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.72572313
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2205223970
Short name T687
Test name
Test status
Simulation time 135348345 ps
CPU time 2.68 seconds
Started Aug 14 04:44:18 PM PDT 24
Finished Aug 14 04:44:21 PM PDT 24
Peak memory 198228 kb
Host smart-0622d6a4-fd9f-408c-bb48-8e858b30135a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205223970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2205223970
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3197042268
Short name T493
Test name
Test status
Simulation time 45410656 ps
CPU time 1.17 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:08 PM PDT 24
Peak memory 195856 kb
Host smart-8f23fbfb-c133-46ee-93f4-6fddfdc569af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197042268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3197042268
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1498069321
Short name T448
Test name
Test status
Simulation time 71273823 ps
CPU time 0.77 seconds
Started Aug 14 04:44:03 PM PDT 24
Finished Aug 14 04:44:04 PM PDT 24
Peak memory 195652 kb
Host smart-733e1874-0d13-48ac-a1d6-2dad6d689cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498069321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1498069321
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3981837671
Short name T329
Test name
Test status
Simulation time 50110651 ps
CPU time 1.09 seconds
Started Aug 14 04:44:05 PM PDT 24
Finished Aug 14 04:44:06 PM PDT 24
Peak memory 196196 kb
Host smart-c77b5371-7b73-4903-9711-7edf58d64bd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981837671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3981837671
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.886249466
Short name T133
Test name
Test status
Simulation time 573661474 ps
CPU time 2.72 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:17 PM PDT 24
Peak memory 198096 kb
Host smart-00e93bab-cff0-4762-9bdd-a2040973d3b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886249466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.886249466
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3761574302
Short name T643
Test name
Test status
Simulation time 118887313 ps
CPU time 1.06 seconds
Started Aug 14 04:44:03 PM PDT 24
Finished Aug 14 04:44:04 PM PDT 24
Peak memory 195792 kb
Host smart-9fe26a7a-3289-4cd4-8967-d3d309bfb53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761574302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3761574302
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2568289834
Short name T449
Test name
Test status
Simulation time 90133698 ps
CPU time 1.26 seconds
Started Aug 14 04:44:05 PM PDT 24
Finished Aug 14 04:44:06 PM PDT 24
Peak memory 195676 kb
Host smart-00c5cac4-606a-4200-a285-c370688eb4f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568289834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2568289834
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1814917170
Short name T324
Test name
Test status
Simulation time 14661838957 ps
CPU time 176.65 seconds
Started Aug 14 04:43:59 PM PDT 24
Finished Aug 14 04:46:56 PM PDT 24
Peak memory 198316 kb
Host smart-d7e3c2d3-28b8-4d66-9413-5a915b577ef4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814917170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1814917170
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.2642809712
Short name T636
Test name
Test status
Simulation time 14254566109 ps
CPU time 123.56 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:46:08 PM PDT 24
Peak memory 198588 kb
Host smart-1d8d66e9-0f9c-4760-a2c3-5f6d1a8584a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2642809712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.2642809712
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2579185994
Short name T294
Test name
Test status
Simulation time 12764795 ps
CPU time 0.56 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:11 PM PDT 24
Peak memory 194064 kb
Host smart-facba1ff-02e9-4e8b-9832-a7a266c84827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579185994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2579185994
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3906459543
Short name T592
Test name
Test status
Simulation time 137759923 ps
CPU time 0.89 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:05 PM PDT 24
Peak memory 197364 kb
Host smart-ba76d73c-b548-4ed4-a558-3a620450d57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906459543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3906459543
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3148850398
Short name T221
Test name
Test status
Simulation time 1277527964 ps
CPU time 23.45 seconds
Started Aug 14 04:44:03 PM PDT 24
Finished Aug 14 04:44:26 PM PDT 24
Peak memory 196796 kb
Host smart-ecca1529-72ba-479a-a2c0-94ff45977bd3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148850398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3148850398
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2822189079
Short name T387
Test name
Test status
Simulation time 377447883 ps
CPU time 0.74 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:08 PM PDT 24
Peak memory 195784 kb
Host smart-727fb222-aefd-495f-b312-b64ad2c1ed4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822189079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2822189079
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2037042807
Short name T523
Test name
Test status
Simulation time 27607648 ps
CPU time 0.86 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:16 PM PDT 24
Peak memory 196824 kb
Host smart-2e78b977-409f-466c-8203-0f1fd903e3e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037042807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2037042807
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3529884133
Short name T621
Test name
Test status
Simulation time 319815938 ps
CPU time 2.85 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 196452 kb
Host smart-7fc446f8-81ce-4e25-8fdb-3edb414be07d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529884133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3529884133
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3345462139
Short name T182
Test name
Test status
Simulation time 193739903 ps
CPU time 1.18 seconds
Started Aug 14 04:44:02 PM PDT 24
Finished Aug 14 04:44:03 PM PDT 24
Peak memory 197524 kb
Host smart-28d1f5c1-254d-4ec0-8d56-23ca24b0337a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345462139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3345462139
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3387048221
Short name T543
Test name
Test status
Simulation time 31291079 ps
CPU time 0.72 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:12 PM PDT 24
Peak memory 195540 kb
Host smart-34fef5f7-2a72-4498-acff-20a1c045342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387048221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3387048221
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2232755333
Short name T705
Test name
Test status
Simulation time 48097796 ps
CPU time 0.72 seconds
Started Aug 14 04:44:08 PM PDT 24
Finished Aug 14 04:44:09 PM PDT 24
Peak memory 195596 kb
Host smart-de43a23f-a76c-4f7a-8369-b4ef5f76f03a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232755333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2232755333
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.271271917
Short name T453
Test name
Test status
Simulation time 284099516 ps
CPU time 4.9 seconds
Started Aug 14 04:43:58 PM PDT 24
Finished Aug 14 04:44:03 PM PDT 24
Peak memory 198156 kb
Host smart-ae3907d2-59f0-4930-ba25-0219ee61c733
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271271917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.271271917
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1924436298
Short name T197
Test name
Test status
Simulation time 86084417 ps
CPU time 1.28 seconds
Started Aug 14 04:44:05 PM PDT 24
Finished Aug 14 04:44:06 PM PDT 24
Peak memory 197088 kb
Host smart-866c8eaa-4b28-460c-b3de-9bc4351f0cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924436298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1924436298
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3781358094
Short name T455
Test name
Test status
Simulation time 57035552 ps
CPU time 1.16 seconds
Started Aug 14 04:44:00 PM PDT 24
Finished Aug 14 04:44:01 PM PDT 24
Peak memory 195912 kb
Host smart-306ee942-5c71-44be-98d8-fc2cf1db21e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781358094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3781358094
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1971675047
Short name T314
Test name
Test status
Simulation time 17752261579 ps
CPU time 128.52 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:46:16 PM PDT 24
Peak memory 198276 kb
Host smart-17498abb-6db9-42fd-bd5f-e1db30617305
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971675047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1971675047
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2021679774
Short name T69
Test name
Test status
Simulation time 2635807875 ps
CPU time 87.34 seconds
Started Aug 14 04:44:06 PM PDT 24
Finished Aug 14 04:45:34 PM PDT 24
Peak memory 197868 kb
Host smart-2aeb289e-9b3d-496c-b10f-025706ca3ebc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2021679774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2021679774
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.4070353257
Short name T532
Test name
Test status
Simulation time 33048608 ps
CPU time 0.57 seconds
Started Aug 14 04:43:58 PM PDT 24
Finished Aug 14 04:43:58 PM PDT 24
Peak memory 194788 kb
Host smart-22716fd9-e12c-4159-b37d-e8b21011bf57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070353257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.4070353257
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1050883599
Short name T138
Test name
Test status
Simulation time 58754720 ps
CPU time 0.74 seconds
Started Aug 14 04:44:02 PM PDT 24
Finished Aug 14 04:44:03 PM PDT 24
Peak memory 196088 kb
Host smart-662fc9c4-4339-4849-b205-e42bd3635363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050883599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1050883599
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2469604239
Short name T293
Test name
Test status
Simulation time 927952305 ps
CPU time 17.05 seconds
Started Aug 14 04:44:17 PM PDT 24
Finished Aug 14 04:44:34 PM PDT 24
Peak memory 195688 kb
Host smart-405a5373-87f8-4ace-bd85-b7bd3d70eaff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469604239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2469604239
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.200169415
Short name T130
Test name
Test status
Simulation time 378522924 ps
CPU time 0.68 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:07 PM PDT 24
Peak memory 194848 kb
Host smart-0fea55fe-dcff-408d-8d89-8869f9f1dfdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200169415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.200169415
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3806041939
Short name T262
Test name
Test status
Simulation time 232910131 ps
CPU time 1.02 seconds
Started Aug 14 04:44:05 PM PDT 24
Finished Aug 14 04:44:06 PM PDT 24
Peak memory 195912 kb
Host smart-d9050b41-441a-4091-a378-f40294fefb80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806041939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3806041939
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2216732599
Short name T617
Test name
Test status
Simulation time 235591592 ps
CPU time 1.5 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:12 PM PDT 24
Peak memory 196740 kb
Host smart-e66c88ac-97d5-4091-a1e2-ad5af27697f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216732599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2216732599
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.420005807
Short name T478
Test name
Test status
Simulation time 103964788 ps
CPU time 2.1 seconds
Started Aug 14 04:43:59 PM PDT 24
Finished Aug 14 04:44:01 PM PDT 24
Peak memory 196156 kb
Host smart-b2ae79c8-1422-4490-bf5a-3eb45e73fce3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420005807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
420005807
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1952017232
Short name T165
Test name
Test status
Simulation time 130462134 ps
CPU time 0.72 seconds
Started Aug 14 04:44:01 PM PDT 24
Finished Aug 14 04:44:02 PM PDT 24
Peak memory 196228 kb
Host smart-d6863a6f-c11b-4596-b5b0-5cde1f7ca465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952017232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1952017232
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3213062676
Short name T557
Test name
Test status
Simulation time 56431714 ps
CPU time 0.81 seconds
Started Aug 14 04:43:55 PM PDT 24
Finished Aug 14 04:43:56 PM PDT 24
Peak memory 196308 kb
Host smart-6bc24b43-a480-43dc-a818-4249d05d43bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213062676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3213062676
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2597476920
Short name T311
Test name
Test status
Simulation time 514397354 ps
CPU time 4.25 seconds
Started Aug 14 04:44:08 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 198124 kb
Host smart-7d914f00-a6e2-4938-a4d3-2ea0a70fe094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597476920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2597476920
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1483025800
Short name T465
Test name
Test status
Simulation time 149982577 ps
CPU time 0.94 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:11 PM PDT 24
Peak memory 196596 kb
Host smart-97aec47b-8588-4db4-a70b-96e5dec78d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483025800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1483025800
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1219195380
Short name T107
Test name
Test status
Simulation time 225416320 ps
CPU time 1.39 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:09 PM PDT 24
Peak memory 196308 kb
Host smart-44a180b9-f081-4747-adf8-dd8b3b4e2060
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219195380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1219195380
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3722470385
Short name T589
Test name
Test status
Simulation time 19515627265 ps
CPU time 62.35 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:45:14 PM PDT 24
Peak memory 198316 kb
Host smart-5f5e533f-6176-424b-8706-aa4d9cba20c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722470385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3722470385
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1375176068
Short name T63
Test name
Test status
Simulation time 1416967210 ps
CPU time 23.88 seconds
Started Aug 14 04:43:59 PM PDT 24
Finished Aug 14 04:44:23 PM PDT 24
Peak memory 197516 kb
Host smart-9a3da84b-be69-4dba-ad38-2a071b8aa10a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1375176068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1375176068
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2686463734
Short name T510
Test name
Test status
Simulation time 38082305 ps
CPU time 0.6 seconds
Started Aug 14 04:44:17 PM PDT 24
Finished Aug 14 04:44:17 PM PDT 24
Peak memory 193992 kb
Host smart-c26db324-ed3d-42c5-8570-70ed2d8095fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686463734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2686463734
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3861043357
Short name T40
Test name
Test status
Simulation time 15571199 ps
CPU time 0.65 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:43:58 PM PDT 24
Peak memory 194716 kb
Host smart-2bf367ed-07a9-4549-b01b-b89a76de1271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861043357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3861043357
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.112885018
Short name T384
Test name
Test status
Simulation time 716021434 ps
CPU time 24.37 seconds
Started Aug 14 04:44:27 PM PDT 24
Finished Aug 14 04:44:52 PM PDT 24
Peak memory 198024 kb
Host smart-6c38815e-d3fb-42e6-a5bc-946832f01610
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112885018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.112885018
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.541520425
Short name T404
Test name
Test status
Simulation time 226547995 ps
CPU time 0.83 seconds
Started Aug 14 04:44:13 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 196140 kb
Host smart-7097726d-707d-41de-807d-241fbacd7d4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541520425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.541520425
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2789112411
Short name T600
Test name
Test status
Simulation time 124387003 ps
CPU time 0.75 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:44:16 PM PDT 24
Peak memory 195612 kb
Host smart-e518f916-2215-4773-9985-cc4e1f6cb6a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789112411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2789112411
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2989748723
Short name T566
Test name
Test status
Simulation time 166631707 ps
CPU time 1.96 seconds
Started Aug 14 04:44:13 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 198196 kb
Host smart-69884833-c7a1-4e74-8dc3-6ae2967b81f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989748723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2989748723
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2682482347
Short name T603
Test name
Test status
Simulation time 29123916 ps
CPU time 0.87 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:10 PM PDT 24
Peak memory 194548 kb
Host smart-c8e41dad-c2cc-46c1-9cd7-5cb1ca0a251d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682482347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2682482347
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2624856022
Short name T354
Test name
Test status
Simulation time 32588430 ps
CPU time 0.82 seconds
Started Aug 14 04:44:03 PM PDT 24
Finished Aug 14 04:44:04 PM PDT 24
Peak memory 195524 kb
Host smart-45f4f44b-3870-44f5-bca9-3a6d4c7ead6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624856022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2624856022
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2639227540
Short name T348
Test name
Test status
Simulation time 45209538 ps
CPU time 0.99 seconds
Started Aug 14 04:44:01 PM PDT 24
Finished Aug 14 04:44:02 PM PDT 24
Peak memory 196168 kb
Host smart-b1381f32-a75b-4fba-9320-8a604e36048e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639227540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2639227540
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1631706889
Short name T287
Test name
Test status
Simulation time 334106516 ps
CPU time 5.36 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:17 PM PDT 24
Peak memory 198144 kb
Host smart-9dfb6553-02ae-4dd9-bc2f-3912165cf88c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631706889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1631706889
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3737554583
Short name T646
Test name
Test status
Simulation time 77049065 ps
CPU time 1.32 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:43:58 PM PDT 24
Peak memory 196892 kb
Host smart-d7d25a8c-4101-4685-aadc-116c62291528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737554583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3737554583
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2061246971
Short name T524
Test name
Test status
Simulation time 114316000 ps
CPU time 0.83 seconds
Started Aug 14 04:43:53 PM PDT 24
Finished Aug 14 04:43:56 PM PDT 24
Peak memory 195456 kb
Host smart-9817d52c-9a58-4af8-b433-983180c3206b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061246971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2061246971
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.723387605
Short name T208
Test name
Test status
Simulation time 25666113781 ps
CPU time 146.04 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:46:40 PM PDT 24
Peak memory 198260 kb
Host smart-443dc08c-f203-45d8-a503-a1adc8b0246c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723387605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.723387605
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.968304052
Short name T134
Test name
Test status
Simulation time 12895151 ps
CPU time 0.57 seconds
Started Aug 14 04:44:30 PM PDT 24
Finished Aug 14 04:44:30 PM PDT 24
Peak memory 193992 kb
Host smart-6872a2e8-fea5-4329-bbbb-b4d87c2943b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968304052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.968304052
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3019237798
Short name T228
Test name
Test status
Simulation time 51430964 ps
CPU time 0.94 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:11 PM PDT 24
Peak memory 196212 kb
Host smart-3122660c-451e-40ed-b158-84cb308e0396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019237798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3019237798
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1206339558
Short name T428
Test name
Test status
Simulation time 174830421 ps
CPU time 4.36 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:23 PM PDT 24
Peak memory 196100 kb
Host smart-e8c6a074-9f89-41f6-8f89-820c08a8ff38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206339558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1206339558
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.4065592147
Short name T529
Test name
Test status
Simulation time 162740664 ps
CPU time 1.07 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:44:16 PM PDT 24
Peak memory 196724 kb
Host smart-062edd22-7d5c-46ee-8f70-a0579bc23633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065592147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.4065592147
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1758460088
Short name T427
Test name
Test status
Simulation time 24214235 ps
CPU time 0.72 seconds
Started Aug 14 04:44:05 PM PDT 24
Finished Aug 14 04:44:06 PM PDT 24
Peak memory 194372 kb
Host smart-172e1367-773c-46d8-bd34-d8d97c58f4b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758460088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1758460088
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1577240492
Short name T688
Test name
Test status
Simulation time 117911692 ps
CPU time 1.22 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:12 PM PDT 24
Peak memory 196916 kb
Host smart-4cad37b5-abb2-4b71-b10c-3d8dd4ba81fb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577240492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1577240492
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1346296433
Short name T238
Test name
Test status
Simulation time 360672858 ps
CPU time 2.54 seconds
Started Aug 14 04:44:22 PM PDT 24
Finished Aug 14 04:44:25 PM PDT 24
Peak memory 196912 kb
Host smart-0fab0d6e-6401-452e-bcab-70fe776d56ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346296433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1346296433
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1769347628
Short name T196
Test name
Test status
Simulation time 100116829 ps
CPU time 1.07 seconds
Started Aug 14 04:44:08 PM PDT 24
Finished Aug 14 04:44:09 PM PDT 24
Peak memory 196744 kb
Host smart-6068a09f-a5b9-4306-b553-723ff709fedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769347628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1769347628
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2945997788
Short name T629
Test name
Test status
Simulation time 233306870 ps
CPU time 1.22 seconds
Started Aug 14 04:44:09 PM PDT 24
Finished Aug 14 04:44:11 PM PDT 24
Peak memory 196756 kb
Host smart-7d2b8a4a-53b6-482d-b72d-36ea3962fcd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945997788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2945997788
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2446393420
Short name T385
Test name
Test status
Simulation time 783260971 ps
CPU time 2.3 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 198132 kb
Host smart-a4381566-ceea-4f8b-bfef-040e2bdc5742
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446393420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2446393420
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.541764021
Short name T630
Test name
Test status
Simulation time 329438084 ps
CPU time 1.5 seconds
Started Aug 14 04:44:20 PM PDT 24
Finished Aug 14 04:44:22 PM PDT 24
Peak memory 196980 kb
Host smart-92cf1bd9-64f7-49bf-8899-d2f8fc7d0da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541764021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.541764021
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.178880519
Short name T190
Test name
Test status
Simulation time 50732750 ps
CPU time 0.95 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 197356 kb
Host smart-259bc984-b9af-451e-8dc4-b251c3878815
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178880519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.178880519
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1142527318
Short name T301
Test name
Test status
Simulation time 3134298953 ps
CPU time 94.13 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:45:45 PM PDT 24
Peak memory 198296 kb
Host smart-6a4c75f5-07ae-46dc-a630-7a85e5fe8920
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142527318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1142527318
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.397888279
Short name T253
Test name
Test status
Simulation time 15222813 ps
CPU time 0.57 seconds
Started Aug 14 04:43:53 PM PDT 24
Finished Aug 14 04:43:53 PM PDT 24
Peak memory 194984 kb
Host smart-1c3add35-b125-4a6b-be7f-f77d44cbaecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397888279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.397888279
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.4077189262
Short name T223
Test name
Test status
Simulation time 37495734 ps
CPU time 0.61 seconds
Started Aug 14 04:43:26 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 194124 kb
Host smart-b3937291-a5ce-4e24-8370-a9a195f6a00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077189262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.4077189262
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.394509942
Short name T451
Test name
Test status
Simulation time 1954662210 ps
CPU time 17.86 seconds
Started Aug 14 04:43:50 PM PDT 24
Finished Aug 14 04:44:08 PM PDT 24
Peak memory 197132 kb
Host smart-870a16ca-57c9-4087-bd76-231bd0903c97
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394509942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.394509942
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3950134486
Short name T476
Test name
Test status
Simulation time 65439168 ps
CPU time 0.72 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 194868 kb
Host smart-51b33c4f-20a4-412c-bd2e-b5e464fde689
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950134486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3950134486
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2594084535
Short name T97
Test name
Test status
Simulation time 167890904 ps
CPU time 1.21 seconds
Started Aug 14 04:43:47 PM PDT 24
Finished Aug 14 04:43:48 PM PDT 24
Peak memory 195988 kb
Host smart-3d70e12a-ce14-4e8c-a094-abfc4f33a7b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594084535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2594084535
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2770456770
Short name T291
Test name
Test status
Simulation time 27445643 ps
CPU time 1.17 seconds
Started Aug 14 04:43:51 PM PDT 24
Finished Aug 14 04:43:52 PM PDT 24
Peak memory 198068 kb
Host smart-929a629e-ee3f-4f92-a069-03d7c9ddd57d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770456770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2770456770
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.4047972179
Short name T118
Test name
Test status
Simulation time 276262458 ps
CPU time 2.64 seconds
Started Aug 14 04:43:50 PM PDT 24
Finished Aug 14 04:43:53 PM PDT 24
Peak memory 198252 kb
Host smart-86dae0a8-27f9-49db-a6df-dadb1b0528de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047972179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
4047972179
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2984033070
Short name T667
Test name
Test status
Simulation time 76915804 ps
CPU time 1.26 seconds
Started Aug 14 04:43:37 PM PDT 24
Finished Aug 14 04:43:38 PM PDT 24
Peak memory 195992 kb
Host smart-31c320e6-e5ac-4c89-841f-309b61a7664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984033070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2984033070
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2733564292
Short name T656
Test name
Test status
Simulation time 24517791 ps
CPU time 0.8 seconds
Started Aug 14 04:43:41 PM PDT 24
Finished Aug 14 04:43:42 PM PDT 24
Peak memory 196580 kb
Host smart-8cc59994-7245-4b20-b8bc-7395f00889d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733564292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2733564292
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.4153720783
Short name T657
Test name
Test status
Simulation time 66573382 ps
CPU time 2.9 seconds
Started Aug 14 04:43:23 PM PDT 24
Finished Aug 14 04:43:31 PM PDT 24
Peak memory 198188 kb
Host smart-7bfb3183-6340-437b-9f31-4bec368b109e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153720783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.4153720783
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1320868240
Short name T55
Test name
Test status
Simulation time 146979481 ps
CPU time 0.93 seconds
Started Aug 14 04:43:18 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 215136 kb
Host smart-b6379e54-5a02-47f0-8121-6feda545a8c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320868240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1320868240
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.4062015869
Short name T683
Test name
Test status
Simulation time 48713086 ps
CPU time 1.01 seconds
Started Aug 14 04:43:39 PM PDT 24
Finished Aug 14 04:43:45 PM PDT 24
Peak memory 195920 kb
Host smart-752721b1-e7b4-4e11-b4b7-81bec5132ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062015869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.4062015869
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.505931103
Short name T179
Test name
Test status
Simulation time 77956494 ps
CPU time 1.13 seconds
Started Aug 14 04:43:26 PM PDT 24
Finished Aug 14 04:43:28 PM PDT 24
Peak memory 195912 kb
Host smart-6c41487e-bcba-4ab5-9869-b84d6477f8bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505931103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.505931103
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1178579064
Short name T242
Test name
Test status
Simulation time 5118544646 ps
CPU time 130.72 seconds
Started Aug 14 04:43:39 PM PDT 24
Finished Aug 14 04:45:50 PM PDT 24
Peak memory 198300 kb
Host smart-b9b6aeed-7945-494a-a712-748d61c307a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178579064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1178579064
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1412076846
Short name T58
Test name
Test status
Simulation time 29472921 ps
CPU time 0.58 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:10 PM PDT 24
Peak memory 194148 kb
Host smart-b0ae12ec-80bd-4ce7-96dd-ab3c25cd677d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412076846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1412076846
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2503230015
Short name T11
Test name
Test status
Simulation time 74117668 ps
CPU time 0.79 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 196156 kb
Host smart-e25ae9ca-9c41-48eb-9a49-4cc1c9d40b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503230015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2503230015
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.536934143
Short name T682
Test name
Test status
Simulation time 10205517045 ps
CPU time 25.01 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:35 PM PDT 24
Peak memory 197868 kb
Host smart-456fe081-b9b6-4ef8-b3bf-5bdc27afdf84
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536934143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.536934143
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3996913574
Short name T209
Test name
Test status
Simulation time 93858133 ps
CPU time 0.97 seconds
Started Aug 14 04:44:22 PM PDT 24
Finished Aug 14 04:44:23 PM PDT 24
Peak memory 196556 kb
Host smart-95a6b7f9-1c68-4498-a431-72e9e9f7d194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996913574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3996913574
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3274188696
Short name T584
Test name
Test status
Simulation time 162476631 ps
CPU time 0.9 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:12 PM PDT 24
Peak memory 196200 kb
Host smart-31726d3e-0359-429a-b3c7-b19bf15f3f6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274188696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3274188696
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3499276127
Short name T499
Test name
Test status
Simulation time 254438838 ps
CPU time 2.73 seconds
Started Aug 14 04:44:35 PM PDT 24
Finished Aug 14 04:44:38 PM PDT 24
Peak memory 198068 kb
Host smart-ab24202c-6a71-41e1-bb64-5464b39e21ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499276127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3499276127
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2271685442
Short name T563
Test name
Test status
Simulation time 450267040 ps
CPU time 2.74 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:06 PM PDT 24
Peak memory 198076 kb
Host smart-2362a935-35b2-4424-9856-5f5a29f5d61d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271685442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2271685442
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3907005660
Short name T139
Test name
Test status
Simulation time 129997385 ps
CPU time 0.9 seconds
Started Aug 14 04:44:48 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 196996 kb
Host smart-899d5912-3408-4e7b-a47e-f9d205bc4095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907005660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3907005660
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.20740433
Short name T517
Test name
Test status
Simulation time 65162823 ps
CPU time 1.32 seconds
Started Aug 14 04:44:09 PM PDT 24
Finished Aug 14 04:44:11 PM PDT 24
Peak memory 197028 kb
Host smart-f98ecb8f-0932-410f-b7a5-2e9acdb79cfc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20740433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup_
pulldown.20740433
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2652439052
Short name T538
Test name
Test status
Simulation time 88582743 ps
CPU time 3.08 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:10 PM PDT 24
Peak memory 198168 kb
Host smart-6e41b6d6-a71e-4137-9601-0fe57f0564ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652439052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2652439052
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.4082186242
Short name T454
Test name
Test status
Simulation time 36315948 ps
CPU time 0.91 seconds
Started Aug 14 04:44:08 PM PDT 24
Finished Aug 14 04:44:09 PM PDT 24
Peak memory 195988 kb
Host smart-e4e58c42-d80d-44f2-a62b-21b986a74db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082186242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.4082186242
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.867439662
Short name T171
Test name
Test status
Simulation time 36940946 ps
CPU time 1.01 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 195696 kb
Host smart-5bc107f8-ce7d-4bd4-bc92-0f2f4cf385a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867439662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.867439662
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2177883375
Short name T412
Test name
Test status
Simulation time 3932939200 ps
CPU time 43.08 seconds
Started Aug 14 04:44:09 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 197512 kb
Host smart-1aec073e-92e8-447c-834e-41709a53f04e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177883375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2177883375
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.1540297311
Short name T65
Test name
Test status
Simulation time 6390872483 ps
CPU time 21.81 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:32 PM PDT 24
Peak memory 198584 kb
Host smart-2197c21d-062f-44f6-a0c4-5b920ed3296c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1540297311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.1540297311
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2517175241
Short name T580
Test name
Test status
Simulation time 13408612 ps
CPU time 0.56 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:05 PM PDT 24
Peak memory 194908 kb
Host smart-aa6c8e99-dbc1-4e42-b3d6-1ad5b36c0239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517175241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2517175241
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2988930453
Short name T436
Test name
Test status
Simulation time 37401483 ps
CPU time 0.76 seconds
Started Aug 14 04:44:20 PM PDT 24
Finished Aug 14 04:44:20 PM PDT 24
Peak memory 195292 kb
Host smart-9a58b866-aa12-46b0-9845-89c1105482aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988930453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2988930453
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1736249208
Short name T224
Test name
Test status
Simulation time 363529930 ps
CPU time 18.1 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:28 PM PDT 24
Peak memory 197136 kb
Host smart-040486b9-307a-48ae-a498-8fc6eae1a143
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736249208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1736249208
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.648184208
Short name T581
Test name
Test status
Simulation time 119259946 ps
CPU time 0.91 seconds
Started Aug 14 04:44:25 PM PDT 24
Finished Aug 14 04:44:26 PM PDT 24
Peak memory 197288 kb
Host smart-b9aa48b6-99bb-46a2-b623-674a6c4fc517
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648184208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.648184208
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3007209264
Short name T490
Test name
Test status
Simulation time 173975935 ps
CPU time 1.15 seconds
Started Aug 14 04:44:16 PM PDT 24
Finished Aug 14 04:44:18 PM PDT 24
Peak memory 196620 kb
Host smart-691525f4-7308-4afe-907a-791f4d421f51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007209264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3007209264
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1194253028
Short name T681
Test name
Test status
Simulation time 243404133 ps
CPU time 2.34 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 198088 kb
Host smart-aae0cfaa-cd34-4031-90be-17e425e7cf42
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194253028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1194253028
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1798065466
Short name T641
Test name
Test status
Simulation time 190504274 ps
CPU time 2.11 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:06 PM PDT 24
Peak memory 196916 kb
Host smart-cf7d0539-2f32-4dbd-b3d2-a22bf6c3bd6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798065466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1798065466
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2244966982
Short name T653
Test name
Test status
Simulation time 35781626 ps
CPU time 0.87 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:08 PM PDT 24
Peak memory 195968 kb
Host smart-f2f0028b-3290-4e44-8b31-aa87165d543e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244966982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2244966982
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.411889186
Short name T219
Test name
Test status
Simulation time 65931452 ps
CPU time 1.16 seconds
Started Aug 14 04:44:21 PM PDT 24
Finished Aug 14 04:44:22 PM PDT 24
Peak memory 198076 kb
Host smart-29c3cb6c-1979-4d3b-8565-4ae20eb8f62e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411889186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.411889186
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1445401818
Short name T604
Test name
Test status
Simulation time 242433757 ps
CPU time 3.83 seconds
Started Aug 14 04:44:09 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 198040 kb
Host smart-647a9b04-83a5-46ec-8155-63b0e0598488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445401818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1445401818
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.253947703
Short name T160
Test name
Test status
Simulation time 158752840 ps
CPU time 1.09 seconds
Started Aug 14 04:44:32 PM PDT 24
Finished Aug 14 04:44:33 PM PDT 24
Peak memory 195908 kb
Host smart-ed8b2147-f9ac-463c-b2ce-450ac2193ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253947703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.253947703
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3943020188
Short name T158
Test name
Test status
Simulation time 294656878 ps
CPU time 1.2 seconds
Started Aug 14 04:44:13 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 195988 kb
Host smart-b4e1aa8a-d93f-4797-b884-0bf9f040fb78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943020188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3943020188
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.4201809721
Short name T425
Test name
Test status
Simulation time 11821672342 ps
CPU time 77.92 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:45:28 PM PDT 24
Peak memory 198236 kb
Host smart-092ad45b-704e-433f-8822-885e1320be65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201809721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.4201809721
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3083415651
Short name T233
Test name
Test status
Simulation time 14510726 ps
CPU time 0.6 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:44:16 PM PDT 24
Peak memory 194312 kb
Host smart-29e84dea-1ec3-4855-ada7-60f1e28f8085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083415651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3083415651
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.906006594
Short name T509
Test name
Test status
Simulation time 40597572 ps
CPU time 0.83 seconds
Started Aug 14 04:44:23 PM PDT 24
Finished Aug 14 04:44:24 PM PDT 24
Peak memory 195560 kb
Host smart-fb35351f-30c2-4e77-b853-5d33b94a93a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906006594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.906006594
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2066250041
Short name T481
Test name
Test status
Simulation time 2891360304 ps
CPU time 25.7 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:33 PM PDT 24
Peak memory 197488 kb
Host smart-b1e73dca-710d-4e08-89fc-77cd87316c17
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066250041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2066250041
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3374851495
Short name T704
Test name
Test status
Simulation time 92365041 ps
CPU time 1.06 seconds
Started Aug 14 04:44:22 PM PDT 24
Finished Aug 14 04:44:24 PM PDT 24
Peak memory 196616 kb
Host smart-2efb5c93-436d-4bcb-82be-731a8b97940b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374851495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3374851495
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2481667833
Short name T670
Test name
Test status
Simulation time 51367818 ps
CPU time 0.65 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 194292 kb
Host smart-e943bf44-0942-438b-999c-80f024404520
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481667833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2481667833
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3996394345
Short name T684
Test name
Test status
Simulation time 90838545 ps
CPU time 3.37 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 196376 kb
Host smart-813cb001-ff40-4608-afee-8955b11d1b82
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996394345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3996394345
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2154955102
Short name T191
Test name
Test status
Simulation time 412054563 ps
CPU time 3.49 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 197304 kb
Host smart-2311403f-45b3-457f-a8b9-627da636bec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154955102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2154955102
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.4237421532
Short name T658
Test name
Test status
Simulation time 68404257 ps
CPU time 0.8 seconds
Started Aug 14 04:44:24 PM PDT 24
Finished Aug 14 04:44:25 PM PDT 24
Peak memory 196428 kb
Host smart-5f1fb77f-39aa-4dda-94f9-cf4a1614dd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237421532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.4237421532
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2634750324
Short name T437
Test name
Test status
Simulation time 52215617 ps
CPU time 1.13 seconds
Started Aug 14 04:44:21 PM PDT 24
Finished Aug 14 04:44:23 PM PDT 24
Peak memory 196192 kb
Host smart-32edd933-6ac8-4683-992d-287270b2a2e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634750324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2634750324
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2245721855
Short name T302
Test name
Test status
Simulation time 82037502 ps
CPU time 3.72 seconds
Started Aug 14 04:44:13 PM PDT 24
Finished Aug 14 04:44:16 PM PDT 24
Peak memory 198096 kb
Host smart-26f1e48b-8a6a-45a8-bc66-51a3adafbf5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245721855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2245721855
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3413215929
Short name T515
Test name
Test status
Simulation time 126748057 ps
CPU time 1.02 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:12 PM PDT 24
Peak memory 195888 kb
Host smart-33a5865c-149b-4a99-8139-499d3956609a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413215929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3413215929
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3221874932
Short name T297
Test name
Test status
Simulation time 105440720 ps
CPU time 0.78 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:12 PM PDT 24
Peak memory 195192 kb
Host smart-76f7de6c-8726-420f-a905-a5ac8a6abd4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221874932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3221874932
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3315510880
Short name T598
Test name
Test status
Simulation time 4471472765 ps
CPU time 24.92 seconds
Started Aug 14 04:44:09 PM PDT 24
Finished Aug 14 04:44:34 PM PDT 24
Peak memory 198380 kb
Host smart-e7d9be5c-44a9-47b3-9e38-c98c9be4c17b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315510880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3315510880
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3757038581
Short name T187
Test name
Test status
Simulation time 22148522 ps
CPU time 0.58 seconds
Started Aug 14 04:44:44 PM PDT 24
Finished Aug 14 04:44:45 PM PDT 24
Peak memory 194076 kb
Host smart-46ab11aa-5138-43fc-8f49-0df47fa9c617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757038581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3757038581
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.129375345
Short name T662
Test name
Test status
Simulation time 173819686 ps
CPU time 0.93 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 196676 kb
Host smart-9a044e07-e679-487d-adbf-6a4400093087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129375345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.129375345
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1640803959
Short name T678
Test name
Test status
Simulation time 2312067433 ps
CPU time 19.49 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:32 PM PDT 24
Peak memory 195744 kb
Host smart-c26ccfd2-5fcd-46a5-80a7-3ae1cf5e54bc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640803959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1640803959
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1013642394
Short name T255
Test name
Test status
Simulation time 223357574 ps
CPU time 0.79 seconds
Started Aug 14 04:44:40 PM PDT 24
Finished Aug 14 04:44:41 PM PDT 24
Peak memory 195900 kb
Host smart-cfed8945-6f45-40f0-b8b4-83b563aa1482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013642394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1013642394
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2840904541
Short name T62
Test name
Test status
Simulation time 87257374 ps
CPU time 0.92 seconds
Started Aug 14 04:44:22 PM PDT 24
Finished Aug 14 04:44:23 PM PDT 24
Peak memory 195980 kb
Host smart-aca34c0c-156a-41b7-932d-f8e1d7c890e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840904541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2840904541
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1718270342
Short name T709
Test name
Test status
Simulation time 108647911 ps
CPU time 0.92 seconds
Started Aug 14 04:44:39 PM PDT 24
Finished Aug 14 04:44:40 PM PDT 24
Peak memory 196284 kb
Host smart-6f4dd173-399a-4caa-9230-006b49373cb1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718270342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1718270342
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2983069650
Short name T619
Test name
Test status
Simulation time 109655387 ps
CPU time 3.02 seconds
Started Aug 14 04:44:30 PM PDT 24
Finished Aug 14 04:44:33 PM PDT 24
Peak memory 198176 kb
Host smart-10407bfc-fb5f-4b55-beef-8c6f720a54a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983069650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2983069650
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.814075995
Short name T421
Test name
Test status
Simulation time 192025195 ps
CPU time 1.01 seconds
Started Aug 14 04:44:42 PM PDT 24
Finished Aug 14 04:44:44 PM PDT 24
Peak memory 195984 kb
Host smart-12d3226e-efc5-4406-a5a1-7c85314ad804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814075995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.814075995
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2981353037
Short name T475
Test name
Test status
Simulation time 117962139 ps
CPU time 1.11 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 196028 kb
Host smart-34d87ced-d673-44cc-934d-9a95e7c27cd2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981353037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2981353037
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1591471718
Short name T512
Test name
Test status
Simulation time 396439818 ps
CPU time 4.97 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:16 PM PDT 24
Peak memory 198080 kb
Host smart-37b85c98-24f6-4625-bfd8-cc1526f0babe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591471718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1591471718
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3739164223
Short name T309
Test name
Test status
Simulation time 113932195 ps
CPU time 0.95 seconds
Started Aug 14 04:44:38 PM PDT 24
Finished Aug 14 04:44:39 PM PDT 24
Peak memory 195880 kb
Host smart-0fb946ba-c1c8-4adb-948e-2ad5835eea72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739164223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3739164223
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.4105292332
Short name T450
Test name
Test status
Simulation time 150036991 ps
CPU time 1.35 seconds
Started Aug 14 04:44:13 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 196844 kb
Host smart-cc8d0893-31c4-4920-b4f7-61ea2ffbea0c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105292332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.4105292332
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1853763950
Short name T8
Test name
Test status
Simulation time 66085586227 ps
CPU time 167.8 seconds
Started Aug 14 04:44:23 PM PDT 24
Finished Aug 14 04:47:11 PM PDT 24
Peak memory 198260 kb
Host smart-72bd0739-10f7-46cf-ab63-b61237f442d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853763950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1853763950
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2068343865
Short name T694
Test name
Test status
Simulation time 18203677773 ps
CPU time 23.48 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:36 PM PDT 24
Peak memory 198500 kb
Host smart-005c21c2-9533-44e5-9733-8e6f1180af25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2068343865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2068343865
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.102817624
Short name T232
Test name
Test status
Simulation time 12220416 ps
CPU time 0.57 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 194268 kb
Host smart-4ba6bd78-32e0-43e0-af3c-23ac6ecd9ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102817624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.102817624
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3867321520
Short name T143
Test name
Test status
Simulation time 53630306 ps
CPU time 0.92 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 196248 kb
Host smart-0614a86c-0c0f-4ef8-bdf0-41e3fcd1641b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867321520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3867321520
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1485209200
Short name T252
Test name
Test status
Simulation time 552831438 ps
CPU time 27.24 seconds
Started Aug 14 04:44:33 PM PDT 24
Finished Aug 14 04:45:00 PM PDT 24
Peak memory 196468 kb
Host smart-c9017729-57cd-4622-a57c-fb83148c3061
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485209200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1485209200
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.920003600
Short name T707
Test name
Test status
Simulation time 62952591 ps
CPU time 0.86 seconds
Started Aug 14 04:44:28 PM PDT 24
Finished Aug 14 04:44:29 PM PDT 24
Peak memory 196064 kb
Host smart-f887efb0-dbdb-4266-ad07-c143e23b1686
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920003600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.920003600
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3693076168
Short name T108
Test name
Test status
Simulation time 215056424 ps
CPU time 1.34 seconds
Started Aug 14 04:44:28 PM PDT 24
Finished Aug 14 04:44:30 PM PDT 24
Peak memory 197348 kb
Host smart-fa78829b-3fb1-4877-a7dd-1f3ce74b4eb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693076168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3693076168
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2273396207
Short name T274
Test name
Test status
Simulation time 42576803 ps
CPU time 1.66 seconds
Started Aug 14 04:44:40 PM PDT 24
Finished Aug 14 04:44:41 PM PDT 24
Peak memory 196608 kb
Host smart-01f932a0-c657-45a9-9be7-3d5e1e540e42
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273396207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2273396207
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.883212660
Short name T696
Test name
Test status
Simulation time 289676712 ps
CPU time 1.26 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 195924 kb
Host smart-8662fa25-f613-4604-ba73-66c87b5190e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883212660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
883212660
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3038943037
Short name T142
Test name
Test status
Simulation time 196963328 ps
CPU time 0.94 seconds
Started Aug 14 04:44:18 PM PDT 24
Finished Aug 14 04:44:19 PM PDT 24
Peak memory 196920 kb
Host smart-c74ad105-d69c-4121-9a0e-e217afd8319e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038943037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3038943037
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3648024334
Short name T305
Test name
Test status
Simulation time 281918028 ps
CPU time 1.18 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 197452 kb
Host smart-82accee8-e1e3-429c-ac9c-dc4561a656de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648024334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3648024334
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1158440870
Short name T433
Test name
Test status
Simulation time 232805626 ps
CPU time 3 seconds
Started Aug 14 04:44:21 PM PDT 24
Finished Aug 14 04:44:25 PM PDT 24
Peak memory 198076 kb
Host smart-83d37f35-a947-447d-8084-3c6f8f1a104b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158440870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1158440870
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1489193351
Short name T452
Test name
Test status
Simulation time 62632238 ps
CPU time 0.96 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 195752 kb
Host smart-69200104-add6-4a20-8677-57850830262a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489193351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1489193351
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2520171672
Short name T144
Test name
Test status
Simulation time 57911551 ps
CPU time 1.27 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 197020 kb
Host smart-d6c1d844-0eed-4386-a99c-423643735317
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520171672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2520171672
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.999865924
Short name T652
Test name
Test status
Simulation time 12727629036 ps
CPU time 81.67 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:45:39 PM PDT 24
Peak memory 198280 kb
Host smart-d407f0df-870c-4aa2-a216-3cd093b53d54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999865924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.999865924
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.205662778
Short name T708
Test name
Test status
Simulation time 32263672914 ps
CPU time 269.24 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:48:40 PM PDT 24
Peak memory 198484 kb
Host smart-01302bc4-bbac-43ff-97a0-7903c1438be3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=205662778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.205662778
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3324989947
Short name T24
Test name
Test status
Simulation time 12795450 ps
CPU time 0.55 seconds
Started Aug 14 04:44:19 PM PDT 24
Finished Aug 14 04:44:19 PM PDT 24
Peak memory 194704 kb
Host smart-13a925d8-ba0b-44b8-aa27-90ef786f82b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324989947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3324989947
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.143326043
Short name T181
Test name
Test status
Simulation time 174810826 ps
CPU time 0.84 seconds
Started Aug 14 04:44:30 PM PDT 24
Finished Aug 14 04:44:31 PM PDT 24
Peak memory 197128 kb
Host smart-5324de7a-bf6f-45b5-a98f-72aac31d6ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143326043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.143326043
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.4080476633
Short name T519
Test name
Test status
Simulation time 930740112 ps
CPU time 13.19 seconds
Started Aug 14 04:44:38 PM PDT 24
Finished Aug 14 04:44:51 PM PDT 24
Peak memory 197112 kb
Host smart-e0930d79-c913-43f8-a2b7-6050c3e58ada
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080476633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.4080476633
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3609158774
Short name T471
Test name
Test status
Simulation time 49663233 ps
CPU time 0.85 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:12 PM PDT 24
Peak memory 197184 kb
Host smart-82abc76b-6c59-4a2d-8e16-17cb04a8487f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609158774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3609158774
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1363760008
Short name T398
Test name
Test status
Simulation time 34418746 ps
CPU time 0.73 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:12 PM PDT 24
Peak memory 195652 kb
Host smart-794527cc-f0a9-4f61-a2f7-878578d023e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363760008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1363760008
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2720705724
Short name T200
Test name
Test status
Simulation time 802749505 ps
CPU time 3.05 seconds
Started Aug 14 04:44:25 PM PDT 24
Finished Aug 14 04:44:28 PM PDT 24
Peak memory 196552 kb
Host smart-c898e05f-37bc-4c5f-ac74-50a23a2f8d9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720705724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2720705724
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.558544417
Short name T544
Test name
Test status
Simulation time 42161422 ps
CPU time 1.31 seconds
Started Aug 14 04:44:13 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 196272 kb
Host smart-4bc7f7b4-22b6-4652-bcdf-6a3944b9e2aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558544417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
558544417
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2046738117
Short name T663
Test name
Test status
Simulation time 53662282 ps
CPU time 1.23 seconds
Started Aug 14 04:44:18 PM PDT 24
Finished Aug 14 04:44:20 PM PDT 24
Peak memory 196112 kb
Host smart-d9cac532-1444-4be9-b6f3-b2df5aa1b6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046738117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2046738117
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2162007283
Short name T216
Test name
Test status
Simulation time 22272086 ps
CPU time 0.86 seconds
Started Aug 14 04:44:23 PM PDT 24
Finished Aug 14 04:44:24 PM PDT 24
Peak memory 196056 kb
Host smart-9cb27529-cf75-4d07-98a0-f06da3391bc1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162007283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2162007283
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1944881229
Short name T368
Test name
Test status
Simulation time 106662740 ps
CPU time 4.69 seconds
Started Aug 14 04:44:38 PM PDT 24
Finished Aug 14 04:44:43 PM PDT 24
Peak memory 198160 kb
Host smart-954e7490-d524-44d8-bbf6-2c64bdbab6fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944881229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1944881229
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1327826959
Short name T611
Test name
Test status
Simulation time 40091416 ps
CPU time 1.03 seconds
Started Aug 14 04:44:13 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 195940 kb
Host smart-059546a7-fde0-4824-8357-3f5722f36d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327826959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1327826959
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3077199474
Short name T470
Test name
Test status
Simulation time 138115292 ps
CPU time 1.32 seconds
Started Aug 14 04:44:22 PM PDT 24
Finished Aug 14 04:44:24 PM PDT 24
Peak memory 196952 kb
Host smart-fb12405f-cbef-4cdf-9d97-98d0b2294289
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077199474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3077199474
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1559396992
Short name T526
Test name
Test status
Simulation time 72782607778 ps
CPU time 118.88 seconds
Started Aug 14 04:44:21 PM PDT 24
Finished Aug 14 04:46:20 PM PDT 24
Peak memory 198352 kb
Host smart-d6fa1aaa-349e-4aac-ba64-61c3b263477e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559396992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1559396992
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3039726901
Short name T533
Test name
Test status
Simulation time 13441236 ps
CPU time 0.57 seconds
Started Aug 14 04:44:30 PM PDT 24
Finished Aug 14 04:44:31 PM PDT 24
Peak memory 194652 kb
Host smart-d61c10e3-f9f4-4651-8f19-595fdf65b470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039726901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3039726901
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1278741226
Short name T377
Test name
Test status
Simulation time 15567041 ps
CPU time 0.61 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 194764 kb
Host smart-bb96400f-110a-4c82-a480-61436a20af7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278741226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1278741226
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.4227522349
Short name T372
Test name
Test status
Simulation time 1673899300 ps
CPU time 28.1 seconds
Started Aug 14 04:44:20 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 198152 kb
Host smart-f9cf5078-438b-4827-ab40-1fb23939037c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227522349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.4227522349
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1639987137
Short name T162
Test name
Test status
Simulation time 22391339 ps
CPU time 0.62 seconds
Started Aug 14 04:44:28 PM PDT 24
Finished Aug 14 04:44:29 PM PDT 24
Peak memory 195392 kb
Host smart-a8ee9d8f-d204-434a-8dc7-d6c78c4d148e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639987137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1639987137
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3344375342
Short name T28
Test name
Test status
Simulation time 65964582 ps
CPU time 0.79 seconds
Started Aug 14 04:44:20 PM PDT 24
Finished Aug 14 04:44:21 PM PDT 24
Peak memory 196440 kb
Host smart-40264b71-b57d-4748-b6fc-8b337ce57e6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344375342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3344375342
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3066538585
Short name T248
Test name
Test status
Simulation time 531334278 ps
CPU time 3.01 seconds
Started Aug 14 04:44:22 PM PDT 24
Finished Aug 14 04:44:25 PM PDT 24
Peak memory 198248 kb
Host smart-60f601d8-1694-42a0-a3fd-a258537eb021
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066538585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3066538585
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.621118317
Short name T229
Test name
Test status
Simulation time 144412311 ps
CPU time 3.1 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 197276 kb
Host smart-2024660d-e5d3-49c2-bbf0-06660e0ddfdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621118317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
621118317
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2692385555
Short name T676
Test name
Test status
Simulation time 35179047 ps
CPU time 1.18 seconds
Started Aug 14 04:44:24 PM PDT 24
Finished Aug 14 04:44:26 PM PDT 24
Peak memory 197108 kb
Host smart-975b2d00-f1c9-4f29-ae1b-13887d5bfe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692385555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2692385555
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3562615151
Short name T396
Test name
Test status
Simulation time 110682612 ps
CPU time 1.07 seconds
Started Aug 14 04:44:40 PM PDT 24
Finished Aug 14 04:44:41 PM PDT 24
Peak memory 195884 kb
Host smart-61536dcf-ca60-446a-ab66-1515b95d4f94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562615151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3562615151
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3337084166
Short name T697
Test name
Test status
Simulation time 355155394 ps
CPU time 1.86 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 198080 kb
Host smart-386d5024-4402-489c-84e7-2d984fe0d37d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337084166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3337084166
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.596971526
Short name T477
Test name
Test status
Simulation time 274105567 ps
CPU time 0.87 seconds
Started Aug 14 04:44:20 PM PDT 24
Finished Aug 14 04:44:21 PM PDT 24
Peak memory 195296 kb
Host smart-5db13cbe-df89-4584-ad0d-3a8342c46f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596971526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.596971526
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.63067809
Short name T115
Test name
Test status
Simulation time 240390472 ps
CPU time 0.97 seconds
Started Aug 14 04:44:16 PM PDT 24
Finished Aug 14 04:44:17 PM PDT 24
Peak memory 195888 kb
Host smart-4a4a4c8b-b16f-4be3-9ee1-63d73ed88cc1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63067809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.63067809
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2208460067
Short name T700
Test name
Test status
Simulation time 2054939908 ps
CPU time 21.93 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:34 PM PDT 24
Peak memory 198256 kb
Host smart-6caa42bc-2d74-429f-af74-1556f5ecf099
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208460067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2208460067
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2392312431
Short name T151
Test name
Test status
Simulation time 15687219 ps
CPU time 0.6 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 193492 kb
Host smart-74bfbd79-d8bf-4f43-922e-3aac2355319e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392312431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2392312431
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1558683411
Short name T45
Test name
Test status
Simulation time 31924766 ps
CPU time 0.9 seconds
Started Aug 14 04:44:46 PM PDT 24
Finished Aug 14 04:44:47 PM PDT 24
Peak memory 196068 kb
Host smart-9f15b8b3-d96a-45ad-954a-ce58e8b84ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558683411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1558683411
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3049589709
Short name T122
Test name
Test status
Simulation time 427158473 ps
CPU time 23.34 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:34 PM PDT 24
Peak memory 198036 kb
Host smart-c5481794-a550-40c4-8ed4-7a1151b28d39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049589709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3049589709
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3025060393
Short name T198
Test name
Test status
Simulation time 63533017 ps
CPU time 1.04 seconds
Started Aug 14 04:44:11 PM PDT 24
Finished Aug 14 04:44:12 PM PDT 24
Peak memory 196192 kb
Host smart-9d8c17ea-b788-4fe2-a159-af9f30b00d2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025060393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3025060393
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3192552735
Short name T120
Test name
Test status
Simulation time 76108822 ps
CPU time 2.88 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:44:18 PM PDT 24
Peak memory 198156 kb
Host smart-0fa022b0-33a5-4812-92ff-cff673ad3a9c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192552735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3192552735
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1573606198
Short name T280
Test name
Test status
Simulation time 119404909 ps
CPU time 2.1 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:16 PM PDT 24
Peak memory 196864 kb
Host smart-ed4d1e16-31e5-46b9-96f3-da5e9cbb5850
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573606198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1573606198
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1365628115
Short name T321
Test name
Test status
Simulation time 399963167 ps
CPU time 1.13 seconds
Started Aug 14 04:44:36 PM PDT 24
Finished Aug 14 04:44:37 PM PDT 24
Peak memory 198108 kb
Host smart-e217ce92-e887-4cde-b20c-82b4f127fdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365628115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1365628115
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3044964995
Short name T117
Test name
Test status
Simulation time 288393126 ps
CPU time 1.26 seconds
Started Aug 14 04:44:19 PM PDT 24
Finished Aug 14 04:44:20 PM PDT 24
Peak memory 195208 kb
Host smart-29bcd83e-9066-4cef-9b6e-dd59a8726d88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044964995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3044964995
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.725210623
Short name T535
Test name
Test status
Simulation time 728956230 ps
CPU time 3.21 seconds
Started Aug 14 04:44:38 PM PDT 24
Finished Aug 14 04:44:41 PM PDT 24
Peak memory 198172 kb
Host smart-139c3da9-cef9-4844-8982-74c7021435ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725210623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.725210623
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.451069175
Short name T199
Test name
Test status
Simulation time 316256930 ps
CPU time 1.39 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 197024 kb
Host smart-d8cd50dd-06d6-4f24-8538-1b0c2d037228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451069175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.451069175
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4153373142
Short name T159
Test name
Test status
Simulation time 544339431 ps
CPU time 0.94 seconds
Started Aug 14 04:44:38 PM PDT 24
Finished Aug 14 04:44:39 PM PDT 24
Peak memory 195800 kb
Host smart-3ccf7ed8-4baa-46e9-96d5-a9f6494868f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153373142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4153373142
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.778669863
Short name T236
Test name
Test status
Simulation time 11177305417 ps
CPU time 77.05 seconds
Started Aug 14 04:44:30 PM PDT 24
Finished Aug 14 04:45:47 PM PDT 24
Peak memory 198360 kb
Host smart-795685d4-6065-4ae4-981c-3fdf12da9399
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778669863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.778669863
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3250307216
Short name T442
Test name
Test status
Simulation time 15728548 ps
CPU time 0.6 seconds
Started Aug 14 04:44:41 PM PDT 24
Finished Aug 14 04:44:42 PM PDT 24
Peak memory 194196 kb
Host smart-ae83ca52-22fb-4f99-a159-e3ccbdf4eb42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250307216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3250307216
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1036121604
Short name T183
Test name
Test status
Simulation time 128378292 ps
CPU time 0.71 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 195396 kb
Host smart-f2c8aac2-11e3-44ea-b4f8-1e125b767f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036121604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1036121604
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1077625603
Short name T161
Test name
Test status
Simulation time 2913543065 ps
CPU time 22.09 seconds
Started Aug 14 04:44:53 PM PDT 24
Finished Aug 14 04:45:15 PM PDT 24
Peak memory 196104 kb
Host smart-bb5180cb-4db9-4e7c-86b6-529cfb7b9da6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077625603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1077625603
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.828366387
Short name T312
Test name
Test status
Simulation time 265930519 ps
CPU time 0.76 seconds
Started Aug 14 04:44:27 PM PDT 24
Finished Aug 14 04:44:27 PM PDT 24
Peak memory 196028 kb
Host smart-9156a47e-ae81-4b9d-a9f3-e6115e8dadb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828366387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.828366387
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1854997413
Short name T288
Test name
Test status
Simulation time 177199547 ps
CPU time 1.26 seconds
Started Aug 14 04:44:13 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 196248 kb
Host smart-d9ec8c9d-ac28-4264-800f-f4ba42982288
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854997413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1854997413
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1291489677
Short name T434
Test name
Test status
Simulation time 130288667 ps
CPU time 1.39 seconds
Started Aug 14 04:44:22 PM PDT 24
Finished Aug 14 04:44:23 PM PDT 24
Peak memory 196840 kb
Host smart-01ecf22e-8a08-4d1e-b82b-93d3eed4407e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291489677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1291489677
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2586549988
Short name T300
Test name
Test status
Simulation time 101547376 ps
CPU time 0.96 seconds
Started Aug 14 04:44:43 PM PDT 24
Finished Aug 14 04:44:45 PM PDT 24
Peak memory 195528 kb
Host smart-480db2ad-2369-4fca-883d-0c7d6f24d258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586549988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2586549988
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1503520543
Short name T659
Test name
Test status
Simulation time 217644329 ps
CPU time 1.07 seconds
Started Aug 14 04:44:10 PM PDT 24
Finished Aug 14 04:44:11 PM PDT 24
Peak memory 196960 kb
Host smart-d7152ca3-01de-4a28-98d8-b30fa48ac680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503520543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1503520543
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1672589631
Short name T295
Test name
Test status
Simulation time 154932527 ps
CPU time 1.12 seconds
Started Aug 14 04:44:38 PM PDT 24
Finished Aug 14 04:44:39 PM PDT 24
Peak memory 196100 kb
Host smart-d0a07fd0-7bdc-4fe9-8ded-2fcc90eea0f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672589631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1672589631
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.428705417
Short name T169
Test name
Test status
Simulation time 41609735 ps
CPU time 1.88 seconds
Started Aug 14 04:44:38 PM PDT 24
Finished Aug 14 04:44:40 PM PDT 24
Peak memory 198156 kb
Host smart-a4ce2b6d-51e4-499e-804b-bc5150f291f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428705417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.428705417
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.264010307
Short name T444
Test name
Test status
Simulation time 317851673 ps
CPU time 1.15 seconds
Started Aug 14 04:44:31 PM PDT 24
Finished Aug 14 04:44:32 PM PDT 24
Peak memory 195860 kb
Host smart-c0fc3b96-e33e-4759-873d-4f3efaefb041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264010307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.264010307
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.922275587
Short name T283
Test name
Test status
Simulation time 399782125 ps
CPU time 1.51 seconds
Started Aug 14 04:44:30 PM PDT 24
Finished Aug 14 04:44:31 PM PDT 24
Peak memory 197016 kb
Host smart-98bd09a0-c24f-4020-b3e1-4bdd04674352
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922275587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.922275587
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2805192487
Short name T497
Test name
Test status
Simulation time 38664063166 ps
CPU time 142.4 seconds
Started Aug 14 04:44:27 PM PDT 24
Finished Aug 14 04:46:49 PM PDT 24
Peak memory 198188 kb
Host smart-43229fa1-8945-4a00-ae15-ab41919ca36e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805192487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2805192487
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1312091275
Short name T586
Test name
Test status
Simulation time 40928876 ps
CPU time 0.58 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:20 PM PDT 24
Peak memory 194148 kb
Host smart-39dc7655-1bc5-4747-8678-d2a5aeccf884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312091275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1312091275
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2820794681
Short name T634
Test name
Test status
Simulation time 86509125 ps
CPU time 0.69 seconds
Started Aug 14 04:44:34 PM PDT 24
Finished Aug 14 04:44:34 PM PDT 24
Peak memory 194928 kb
Host smart-3af12ec5-bcbc-4915-982d-da47373a70d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820794681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2820794681
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2028325565
Short name T542
Test name
Test status
Simulation time 156374102 ps
CPU time 7.84 seconds
Started Aug 14 04:44:37 PM PDT 24
Finished Aug 14 04:44:44 PM PDT 24
Peak memory 197168 kb
Host smart-6c7f2cff-66da-4f91-9cd4-0712afcdd8dc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028325565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2028325565
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.4278896414
Short name T627
Test name
Test status
Simulation time 384639698 ps
CPU time 1.01 seconds
Started Aug 14 04:44:52 PM PDT 24
Finished Aug 14 04:44:54 PM PDT 24
Peak memory 196560 kb
Host smart-4f0d11e1-8c93-4f4d-b839-ea842e17b982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278896414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.4278896414
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1559358171
Short name T188
Test name
Test status
Simulation time 44415481 ps
CPU time 1.27 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 198136 kb
Host smart-0754db03-e95d-4466-8a49-08204485259e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559358171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1559358171
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3699406678
Short name T98
Test name
Test status
Simulation time 299074040 ps
CPU time 3.4 seconds
Started Aug 14 04:44:50 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 198292 kb
Host smart-e347e47c-7391-41c0-ab74-c4439a89c6cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699406678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3699406678
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3854466340
Short name T365
Test name
Test status
Simulation time 431121650 ps
CPU time 1.15 seconds
Started Aug 14 04:44:41 PM PDT 24
Finished Aug 14 04:44:43 PM PDT 24
Peak memory 196508 kb
Host smart-5029f4bf-f190-4366-bbf9-f8c535bb5a4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854466340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3854466340
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3857501799
Short name T104
Test name
Test status
Simulation time 31464768 ps
CPU time 1.16 seconds
Started Aug 14 04:44:41 PM PDT 24
Finished Aug 14 04:44:42 PM PDT 24
Peak memory 196828 kb
Host smart-1923508f-6a3b-4e42-933f-a1a3c74d93ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857501799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3857501799
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.4058847596
Short name T361
Test name
Test status
Simulation time 105687482 ps
CPU time 1.15 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 197008 kb
Host smart-7cd1141e-42f3-403c-b432-8c665efe1dd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058847596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.4058847596
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.4230755182
Short name T317
Test name
Test status
Simulation time 717722235 ps
CPU time 4.59 seconds
Started Aug 14 04:44:44 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 196520 kb
Host smart-29180223-7f3b-45e8-8af1-83e50ccbb4e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230755182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.4230755182
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2479568957
Short name T409
Test name
Test status
Simulation time 116089024 ps
CPU time 0.95 seconds
Started Aug 14 04:44:48 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 195648 kb
Host smart-abe998f7-a80a-4307-8606-c5bfed2add5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479568957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2479568957
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1498271451
Short name T345
Test name
Test status
Simulation time 69231765 ps
CPU time 1.13 seconds
Started Aug 14 04:44:13 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 195944 kb
Host smart-a63de7f3-646b-438a-8ffb-5b1ac093084d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498271451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1498271451
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3521705219
Short name T263
Test name
Test status
Simulation time 76038277738 ps
CPU time 206.78 seconds
Started Aug 14 04:44:34 PM PDT 24
Finished Aug 14 04:48:01 PM PDT 24
Peak memory 198364 kb
Host smart-3aa224d6-2084-4d9e-854b-1d3d0b2adcc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521705219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3521705219
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1568906252
Short name T41
Test name
Test status
Simulation time 19202025 ps
CPU time 0.56 seconds
Started Aug 14 04:43:39 PM PDT 24
Finished Aug 14 04:43:39 PM PDT 24
Peak memory 193984 kb
Host smart-262d03c6-1237-40a1-9031-b655228e6ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568906252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1568906252
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.4143808869
Short name T146
Test name
Test status
Simulation time 31347273 ps
CPU time 0.73 seconds
Started Aug 14 04:43:46 PM PDT 24
Finished Aug 14 04:43:47 PM PDT 24
Peak memory 194256 kb
Host smart-acc6f565-3f4d-46b2-aa22-2f8bfeef7367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143808869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.4143808869
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2762057515
Short name T214
Test name
Test status
Simulation time 258025520 ps
CPU time 8.84 seconds
Started Aug 14 04:43:34 PM PDT 24
Finished Aug 14 04:43:43 PM PDT 24
Peak memory 197096 kb
Host smart-69146a69-a5fc-4022-aac9-ba8a15afc44a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762057515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2762057515
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2013070452
Short name T269
Test name
Test status
Simulation time 80204034 ps
CPU time 1.05 seconds
Started Aug 14 04:43:35 PM PDT 24
Finished Aug 14 04:43:36 PM PDT 24
Peak memory 196556 kb
Host smart-f181735b-709f-4b8e-956b-66e403dbb1ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013070452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2013070452
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3371964752
Short name T150
Test name
Test status
Simulation time 904155944 ps
CPU time 1.27 seconds
Started Aug 14 04:43:37 PM PDT 24
Finished Aug 14 04:43:38 PM PDT 24
Peak memory 196188 kb
Host smart-c8674444-22ff-4ee4-9770-a9a8007f6395
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371964752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3371964752
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.927735449
Short name T185
Test name
Test status
Simulation time 99190905 ps
CPU time 1.25 seconds
Started Aug 14 04:43:27 PM PDT 24
Finished Aug 14 04:43:29 PM PDT 24
Peak memory 198208 kb
Host smart-475188c6-2246-48d4-8181-15307c335982
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927735449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.927735449
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2213535795
Short name T112
Test name
Test status
Simulation time 984114781 ps
CPU time 1.26 seconds
Started Aug 14 04:43:54 PM PDT 24
Finished Aug 14 04:44:00 PM PDT 24
Peak memory 196932 kb
Host smart-67e6a5d9-a1d5-47de-8b19-857e0002dcef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213535795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2213535795
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1102250068
Short name T340
Test name
Test status
Simulation time 82853764 ps
CPU time 1.06 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:21 PM PDT 24
Peak memory 195996 kb
Host smart-00ae7135-10d8-4f63-bee7-dd2fa3b71b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102250068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1102250068
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2022772043
Short name T706
Test name
Test status
Simulation time 227552787 ps
CPU time 0.83 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:43:58 PM PDT 24
Peak memory 196640 kb
Host smart-e261eb4a-4150-4aa9-89f7-2b09c3d69b55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022772043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2022772043
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4045605033
Short name T610
Test name
Test status
Simulation time 180571114 ps
CPU time 1.99 seconds
Started Aug 14 04:43:28 PM PDT 24
Finished Aug 14 04:43:31 PM PDT 24
Peak memory 198068 kb
Host smart-449a8825-3988-4570-91d6-36104125088f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045605033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4045605033
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2636162249
Short name T38
Test name
Test status
Simulation time 57965563 ps
CPU time 0.84 seconds
Started Aug 14 04:43:19 PM PDT 24
Finished Aug 14 04:43:20 PM PDT 24
Peak memory 214060 kb
Host smart-c44c33c8-7bf2-46d8-a171-a0809111537f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636162249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2636162249
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3631718536
Short name T264
Test name
Test status
Simulation time 186504072 ps
CPU time 1.35 seconds
Started Aug 14 04:43:46 PM PDT 24
Finished Aug 14 04:43:48 PM PDT 24
Peak memory 196868 kb
Host smart-a54d51ac-adc2-4dac-8c35-538ccaa672a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631718536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3631718536
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2920735350
Short name T547
Test name
Test status
Simulation time 129748423 ps
CPU time 0.81 seconds
Started Aug 14 04:44:03 PM PDT 24
Finished Aug 14 04:44:04 PM PDT 24
Peak memory 195292 kb
Host smart-5e8d61d1-c18d-4648-ba84-5906c68e415e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920735350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2920735350
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1014771355
Short name T110
Test name
Test status
Simulation time 7282169456 ps
CPU time 192.65 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:46:33 PM PDT 24
Peak memory 198348 kb
Host smart-7f8c7990-dc38-418c-adcc-78f618ee382d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014771355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1014771355
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3439064784
Short name T445
Test name
Test status
Simulation time 41330836 ps
CPU time 0.58 seconds
Started Aug 14 04:44:38 PM PDT 24
Finished Aug 14 04:44:39 PM PDT 24
Peak memory 194232 kb
Host smart-0d627d69-b9f3-4c21-855f-de9a4cb872c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439064784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3439064784
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2014345878
Short name T349
Test name
Test status
Simulation time 154989872 ps
CPU time 0.88 seconds
Started Aug 14 04:44:38 PM PDT 24
Finished Aug 14 04:44:38 PM PDT 24
Peak memory 196704 kb
Host smart-d9de87e0-28c4-4491-9ccf-55c4c9da2646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014345878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2014345878
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3325757240
Short name T322
Test name
Test status
Simulation time 2201331412 ps
CPU time 18.43 seconds
Started Aug 14 04:44:46 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 198280 kb
Host smart-7cdef08f-84bc-481c-8324-68f12b7162db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325757240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3325757240
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2940334150
Short name T167
Test name
Test status
Simulation time 45446065 ps
CPU time 0.71 seconds
Started Aug 14 04:44:36 PM PDT 24
Finished Aug 14 04:44:36 PM PDT 24
Peak memory 194756 kb
Host smart-bb9a0dbc-479d-4c68-88d8-64d237f18e5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940334150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2940334150
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.665345545
Short name T15
Test name
Test status
Simulation time 301134777 ps
CPU time 1.25 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:44:17 PM PDT 24
Peak memory 197576 kb
Host smart-2b1bb302-0389-4dc7-ae08-5208bda0185c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665345545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.665345545
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.844746796
Short name T243
Test name
Test status
Simulation time 39430607 ps
CPU time 1.56 seconds
Started Aug 14 04:44:48 PM PDT 24
Finished Aug 14 04:44:50 PM PDT 24
Peak memory 196956 kb
Host smart-d94fd080-d7a7-4831-be9c-1eab8fec7fa6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844746796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.844746796
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1728152568
Short name T406
Test name
Test status
Simulation time 144772091 ps
CPU time 3.04 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:44:18 PM PDT 24
Peak memory 196672 kb
Host smart-192ba2ef-a8d1-478a-a447-4332f46fb14b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728152568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1728152568
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3410484730
Short name T123
Test name
Test status
Simulation time 22428341 ps
CPU time 0.7 seconds
Started Aug 14 04:44:44 PM PDT 24
Finished Aug 14 04:44:45 PM PDT 24
Peak memory 195436 kb
Host smart-a6475f09-0175-4582-bc79-1bc3b45dbb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410484730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3410484730
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1014870745
Short name T336
Test name
Test status
Simulation time 117737479 ps
CPU time 1.17 seconds
Started Aug 14 04:44:52 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 196264 kb
Host smart-b8ab6818-3dec-4484-bc6e-f808e9629c62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014870745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1014870745
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3585755485
Short name T102
Test name
Test status
Simulation time 263862765 ps
CPU time 4.27 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 198164 kb
Host smart-63f9696f-ae83-4980-9136-652e47ef54a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585755485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3585755485
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2045445307
Short name T310
Test name
Test status
Simulation time 825349672 ps
CPU time 1.27 seconds
Started Aug 14 04:44:24 PM PDT 24
Finished Aug 14 04:44:31 PM PDT 24
Peak memory 196796 kb
Host smart-f95320b6-b716-4a24-9d9d-cdb13b834a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045445307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2045445307
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3543491747
Short name T299
Test name
Test status
Simulation time 155395669 ps
CPU time 0.9 seconds
Started Aug 14 04:44:46 PM PDT 24
Finished Aug 14 04:44:47 PM PDT 24
Peak memory 195248 kb
Host smart-a384eeb4-dac0-4aef-90bf-f4ba69986af4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543491747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3543491747
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2134827295
Short name T319
Test name
Test status
Simulation time 5098913772 ps
CPU time 125.51 seconds
Started Aug 14 04:44:51 PM PDT 24
Finished Aug 14 04:46:56 PM PDT 24
Peak memory 198244 kb
Host smart-2266fff3-d4cb-4b33-8e49-e3b9623ec77c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134827295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2134827295
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3793376787
Short name T32
Test name
Test status
Simulation time 3895835960 ps
CPU time 72.51 seconds
Started Aug 14 04:44:33 PM PDT 24
Finished Aug 14 04:45:46 PM PDT 24
Peak memory 198520 kb
Host smart-dae6bcb8-19ab-454d-a855-9f8a90f224ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3793376787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3793376787
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1790945367
Short name T131
Test name
Test status
Simulation time 11906381 ps
CPU time 0.61 seconds
Started Aug 14 04:44:48 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 194036 kb
Host smart-850d780f-8763-4d4b-8770-d1e540fd0925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790945367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1790945367
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.24110989
Short name T632
Test name
Test status
Simulation time 36126087 ps
CPU time 0.62 seconds
Started Aug 14 04:44:24 PM PDT 24
Finished Aug 14 04:44:25 PM PDT 24
Peak memory 194244 kb
Host smart-0254a187-43dd-4ea6-a86d-ac527706033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24110989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.24110989
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.266273882
Short name T292
Test name
Test status
Simulation time 1028364955 ps
CPU time 9.72 seconds
Started Aug 14 04:44:41 PM PDT 24
Finished Aug 14 04:44:51 PM PDT 24
Peak memory 195736 kb
Host smart-301312a5-4b88-439d-96b0-86b2b622dcff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266273882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.266273882
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3451559603
Short name T531
Test name
Test status
Simulation time 48506115 ps
CPU time 0.67 seconds
Started Aug 14 04:44:44 PM PDT 24
Finished Aug 14 04:44:45 PM PDT 24
Peak memory 194600 kb
Host smart-aeab4221-571f-499f-a994-d3e8435c68bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451559603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3451559603
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1217383284
Short name T14
Test name
Test status
Simulation time 98171637 ps
CPU time 0.76 seconds
Started Aug 14 04:44:52 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 196368 kb
Host smart-fe83f308-ffda-4e6b-b37e-4183af7fac6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217383284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1217383284
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.930977553
Short name T574
Test name
Test status
Simulation time 305444275 ps
CPU time 3.04 seconds
Started Aug 14 04:44:35 PM PDT 24
Finished Aug 14 04:44:38 PM PDT 24
Peak memory 197364 kb
Host smart-c6b9426f-3163-4030-8c7f-df38843b5e4d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930977553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.930977553
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3681765333
Short name T380
Test name
Test status
Simulation time 132183549 ps
CPU time 2.3 seconds
Started Aug 14 04:44:53 PM PDT 24
Finished Aug 14 04:44:56 PM PDT 24
Peak memory 195944 kb
Host smart-55b5dfbd-cfd0-4a9c-b32c-4e8be306aa59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681765333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3681765333
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2971980690
Short name T128
Test name
Test status
Simulation time 31392479 ps
CPU time 0.88 seconds
Started Aug 14 04:44:46 PM PDT 24
Finished Aug 14 04:44:47 PM PDT 24
Peak memory 196612 kb
Host smart-22b35528-629e-4414-a713-4afc112cde7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971980690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2971980690
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2902379084
Short name T16
Test name
Test status
Simulation time 60146072 ps
CPU time 0.87 seconds
Started Aug 14 04:44:31 PM PDT 24
Finished Aug 14 04:44:32 PM PDT 24
Peak memory 196180 kb
Host smart-0aefde1c-12b7-4cef-8456-15bd5e184993
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902379084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2902379084
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.756953363
Short name T296
Test name
Test status
Simulation time 60893515 ps
CPU time 2.63 seconds
Started Aug 14 04:44:46 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 198136 kb
Host smart-1a5c93c1-a86f-4ec9-8b14-0a28580af587
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756953363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.756953363
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.4089984576
Short name T23
Test name
Test status
Simulation time 62684848 ps
CPU time 1.21 seconds
Started Aug 14 04:44:22 PM PDT 24
Finished Aug 14 04:44:23 PM PDT 24
Peak memory 196028 kb
Host smart-4e254019-87c1-4111-a0b8-79ec75db2835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089984576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.4089984576
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3761974837
Short name T695
Test name
Test status
Simulation time 311043597 ps
CPU time 1.11 seconds
Started Aug 14 04:44:29 PM PDT 24
Finished Aug 14 04:44:30 PM PDT 24
Peak memory 197124 kb
Host smart-78ae786c-b76c-4c23-bdad-1e5f694de0c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761974837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3761974837
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3678163109
Short name T564
Test name
Test status
Simulation time 5896548528 ps
CPU time 113.06 seconds
Started Aug 14 04:44:13 PM PDT 24
Finished Aug 14 04:46:06 PM PDT 24
Peak memory 198364 kb
Host smart-ea327e15-e3f2-4ffa-8683-021836a103b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678163109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3678163109
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3722966529
Short name T226
Test name
Test status
Simulation time 68735517 ps
CPU time 0.56 seconds
Started Aug 14 04:44:44 PM PDT 24
Finished Aug 14 04:44:44 PM PDT 24
Peak memory 194272 kb
Host smart-ddc84443-6415-4ca6-90bd-6db2089b4c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722966529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3722966529
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3949473948
Short name T193
Test name
Test status
Simulation time 61076945 ps
CPU time 0.72 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:48 PM PDT 24
Peak memory 195368 kb
Host smart-57da536c-4caa-4db1-bc9e-fbc483c6f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949473948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3949473948
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.4182516622
Short name T456
Test name
Test status
Simulation time 804577689 ps
CPU time 22.68 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:37 PM PDT 24
Peak memory 197996 kb
Host smart-738df45b-517a-4f64-96c2-29f88c86b001
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182516622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.4182516622
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.418514720
Short name T374
Test name
Test status
Simulation time 248565441 ps
CPU time 1.03 seconds
Started Aug 14 04:44:57 PM PDT 24
Finished Aug 14 04:44:58 PM PDT 24
Peak memory 198024 kb
Host smart-3facda49-1420-4055-a600-382782f6882e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418514720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.418514720
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.660665642
Short name T467
Test name
Test status
Simulation time 16318654 ps
CPU time 0.67 seconds
Started Aug 14 04:44:20 PM PDT 24
Finished Aug 14 04:44:21 PM PDT 24
Peak memory 194580 kb
Host smart-3b1410f3-f2b3-4b96-9da9-fd93881d1914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660665642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.660665642
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1450021956
Short name T487
Test name
Test status
Simulation time 61935959 ps
CPU time 1.32 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:44:16 PM PDT 24
Peak memory 196648 kb
Host smart-a15b51a2-db42-4adc-9e7d-2d4d026fd76c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450021956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1450021956
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2206607299
Short name T424
Test name
Test status
Simulation time 386520743 ps
CPU time 3.06 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 197288 kb
Host smart-a9db51a6-b7e7-4532-a00c-5ddf523036d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206607299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2206607299
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.744423143
Short name T506
Test name
Test status
Simulation time 37203353 ps
CPU time 0.83 seconds
Started Aug 14 04:44:33 PM PDT 24
Finished Aug 14 04:44:34 PM PDT 24
Peak memory 196728 kb
Host smart-0478bc83-e0cf-42d1-8138-6afc72b1b9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744423143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.744423143
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.4200580241
Short name T489
Test name
Test status
Simulation time 40716669 ps
CPU time 0.77 seconds
Started Aug 14 04:44:14 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 195696 kb
Host smart-795d56d1-e0c1-4060-aeb0-d120b9771416
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200580241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.4200580241
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.551398411
Short name T364
Test name
Test status
Simulation time 36037945 ps
CPU time 1.53 seconds
Started Aug 14 04:44:22 PM PDT 24
Finished Aug 14 04:44:24 PM PDT 24
Peak memory 198004 kb
Host smart-61fcb0aa-493d-46fa-80b3-8f106ec619c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551398411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.551398411
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.222361619
Short name T39
Test name
Test status
Simulation time 74063387 ps
CPU time 0.8 seconds
Started Aug 14 04:44:27 PM PDT 24
Finished Aug 14 04:44:27 PM PDT 24
Peak memory 196092 kb
Host smart-b3fdeb9b-478e-4c72-9f71-3786f721704b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222361619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.222361619
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.604583373
Short name T270
Test name
Test status
Simulation time 65593193 ps
CPU time 1.09 seconds
Started Aug 14 04:44:49 PM PDT 24
Finished Aug 14 04:44:51 PM PDT 24
Peak memory 195716 kb
Host smart-17b53c49-6c01-47ac-aadd-52a8902d5576
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604583373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.604583373
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2251842240
Short name T418
Test name
Test status
Simulation time 34529062864 ps
CPU time 156.1 seconds
Started Aug 14 04:44:33 PM PDT 24
Finished Aug 14 04:47:09 PM PDT 24
Peak memory 198188 kb
Host smart-60be8c5c-0960-4b28-930f-e0f051d3df2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251842240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2251842240
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2931351860
Short name T429
Test name
Test status
Simulation time 40956269 ps
CPU time 0.63 seconds
Started Aug 14 04:44:48 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 194784 kb
Host smart-43dd0a10-c476-4ffb-aec3-461e5748f27e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931351860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2931351860
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3496308524
Short name T655
Test name
Test status
Simulation time 23662401 ps
CPU time 0.66 seconds
Started Aug 14 04:44:23 PM PDT 24
Finished Aug 14 04:44:24 PM PDT 24
Peak memory 194132 kb
Host smart-99c48112-375b-4697-8066-c8048b94f72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496308524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3496308524
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3239319983
Short name T156
Test name
Test status
Simulation time 726655915 ps
CPU time 21.57 seconds
Started Aug 14 04:44:25 PM PDT 24
Finished Aug 14 04:44:46 PM PDT 24
Peak memory 196812 kb
Host smart-2d0e9424-f8ee-4690-bbb8-04877278e312
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239319983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3239319983
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1381228029
Short name T545
Test name
Test status
Simulation time 55565620 ps
CPU time 0.84 seconds
Started Aug 14 04:45:09 PM PDT 24
Finished Aug 14 04:45:10 PM PDT 24
Peak memory 196732 kb
Host smart-469d8f15-86b3-4128-b270-88258a434563
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381228029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1381228029
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1965441648
Short name T251
Test name
Test status
Simulation time 26076373 ps
CPU time 0.69 seconds
Started Aug 14 04:44:29 PM PDT 24
Finished Aug 14 04:44:30 PM PDT 24
Peak memory 194480 kb
Host smart-af37f3d1-8b80-4477-864a-f42e52aa434c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965441648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1965441648
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3804718698
Short name T441
Test name
Test status
Simulation time 362843911 ps
CPU time 3.55 seconds
Started Aug 14 04:44:52 PM PDT 24
Finished Aug 14 04:44:56 PM PDT 24
Peak memory 198128 kb
Host smart-b891b93d-d45a-4afe-b673-d0fa95cd470d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804718698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3804718698
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1274077744
Short name T400
Test name
Test status
Simulation time 248390472 ps
CPU time 0.87 seconds
Started Aug 14 04:44:31 PM PDT 24
Finished Aug 14 04:44:32 PM PDT 24
Peak memory 195552 kb
Host smart-1e8d78fc-6a24-4522-8e80-856da732e9a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274077744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1274077744
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3293219464
Short name T207
Test name
Test status
Simulation time 35623811 ps
CPU time 0.82 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 195412 kb
Host smart-02bc2cd9-35d5-446f-b726-87cd135261a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293219464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3293219464
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2743334331
Short name T371
Test name
Test status
Simulation time 30730790 ps
CPU time 0.74 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:44:16 PM PDT 24
Peak memory 196332 kb
Host smart-f2d34d1f-0519-4d58-bb06-4a39601d019b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743334331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2743334331
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1991201547
Short name T573
Test name
Test status
Simulation time 74260769 ps
CPU time 3.45 seconds
Started Aug 14 04:44:45 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 198208 kb
Host smart-af70db7a-5957-45ca-838c-1c543ab67901
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991201547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1991201547
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.463837245
Short name T318
Test name
Test status
Simulation time 64987394 ps
CPU time 0.75 seconds
Started Aug 14 04:44:59 PM PDT 24
Finished Aug 14 04:45:00 PM PDT 24
Peak memory 195336 kb
Host smart-609c7f9f-ba4e-4080-991e-37b0e837ee20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463837245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.463837245
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2767480287
Short name T276
Test name
Test status
Simulation time 40902294 ps
CPU time 0.99 seconds
Started Aug 14 04:44:38 PM PDT 24
Finished Aug 14 04:44:39 PM PDT 24
Peak memory 195988 kb
Host smart-1c47d1f8-a2c3-4a47-bbc1-0394962bc8ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767480287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2767480287
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1749594108
Short name T546
Test name
Test status
Simulation time 9216889852 ps
CPU time 121.74 seconds
Started Aug 14 04:44:29 PM PDT 24
Finished Aug 14 04:46:30 PM PDT 24
Peak memory 198248 kb
Host smart-26958417-3bf9-47e8-b012-7745f2932cdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749594108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1749594108
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.3052496335
Short name T64
Test name
Test status
Simulation time 850183011 ps
CPU time 16.51 seconds
Started Aug 14 04:44:40 PM PDT 24
Finished Aug 14 04:44:57 PM PDT 24
Peak memory 197528 kb
Host smart-52c64b92-f057-4ca9-9d60-785d776e38a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3052496335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.3052496335
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2168155424
Short name T624
Test name
Test status
Simulation time 40209837 ps
CPU time 0.59 seconds
Started Aug 14 04:44:40 PM PDT 24
Finished Aug 14 04:44:41 PM PDT 24
Peak memory 194300 kb
Host smart-bb43ab6e-1f33-46a0-9b4c-df6863231401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168155424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2168155424
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.505460912
Short name T147
Test name
Test status
Simulation time 35915690 ps
CPU time 0.79 seconds
Started Aug 14 04:44:25 PM PDT 24
Finished Aug 14 04:44:26 PM PDT 24
Peak memory 195452 kb
Host smart-448f1d66-de53-41bd-b964-c3c71d3076a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505460912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.505460912
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.4257645153
Short name T585
Test name
Test status
Simulation time 84904657 ps
CPU time 4.1 seconds
Started Aug 14 04:44:48 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 196748 kb
Host smart-713a3301-9201-4f78-a5ec-b2b28d92c283
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257645153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.4257645153
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1375036033
Short name T335
Test name
Test status
Simulation time 45974855 ps
CPU time 0.9 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:48 PM PDT 24
Peak memory 197344 kb
Host smart-82780a72-5483-471b-8107-d8f578463b64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375036033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1375036033
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2063676231
Short name T473
Test name
Test status
Simulation time 94207896 ps
CPU time 1.48 seconds
Started Aug 14 04:44:33 PM PDT 24
Finished Aug 14 04:44:35 PM PDT 24
Peak memory 197232 kb
Host smart-9392adfe-8f22-44d3-8ce6-ca31bd466dc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063676231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2063676231
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1839979629
Short name T389
Test name
Test status
Simulation time 313230340 ps
CPU time 1.89 seconds
Started Aug 14 04:44:45 PM PDT 24
Finished Aug 14 04:44:47 PM PDT 24
Peak memory 197276 kb
Host smart-b25456c8-303c-4296-82f8-903000e47801
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839979629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1839979629
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2543268772
Short name T402
Test name
Test status
Simulation time 41236701 ps
CPU time 0.94 seconds
Started Aug 14 04:44:16 PM PDT 24
Finished Aug 14 04:44:17 PM PDT 24
Peak memory 196192 kb
Host smart-e844e4ec-2624-452c-9c28-4ba4d98c33ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543268772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2543268772
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.4045488202
Short name T579
Test name
Test status
Simulation time 16916796 ps
CPU time 0.63 seconds
Started Aug 14 04:44:26 PM PDT 24
Finished Aug 14 04:44:27 PM PDT 24
Peak memory 194304 kb
Host smart-eac3f9cf-9fe4-4ad2-b8b5-6cdbac2d9cfa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045488202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.4045488202
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1315653057
Short name T101
Test name
Test status
Simulation time 521198271 ps
CPU time 2.31 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 198148 kb
Host smart-db8fdf91-1db4-4bc6-b6fd-c47fd3d21f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315653057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1315653057
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.659100441
Short name T204
Test name
Test status
Simulation time 33522480 ps
CPU time 0.77 seconds
Started Aug 14 04:44:24 PM PDT 24
Finished Aug 14 04:44:25 PM PDT 24
Peak memory 195292 kb
Host smart-57d2aa3a-28ec-4712-92a2-ef88229fa582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659100441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.659100441
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3870769181
Short name T298
Test name
Test status
Simulation time 45818106 ps
CPU time 0.92 seconds
Started Aug 14 04:44:38 PM PDT 24
Finished Aug 14 04:44:39 PM PDT 24
Peak memory 197368 kb
Host smart-1abd3626-6ce4-45ba-be5f-a2bc90a03452
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870769181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3870769181
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3424857895
Short name T559
Test name
Test status
Simulation time 15433138282 ps
CPU time 91.27 seconds
Started Aug 14 04:44:46 PM PDT 24
Finished Aug 14 04:46:17 PM PDT 24
Peak memory 198392 kb
Host smart-68b90da7-a7d9-4c9c-9c43-118ca078e1aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424857895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3424857895
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1382759845
Short name T463
Test name
Test status
Simulation time 6593814781 ps
CPU time 218.6 seconds
Started Aug 14 04:44:53 PM PDT 24
Finished Aug 14 04:48:32 PM PDT 24
Peak memory 198492 kb
Host smart-7e915df1-dd46-4567-acf2-2e66ea905950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1382759845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1382759845
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2032821611
Short name T642
Test name
Test status
Simulation time 46046619 ps
CPU time 0.57 seconds
Started Aug 14 04:44:51 PM PDT 24
Finished Aug 14 04:44:52 PM PDT 24
Peak memory 194272 kb
Host smart-4580c309-6f6e-426f-90a8-bb702fe35981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032821611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2032821611
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3326870149
Short name T486
Test name
Test status
Simulation time 20404333 ps
CPU time 0.62 seconds
Started Aug 14 04:45:23 PM PDT 24
Finished Aug 14 04:45:24 PM PDT 24
Peak memory 194852 kb
Host smart-0566f682-1ebd-4a30-b0f8-5892a36c7085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326870149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3326870149
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.330644032
Short name T246
Test name
Test status
Simulation time 2258494065 ps
CPU time 17.6 seconds
Started Aug 14 04:44:52 PM PDT 24
Finished Aug 14 04:45:10 PM PDT 24
Peak memory 196592 kb
Host smart-75d5d5bb-28d2-4996-abbd-ecffbbc4144a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330644032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.330644032
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3064818427
Short name T686
Test name
Test status
Simulation time 280030880 ps
CPU time 0.92 seconds
Started Aug 14 04:44:44 PM PDT 24
Finished Aug 14 04:44:45 PM PDT 24
Peak memory 197212 kb
Host smart-4767b3b1-1478-4de5-a8b7-6f954686c343
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064818427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3064818427
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.823409007
Short name T460
Test name
Test status
Simulation time 37821998 ps
CPU time 0.79 seconds
Started Aug 14 04:44:51 PM PDT 24
Finished Aug 14 04:44:52 PM PDT 24
Peak memory 195588 kb
Host smart-a18e309c-3f5d-4bd9-93f3-0636291f92ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823409007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.823409007
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.4238777706
Short name T638
Test name
Test status
Simulation time 58619583 ps
CPU time 2.39 seconds
Started Aug 14 04:44:50 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 198296 kb
Host smart-fad10fce-d712-4240-91fa-295e5cf09775
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238777706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.4238777706
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2145237428
Short name T379
Test name
Test status
Simulation time 198527990 ps
CPU time 2.28 seconds
Started Aug 14 04:44:50 PM PDT 24
Finished Aug 14 04:44:52 PM PDT 24
Peak memory 196780 kb
Host smart-3748980b-0a4b-4bf0-a563-aefcf9d25365
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145237428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2145237428
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.662349621
Short name T13
Test name
Test status
Simulation time 82785525 ps
CPU time 1 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:48 PM PDT 24
Peak memory 196748 kb
Host smart-6849d83f-f2ed-431a-82f5-e69b738f1702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662349621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.662349621
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2372953636
Short name T157
Test name
Test status
Simulation time 79542550 ps
CPU time 0.89 seconds
Started Aug 14 04:45:01 PM PDT 24
Finished Aug 14 04:45:02 PM PDT 24
Peak memory 196152 kb
Host smart-b0737e66-009d-4150-8d9d-931545b5bbf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372953636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2372953636
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2251283540
Short name T178
Test name
Test status
Simulation time 1231770785 ps
CPU time 4.31 seconds
Started Aug 14 04:44:56 PM PDT 24
Finished Aug 14 04:45:00 PM PDT 24
Peak memory 198136 kb
Host smart-3b796096-f29b-45f3-9e1d-269a7c0625a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251283540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2251283540
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.4051352120
Short name T316
Test name
Test status
Simulation time 116597433 ps
CPU time 0.81 seconds
Started Aug 14 04:44:34 PM PDT 24
Finished Aug 14 04:44:35 PM PDT 24
Peak memory 195496 kb
Host smart-cbeaa88f-b54c-4d81-8258-01aeef753b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051352120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.4051352120
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1852134588
Short name T136
Test name
Test status
Simulation time 295691994 ps
CPU time 0.97 seconds
Started Aug 14 04:44:48 PM PDT 24
Finished Aug 14 04:44:50 PM PDT 24
Peak memory 196484 kb
Host smart-ee7301b0-0806-4920-adcd-d3f35f88761c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852134588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1852134588
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1405044748
Short name T464
Test name
Test status
Simulation time 17507999667 ps
CPU time 41.23 seconds
Started Aug 14 04:44:33 PM PDT 24
Finished Aug 14 04:45:14 PM PDT 24
Peak memory 198380 kb
Host smart-59e57c1e-6f2b-4093-8849-ff1c10cb8dd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405044748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1405044748
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.832670129
Short name T260
Test name
Test status
Simulation time 15499886 ps
CPU time 0.61 seconds
Started Aug 14 04:44:49 PM PDT 24
Finished Aug 14 04:44:50 PM PDT 24
Peak memory 194288 kb
Host smart-518337ed-c391-4bc8-8823-e1cb773616b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832670129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.832670129
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3548391539
Short name T210
Test name
Test status
Simulation time 35235752 ps
CPU time 0.77 seconds
Started Aug 14 04:44:41 PM PDT 24
Finished Aug 14 04:44:42 PM PDT 24
Peak memory 195424 kb
Host smart-3d4342e9-50b0-421c-9e5b-5f70e00ab990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548391539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3548391539
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.4256015081
Short name T701
Test name
Test status
Simulation time 1205589556 ps
CPU time 9.65 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:57 PM PDT 24
Peak memory 195528 kb
Host smart-498b6c03-f349-43f3-84aa-78046571e65b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256015081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.4256015081
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2099083600
Short name T423
Test name
Test status
Simulation time 44347937 ps
CPU time 0.77 seconds
Started Aug 14 04:44:39 PM PDT 24
Finished Aug 14 04:44:40 PM PDT 24
Peak memory 196720 kb
Host smart-91ae3234-8da3-4333-a893-2bb635823b57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099083600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2099083600
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3273400543
Short name T206
Test name
Test status
Simulation time 51664009 ps
CPU time 1.33 seconds
Started Aug 14 04:44:41 PM PDT 24
Finished Aug 14 04:44:43 PM PDT 24
Peak memory 196012 kb
Host smart-4dcbe6e0-8c9b-4e72-a9c7-2bc44e7cba9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273400543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3273400543
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.203482293
Short name T494
Test name
Test status
Simulation time 420159487 ps
CPU time 1.39 seconds
Started Aug 14 04:44:41 PM PDT 24
Finished Aug 14 04:44:43 PM PDT 24
Peak memory 198192 kb
Host smart-ec08e037-e40d-4196-baf0-6a4d1eb233eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203482293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.203482293
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.222038683
Short name T12
Test name
Test status
Simulation time 174479701 ps
CPU time 3.11 seconds
Started Aug 14 04:44:49 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 196736 kb
Host smart-db4b9df7-f8d4-4520-9c79-42c71a07c2e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222038683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
222038683
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1016426093
Short name T485
Test name
Test status
Simulation time 129039246 ps
CPU time 0.8 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:48 PM PDT 24
Peak memory 196684 kb
Host smart-31a8f91e-d0d3-4ab8-8fc7-631538dbaf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016426093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1016426093
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2013505192
Short name T217
Test name
Test status
Simulation time 122549816 ps
CPU time 0.92 seconds
Started Aug 14 04:44:48 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 196916 kb
Host smart-55846127-3605-405a-945f-811e3fa7a9b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013505192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2013505192
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.4181877808
Short name T3
Test name
Test status
Simulation time 385687569 ps
CPU time 4.53 seconds
Started Aug 14 04:44:52 PM PDT 24
Finished Aug 14 04:44:56 PM PDT 24
Peak memory 198160 kb
Host smart-49dfc461-bdf2-41a3-97ac-63a70a4fac52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181877808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.4181877808
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2207745843
Short name T282
Test name
Test status
Simulation time 178110835 ps
CPU time 1.24 seconds
Started Aug 14 04:44:42 PM PDT 24
Finished Aug 14 04:44:44 PM PDT 24
Peak memory 198164 kb
Host smart-e3fd358e-d8be-4c30-9335-02564d7b069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207745843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2207745843
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1484573066
Short name T153
Test name
Test status
Simulation time 78091785 ps
CPU time 1.46 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 198176 kb
Host smart-4eb4d293-f0b7-4acb-8a22-966dd5cc3493
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484573066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1484573066
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3145988287
Short name T447
Test name
Test status
Simulation time 63044160867 ps
CPU time 176.39 seconds
Started Aug 14 04:44:34 PM PDT 24
Finished Aug 14 04:47:31 PM PDT 24
Peak memory 198352 kb
Host smart-92ae8479-d2cc-4cac-a5a3-585654a23f10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145988287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3145988287
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.623857608
Short name T541
Test name
Test status
Simulation time 19185136 ps
CPU time 0.58 seconds
Started Aug 14 04:44:48 PM PDT 24
Finished Aug 14 04:44:49 PM PDT 24
Peak memory 194100 kb
Host smart-c3a77781-5303-49ea-bed8-0b43ac3a077d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623857608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.623857608
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.18716966
Short name T205
Test name
Test status
Simulation time 33575767 ps
CPU time 0.74 seconds
Started Aug 14 04:44:55 PM PDT 24
Finished Aug 14 04:44:56 PM PDT 24
Peak memory 195276 kb
Host smart-0f875d77-2d47-4769-8e07-6e22946b95af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18716966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.18716966
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1948781621
Short name T484
Test name
Test status
Simulation time 1463052135 ps
CPU time 20.95 seconds
Started Aug 14 04:44:44 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 196472 kb
Host smart-6dc9b3bf-b831-42da-af4d-5aa95a053700
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948781621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1948781621
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1608263832
Short name T237
Test name
Test status
Simulation time 47861553 ps
CPU time 0.82 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 196872 kb
Host smart-ed888c74-60bc-4616-90f9-5feb04a69de6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608263832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1608263832
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.44855586
Short name T254
Test name
Test status
Simulation time 44398596 ps
CPU time 1.14 seconds
Started Aug 14 04:44:50 PM PDT 24
Finished Aug 14 04:44:51 PM PDT 24
Peak memory 196000 kb
Host smart-31e41ef7-01e9-40e3-aea6-1d7415d3087a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44855586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.44855586
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3452177987
Short name T22
Test name
Test status
Simulation time 638530205 ps
CPU time 3.26 seconds
Started Aug 14 04:44:34 PM PDT 24
Finished Aug 14 04:44:37 PM PDT 24
Peak memory 198264 kb
Host smart-75958c7a-a77f-4140-a9ac-673176be6fba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452177987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3452177987
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2787997811
Short name T443
Test name
Test status
Simulation time 114772102 ps
CPU time 2.42 seconds
Started Aug 14 04:44:52 PM PDT 24
Finished Aug 14 04:44:54 PM PDT 24
Peak memory 198220 kb
Host smart-090ede2e-87c6-435d-aeeb-cb2d3fdede9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787997811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2787997811
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2173956966
Short name T126
Test name
Test status
Simulation time 314809295 ps
CPU time 1.07 seconds
Started Aug 14 04:44:51 PM PDT 24
Finished Aug 14 04:44:52 PM PDT 24
Peak memory 196960 kb
Host smart-517b36f6-4e26-4eba-ac28-3644a3dc45f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173956966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2173956966
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3980728720
Short name T30
Test name
Test status
Simulation time 200073474 ps
CPU time 1.19 seconds
Started Aug 14 04:44:56 PM PDT 24
Finished Aug 14 04:44:57 PM PDT 24
Peak memory 197260 kb
Host smart-cc209dae-80b7-4302-ab9d-fc4ac4f9c460
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980728720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3980728720
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.4216727618
Short name T394
Test name
Test status
Simulation time 366919675 ps
CPU time 3.05 seconds
Started Aug 14 04:44:40 PM PDT 24
Finished Aug 14 04:44:43 PM PDT 24
Peak memory 198056 kb
Host smart-bcdff221-c65c-494f-b8f0-c484efc78c03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216727618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.4216727618
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2135661643
Short name T278
Test name
Test status
Simulation time 55097234 ps
CPU time 0.96 seconds
Started Aug 14 04:44:55 PM PDT 24
Finished Aug 14 04:44:56 PM PDT 24
Peak memory 195696 kb
Host smart-d414544c-96b5-4e7d-b143-8d3eb913ab8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135661643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2135661643
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1978804106
Short name T395
Test name
Test status
Simulation time 150199458 ps
CPU time 1.06 seconds
Started Aug 14 04:44:51 PM PDT 24
Finished Aug 14 04:44:52 PM PDT 24
Peak memory 195972 kb
Host smart-75e3bd0e-8716-474d-8a39-202e59676de3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978804106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1978804106
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.301586738
Short name T591
Test name
Test status
Simulation time 12791280937 ps
CPU time 150.26 seconds
Started Aug 14 04:44:48 PM PDT 24
Finished Aug 14 04:47:18 PM PDT 24
Peak memory 198388 kb
Host smart-31cff94a-77c3-45aa-8792-33f799551a92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301586738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.301586738
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1663617665
Short name T690
Test name
Test status
Simulation time 40732159 ps
CPU time 0.6 seconds
Started Aug 14 04:44:53 PM PDT 24
Finished Aug 14 04:44:54 PM PDT 24
Peak memory 195124 kb
Host smart-42c6fdd3-6afd-4b32-b1bd-be0638915ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663617665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1663617665
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2116931483
Short name T328
Test name
Test status
Simulation time 36225203 ps
CPU time 0.77 seconds
Started Aug 14 04:44:53 PM PDT 24
Finished Aug 14 04:45:00 PM PDT 24
Peak memory 196184 kb
Host smart-45e666e5-59d8-4c61-b0d9-e0f34a87435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116931483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2116931483
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.668194485
Short name T528
Test name
Test status
Simulation time 429264815 ps
CPU time 20.94 seconds
Started Aug 14 04:44:53 PM PDT 24
Finished Aug 14 04:45:15 PM PDT 24
Peak memory 195640 kb
Host smart-a29dd267-6476-49fa-9f60-da4b3cfbbde0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668194485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.668194485
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.4290834177
Short name T174
Test name
Test status
Simulation time 24264239 ps
CPU time 0.66 seconds
Started Aug 14 04:45:01 PM PDT 24
Finished Aug 14 04:45:02 PM PDT 24
Peak memory 194528 kb
Host smart-20cece6c-2f4c-4273-87e8-db9b4a469ca0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290834177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.4290834177
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.939962417
Short name T501
Test name
Test status
Simulation time 230969859 ps
CPU time 0.99 seconds
Started Aug 14 04:44:55 PM PDT 24
Finished Aug 14 04:44:56 PM PDT 24
Peak memory 195900 kb
Host smart-839fe10b-55d2-494b-ba2a-c09377b864ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939962417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.939962417
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.466503813
Short name T116
Test name
Test status
Simulation time 312834719 ps
CPU time 2.17 seconds
Started Aug 14 04:44:51 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 198232 kb
Host smart-5998a8a7-5bae-4e88-b4c6-fbcb29aebfe2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466503813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.466503813
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.4020151292
Short name T461
Test name
Test status
Simulation time 176554250 ps
CPU time 2.59 seconds
Started Aug 14 04:44:55 PM PDT 24
Finished Aug 14 04:44:57 PM PDT 24
Peak memory 196892 kb
Host smart-5ef4e55e-a3f8-4d48-8fa0-047a15f87d7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020151292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.4020151292
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.559537359
Short name T534
Test name
Test status
Simulation time 43948385 ps
CPU time 0.65 seconds
Started Aug 14 04:44:40 PM PDT 24
Finished Aug 14 04:44:45 PM PDT 24
Peak memory 194284 kb
Host smart-f78343a5-1cde-462e-a893-fc7bed897cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559537359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.559537359
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3707094970
Short name T326
Test name
Test status
Simulation time 100713740 ps
CPU time 1.11 seconds
Started Aug 14 04:44:36 PM PDT 24
Finished Aug 14 04:44:37 PM PDT 24
Peak memory 196760 kb
Host smart-55dbdc40-e5f3-469b-9187-16fb02c4daa6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707094970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3707094970
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2108303055
Short name T553
Test name
Test status
Simulation time 330739161 ps
CPU time 5.2 seconds
Started Aug 14 04:45:01 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 198068 kb
Host smart-5532b234-cfde-4da7-af7d-6fc7e5b98179
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108303055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2108303055
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1126667000
Short name T575
Test name
Test status
Simulation time 318866563 ps
CPU time 0.9 seconds
Started Aug 14 04:44:46 PM PDT 24
Finished Aug 14 04:44:47 PM PDT 24
Peak memory 195944 kb
Host smart-bdb108f6-ef63-4684-b39a-6505acf9bfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126667000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1126667000
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.744393830
Short name T366
Test name
Test status
Simulation time 20082484 ps
CPU time 0.76 seconds
Started Aug 14 04:44:55 PM PDT 24
Finished Aug 14 04:44:56 PM PDT 24
Peak memory 196004 kb
Host smart-c33dd8fc-d685-4ec1-8cb4-fb790737e1ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744393830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.744393830
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.4253460726
Short name T576
Test name
Test status
Simulation time 21450928554 ps
CPU time 41.21 seconds
Started Aug 14 04:44:51 PM PDT 24
Finished Aug 14 04:45:32 PM PDT 24
Peak memory 192204 kb
Host smart-5d496dfb-f4a1-4578-860c-9c8dd9969b5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253460726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.4253460726
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1746309659
Short name T674
Test name
Test status
Simulation time 14102985 ps
CPU time 0.59 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:02 PM PDT 24
Peak memory 194084 kb
Host smart-9c59ad5b-4043-4623-b9a7-2116f2f89efe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746309659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1746309659
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3992135295
Short name T149
Test name
Test status
Simulation time 108264979 ps
CPU time 0.88 seconds
Started Aug 14 04:44:54 PM PDT 24
Finished Aug 14 04:44:55 PM PDT 24
Peak memory 195708 kb
Host smart-5570f7b1-964b-4c37-a0fa-f7e3f268d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992135295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3992135295
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.4056898503
Short name T173
Test name
Test status
Simulation time 6925435048 ps
CPU time 19.47 seconds
Started Aug 14 04:44:59 PM PDT 24
Finished Aug 14 04:45:19 PM PDT 24
Peak memory 198156 kb
Host smart-e725f880-4ee0-4e38-8710-f25b7a996c77
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056898503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.4056898503
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.309554777
Short name T457
Test name
Test status
Simulation time 176489319 ps
CPU time 0.72 seconds
Started Aug 14 04:45:00 PM PDT 24
Finished Aug 14 04:45:01 PM PDT 24
Peak memory 195832 kb
Host smart-746f072c-afea-446f-ab04-62f9298630b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309554777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.309554777
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.150736787
Short name T109
Test name
Test status
Simulation time 210761017 ps
CPU time 1.44 seconds
Started Aug 14 04:44:49 PM PDT 24
Finished Aug 14 04:44:50 PM PDT 24
Peak memory 198236 kb
Host smart-a33cbfd3-ffe7-4277-855f-e9cb1f648b38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150736787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.150736787
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.813310529
Short name T172
Test name
Test status
Simulation time 79798362 ps
CPU time 1.69 seconds
Started Aug 14 04:45:00 PM PDT 24
Finished Aug 14 04:45:02 PM PDT 24
Peak memory 198232 kb
Host smart-5cfb7528-18dc-4b79-8a1f-5d1039ad0d6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813310529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.813310529
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.4288257803
Short name T213
Test name
Test status
Simulation time 678648511 ps
CPU time 2.88 seconds
Started Aug 14 04:44:55 PM PDT 24
Finished Aug 14 04:44:58 PM PDT 24
Peak memory 195880 kb
Host smart-c0589959-a5a3-49f1-b5b4-804f72d340d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288257803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.4288257803
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2330558425
Short name T358
Test name
Test status
Simulation time 23363697 ps
CPU time 0.88 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 196736 kb
Host smart-437e6708-fee1-4f25-8de3-09e62ccdecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330558425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2330558425
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2604010025
Short name T261
Test name
Test status
Simulation time 222744664 ps
CPU time 0.93 seconds
Started Aug 14 04:44:37 PM PDT 24
Finished Aug 14 04:44:38 PM PDT 24
Peak memory 196060 kb
Host smart-edab16a9-f555-4129-84ea-6973d1556e5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604010025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2604010025
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2219641016
Short name T491
Test name
Test status
Simulation time 191970698 ps
CPU time 1.07 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:12 PM PDT 24
Peak memory 198116 kb
Host smart-f70396e9-3b6d-4d7f-9eab-ba4e783e3bda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219641016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2219641016
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2253777333
Short name T637
Test name
Test status
Simulation time 40655549 ps
CPU time 1.12 seconds
Started Aug 14 04:44:47 PM PDT 24
Finished Aug 14 04:44:48 PM PDT 24
Peak memory 196516 kb
Host smart-58271586-68f9-4110-82d5-c1820b06fe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253777333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2253777333
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.658461267
Short name T618
Test name
Test status
Simulation time 69306263 ps
CPU time 1.07 seconds
Started Aug 14 04:44:40 PM PDT 24
Finished Aug 14 04:44:41 PM PDT 24
Peak memory 196592 kb
Host smart-b3d62380-8e75-4a07-be51-91dd0a3a7825
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658461267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.658461267
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2756123054
Short name T703
Test name
Test status
Simulation time 72889130974 ps
CPU time 147.89 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:47:37 PM PDT 24
Peak memory 198396 kb
Host smart-09028cdd-fc8b-4b38-adfa-d24dc260877c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756123054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2756123054
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.3156641782
Short name T31
Test name
Test status
Simulation time 2296972859 ps
CPU time 22.17 seconds
Started Aug 14 04:45:15 PM PDT 24
Finished Aug 14 04:45:38 PM PDT 24
Peak memory 198076 kb
Host smart-c37f32f7-f80e-4c20-9c39-9fdbcdd84487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3156641782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.3156641782
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2296971801
Short name T332
Test name
Test status
Simulation time 41186443 ps
CPU time 0.57 seconds
Started Aug 14 04:43:48 PM PDT 24
Finished Aug 14 04:43:49 PM PDT 24
Peak memory 193940 kb
Host smart-6cdc89cb-ed30-45e2-8821-163ea48bde13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296971801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2296971801
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3924748863
Short name T344
Test name
Test status
Simulation time 47694608 ps
CPU time 0.93 seconds
Started Aug 14 04:43:29 PM PDT 24
Finished Aug 14 04:43:41 PM PDT 24
Peak memory 196524 kb
Host smart-5f97d091-7ed0-4ef0-9e58-5746d0b28ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924748863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3924748863
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3198829429
Short name T390
Test name
Test status
Simulation time 1595073960 ps
CPU time 21.02 seconds
Started Aug 14 04:43:42 PM PDT 24
Finished Aug 14 04:44:04 PM PDT 24
Peak memory 196748 kb
Host smart-7f12013d-4d99-4bb8-b69e-84cedf25d8d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198829429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3198829429
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2729127722
Short name T369
Test name
Test status
Simulation time 47941764 ps
CPU time 0.81 seconds
Started Aug 14 04:43:54 PM PDT 24
Finished Aug 14 04:43:55 PM PDT 24
Peak memory 196660 kb
Host smart-1484b060-2696-4aa1-a32c-1870929af0db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729127722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2729127722
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3091810930
Short name T608
Test name
Test status
Simulation time 121340536 ps
CPU time 1.04 seconds
Started Aug 14 04:43:34 PM PDT 24
Finished Aug 14 04:43:35 PM PDT 24
Peak memory 196216 kb
Host smart-821c7a1b-065e-4b03-bc8e-9663c2fcd811
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091810930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3091810930
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1524743590
Short name T164
Test name
Test status
Simulation time 26156807 ps
CPU time 1.07 seconds
Started Aug 14 04:43:52 PM PDT 24
Finished Aug 14 04:43:53 PM PDT 24
Peak memory 196352 kb
Host smart-c3c6a9ff-bd05-456c-93e7-e4ded8b70b81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524743590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1524743590
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1710892502
Short name T100
Test name
Test status
Simulation time 362116826 ps
CPU time 3.05 seconds
Started Aug 14 04:43:27 PM PDT 24
Finished Aug 14 04:43:31 PM PDT 24
Peak memory 198144 kb
Host smart-3963e244-d04b-4a29-8a16-26640a6b1fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710892502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1710892502
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2414846592
Short name T304
Test name
Test status
Simulation time 276804632 ps
CPU time 0.85 seconds
Started Aug 14 04:43:41 PM PDT 24
Finished Aug 14 04:43:41 PM PDT 24
Peak memory 196756 kb
Host smart-478afeda-e407-444c-83e7-e5299a2ecd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414846592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2414846592
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.905551375
Short name T277
Test name
Test status
Simulation time 19656887 ps
CPU time 0.84 seconds
Started Aug 14 04:43:37 PM PDT 24
Finished Aug 14 04:43:38 PM PDT 24
Peak memory 196728 kb
Host smart-a7342dc0-7e45-4bd2-94d5-d414e4c61c2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905551375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.905551375
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3922451944
Short name T330
Test name
Test status
Simulation time 365395622 ps
CPU time 4.23 seconds
Started Aug 14 04:43:20 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 198152 kb
Host smart-b964db33-d1c3-434c-8d0e-cadccef2c006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922451944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3922451944
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.408149327
Short name T54
Test name
Test status
Simulation time 121209079 ps
CPU time 0.72 seconds
Started Aug 14 04:43:48 PM PDT 24
Finished Aug 14 04:43:49 PM PDT 24
Peak memory 214944 kb
Host smart-e8c72621-2285-4a97-b906-5c7e5b830317
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408149327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.408149327
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3731921727
Short name T215
Test name
Test status
Simulation time 75547935 ps
CPU time 1.25 seconds
Started Aug 14 04:43:33 PM PDT 24
Finished Aug 14 04:43:34 PM PDT 24
Peak memory 198188 kb
Host smart-670a5509-6181-49af-856d-64c0294a9193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731921727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3731921727
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1091433912
Short name T266
Test name
Test status
Simulation time 34213746 ps
CPU time 0.81 seconds
Started Aug 14 04:43:23 PM PDT 24
Finished Aug 14 04:43:24 PM PDT 24
Peak memory 195484 kb
Host smart-941eef2a-ec8b-4f7b-aa34-5d195bd868ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091433912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1091433912
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1241279877
Short name T56
Test name
Test status
Simulation time 13955837006 ps
CPU time 188.94 seconds
Started Aug 14 04:43:30 PM PDT 24
Finished Aug 14 04:46:39 PM PDT 24
Peak memory 198360 kb
Host smart-dd5f194f-6f4e-4467-86a4-266a47a54622
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241279877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1241279877
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1119254263
Short name T537
Test name
Test status
Simulation time 20633276859 ps
CPU time 166.8 seconds
Started Aug 14 04:43:46 PM PDT 24
Finished Aug 14 04:46:33 PM PDT 24
Peak memory 198572 kb
Host smart-a382a302-5de0-4fda-aa9e-f8ddb12fed60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1119254263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1119254263
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3352592370
Short name T350
Test name
Test status
Simulation time 12317763 ps
CPU time 0.57 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 194092 kb
Host smart-c810e7cf-bce2-4f12-8075-4af3405792a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352592370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3352592370
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3543633386
Short name T479
Test name
Test status
Simulation time 106906912 ps
CPU time 0.88 seconds
Started Aug 14 04:44:57 PM PDT 24
Finished Aug 14 04:44:58 PM PDT 24
Peak memory 196092 kb
Host smart-44d02311-6122-4087-ab60-11dfd4fe731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543633386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3543633386
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.69355757
Short name T482
Test name
Test status
Simulation time 316361698 ps
CPU time 15.9 seconds
Started Aug 14 04:45:10 PM PDT 24
Finished Aug 14 04:45:26 PM PDT 24
Peak memory 195652 kb
Host smart-be980684-3a38-4e56-abba-afd897717a95
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69355757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stress
.69355757
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.4222261179
Short name T357
Test name
Test status
Simulation time 142613539 ps
CPU time 0.93 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:03 PM PDT 24
Peak memory 196596 kb
Host smart-cff1fafa-822e-4bb3-aec1-881b34065c89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222261179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.4222261179
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3289116409
Short name T225
Test name
Test status
Simulation time 39472829 ps
CPU time 0.86 seconds
Started Aug 14 04:44:53 PM PDT 24
Finished Aug 14 04:44:54 PM PDT 24
Peak memory 197480 kb
Host smart-d90cffe4-bbfd-423a-bb10-afa02c600fe1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289116409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3289116409
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.4006752067
Short name T633
Test name
Test status
Simulation time 177813504 ps
CPU time 2.01 seconds
Started Aug 14 04:44:51 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 198272 kb
Host smart-80384a55-587f-4c2b-8442-1e5b46e39615
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006752067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.4006752067
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.4104736881
Short name T289
Test name
Test status
Simulation time 84515295 ps
CPU time 1.21 seconds
Started Aug 14 04:44:56 PM PDT 24
Finished Aug 14 04:44:57 PM PDT 24
Peak memory 195760 kb
Host smart-7f949104-0e26-4b58-a60a-d92ed723442b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104736881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.4104736881
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3921253408
Short name T685
Test name
Test status
Simulation time 61508793 ps
CPU time 0.71 seconds
Started Aug 14 04:45:00 PM PDT 24
Finished Aug 14 04:45:00 PM PDT 24
Peak memory 195436 kb
Host smart-1af1c20a-c7c2-463a-a779-43a14c73008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921253408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3921253408
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2447794753
Short name T325
Test name
Test status
Simulation time 91734040 ps
CPU time 0.96 seconds
Started Aug 14 04:44:56 PM PDT 24
Finished Aug 14 04:44:57 PM PDT 24
Peak memory 196224 kb
Host smart-595b8520-8107-40b0-a95d-3674c1cac2e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447794753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2447794753
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.743833301
Short name T480
Test name
Test status
Simulation time 141747018 ps
CPU time 3.45 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:15 PM PDT 24
Peak memory 198056 kb
Host smart-23228a11-bf95-4882-9669-5f92fd929e20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743833301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.743833301
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3639724352
Short name T665
Test name
Test status
Simulation time 44789562 ps
CPU time 0.91 seconds
Started Aug 14 04:44:57 PM PDT 24
Finished Aug 14 04:44:58 PM PDT 24
Peak memory 195628 kb
Host smart-e354d9ca-8b0c-48c8-830d-aa1516c87326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639724352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3639724352
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1495229397
Short name T492
Test name
Test status
Simulation time 236743515 ps
CPU time 1.08 seconds
Started Aug 14 04:44:53 PM PDT 24
Finished Aug 14 04:44:55 PM PDT 24
Peak memory 196612 kb
Host smart-0730b2de-3580-44d5-bf4a-a6ba048df666
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495229397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1495229397
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.241583104
Short name T691
Test name
Test status
Simulation time 7314243669 ps
CPU time 96.01 seconds
Started Aug 14 04:44:57 PM PDT 24
Finished Aug 14 04:46:33 PM PDT 24
Peak memory 198272 kb
Host smart-a479146e-1839-4710-8ac4-aa49f1e08900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241583104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.241583104
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.443481416
Short name T498
Test name
Test status
Simulation time 38173125180 ps
CPU time 272.33 seconds
Started Aug 14 04:44:52 PM PDT 24
Finished Aug 14 04:49:24 PM PDT 24
Peak memory 198484 kb
Host smart-caf0ade9-2509-4c79-8fde-a9030a5a282d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=443481416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.443481416
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3223262516
Short name T605
Test name
Test status
Simulation time 16270750 ps
CPU time 0.6 seconds
Started Aug 14 04:44:52 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 194260 kb
Host smart-f8b8cade-557e-40e3-9f06-0ed13d4e962c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223262516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3223262516
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3602471572
Short name T281
Test name
Test status
Simulation time 26898561 ps
CPU time 0.71 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:12 PM PDT 24
Peak memory 195284 kb
Host smart-2cc2a49c-015d-4763-82da-575969916fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602471572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3602471572
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2574458449
Short name T168
Test name
Test status
Simulation time 459604952 ps
CPU time 12.11 seconds
Started Aug 14 04:44:59 PM PDT 24
Finished Aug 14 04:45:11 PM PDT 24
Peak memory 198000 kb
Host smart-c7d25e85-8846-4786-a180-0c6a4468c527
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574458449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2574458449
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2885580192
Short name T247
Test name
Test status
Simulation time 339817141 ps
CPU time 1.06 seconds
Started Aug 14 04:45:19 PM PDT 24
Finished Aug 14 04:45:20 PM PDT 24
Peak memory 198048 kb
Host smart-993576e6-434c-4982-921a-865e6f78ecf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885580192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2885580192
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.998899894
Short name T145
Test name
Test status
Simulation time 196005258 ps
CPU time 1.31 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 197188 kb
Host smart-d27d272d-b149-445d-9521-f23defb1d595
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998899894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.998899894
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3505931459
Short name T414
Test name
Test status
Simulation time 65953668 ps
CPU time 2.42 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 196600 kb
Host smart-6a44fcc7-2fce-433f-bb50-695911d840f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505931459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3505931459
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.35338859
Short name T513
Test name
Test status
Simulation time 617703257 ps
CPU time 3.16 seconds
Started Aug 14 04:44:55 PM PDT 24
Finished Aug 14 04:44:58 PM PDT 24
Peak memory 198300 kb
Host smart-4b5aabdc-daad-4e29-bd7c-d9c1ea5d14a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35338859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.35338859
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3607863493
Short name T227
Test name
Test status
Simulation time 28845457 ps
CPU time 0.83 seconds
Started Aug 14 04:44:59 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 197404 kb
Host smart-31a4285f-1f54-416f-84f7-1d4ee7b97b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607863493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3607863493
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1582999673
Short name T711
Test name
Test status
Simulation time 34939097 ps
CPU time 1.2 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 198228 kb
Host smart-5c0ae55a-7852-4889-95bb-0f735c7286ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582999673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1582999673
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1401704750
Short name T6
Test name
Test status
Simulation time 631510040 ps
CPU time 2.17 seconds
Started Aug 14 04:44:57 PM PDT 24
Finished Aug 14 04:44:59 PM PDT 24
Peak memory 198164 kb
Host smart-50576f20-55da-4ea9-9dc2-f4d43535b5b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401704750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1401704750
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1092511943
Short name T422
Test name
Test status
Simulation time 147787397 ps
CPU time 0.94 seconds
Started Aug 14 04:45:16 PM PDT 24
Finished Aug 14 04:45:17 PM PDT 24
Peak memory 196356 kb
Host smart-a6a48c22-6e54-4d03-8a4c-e6bee3e91ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092511943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1092511943
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3369831798
Short name T234
Test name
Test status
Simulation time 106255804 ps
CPU time 1.18 seconds
Started Aug 14 04:45:10 PM PDT 24
Finished Aug 14 04:45:11 PM PDT 24
Peak memory 196348 kb
Host smart-156d436f-e83e-47ac-b658-e3f1c142467b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369831798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3369831798
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2628596590
Short name T671
Test name
Test status
Simulation time 1402573862 ps
CPU time 15.6 seconds
Started Aug 14 04:45:00 PM PDT 24
Finished Aug 14 04:45:15 PM PDT 24
Peak memory 198268 kb
Host smart-aaf05074-5fdb-4f2a-90a5-1f8e307ea8ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628596590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2628596590
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.339920503
Short name T367
Test name
Test status
Simulation time 43251979 ps
CPU time 0.64 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:12 PM PDT 24
Peak memory 194264 kb
Host smart-5ca94eab-a209-48c1-8adc-38300b092042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339920503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.339920503
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3166968056
Short name T666
Test name
Test status
Simulation time 32658131 ps
CPU time 0.73 seconds
Started Aug 14 04:44:59 PM PDT 24
Finished Aug 14 04:45:00 PM PDT 24
Peak memory 195280 kb
Host smart-ff74d2fe-9204-4cbe-a47d-b3fed1378a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166968056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3166968056
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1613880057
Short name T459
Test name
Test status
Simulation time 3653603530 ps
CPU time 26.6 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:31 PM PDT 24
Peak memory 197180 kb
Host smart-6abe9ce2-1a95-4aa4-86d4-5123b02457cd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613880057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1613880057
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2679573282
Short name T615
Test name
Test status
Simulation time 156281956 ps
CPU time 0.72 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 194924 kb
Host smart-361e6f23-a588-415f-bc5e-b229374e86ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679573282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2679573282
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1514742127
Short name T155
Test name
Test status
Simulation time 143367598 ps
CPU time 1.25 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 196284 kb
Host smart-d511ba44-e3dd-44f2-8b27-ad930dd9b161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514742127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1514742127
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1020920171
Short name T514
Test name
Test status
Simulation time 74425627 ps
CPU time 2.95 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:14 PM PDT 24
Peak memory 198200 kb
Host smart-4a7ad732-e30f-46c4-b021-5d31709184a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020920171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1020920171
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2030246575
Short name T249
Test name
Test status
Simulation time 83483002 ps
CPU time 1.02 seconds
Started Aug 14 04:44:56 PM PDT 24
Finished Aug 14 04:44:57 PM PDT 24
Peak memory 195692 kb
Host smart-4285f342-80d5-42d7-ac97-34bc21e5b441
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030246575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2030246575
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.704612434
Short name T239
Test name
Test status
Simulation time 220388498 ps
CPU time 1.22 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:03 PM PDT 24
Peak memory 197156 kb
Host smart-ae469b96-5f5f-482c-b1fb-3e848f917599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704612434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.704612434
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1297072480
Short name T399
Test name
Test status
Simulation time 94427769 ps
CPU time 0.74 seconds
Started Aug 14 04:45:00 PM PDT 24
Finished Aug 14 04:45:01 PM PDT 24
Peak memory 195588 kb
Host smart-4c3d2848-01b1-45eb-8396-a7058e082e5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297072480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1297072480
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.298911233
Short name T483
Test name
Test status
Simulation time 1911937520 ps
CPU time 3.92 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 197932 kb
Host smart-fd069b96-2c67-4027-a035-d94650fa2153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298911233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.298911233
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.756115131
Short name T458
Test name
Test status
Simulation time 108678530 ps
CPU time 0.92 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:03 PM PDT 24
Peak memory 196332 kb
Host smart-20ba142b-7bd7-4493-93a5-8b07b5c00f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756115131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.756115131
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2118287877
Short name T359
Test name
Test status
Simulation time 65987182 ps
CPU time 1.21 seconds
Started Aug 14 04:44:56 PM PDT 24
Finished Aug 14 04:44:58 PM PDT 24
Peak memory 195824 kb
Host smart-7cce2819-36de-4789-88f3-bdb08ac8a1c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118287877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2118287877
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2595964329
Short name T588
Test name
Test status
Simulation time 10835834412 ps
CPU time 55.19 seconds
Started Aug 14 04:45:00 PM PDT 24
Finished Aug 14 04:45:56 PM PDT 24
Peak memory 198472 kb
Host smart-9b8712bf-c051-42c9-8014-1ffb142d6883
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595964329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2595964329
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2442309935
Short name T639
Test name
Test status
Simulation time 15135412 ps
CPU time 0.59 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:03 PM PDT 24
Peak memory 194988 kb
Host smart-938fb060-99e3-45f9-891b-81f86d9b42f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442309935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2442309935
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2063721457
Short name T408
Test name
Test status
Simulation time 45887248 ps
CPU time 0.9 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 196872 kb
Host smart-d766099a-434a-4b0b-9f1c-8d616862cb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063721457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2063721457
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3976974663
Short name T360
Test name
Test status
Simulation time 301324873 ps
CPU time 12.09 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:18 PM PDT 24
Peak memory 197148 kb
Host smart-90336368-992f-4f26-9b85-f8d9843cbe1b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976974663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3976974663
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3508196391
Short name T18
Test name
Test status
Simulation time 106436977 ps
CPU time 1.04 seconds
Started Aug 14 04:44:57 PM PDT 24
Finished Aug 14 04:44:59 PM PDT 24
Peak memory 196488 kb
Host smart-9e51da86-a02d-4422-95ee-e3da37ffd7a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508196391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3508196391
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3311910006
Short name T124
Test name
Test status
Simulation time 161243259 ps
CPU time 0.72 seconds
Started Aug 14 04:44:52 PM PDT 24
Finished Aug 14 04:44:53 PM PDT 24
Peak memory 195444 kb
Host smart-44fa3738-e0f7-4927-8c97-965741ec9c2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311910006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3311910006
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3451101005
Short name T570
Test name
Test status
Simulation time 88146947 ps
CPU time 3.33 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 196624 kb
Host smart-6b082bff-b569-4194-84db-fab96ce06d5f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451101005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3451101005
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1500690
Short name T268
Test name
Test status
Simulation time 87924647 ps
CPU time 2.58 seconds
Started Aug 14 04:45:01 PM PDT 24
Finished Aug 14 04:45:03 PM PDT 24
Peak memory 197016 kb
Host smart-b23f11ee-e8d8-4d9c-880e-8abe7ce0720e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.1500690
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2720524815
Short name T578
Test name
Test status
Simulation time 213070672 ps
CPU time 1.14 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 196900 kb
Host smart-653db1c9-e2bd-4a43-81d9-b94ccc1f7d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720524815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2720524815
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3090102273
Short name T176
Test name
Test status
Simulation time 391384483 ps
CPU time 0.97 seconds
Started Aug 14 04:44:57 PM PDT 24
Finished Aug 14 04:44:59 PM PDT 24
Peak memory 196208 kb
Host smart-7b8373f3-80ff-4d29-8cc6-b5b045787d18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090102273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3090102273
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.133515928
Short name T5
Test name
Test status
Simulation time 182573185 ps
CPU time 1.44 seconds
Started Aug 14 04:45:13 PM PDT 24
Finished Aug 14 04:45:14 PM PDT 24
Peak memory 198000 kb
Host smart-5b946292-6349-43fb-8732-92b005ef8733
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133515928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.133515928
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.965675946
Short name T393
Test name
Test status
Simulation time 44088075 ps
CPU time 0.87 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 195468 kb
Host smart-48033975-0db3-440e-b9e1-28bc1deb2829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965675946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.965675946
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.729232696
Short name T29
Test name
Test status
Simulation time 192400563 ps
CPU time 1 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:03 PM PDT 24
Peak memory 195744 kb
Host smart-51d2b222-6944-45fa-a297-260c2c9d7ea1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729232696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.729232696
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.682210888
Short name T306
Test name
Test status
Simulation time 29079794519 ps
CPU time 112.82 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:46:57 PM PDT 24
Peak memory 198360 kb
Host smart-ff864d05-9393-4858-b656-232a48f205c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682210888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.682210888
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2092288418
Short name T661
Test name
Test status
Simulation time 13229311620 ps
CPU time 50.44 seconds
Started Aug 14 04:44:57 PM PDT 24
Finished Aug 14 04:45:47 PM PDT 24
Peak memory 198508 kb
Host smart-8c7f49bc-a496-4ddf-9c06-7b12af5d7e89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2092288418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2092288418
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2097472812
Short name T397
Test name
Test status
Simulation time 15896384 ps
CPU time 0.58 seconds
Started Aug 14 04:44:59 PM PDT 24
Finished Aug 14 04:45:00 PM PDT 24
Peak memory 193996 kb
Host smart-115a1216-2072-4fd3-8992-730152bd648d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097472812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2097472812
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1652060741
Short name T416
Test name
Test status
Simulation time 23042796 ps
CPU time 0.68 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 194212 kb
Host smart-5d82941f-fdbc-4cc7-bc7f-b05916af18b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652060741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1652060741
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3290747279
Short name T556
Test name
Test status
Simulation time 169052239 ps
CPU time 5.31 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:13 PM PDT 24
Peak memory 198180 kb
Host smart-d58395ce-5686-4fb7-ba73-65e726e9ca8d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290747279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3290747279
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.70225298
Short name T235
Test name
Test status
Simulation time 149658166 ps
CPU time 0.67 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:02 PM PDT 24
Peak memory 194628 kb
Host smart-12aca23d-664a-4751-a762-dcb5d763f9ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70225298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.70225298
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1034399012
Short name T279
Test name
Test status
Simulation time 130061076 ps
CPU time 1.21 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 195980 kb
Host smart-c1e92ca3-6ba6-4c52-9b72-4919f89d8776
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034399012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1034399012
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2195380146
Short name T668
Test name
Test status
Simulation time 34068740 ps
CPU time 0.87 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 196056 kb
Host smart-ee2adec9-4f5a-4f33-824b-68184f3c7e4d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195380146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2195380146
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1734405119
Short name T189
Test name
Test status
Simulation time 97267199 ps
CPU time 0.89 seconds
Started Aug 14 04:45:12 PM PDT 24
Finished Aug 14 04:45:14 PM PDT 24
Peak memory 195580 kb
Host smart-5375b579-f47f-44ab-b2be-a2733787ca74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734405119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1734405119
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2939938919
Short name T170
Test name
Test status
Simulation time 69138058 ps
CPU time 0.88 seconds
Started Aug 14 04:45:15 PM PDT 24
Finished Aug 14 04:45:16 PM PDT 24
Peak memory 195968 kb
Host smart-ff1a8dcf-10ee-4d30-9823-f439266866fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939938919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2939938919
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3382942118
Short name T286
Test name
Test status
Simulation time 39795664 ps
CPU time 0.65 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 194484 kb
Host smart-9856822e-4c6f-43b2-ad12-91b4071ef0f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382942118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3382942118
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2895278190
Short name T20
Test name
Test status
Simulation time 842691138 ps
CPU time 2.65 seconds
Started Aug 14 04:45:28 PM PDT 24
Finished Aug 14 04:45:31 PM PDT 24
Peak memory 198088 kb
Host smart-57c6da33-3e67-4876-a27f-000f8679bc01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895278190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2895278190
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.562974310
Short name T613
Test name
Test status
Simulation time 260806698 ps
CPU time 1.15 seconds
Started Aug 14 04:44:57 PM PDT 24
Finished Aug 14 04:44:58 PM PDT 24
Peak memory 196020 kb
Host smart-335494a7-37ea-4bb1-ba11-003064e37cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562974310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.562974310
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3181135056
Short name T106
Test name
Test status
Simulation time 31338722 ps
CPU time 0.78 seconds
Started Aug 14 04:45:13 PM PDT 24
Finished Aug 14 04:45:14 PM PDT 24
Peak memory 196176 kb
Host smart-4abfd73b-f47f-4635-8019-8a7f861b5f7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181135056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3181135056
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2248652575
Short name T549
Test name
Test status
Simulation time 16456474821 ps
CPU time 207.86 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:48:31 PM PDT 24
Peak memory 198264 kb
Host smart-c922a661-d8ac-4346-9955-7d8056c1fd13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248652575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2248652575
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2940222724
Short name T230
Test name
Test status
Simulation time 18057373 ps
CPU time 0.55 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 194080 kb
Host smart-f2373308-a4c3-4a61-89ff-9cfa78562a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940222724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2940222724
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1787427739
Short name T333
Test name
Test status
Simulation time 86128995 ps
CPU time 0.76 seconds
Started Aug 14 04:45:19 PM PDT 24
Finished Aug 14 04:45:20 PM PDT 24
Peak memory 195420 kb
Host smart-7dd23cfe-bc39-4f40-b9cc-02feb1f66707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787427739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1787427739
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2341384981
Short name T121
Test name
Test status
Simulation time 529009176 ps
CPU time 3.59 seconds
Started Aug 14 04:44:55 PM PDT 24
Finished Aug 14 04:44:59 PM PDT 24
Peak memory 196132 kb
Host smart-021a8632-26ae-49a2-89b5-b59855f8f7a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341384981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2341384981
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1137069651
Short name T60
Test name
Test status
Simulation time 131967767 ps
CPU time 0.75 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 196012 kb
Host smart-66969885-80ae-498c-97fc-0eb4ee385fc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137069651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1137069651
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3758739472
Short name T554
Test name
Test status
Simulation time 186609644 ps
CPU time 1.31 seconds
Started Aug 14 04:44:57 PM PDT 24
Finished Aug 14 04:44:58 PM PDT 24
Peak memory 196136 kb
Host smart-24672afc-b6ed-48a3-9b86-c5069deb4394
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758739472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3758739472
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3611857180
Short name T347
Test name
Test status
Simulation time 359784017 ps
CPU time 2.56 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 198172 kb
Host smart-d66901d5-ad81-41a1-a9e2-2f66f0f5a0a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611857180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3611857180
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.178654884
Short name T338
Test name
Test status
Simulation time 790812420 ps
CPU time 3.1 seconds
Started Aug 14 04:45:18 PM PDT 24
Finished Aug 14 04:45:21 PM PDT 24
Peak memory 197152 kb
Host smart-dcc810ca-40f8-4ad1-9310-96cbedefe56c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178654884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
178654884
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.855132227
Short name T375
Test name
Test status
Simulation time 76227052 ps
CPU time 0.88 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:03 PM PDT 24
Peak memory 195880 kb
Host smart-7f272877-66e2-4b11-a504-09ad57b62d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855132227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.855132227
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.26610053
Short name T391
Test name
Test status
Simulation time 17586971 ps
CPU time 0.64 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 194452 kb
Host smart-b96ece66-e3dd-4bda-b449-746b80d1410c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26610053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup_
pulldown.26610053
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.273770669
Short name T244
Test name
Test status
Simulation time 1265314092 ps
CPU time 5.8 seconds
Started Aug 14 04:45:01 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 198104 kb
Host smart-3ee1e049-91c4-4f25-a54c-89cd5d910a80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273770669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.273770669
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2976921940
Short name T496
Test name
Test status
Simulation time 41615091 ps
CPU time 1.19 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:12 PM PDT 24
Peak memory 197108 kb
Host smart-390dbb14-6e9b-4770-8e11-9bd0f6f864de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976921940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2976921940
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2519208341
Short name T654
Test name
Test status
Simulation time 57610527 ps
CPU time 0.91 seconds
Started Aug 14 04:44:53 PM PDT 24
Finished Aug 14 04:44:54 PM PDT 24
Peak memory 197124 kb
Host smart-6cb934ee-6f34-482e-8803-c67bab58d3ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519208341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2519208341
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2504047215
Short name T527
Test name
Test status
Simulation time 12270892054 ps
CPU time 40.42 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:44 PM PDT 24
Peak memory 198248 kb
Host smart-d39dc20e-12e6-4be4-90bd-b8b68ab532e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504047215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2504047215
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.4286069472
Short name T440
Test name
Test status
Simulation time 15216243 ps
CPU time 0.56 seconds
Started Aug 14 04:45:24 PM PDT 24
Finished Aug 14 04:45:30 PM PDT 24
Peak memory 194716 kb
Host smart-7fab6195-ad1a-4cc2-b338-aa38f33070b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286069472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.4286069472
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.790202414
Short name T363
Test name
Test status
Simulation time 24609738 ps
CPU time 0.75 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 195340 kb
Host smart-cc9d82bf-516a-47f0-9bad-42fd60566ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790202414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.790202414
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.4068819913
Short name T413
Test name
Test status
Simulation time 1652962184 ps
CPU time 14.49 seconds
Started Aug 14 04:45:49 PM PDT 24
Finished Aug 14 04:46:03 PM PDT 24
Peak memory 196748 kb
Host smart-94fc6248-3050-4086-9009-22797541c213
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068819913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.4068819913
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2384046648
Short name T240
Test name
Test status
Simulation time 70633733 ps
CPU time 0.96 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:12 PM PDT 24
Peak memory 196284 kb
Host smart-4f5d0512-2c7e-4ae0-88a8-c6fce26b8966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384046648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2384046648
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.530943847
Short name T370
Test name
Test status
Simulation time 29558770 ps
CPU time 0.7 seconds
Started Aug 14 04:44:59 PM PDT 24
Finished Aug 14 04:45:00 PM PDT 24
Peak memory 194448 kb
Host smart-047c7b71-b3d7-462e-a54f-3f6b8b79f12e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530943847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.530943847
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.231722948
Short name T438
Test name
Test status
Simulation time 199180761 ps
CPU time 2.12 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 198220 kb
Host smart-00391796-5249-4413-beb0-cf1e3462bab9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231722948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.231722948
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3308370005
Short name T259
Test name
Test status
Simulation time 271085818 ps
CPU time 2.26 seconds
Started Aug 14 04:45:13 PM PDT 24
Finished Aug 14 04:45:15 PM PDT 24
Peak memory 197172 kb
Host smart-d45fad29-eb89-4873-b61a-cf218b6b389d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308370005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3308370005
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2966783558
Short name T577
Test name
Test status
Simulation time 28382600 ps
CPU time 0.82 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 196228 kb
Host smart-374030d9-a7ab-4fd4-a0da-6bd036db79d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966783558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2966783558
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3535673153
Short name T341
Test name
Test status
Simulation time 30353853 ps
CPU time 0.84 seconds
Started Aug 14 04:45:09 PM PDT 24
Finished Aug 14 04:45:10 PM PDT 24
Peak memory 197476 kb
Host smart-91babd3c-16d5-4faa-b2b9-dbd5f8c80fdb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535673153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3535673153
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1796710527
Short name T4
Test name
Test status
Simulation time 690593466 ps
CPU time 2.32 seconds
Started Aug 14 04:44:55 PM PDT 24
Finished Aug 14 04:44:57 PM PDT 24
Peak memory 198196 kb
Host smart-9d44dd79-c847-4e1c-bcb1-c5d00b15bebc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796710527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1796710527
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2324241561
Short name T516
Test name
Test status
Simulation time 28382550 ps
CPU time 0.83 seconds
Started Aug 14 04:45:15 PM PDT 24
Finished Aug 14 04:45:16 PM PDT 24
Peak memory 195412 kb
Host smart-fb37ebe8-ff91-4a33-8351-a0d0608905be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324241561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2324241561
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1530352903
Short name T664
Test name
Test status
Simulation time 198915572 ps
CPU time 1.11 seconds
Started Aug 14 04:45:20 PM PDT 24
Finished Aug 14 04:45:21 PM PDT 24
Peak memory 196736 kb
Host smart-cebfb29e-73b1-4d6e-a185-4b6cfa024e94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530352903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1530352903
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.598240996
Short name T308
Test name
Test status
Simulation time 9227160974 ps
CPU time 65.84 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:46:12 PM PDT 24
Peak memory 198236 kb
Host smart-5e393d08-4ddb-40bc-9fe1-784d0b42b937
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598240996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.598240996
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3749204669
Short name T392
Test name
Test status
Simulation time 38404171 ps
CPU time 0.58 seconds
Started Aug 14 04:45:10 PM PDT 24
Finished Aug 14 04:45:11 PM PDT 24
Peak memory 194188 kb
Host smart-9f5e2c29-fc9e-47df-8c89-f6c80a88f8d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749204669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3749204669
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3647418320
Short name T582
Test name
Test status
Simulation time 19828538 ps
CPU time 0.63 seconds
Started Aug 14 04:45:10 PM PDT 24
Finished Aug 14 04:45:11 PM PDT 24
Peak memory 194152 kb
Host smart-940f8627-5066-40b4-9feb-bf5b54ee40a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647418320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3647418320
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.180578448
Short name T660
Test name
Test status
Simulation time 84732682 ps
CPU time 4.37 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:11 PM PDT 24
Peak memory 195940 kb
Host smart-af5afac2-e631-43af-a27b-112854a49ad7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180578448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.180578448
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1509320681
Short name T680
Test name
Test status
Simulation time 264772591 ps
CPU time 0.85 seconds
Started Aug 14 04:44:53 PM PDT 24
Finished Aug 14 04:44:54 PM PDT 24
Peak memory 195920 kb
Host smart-0c057aa0-e057-42c6-8944-64b843345d64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509320681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1509320681
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1393942980
Short name T337
Test name
Test status
Simulation time 93395547 ps
CPU time 1.28 seconds
Started Aug 14 04:45:17 PM PDT 24
Finished Aug 14 04:45:18 PM PDT 24
Peak memory 196756 kb
Host smart-bf12ea09-443e-4dce-ac0f-ea6895ea40bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393942980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1393942980
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2953137513
Short name T590
Test name
Test status
Simulation time 148603652 ps
CPU time 1.61 seconds
Started Aug 14 04:45:10 PM PDT 24
Finished Aug 14 04:45:12 PM PDT 24
Peak memory 196540 kb
Host smart-7749d4df-f2a7-4734-8e4d-03316c67864d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953137513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2953137513
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3501135876
Short name T572
Test name
Test status
Simulation time 87470019 ps
CPU time 2.6 seconds
Started Aug 14 04:45:01 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 198196 kb
Host smart-1968731c-4bec-45e1-9202-d66cce96655a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501135876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3501135876
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2632027350
Short name T307
Test name
Test status
Simulation time 109744347 ps
CPU time 1.15 seconds
Started Aug 14 04:45:18 PM PDT 24
Finished Aug 14 04:45:19 PM PDT 24
Peak memory 197468 kb
Host smart-7bc5fc58-eacb-40e3-bb65-312d9cc5b9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632027350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2632027350
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2738581995
Short name T180
Test name
Test status
Simulation time 37150746 ps
CPU time 0.96 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 196104 kb
Host smart-9dbc5d82-8d82-4536-9ca2-18a50de2b202
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738581995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2738581995
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1144275057
Short name T351
Test name
Test status
Simulation time 38437511 ps
CPU time 1.86 seconds
Started Aug 14 04:45:16 PM PDT 24
Finished Aug 14 04:45:18 PM PDT 24
Peak memory 198100 kb
Host smart-7904fd36-3627-42e8-9075-e39bfd596796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144275057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1144275057
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1774361665
Short name T609
Test name
Test status
Simulation time 39482297 ps
CPU time 1.1 seconds
Started Aug 14 04:45:19 PM PDT 24
Finished Aug 14 04:45:20 PM PDT 24
Peak memory 196360 kb
Host smart-22b48bed-3027-4fec-90c7-b948207f2af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774361665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1774361665
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.853142322
Short name T599
Test name
Test status
Simulation time 75078230 ps
CPU time 1.34 seconds
Started Aug 14 04:45:17 PM PDT 24
Finished Aug 14 04:45:19 PM PDT 24
Peak memory 196596 kb
Host smart-a45d18fe-9940-4b89-a2a9-96b0c1960254
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853142322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.853142322
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1330596122
Short name T245
Test name
Test status
Simulation time 52390065659 ps
CPU time 161.65 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:47:45 PM PDT 24
Peak memory 198284 kb
Host smart-43c2b93b-eb14-4d06-87b2-52716f5c78fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330596122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1330596122
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.4293838584
Short name T303
Test name
Test status
Simulation time 31334530 ps
CPU time 0.54 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 194072 kb
Host smart-e800685d-ee3e-43a1-ad8a-b54a979b18ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293838584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.4293838584
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3096322563
Short name T504
Test name
Test status
Simulation time 226106940 ps
CPU time 0.77 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 195404 kb
Host smart-465934ce-5a03-49ff-85af-28b48177b026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096322563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3096322563
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2995236223
Short name T647
Test name
Test status
Simulation time 6238507318 ps
CPU time 8.99 seconds
Started Aug 14 04:45:02 PM PDT 24
Finished Aug 14 04:45:11 PM PDT 24
Peak memory 197260 kb
Host smart-8805d006-3736-4899-b8f5-151544178f73
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995236223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2995236223
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2945714290
Short name T407
Test name
Test status
Simulation time 612980577 ps
CPU time 0.87 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 195984 kb
Host smart-05280a44-9786-4b26-b431-c7a87ced4da0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945714290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2945714290
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3587165395
Short name T430
Test name
Test status
Simulation time 182139723 ps
CPU time 1.31 seconds
Started Aug 14 04:45:17 PM PDT 24
Finished Aug 14 04:45:19 PM PDT 24
Peak memory 197096 kb
Host smart-74642853-e4bc-4b3c-8d2f-7eecfbad6939
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587165395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3587165395
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3486162843
Short name T373
Test name
Test status
Simulation time 200717182 ps
CPU time 2.18 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:10 PM PDT 24
Peak memory 197980 kb
Host smart-c6719024-22cf-4ac0-8ea2-4a11347cd39e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486162843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3486162843
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3272300543
Short name T192
Test name
Test status
Simulation time 110563854 ps
CPU time 1.24 seconds
Started Aug 14 04:45:27 PM PDT 24
Finished Aug 14 04:45:28 PM PDT 24
Peak memory 196632 kb
Host smart-26c6aecb-41a1-4504-a944-832283da5670
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272300543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3272300543
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2309136615
Short name T620
Test name
Test status
Simulation time 50831348 ps
CPU time 1.12 seconds
Started Aug 14 04:45:14 PM PDT 24
Finished Aug 14 04:45:15 PM PDT 24
Peak memory 196932 kb
Host smart-862a95d6-7737-4e14-8cfe-8ad3d2a312c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309136615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2309136615
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.341991889
Short name T536
Test name
Test status
Simulation time 129032273 ps
CPU time 1.26 seconds
Started Aug 14 04:44:59 PM PDT 24
Finished Aug 14 04:45:01 PM PDT 24
Peak memory 197156 kb
Host smart-2f997bca-e3b7-4677-b0ce-cd409e66932c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341991889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.341991889
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.406355904
Short name T710
Test name
Test status
Simulation time 103104269 ps
CPU time 1.27 seconds
Started Aug 14 04:45:00 PM PDT 24
Finished Aug 14 04:45:01 PM PDT 24
Peak memory 198180 kb
Host smart-99bb372b-b10b-445f-bd2b-e953af753a3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406355904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.406355904
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1092347279
Short name T356
Test name
Test status
Simulation time 40002225 ps
CPU time 1.18 seconds
Started Aug 14 04:45:10 PM PDT 24
Finished Aug 14 04:45:11 PM PDT 24
Peak memory 198136 kb
Host smart-4b88fc5b-b357-45f2-8602-3dd0a5e0bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092347279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1092347279
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1768124821
Short name T203
Test name
Test status
Simulation time 167980585 ps
CPU time 1.16 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 195740 kb
Host smart-38df2132-59d9-4de3-b74f-058677a90e8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768124821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1768124821
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3039313364
Short name T511
Test name
Test status
Simulation time 55759584158 ps
CPU time 181.89 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:48:07 PM PDT 24
Peak memory 198360 kb
Host smart-da2f783e-818c-4331-80da-5581b29b7dcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039313364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3039313364
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.310020084
Short name T67
Test name
Test status
Simulation time 1893068236 ps
CPU time 61.73 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:46:09 PM PDT 24
Peak memory 197672 kb
Host smart-30e63fd3-d971-47ee-9835-a6a0dc81fbcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=310020084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.310020084
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.237079248
Short name T525
Test name
Test status
Simulation time 105036092 ps
CPU time 0.55 seconds
Started Aug 14 04:45:22 PM PDT 24
Finished Aug 14 04:45:22 PM PDT 24
Peak memory 194084 kb
Host smart-07ae2942-a9b6-4444-a6fc-691f4d7c911d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237079248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.237079248
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1224180435
Short name T505
Test name
Test status
Simulation time 58458020 ps
CPU time 0.64 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 194192 kb
Host smart-cbed217f-3013-4ba3-bf04-a79a4f755dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224180435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1224180435
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1517668492
Short name T587
Test name
Test status
Simulation time 632300917 ps
CPU time 22.21 seconds
Started Aug 14 04:45:00 PM PDT 24
Finished Aug 14 04:45:23 PM PDT 24
Peak memory 198188 kb
Host smart-ac7fad63-a5e5-4c56-a7c5-caf4d83bdf8e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517668492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1517668492
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2396027497
Short name T420
Test name
Test status
Simulation time 449956135 ps
CPU time 0.88 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 197312 kb
Host smart-7dc5572e-13b7-42b7-a5f3-c035b36afd27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396027497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2396027497
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.379389773
Short name T114
Test name
Test status
Simulation time 28579212 ps
CPU time 0.84 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 195816 kb
Host smart-5e329829-11e6-4580-a3d3-bd1712ee7a6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379389773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.379389773
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1940698233
Short name T508
Test name
Test status
Simulation time 246889349 ps
CPU time 1.16 seconds
Started Aug 14 04:45:14 PM PDT 24
Finished Aug 14 04:45:15 PM PDT 24
Peak memory 196712 kb
Host smart-0a548903-c826-40db-ac8c-858f826a27ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940698233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1940698233
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2475065455
Short name T530
Test name
Test status
Simulation time 109481150 ps
CPU time 3.02 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:12 PM PDT 24
Peak memory 195964 kb
Host smart-685a567f-9f52-49da-bb52-1575cf50d9da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475065455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2475065455
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.468788825
Short name T426
Test name
Test status
Simulation time 23593403 ps
CPU time 0.71 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 195464 kb
Host smart-73acad59-b88e-4c29-a01d-89b7711525f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468788825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.468788825
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3462449484
Short name T640
Test name
Test status
Simulation time 216522066 ps
CPU time 0.82 seconds
Started Aug 14 04:45:21 PM PDT 24
Finished Aug 14 04:45:22 PM PDT 24
Peak memory 196724 kb
Host smart-87753bd9-77ed-425b-80b3-8873e32f4638
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462449484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3462449484
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1609733957
Short name T540
Test name
Test status
Simulation time 1001527789 ps
CPU time 3.82 seconds
Started Aug 14 04:45:20 PM PDT 24
Finished Aug 14 04:45:24 PM PDT 24
Peak memory 198108 kb
Host smart-d56a44c6-2f60-43bf-8b3f-80332a72b4c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609733957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1609733957
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3041275929
Short name T381
Test name
Test status
Simulation time 70881567 ps
CPU time 0.86 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 196180 kb
Host smart-c3c56998-fa19-445f-870a-0809f0b67aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041275929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3041275929
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2818834084
Short name T614
Test name
Test status
Simulation time 132650241 ps
CPU time 0.83 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 197100 kb
Host smart-e85411b4-d00e-41ea-aac3-a83e3e65a4e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818834084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2818834084
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3173701661
Short name T194
Test name
Test status
Simulation time 8857813901 ps
CPU time 22.83 seconds
Started Aug 14 04:44:59 PM PDT 24
Finished Aug 14 04:45:22 PM PDT 24
Peak memory 198392 kb
Host smart-b7ab2690-8bd7-47e1-b55a-25624c15eec2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173701661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3173701661
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2143710809
Short name T623
Test name
Test status
Simulation time 34017248 ps
CPU time 0.6 seconds
Started Aug 14 04:43:58 PM PDT 24
Finished Aug 14 04:43:59 PM PDT 24
Peak memory 194300 kb
Host smart-ec3aa135-d6f2-4e64-aec5-43e583dda7cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143710809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2143710809
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3609972395
Short name T135
Test name
Test status
Simulation time 268531978 ps
CPU time 0.86 seconds
Started Aug 14 04:43:43 PM PDT 24
Finished Aug 14 04:43:45 PM PDT 24
Peak memory 196636 kb
Host smart-894d34c4-12fd-4599-a52d-c21ad47a0738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609972395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3609972395
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2264177350
Short name T258
Test name
Test status
Simulation time 876371725 ps
CPU time 24.16 seconds
Started Aug 14 04:43:51 PM PDT 24
Finished Aug 14 04:44:15 PM PDT 24
Peak memory 197004 kb
Host smart-b20ea2ec-81ea-4492-ad55-6739433a13f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264177350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2264177350
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.124306183
Short name T435
Test name
Test status
Simulation time 65240826 ps
CPU time 0.96 seconds
Started Aug 14 04:43:45 PM PDT 24
Finished Aug 14 04:43:46 PM PDT 24
Peak memory 197968 kb
Host smart-74c9d8d2-3ff5-4e56-a429-94563d07c3ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124306183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.124306183
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2875822947
Short name T410
Test name
Test status
Simulation time 55159750 ps
CPU time 0.65 seconds
Started Aug 14 04:43:56 PM PDT 24
Finished Aug 14 04:43:56 PM PDT 24
Peak memory 195048 kb
Host smart-86b38773-f481-4d6e-ab40-aaac8bae3c1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875822947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2875822947
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2137550256
Short name T644
Test name
Test status
Simulation time 419145248 ps
CPU time 2.56 seconds
Started Aug 14 04:43:40 PM PDT 24
Finished Aug 14 04:43:43 PM PDT 24
Peak memory 198276 kb
Host smart-cc078eaa-4e54-4993-8c04-0c41433ee0e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137550256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2137550256
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.863095013
Short name T439
Test name
Test status
Simulation time 295924623 ps
CPU time 2.35 seconds
Started Aug 14 04:43:25 PM PDT 24
Finished Aug 14 04:43:27 PM PDT 24
Peak memory 197052 kb
Host smart-f98d0b4f-894c-4234-8329-94e4269560ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863095013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.863095013
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1830896664
Short name T419
Test name
Test status
Simulation time 69907325 ps
CPU time 0.92 seconds
Started Aug 14 04:43:50 PM PDT 24
Finished Aug 14 04:43:51 PM PDT 24
Peak memory 196856 kb
Host smart-1d303232-8657-4487-a6fe-22949475ddf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830896664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1830896664
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.130954798
Short name T152
Test name
Test status
Simulation time 37795683 ps
CPU time 1.19 seconds
Started Aug 14 04:43:31 PM PDT 24
Finished Aug 14 04:43:33 PM PDT 24
Peak memory 195956 kb
Host smart-7b9a1bc6-12a0-442c-a926-583e8bd60b8a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130954798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.130954798
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.647651993
Short name T607
Test name
Test status
Simulation time 1985995236 ps
CPU time 6.45 seconds
Started Aug 14 04:43:54 PM PDT 24
Finished Aug 14 04:44:01 PM PDT 24
Peak memory 198104 kb
Host smart-2e73c96b-96e2-4734-aa46-a083c5b08b2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647651993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.647651993
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2165264774
Short name T119
Test name
Test status
Simulation time 96056913 ps
CPU time 1 seconds
Started Aug 14 04:43:30 PM PDT 24
Finished Aug 14 04:43:36 PM PDT 24
Peak memory 196532 kb
Host smart-97432489-edec-4a5f-8aec-22fb325ab23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165264774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2165264774
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2537076105
Short name T99
Test name
Test status
Simulation time 189300110 ps
CPU time 1.02 seconds
Started Aug 14 04:43:47 PM PDT 24
Finished Aug 14 04:43:49 PM PDT 24
Peak memory 196476 kb
Host smart-dc967806-6d97-4dc8-90c9-c05a4ba919d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537076105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2537076105
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.938686371
Short name T250
Test name
Test status
Simulation time 5158638656 ps
CPU time 126.06 seconds
Started Aug 14 04:43:44 PM PDT 24
Finished Aug 14 04:45:50 PM PDT 24
Peak memory 198348 kb
Host smart-4c2e4be3-b645-4aeb-a5b6-0d50530eabba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938686371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.938686371
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3337390874
Short name T137
Test name
Test status
Simulation time 21153730 ps
CPU time 0.59 seconds
Started Aug 14 04:44:06 PM PDT 24
Finished Aug 14 04:44:06 PM PDT 24
Peak memory 194256 kb
Host smart-0515825d-bf91-4154-b30d-e7398951064d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337390874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3337390874
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2145462932
Short name T177
Test name
Test status
Simulation time 34335391 ps
CPU time 0.77 seconds
Started Aug 14 04:43:59 PM PDT 24
Finished Aug 14 04:44:00 PM PDT 24
Peak memory 196152 kb
Host smart-ff392886-fbda-4ff2-bc94-be9aaacf4050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145462932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2145462932
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.857875143
Short name T561
Test name
Test status
Simulation time 486871366 ps
CPU time 25.44 seconds
Started Aug 14 04:43:48 PM PDT 24
Finished Aug 14 04:44:14 PM PDT 24
Peak memory 197356 kb
Host smart-72df8a42-dfa3-49ab-8245-fef67bfe3ef5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857875143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.857875143
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3515441188
Short name T111
Test name
Test status
Simulation time 100694360 ps
CPU time 0.65 seconds
Started Aug 14 04:43:55 PM PDT 24
Finished Aug 14 04:43:56 PM PDT 24
Peak memory 194708 kb
Host smart-4e36718b-eafb-4596-bc5a-97e3afcdd24e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515441188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3515441188
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2258369223
Short name T539
Test name
Test status
Simulation time 37033644 ps
CPU time 1.02 seconds
Started Aug 14 04:43:45 PM PDT 24
Finished Aug 14 04:43:46 PM PDT 24
Peak memory 196036 kb
Host smart-aa684d95-1afe-4b86-8d8f-365d879420ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258369223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2258369223
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.276207219
Short name T129
Test name
Test status
Simulation time 242155907 ps
CPU time 2.63 seconds
Started Aug 14 04:44:03 PM PDT 24
Finished Aug 14 04:44:06 PM PDT 24
Peak memory 198236 kb
Host smart-2ff02ef7-c527-4697-a8d7-b6715249d499
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276207219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.276207219
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3520595205
Short name T469
Test name
Test status
Simulation time 278453842 ps
CPU time 2.23 seconds
Started Aug 14 04:43:54 PM PDT 24
Finished Aug 14 04:43:56 PM PDT 24
Peak memory 197040 kb
Host smart-35d0bcc3-4706-415f-9f9b-a2d232a1e9bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520595205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3520595205
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1789464649
Short name T313
Test name
Test status
Simulation time 52876282 ps
CPU time 1.23 seconds
Started Aug 14 04:43:49 PM PDT 24
Finished Aug 14 04:43:51 PM PDT 24
Peak memory 197184 kb
Host smart-9445d5fb-d781-4252-be18-9c6190a9c1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789464649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1789464649
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3711246856
Short name T57
Test name
Test status
Simulation time 61536570 ps
CPU time 0.77 seconds
Started Aug 14 04:44:12 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 196320 kb
Host smart-6973b1ef-f69c-4930-9881-c48c1afd798c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711246856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3711246856
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2882410285
Short name T567
Test name
Test status
Simulation time 1277318699 ps
CPU time 4.12 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:44:02 PM PDT 24
Peak memory 198184 kb
Host smart-e5108eef-b427-4c70-bd22-b57c7d163321
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882410285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2882410285
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2165030258
Short name T551
Test name
Test status
Simulation time 40153583 ps
CPU time 0.85 seconds
Started Aug 14 04:43:46 PM PDT 24
Finished Aug 14 04:43:47 PM PDT 24
Peak memory 195468 kb
Host smart-4379910c-4008-4797-8620-01bba86450ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165030258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2165030258
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.150418977
Short name T417
Test name
Test status
Simulation time 38655277 ps
CPU time 0.91 seconds
Started Aug 14 04:44:23 PM PDT 24
Finished Aug 14 04:44:24 PM PDT 24
Peak memory 195872 kb
Host smart-3744f9f8-3cab-4ee9-acb3-78569f282ad2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150418977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.150418977
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3287266479
Short name T403
Test name
Test status
Simulation time 23483544554 ps
CPU time 46.18 seconds
Started Aug 14 04:43:50 PM PDT 24
Finished Aug 14 04:44:37 PM PDT 24
Peak memory 198364 kb
Host smart-af4ddc3d-e939-44f4-90b1-f7b675650cdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287266479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3287266479
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4084461249
Short name T699
Test name
Test status
Simulation time 108584458 ps
CPU time 0.54 seconds
Started Aug 14 04:43:59 PM PDT 24
Finished Aug 14 04:43:59 PM PDT 24
Peak memory 194000 kb
Host smart-d95b71fb-1e1c-4dd7-8b9e-a951e505b898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084461249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4084461249
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3083255436
Short name T17
Test name
Test status
Simulation time 171129762 ps
CPU time 0.92 seconds
Started Aug 14 04:43:51 PM PDT 24
Finished Aug 14 04:43:52 PM PDT 24
Peak memory 195420 kb
Host smart-f3ecd227-2154-452e-b979-e8d306b10a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083255436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3083255436
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1549759419
Short name T154
Test name
Test status
Simulation time 679559839 ps
CPU time 8.04 seconds
Started Aug 14 04:43:48 PM PDT 24
Finished Aug 14 04:43:56 PM PDT 24
Peak memory 195704 kb
Host smart-d458081d-982a-42b3-ad69-1f056c6bbb50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549759419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1549759419
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.827620229
Short name T692
Test name
Test status
Simulation time 66665939 ps
CPU time 1.05 seconds
Started Aug 14 04:43:59 PM PDT 24
Finished Aug 14 04:44:01 PM PDT 24
Peak memory 196832 kb
Host smart-55824d64-99f0-4167-80d1-87e986fb750f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827620229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.827620229
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.263799615
Short name T672
Test name
Test status
Simulation time 161699689 ps
CPU time 0.9 seconds
Started Aug 14 04:43:43 PM PDT 24
Finished Aug 14 04:43:44 PM PDT 24
Peak memory 197544 kb
Host smart-62cfd7af-b9a9-42ef-ae2f-8a5ce45ec9e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263799615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.263799615
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.604867301
Short name T462
Test name
Test status
Simulation time 71375556 ps
CPU time 1.08 seconds
Started Aug 14 04:43:56 PM PDT 24
Finished Aug 14 04:43:57 PM PDT 24
Peak memory 197076 kb
Host smart-0642ed2a-7334-4a37-b3a0-b4364ee5575e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604867301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.604867301
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3945400950
Short name T446
Test name
Test status
Simulation time 177359012 ps
CPU time 2.01 seconds
Started Aug 14 04:43:54 PM PDT 24
Finished Aug 14 04:43:56 PM PDT 24
Peak memory 196872 kb
Host smart-a40e0403-b2bf-46be-acd8-2e4748c4c2cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945400950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3945400950
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.77103050
Short name T285
Test name
Test status
Simulation time 221761917 ps
CPU time 1.28 seconds
Started Aug 14 04:43:53 PM PDT 24
Finished Aug 14 04:43:54 PM PDT 24
Peak memory 197008 kb
Host smart-3373593e-9f5b-47ed-9af4-89a21685d858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77103050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.77103050
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.40366350
Short name T140
Test name
Test status
Simulation time 29207050 ps
CPU time 0.82 seconds
Started Aug 14 04:44:09 PM PDT 24
Finished Aug 14 04:44:10 PM PDT 24
Peak memory 195536 kb
Host smart-4e9cce29-49cc-416f-8c4c-a3e4d84c6d7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40366350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_p
ulldown.40366350
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2687583003
Short name T2
Test name
Test status
Simulation time 414902006 ps
CPU time 5.3 seconds
Started Aug 14 04:44:15 PM PDT 24
Finished Aug 14 04:44:21 PM PDT 24
Peak memory 198192 kb
Host smart-d9f672ec-5da6-4fa2-b59c-660ce976e061
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687583003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2687583003
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1557511573
Short name T105
Test name
Test status
Simulation time 212150760 ps
CPU time 1.17 seconds
Started Aug 14 04:44:06 PM PDT 24
Finished Aug 14 04:44:07 PM PDT 24
Peak memory 195704 kb
Host smart-faf1293a-6bc2-41a3-ab10-fa08e9190f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557511573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1557511573
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.770032558
Short name T184
Test name
Test status
Simulation time 151921231 ps
CPU time 1.18 seconds
Started Aug 14 04:44:00 PM PDT 24
Finished Aug 14 04:44:01 PM PDT 24
Peak memory 196024 kb
Host smart-8a46a833-ec34-4987-b979-42f36a23b904
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770032558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.770032558
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2332331108
Short name T521
Test name
Test status
Simulation time 15379007791 ps
CPU time 134.8 seconds
Started Aug 14 04:44:00 PM PDT 24
Finished Aug 14 04:46:15 PM PDT 24
Peak memory 198360 kb
Host smart-4cd53b2d-cc79-4e80-89be-0554425085eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332331108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2332331108
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.352737572
Short name T382
Test name
Test status
Simulation time 13493752 ps
CPU time 0.58 seconds
Started Aug 14 04:44:00 PM PDT 24
Finished Aug 14 04:44:00 PM PDT 24
Peak memory 194196 kb
Host smart-4021ebee-8398-438f-b063-ec1c88ce677d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352737572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.352737572
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1867562639
Short name T315
Test name
Test status
Simulation time 156003028 ps
CPU time 0.71 seconds
Started Aug 14 04:43:49 PM PDT 24
Finished Aug 14 04:43:50 PM PDT 24
Peak memory 194904 kb
Host smart-cd398a59-dc32-40e2-b523-97076cead784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867562639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1867562639
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1135427468
Short name T569
Test name
Test status
Simulation time 3042644695 ps
CPU time 25.25 seconds
Started Aug 14 04:44:01 PM PDT 24
Finished Aug 14 04:44:26 PM PDT 24
Peak memory 197172 kb
Host smart-1308a809-b142-46d1-baec-9fe184c419a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135427468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1135427468
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1980413084
Short name T10
Test name
Test status
Simulation time 145358056 ps
CPU time 0.69 seconds
Started Aug 14 04:43:56 PM PDT 24
Finished Aug 14 04:43:57 PM PDT 24
Peak memory 194768 kb
Host smart-c4d2f09a-c29f-4bc1-a1ce-36ab23fd9f69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980413084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1980413084
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.26172199
Short name T320
Test name
Test status
Simulation time 193622719 ps
CPU time 1.02 seconds
Started Aug 14 04:43:53 PM PDT 24
Finished Aug 14 04:43:54 PM PDT 24
Peak memory 195860 kb
Host smart-a83e2c76-3256-4467-8f49-0399dccb261b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26172199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.26172199
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2990072129
Short name T352
Test name
Test status
Simulation time 76742530 ps
CPU time 3.08 seconds
Started Aug 14 04:43:42 PM PDT 24
Finished Aug 14 04:43:46 PM PDT 24
Peak memory 198052 kb
Host smart-d84a9f4a-0dfb-4393-9cf6-faf11289c096
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990072129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2990072129
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2592803134
Short name T334
Test name
Test status
Simulation time 299795799 ps
CPU time 2.29 seconds
Started Aug 14 04:43:52 PM PDT 24
Finished Aug 14 04:43:54 PM PDT 24
Peak memory 198196 kb
Host smart-01f773f2-21f8-46c7-9503-9db453b1378b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592803134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2592803134
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2782966507
Short name T474
Test name
Test status
Simulation time 30497068 ps
CPU time 0.74 seconds
Started Aug 14 04:43:55 PM PDT 24
Finished Aug 14 04:43:56 PM PDT 24
Peak memory 195568 kb
Host smart-b42b530a-f2d2-4ffc-998f-3d3980f467d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782966507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2782966507
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2341337008
Short name T21
Test name
Test status
Simulation time 110974345 ps
CPU time 1.24 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:43:58 PM PDT 24
Peak memory 197160 kb
Host smart-a4907f1d-86f8-4ea9-b034-2e16066ca180
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341337008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2341337008
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1136919489
Short name T222
Test name
Test status
Simulation time 1408871422 ps
CPU time 5.64 seconds
Started Aug 14 04:44:08 PM PDT 24
Finished Aug 14 04:44:13 PM PDT 24
Peak memory 198116 kb
Host smart-aec585a5-3928-428c-83cf-200aab7e271f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136919489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1136919489
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.932909541
Short name T502
Test name
Test status
Simulation time 48164505 ps
CPU time 0.95 seconds
Started Aug 14 04:43:59 PM PDT 24
Finished Aug 14 04:44:01 PM PDT 24
Peak memory 196820 kb
Host smart-aedc2e31-c3d1-47da-9f8e-d46700b944fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932909541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.932909541
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1137507366
Short name T148
Test name
Test status
Simulation time 25305144 ps
CPU time 0.7 seconds
Started Aug 14 04:43:53 PM PDT 24
Finished Aug 14 04:43:53 PM PDT 24
Peak memory 194188 kb
Host smart-3efdd829-adc7-4050-b5ba-ab3f934200a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137507366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1137507366
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2239684945
Short name T362
Test name
Test status
Simulation time 15865964123 ps
CPU time 209.19 seconds
Started Aug 14 04:43:59 PM PDT 24
Finished Aug 14 04:47:28 PM PDT 24
Peak memory 198356 kb
Host smart-558dd80a-0e2c-4284-99b9-9fcc23e0a993
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239684945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2239684945
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3348917513
Short name T560
Test name
Test status
Simulation time 25133191 ps
CPU time 0.56 seconds
Started Aug 14 04:44:04 PM PDT 24
Finished Aug 14 04:44:05 PM PDT 24
Peak memory 193988 kb
Host smart-83b60f0c-dfe7-4bcc-926f-3d6c1436af5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348917513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3348917513
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3198689592
Short name T220
Test name
Test status
Simulation time 133710388 ps
CPU time 0.75 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:43:58 PM PDT 24
Peak memory 195416 kb
Host smart-bf0c58b5-e7b3-48a4-b0d1-25adfe896ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198689592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3198689592
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1796779924
Short name T175
Test name
Test status
Simulation time 275946328 ps
CPU time 12.57 seconds
Started Aug 14 04:44:07 PM PDT 24
Finished Aug 14 04:44:19 PM PDT 24
Peak memory 196876 kb
Host smart-52cdb121-5e59-45ab-a2d6-a881bf0315a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796779924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1796779924
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3340207930
Short name T431
Test name
Test status
Simulation time 89318955 ps
CPU time 0.79 seconds
Started Aug 14 04:43:58 PM PDT 24
Finished Aug 14 04:43:59 PM PDT 24
Peak memory 195944 kb
Host smart-d22f308c-15cd-494a-a688-9372c4ffeff5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340207930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3340207930
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3634911126
Short name T548
Test name
Test status
Simulation time 349808069 ps
CPU time 1.35 seconds
Started Aug 14 04:44:05 PM PDT 24
Finished Aug 14 04:44:07 PM PDT 24
Peak memory 197320 kb
Host smart-51a30a05-c17a-48cf-94d1-588fb01f0e8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634911126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3634911126
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.335736891
Short name T271
Test name
Test status
Simulation time 120389660 ps
CPU time 1.33 seconds
Started Aug 14 04:44:05 PM PDT 24
Finished Aug 14 04:44:07 PM PDT 24
Peak memory 196652 kb
Host smart-ff56f7b0-05af-4c03-b7c8-1e692fadb24c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335736891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.335736891
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3783661845
Short name T25
Test name
Test status
Simulation time 58260786 ps
CPU time 0.89 seconds
Started Aug 14 04:43:52 PM PDT 24
Finished Aug 14 04:43:53 PM PDT 24
Peak memory 194644 kb
Host smart-6252b4de-4de4-470f-98fd-059b97b9c483
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783661845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3783661845
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2191758684
Short name T343
Test name
Test status
Simulation time 20841046 ps
CPU time 0.79 seconds
Started Aug 14 04:44:01 PM PDT 24
Finished Aug 14 04:44:01 PM PDT 24
Peak memory 195648 kb
Host smart-b9374a5e-1588-4430-b763-76ab56a5df2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191758684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2191758684
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3508870023
Short name T645
Test name
Test status
Simulation time 69702459 ps
CPU time 1.33 seconds
Started Aug 14 04:43:57 PM PDT 24
Finished Aug 14 04:43:58 PM PDT 24
Peak memory 197148 kb
Host smart-5f29f6b1-a9ce-4019-bfbc-13435e885c0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508870023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3508870023
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1760161928
Short name T432
Test name
Test status
Simulation time 812324240 ps
CPU time 5.32 seconds
Started Aug 14 04:43:58 PM PDT 24
Finished Aug 14 04:44:03 PM PDT 24
Peak memory 198184 kb
Host smart-7104d96b-3cb8-451b-a7fc-1c97f4510ba1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760161928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1760161928
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2755645065
Short name T378
Test name
Test status
Simulation time 182865574 ps
CPU time 0.86 seconds
Started Aug 14 04:44:05 PM PDT 24
Finished Aug 14 04:44:05 PM PDT 24
Peak memory 195424 kb
Host smart-b987f3cf-8c06-439f-b06a-995ad08a4824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755645065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2755645065
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2943394796
Short name T339
Test name
Test status
Simulation time 368526076 ps
CPU time 1.12 seconds
Started Aug 14 04:44:06 PM PDT 24
Finished Aug 14 04:44:08 PM PDT 24
Peak memory 196356 kb
Host smart-be2b49f4-3528-4b2d-bf6f-74f0cfbfd891
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943394796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2943394796
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1502111626
Short name T411
Test name
Test status
Simulation time 40864860601 ps
CPU time 118.49 seconds
Started Aug 14 04:44:05 PM PDT 24
Finished Aug 14 04:46:04 PM PDT 24
Peak memory 198176 kb
Host smart-3d58fdd3-960c-4e7b-8aeb-fe97ee9e2b30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502111626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1502111626
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4198143198
Short name T858
Test name
Test status
Simulation time 69826044 ps
CPU time 1.02 seconds
Started Aug 14 04:27:22 PM PDT 24
Finished Aug 14 04:27:23 PM PDT 24
Peak memory 191016 kb
Host smart-dc0d8de6-e237-4e8e-87f7-550d35f38274
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4198143198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.4198143198
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3303838605
Short name T932
Test name
Test status
Simulation time 69197118 ps
CPU time 0.84 seconds
Started Aug 14 04:27:32 PM PDT 24
Finished Aug 14 04:27:33 PM PDT 24
Peak memory 197356 kb
Host smart-b3a457d8-d13e-43eb-bfd4-0b99f7591ca1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303838605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3303838605
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1943866770
Short name T846
Test name
Test status
Simulation time 105541552 ps
CPU time 1.15 seconds
Started Aug 14 04:27:22 PM PDT 24
Finished Aug 14 04:27:24 PM PDT 24
Peak memory 191204 kb
Host smart-80701a4d-f085-4f4a-bbf8-c0498fa0b4e5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1943866770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1943866770
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3390603729
Short name T930
Test name
Test status
Simulation time 210251730 ps
CPU time 1.17 seconds
Started Aug 14 04:28:34 PM PDT 24
Finished Aug 14 04:28:36 PM PDT 24
Peak memory 195884 kb
Host smart-20c6cfb4-6925-4716-a905-6ce1255a4c2e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390603729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3390603729
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1839008258
Short name T908
Test name
Test status
Simulation time 765183566 ps
CPU time 1.41 seconds
Started Aug 14 04:27:46 PM PDT 24
Finished Aug 14 04:27:48 PM PDT 24
Peak memory 197580 kb
Host smart-378f5daa-23d6-4847-b1b3-a88832496c56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1839008258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1839008258
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.76920282
Short name T896
Test name
Test status
Simulation time 71143794 ps
CPU time 1.12 seconds
Started Aug 14 04:27:21 PM PDT 24
Finished Aug 14 04:27:22 PM PDT 24
Peak memory 191208 kb
Host smart-7a4de6b6-803f-4028-9bf6-94511f19c41d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76920282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.76920282
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.240759556
Short name T847
Test name
Test status
Simulation time 271759653 ps
CPU time 1.28 seconds
Started Aug 14 04:27:37 PM PDT 24
Finished Aug 14 04:27:38 PM PDT 24
Peak memory 191208 kb
Host smart-0f2c4a9f-0df2-4599-83da-9baefd1121af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=240759556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.240759556
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2756977218
Short name T926
Test name
Test status
Simulation time 184851045 ps
CPU time 0.95 seconds
Started Aug 14 04:27:41 PM PDT 24
Finished Aug 14 04:27:43 PM PDT 24
Peak memory 191192 kb
Host smart-c7d4a5ef-fb2b-411a-a3ee-8df9eaf275f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756977218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2756977218
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3639348758
Short name T934
Test name
Test status
Simulation time 36750026 ps
CPU time 0.83 seconds
Started Aug 14 04:27:31 PM PDT 24
Finished Aug 14 04:27:32 PM PDT 24
Peak memory 191008 kb
Host smart-f12f1672-bdf2-40fa-ac84-6dc4cdf8bcc1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3639348758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3639348758
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2617372719
Short name T920
Test name
Test status
Simulation time 103070481 ps
CPU time 1.47 seconds
Started Aug 14 04:27:51 PM PDT 24
Finished Aug 14 04:27:53 PM PDT 24
Peak memory 190344 kb
Host smart-703c7d20-d450-4100-86a0-4cf52fba64c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617372719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2617372719
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.829578388
Short name T935
Test name
Test status
Simulation time 85125444 ps
CPU time 1.4 seconds
Started Aug 14 04:27:32 PM PDT 24
Finished Aug 14 04:27:33 PM PDT 24
Peak memory 191152 kb
Host smart-f27ff026-0881-48b7-a98e-280a424c9256
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=829578388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.829578388
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3145904859
Short name T852
Test name
Test status
Simulation time 137005113 ps
CPU time 1.14 seconds
Started Aug 14 04:27:28 PM PDT 24
Finished Aug 14 04:27:34 PM PDT 24
Peak memory 197588 kb
Host smart-3646cb52-5951-4401-ae8f-e107f0029acd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145904859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3145904859
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3580985753
Short name T839
Test name
Test status
Simulation time 165819150 ps
CPU time 1.46 seconds
Started Aug 14 04:27:34 PM PDT 24
Finished Aug 14 04:27:35 PM PDT 24
Peak memory 191248 kb
Host smart-af2efe15-8a43-4fba-8600-6ada2ba134b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3580985753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3580985753
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.726453018
Short name T891
Test name
Test status
Simulation time 310086354 ps
CPU time 1.19 seconds
Started Aug 14 04:27:26 PM PDT 24
Finished Aug 14 04:27:28 PM PDT 24
Peak memory 191248 kb
Host smart-722c6315-b4fe-434a-a8b3-5b9922a3b44e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726453018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.726453018
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3645988154
Short name T907
Test name
Test status
Simulation time 241360388 ps
CPU time 1.22 seconds
Started Aug 14 04:27:22 PM PDT 24
Finished Aug 14 04:27:24 PM PDT 24
Peak memory 197552 kb
Host smart-8cbfee05-dd88-4282-a2e4-376047c0d98b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3645988154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3645988154
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.843446663
Short name T859
Test name
Test status
Simulation time 131214167 ps
CPU time 1.04 seconds
Started Aug 14 04:27:29 PM PDT 24
Finished Aug 14 04:27:30 PM PDT 24
Peak memory 191156 kb
Host smart-3eec878d-c460-4c0d-939e-bb3c6aac0cdc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843446663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.843446663
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.934918551
Short name T854
Test name
Test status
Simulation time 130245944 ps
CPU time 0.86 seconds
Started Aug 14 04:28:37 PM PDT 24
Finished Aug 14 04:28:38 PM PDT 24
Peak memory 195620 kb
Host smart-3371ca18-c5e8-464a-9129-5c29de458240
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=934918551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.934918551
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1987171833
Short name T913
Test name
Test status
Simulation time 37128791 ps
CPU time 1.02 seconds
Started Aug 14 04:27:19 PM PDT 24
Finished Aug 14 04:27:20 PM PDT 24
Peak memory 191232 kb
Host smart-eaf3804c-cf0a-43bd-9f7a-9e0c395a24ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987171833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1987171833
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2091905452
Short name T840
Test name
Test status
Simulation time 170594032 ps
CPU time 1.07 seconds
Started Aug 14 04:27:32 PM PDT 24
Finished Aug 14 04:27:33 PM PDT 24
Peak memory 191216 kb
Host smart-6f64868f-690a-4775-9235-33a6f5e11514
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2091905452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2091905452
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1239421692
Short name T844
Test name
Test status
Simulation time 78031219 ps
CPU time 0.71 seconds
Started Aug 14 04:27:34 PM PDT 24
Finished Aug 14 04:27:34 PM PDT 24
Peak memory 191008 kb
Host smart-b58a3662-8d71-4256-9843-aa486662b70c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239421692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1239421692
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1356041506
Short name T911
Test name
Test status
Simulation time 23076264 ps
CPU time 0.69 seconds
Started Aug 14 04:27:49 PM PDT 24
Finished Aug 14 04:27:50 PM PDT 24
Peak memory 194468 kb
Host smart-d5750d65-5df4-489a-8778-2144a7309973
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1356041506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1356041506
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2998267501
Short name T874
Test name
Test status
Simulation time 101002415 ps
CPU time 1.47 seconds
Started Aug 14 04:27:31 PM PDT 24
Finished Aug 14 04:27:33 PM PDT 24
Peak memory 191244 kb
Host smart-b434a520-1136-4f10-b807-8e4eb8b26f36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998267501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2998267501
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1958401213
Short name T922
Test name
Test status
Simulation time 103868452 ps
CPU time 0.7 seconds
Started Aug 14 04:27:34 PM PDT 24
Finished Aug 14 04:27:36 PM PDT 24
Peak memory 190984 kb
Host smart-c3bc3712-b7af-46db-8866-c4c35d6264e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1958401213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1958401213
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.879250534
Short name T912
Test name
Test status
Simulation time 141467536 ps
CPU time 1.21 seconds
Started Aug 14 04:27:36 PM PDT 24
Finished Aug 14 04:27:37 PM PDT 24
Peak memory 191204 kb
Host smart-c7d94963-9d4d-444b-bc04-53b1800497b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879250534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.879250534
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3732926679
Short name T903
Test name
Test status
Simulation time 81562451 ps
CPU time 1.41 seconds
Started Aug 14 04:27:22 PM PDT 24
Finished Aug 14 04:27:23 PM PDT 24
Peak memory 197568 kb
Host smart-096b0f5b-750c-4b28-99c2-0ec6baa86778
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3732926679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3732926679
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1903122316
Short name T918
Test name
Test status
Simulation time 155502952 ps
CPU time 1.16 seconds
Started Aug 14 04:27:32 PM PDT 24
Finished Aug 14 04:27:33 PM PDT 24
Peak memory 191220 kb
Host smart-20aa9580-b76a-4c2a-a3b9-44b67b9e3b1a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903122316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1903122316
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2466037851
Short name T886
Test name
Test status
Simulation time 48510767 ps
CPU time 1.13 seconds
Started Aug 14 04:27:41 PM PDT 24
Finished Aug 14 04:27:43 PM PDT 24
Peak memory 191180 kb
Host smart-8f9a7ea3-293c-49bc-b0b0-b3c9a25c4f24
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2466037851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2466037851
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1573030385
Short name T887
Test name
Test status
Simulation time 63447034 ps
CPU time 0.98 seconds
Started Aug 14 04:27:38 PM PDT 24
Finished Aug 14 04:27:39 PM PDT 24
Peak memory 191248 kb
Host smart-5bfdbe21-0a7b-4956-b058-ef0b2b6f3801
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573030385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1573030385
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3468108739
Short name T883
Test name
Test status
Simulation time 33161533 ps
CPU time 0.91 seconds
Started Aug 14 04:27:41 PM PDT 24
Finished Aug 14 04:27:42 PM PDT 24
Peak memory 191288 kb
Host smart-b559c3d6-5ce9-4eab-a252-1799a6d20312
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3468108739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3468108739
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2227389372
Short name T917
Test name
Test status
Simulation time 136003748 ps
CPU time 1.26 seconds
Started Aug 14 04:27:44 PM PDT 24
Finished Aug 14 04:27:45 PM PDT 24
Peak memory 197560 kb
Host smart-6e7bfabc-4339-462e-a64b-143956b41a82
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227389372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2227389372
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3752993293
Short name T864
Test name
Test status
Simulation time 34048764 ps
CPU time 0.92 seconds
Started Aug 14 04:27:54 PM PDT 24
Finished Aug 14 04:27:55 PM PDT 24
Peak memory 196600 kb
Host smart-66bb6ff6-8954-4fae-94b1-6501bae4e07c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3752993293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3752993293
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4170879214
Short name T867
Test name
Test status
Simulation time 49183440 ps
CPU time 1.24 seconds
Started Aug 14 04:27:42 PM PDT 24
Finished Aug 14 04:27:44 PM PDT 24
Peak memory 191216 kb
Host smart-98181024-8fea-4546-9213-69dc51f488e3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170879214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4170879214
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3007071778
Short name T906
Test name
Test status
Simulation time 337768020 ps
CPU time 1.4 seconds
Started Aug 14 04:27:59 PM PDT 24
Finished Aug 14 04:28:01 PM PDT 24
Peak memory 191172 kb
Host smart-bc80e4fb-1b33-411f-a99c-e7ae5016e70b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3007071778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3007071778
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4032084201
Short name T900
Test name
Test status
Simulation time 188111364 ps
CPU time 0.97 seconds
Started Aug 14 04:27:34 PM PDT 24
Finished Aug 14 04:27:35 PM PDT 24
Peak memory 191212 kb
Host smart-c3bd7ff9-2440-471c-8fbb-e69964a2acf0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032084201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4032084201
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4294896484
Short name T853
Test name
Test status
Simulation time 51670381 ps
CPU time 1.02 seconds
Started Aug 14 04:27:45 PM PDT 24
Finished Aug 14 04:27:46 PM PDT 24
Peak memory 196140 kb
Host smart-7ce273ce-4499-4732-94e0-87de434ccfdc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4294896484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.4294896484
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3299305510
Short name T881
Test name
Test status
Simulation time 57172547 ps
CPU time 1.12 seconds
Started Aug 14 04:27:48 PM PDT 24
Finished Aug 14 04:27:50 PM PDT 24
Peak memory 191204 kb
Host smart-a05cdbdf-5b50-482b-823b-bee41c4aa9e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299305510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3299305510
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3950133006
Short name T866
Test name
Test status
Simulation time 93051934 ps
CPU time 1.24 seconds
Started Aug 14 04:27:36 PM PDT 24
Finished Aug 14 04:27:37 PM PDT 24
Peak memory 191584 kb
Host smart-a7447ae4-2b99-410e-97f0-78851503190b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3950133006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3950133006
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2757140653
Short name T873
Test name
Test status
Simulation time 93931964 ps
CPU time 1.25 seconds
Started Aug 14 04:27:34 PM PDT 24
Finished Aug 14 04:27:41 PM PDT 24
Peak memory 197572 kb
Host smart-ff2c376f-4bcd-47bf-a917-1f1ec5128d9c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757140653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2757140653
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1156188371
Short name T892
Test name
Test status
Simulation time 64873823 ps
CPU time 1.37 seconds
Started Aug 14 04:27:41 PM PDT 24
Finished Aug 14 04:27:42 PM PDT 24
Peak memory 191220 kb
Host smart-955c4af1-dbd7-42c4-a1dc-2a7c0ac94e17
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1156188371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1156188371
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2417146789
Short name T888
Test name
Test status
Simulation time 311411900 ps
CPU time 1.13 seconds
Started Aug 14 04:27:31 PM PDT 24
Finished Aug 14 04:27:32 PM PDT 24
Peak memory 196212 kb
Host smart-8571043e-2ef4-4ee1-942c-d907cbf675e9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417146789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2417146789
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2926530703
Short name T902
Test name
Test status
Simulation time 46779964 ps
CPU time 1.12 seconds
Started Aug 14 04:27:25 PM PDT 24
Finished Aug 14 04:27:26 PM PDT 24
Peak memory 197544 kb
Host smart-d53ba2fc-87e6-4f92-93b4-efdf29932004
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2926530703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2926530703
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2615582860
Short name T904
Test name
Test status
Simulation time 226614770 ps
CPU time 0.86 seconds
Started Aug 14 04:27:50 PM PDT 24
Finished Aug 14 04:27:52 PM PDT 24
Peak memory 195408 kb
Host smart-48e9528e-9b90-477a-acd8-cd30a38e2495
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615582860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2615582860
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1571155069
Short name T901
Test name
Test status
Simulation time 57034844 ps
CPU time 0.91 seconds
Started Aug 14 04:27:31 PM PDT 24
Finished Aug 14 04:27:32 PM PDT 24
Peak memory 195736 kb
Host smart-298d2f2f-ae09-4b66-b1b7-fb17160d15a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1571155069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1571155069
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4067694328
Short name T899
Test name
Test status
Simulation time 80394214 ps
CPU time 1.3 seconds
Started Aug 14 04:27:35 PM PDT 24
Finished Aug 14 04:27:36 PM PDT 24
Peak memory 195892 kb
Host smart-8013527d-5a45-4bed-b2b1-752732f05fdb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067694328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4067694328
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2066988184
Short name T929
Test name
Test status
Simulation time 404491244 ps
CPU time 1.12 seconds
Started Aug 14 04:27:44 PM PDT 24
Finished Aug 14 04:27:45 PM PDT 24
Peak memory 197520 kb
Host smart-e3f89c80-5ef3-4baf-8cc4-f6e4e92269c6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2066988184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2066988184
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4060897745
Short name T884
Test name
Test status
Simulation time 26146931 ps
CPU time 0.8 seconds
Started Aug 14 04:27:48 PM PDT 24
Finished Aug 14 04:27:49 PM PDT 24
Peak memory 191000 kb
Host smart-e21f8777-1d67-4ec8-adf8-140b83d09cd6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060897745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4060897745
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1240338705
Short name T919
Test name
Test status
Simulation time 230935352 ps
CPU time 1.14 seconds
Started Aug 14 04:27:34 PM PDT 24
Finished Aug 14 04:27:36 PM PDT 24
Peak memory 191212 kb
Host smart-bc018c7b-9bb3-4baf-b692-9f49a4e68729
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1240338705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1240338705
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4177228531
Short name T856
Test name
Test status
Simulation time 55667390 ps
CPU time 1.08 seconds
Started Aug 14 04:27:27 PM PDT 24
Finished Aug 14 04:27:28 PM PDT 24
Peak memory 197012 kb
Host smart-cc99e7fc-cfa4-44d0-82cb-512e5bfcf60e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177228531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4177228531
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1811136128
Short name T868
Test name
Test status
Simulation time 289054413 ps
CPU time 1.35 seconds
Started Aug 14 04:27:54 PM PDT 24
Finished Aug 14 04:27:56 PM PDT 24
Peak memory 191188 kb
Host smart-a2310fc9-ef09-4160-8431-be7c7cc4226f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1811136128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1811136128
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.531215241
Short name T849
Test name
Test status
Simulation time 86287608 ps
CPU time 0.8 seconds
Started Aug 14 04:27:45 PM PDT 24
Finished Aug 14 04:27:46 PM PDT 24
Peak memory 190992 kb
Host smart-2dbfe6fe-9bdc-49be-b700-3c8ed833937d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531215241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.531215241
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.641830400
Short name T923
Test name
Test status
Simulation time 133680366 ps
CPU time 1.24 seconds
Started Aug 14 04:27:32 PM PDT 24
Finished Aug 14 04:27:34 PM PDT 24
Peak memory 197548 kb
Host smart-05ccf0cf-a54d-4d5b-b0a6-e64b0c48b05d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=641830400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.641830400
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3498505214
Short name T909
Test name
Test status
Simulation time 375730408 ps
CPU time 1.13 seconds
Started Aug 14 04:27:38 PM PDT 24
Finished Aug 14 04:27:39 PM PDT 24
Peak memory 197480 kb
Host smart-d3f21434-12c6-4351-873e-732025b50593
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498505214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3498505214
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4165752006
Short name T841
Test name
Test status
Simulation time 135761440 ps
CPU time 0.98 seconds
Started Aug 14 04:27:35 PM PDT 24
Finished Aug 14 04:27:36 PM PDT 24
Peak memory 197512 kb
Host smart-b0e36f53-7c5b-4753-9752-26a0bca5869b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4165752006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.4165752006
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2719768983
Short name T928
Test name
Test status
Simulation time 34793880 ps
CPU time 0.88 seconds
Started Aug 14 04:28:00 PM PDT 24
Finished Aug 14 04:28:01 PM PDT 24
Peak memory 191032 kb
Host smart-c0c16d6e-ccf9-4ea2-ba9c-16f5bbee747f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719768983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2719768983
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1647753263
Short name T885
Test name
Test status
Simulation time 219049462 ps
CPU time 1.24 seconds
Started Aug 14 04:27:48 PM PDT 24
Finished Aug 14 04:27:50 PM PDT 24
Peak memory 191176 kb
Host smart-10d2c481-3695-4e86-bd7f-3adc0ad8f767
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1647753263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1647753263
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3783258754
Short name T925
Test name
Test status
Simulation time 186534494 ps
CPU time 1.04 seconds
Started Aug 14 04:27:47 PM PDT 24
Finished Aug 14 04:27:49 PM PDT 24
Peak memory 191172 kb
Host smart-a6a4f3c9-691e-44bd-a4c6-685bbd6c2710
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783258754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3783258754
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3524689838
Short name T914
Test name
Test status
Simulation time 324923472 ps
CPU time 1.28 seconds
Started Aug 14 04:27:41 PM PDT 24
Finished Aug 14 04:27:43 PM PDT 24
Peak memory 197524 kb
Host smart-d7127595-e258-4dd2-b13c-31a0af7acbbe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3524689838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3524689838
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3949876183
Short name T843
Test name
Test status
Simulation time 285345060 ps
CPU time 1.3 seconds
Started Aug 14 04:27:40 PM PDT 24
Finished Aug 14 04:27:42 PM PDT 24
Peak memory 191252 kb
Host smart-25bec127-dddb-480b-8002-cd3b4be2251a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949876183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3949876183
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2369498016
Short name T921
Test name
Test status
Simulation time 157810146 ps
CPU time 0.88 seconds
Started Aug 14 04:27:41 PM PDT 24
Finished Aug 14 04:27:42 PM PDT 24
Peak memory 191016 kb
Host smart-945bb116-b7d1-470a-9fa0-d6f3479df3c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2369498016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2369498016
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2303083184
Short name T871
Test name
Test status
Simulation time 67345877 ps
CPU time 1.15 seconds
Started Aug 14 04:27:56 PM PDT 24
Finished Aug 14 04:27:57 PM PDT 24
Peak memory 191236 kb
Host smart-099aea3b-f584-4966-a599-f7d53ad93b0e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303083184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2303083184
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.4178857686
Short name T842
Test name
Test status
Simulation time 228761016 ps
CPU time 1.21 seconds
Started Aug 14 04:27:24 PM PDT 24
Finished Aug 14 04:27:25 PM PDT 24
Peak memory 191236 kb
Host smart-56a0ba01-9dae-45f5-9cd9-384b3c7aac45
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4178857686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.4178857686
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2088839837
Short name T897
Test name
Test status
Simulation time 78222032 ps
CPU time 1.35 seconds
Started Aug 14 04:27:48 PM PDT 24
Finished Aug 14 04:27:49 PM PDT 24
Peak memory 191148 kb
Host smart-331cc41d-fc6c-43ae-bb1a-dd2981ce00cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088839837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2088839837
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.4258504615
Short name T879
Test name
Test status
Simulation time 87511557 ps
CPU time 1.04 seconds
Started Aug 14 04:27:37 PM PDT 24
Finished Aug 14 04:27:38 PM PDT 24
Peak memory 191240 kb
Host smart-e5fdd566-7d75-42fd-89af-5edaa930003b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4258504615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.4258504615
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.279622311
Short name T880
Test name
Test status
Simulation time 174375174 ps
CPU time 1.15 seconds
Started Aug 14 04:27:37 PM PDT 24
Finished Aug 14 04:27:38 PM PDT 24
Peak memory 191216 kb
Host smart-36ed9a34-05ca-437b-8f8d-eb11f356364a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279622311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.279622311
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3083162468
Short name T915
Test name
Test status
Simulation time 362036415 ps
CPU time 1.32 seconds
Started Aug 14 04:27:53 PM PDT 24
Finished Aug 14 04:27:54 PM PDT 24
Peak memory 191148 kb
Host smart-02a0023f-3819-4400-bb57-c419dc522150
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3083162468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3083162468
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.133171745
Short name T862
Test name
Test status
Simulation time 35579802 ps
CPU time 0.77 seconds
Started Aug 14 04:27:30 PM PDT 24
Finished Aug 14 04:27:31 PM PDT 24
Peak memory 190980 kb
Host smart-9812e07f-ad34-4e54-b5a9-fa7468e194a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133171745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.133171745
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2758819588
Short name T890
Test name
Test status
Simulation time 106817261 ps
CPU time 1.14 seconds
Started Aug 14 04:27:55 PM PDT 24
Finished Aug 14 04:27:56 PM PDT 24
Peak memory 197508 kb
Host smart-ff304d28-5779-4391-a93b-57a6ab16fecd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2758819588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2758819588
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4265351777
Short name T895
Test name
Test status
Simulation time 54968313 ps
CPU time 0.94 seconds
Started Aug 14 04:27:31 PM PDT 24
Finished Aug 14 04:27:32 PM PDT 24
Peak memory 191032 kb
Host smart-a8a8e359-9bba-4392-b6a7-2a92b3e66e49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265351777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4265351777
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3605597935
Short name T876
Test name
Test status
Simulation time 100929838 ps
CPU time 0.94 seconds
Started Aug 14 04:27:39 PM PDT 24
Finished Aug 14 04:27:40 PM PDT 24
Peak memory 191236 kb
Host smart-0e71814d-e4de-4c66-99b4-b4ef8d380b09
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3605597935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3605597935
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1436814067
Short name T910
Test name
Test status
Simulation time 135909706 ps
CPU time 0.94 seconds
Started Aug 14 04:27:27 PM PDT 24
Finished Aug 14 04:27:28 PM PDT 24
Peak memory 191032 kb
Host smart-c398866d-8ac6-4a77-ad9a-9cfdf9ede0f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436814067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1436814067
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.380842950
Short name T863
Test name
Test status
Simulation time 112914211 ps
CPU time 1.42 seconds
Started Aug 14 04:27:27 PM PDT 24
Finished Aug 14 04:27:29 PM PDT 24
Peak memory 191212 kb
Host smart-86592c9e-b1f0-4836-bbba-60236b40cf15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=380842950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.380842950
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1272448626
Short name T931
Test name
Test status
Simulation time 263194574 ps
CPU time 1.14 seconds
Started Aug 14 04:27:38 PM PDT 24
Finished Aug 14 04:27:39 PM PDT 24
Peak memory 191228 kb
Host smart-cc8b327d-5584-4c2e-8796-3fee80f14c55
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272448626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1272448626
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1560193002
Short name T882
Test name
Test status
Simulation time 123878408 ps
CPU time 0.72 seconds
Started Aug 14 04:27:41 PM PDT 24
Finished Aug 14 04:27:42 PM PDT 24
Peak memory 194444 kb
Host smart-9b57b739-84e3-4381-8a78-661defa672bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1560193002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1560193002
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2555501686
Short name T865
Test name
Test status
Simulation time 287630682 ps
CPU time 1.26 seconds
Started Aug 14 04:27:37 PM PDT 24
Finished Aug 14 04:27:39 PM PDT 24
Peak memory 191228 kb
Host smart-6ce08f22-da68-499c-a443-66e9af11b276
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555501686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2555501686
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3501564203
Short name T924
Test name
Test status
Simulation time 24258789 ps
CPU time 0.75 seconds
Started Aug 14 04:27:37 PM PDT 24
Finished Aug 14 04:27:38 PM PDT 24
Peak memory 194524 kb
Host smart-6981998f-d788-45cc-b1a1-3ef526c59b40
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3501564203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3501564203
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.113661602
Short name T889
Test name
Test status
Simulation time 77592837 ps
CPU time 1.1 seconds
Started Aug 14 04:27:41 PM PDT 24
Finished Aug 14 04:27:42 PM PDT 24
Peak memory 197608 kb
Host smart-8c3acd06-6337-4702-8d7f-4a79d4e759a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113661602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.113661602
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.104502133
Short name T878
Test name
Test status
Simulation time 128967786 ps
CPU time 1.11 seconds
Started Aug 14 04:27:34 PM PDT 24
Finished Aug 14 04:27:36 PM PDT 24
Peak memory 191236 kb
Host smart-44271dca-2913-4737-bda6-058c799d09ee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=104502133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.104502133
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.323598944
Short name T893
Test name
Test status
Simulation time 85061071 ps
CPU time 1.08 seconds
Started Aug 14 04:27:54 PM PDT 24
Finished Aug 14 04:27:56 PM PDT 24
Peak memory 191168 kb
Host smart-6886b8b8-cb2c-4c9c-8dcf-ff47931446ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323598944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.323598944
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.685202858
Short name T845
Test name
Test status
Simulation time 300231629 ps
CPU time 1.24 seconds
Started Aug 14 04:27:39 PM PDT 24
Finished Aug 14 04:27:40 PM PDT 24
Peak memory 191264 kb
Host smart-90bce302-1b4d-49b2-80f4-83d40bd2e589
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=685202858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.685202858
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.565997835
Short name T938
Test name
Test status
Simulation time 123234907 ps
CPU time 0.92 seconds
Started Aug 14 04:27:36 PM PDT 24
Finished Aug 14 04:27:37 PM PDT 24
Peak memory 191216 kb
Host smart-9d5bad03-2567-4c5a-baac-499a7da19923
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565997835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.565997835
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.370784570
Short name T850
Test name
Test status
Simulation time 69435747 ps
CPU time 1.16 seconds
Started Aug 14 04:27:50 PM PDT 24
Finished Aug 14 04:27:51 PM PDT 24
Peak memory 191144 kb
Host smart-89b596b6-ff78-47fd-99e0-28d0d453d4cc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=370784570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.370784570
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2916472741
Short name T861
Test name
Test status
Simulation time 84379603 ps
CPU time 0.85 seconds
Started Aug 14 04:27:48 PM PDT 24
Finished Aug 14 04:27:49 PM PDT 24
Peak memory 195416 kb
Host smart-4eb0e22d-f883-4cb3-97c6-3cebe2888d13
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916472741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2916472741
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.517123899
Short name T872
Test name
Test status
Simulation time 180896081 ps
CPU time 1.24 seconds
Started Aug 14 04:27:40 PM PDT 24
Finished Aug 14 04:27:42 PM PDT 24
Peak memory 197476 kb
Host smart-5ca86ae6-3188-43a1-bdb3-2ddd6ad43c30
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=517123899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.517123899
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.280650135
Short name T877
Test name
Test status
Simulation time 152004110 ps
CPU time 0.94 seconds
Started Aug 14 04:27:34 PM PDT 24
Finished Aug 14 04:27:35 PM PDT 24
Peak memory 190976 kb
Host smart-2c84ac15-51e7-4711-b299-d81ff285a057
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280650135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.280650135
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2874768551
Short name T869
Test name
Test status
Simulation time 258981987 ps
CPU time 1.18 seconds
Started Aug 14 04:27:56 PM PDT 24
Finished Aug 14 04:27:58 PM PDT 24
Peak memory 191264 kb
Host smart-de50c25f-e18e-4a1b-ab72-45023da0d6d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2874768551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2874768551
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1678578733
Short name T857
Test name
Test status
Simulation time 278774454 ps
CPU time 1.17 seconds
Started Aug 14 04:28:01 PM PDT 24
Finished Aug 14 04:28:02 PM PDT 24
Peak memory 191144 kb
Host smart-847a6742-686a-4353-8d43-558feae4cd0c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678578733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1678578733
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.896201185
Short name T848
Test name
Test status
Simulation time 47348200 ps
CPU time 1.19 seconds
Started Aug 14 04:27:43 PM PDT 24
Finished Aug 14 04:27:45 PM PDT 24
Peak memory 197492 kb
Host smart-c8a95169-d7d7-4f35-918b-e3421166d2f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=896201185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.896201185
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.26660748
Short name T855
Test name
Test status
Simulation time 170626823 ps
CPU time 1.14 seconds
Started Aug 14 04:27:37 PM PDT 24
Finished Aug 14 04:27:38 PM PDT 24
Peak memory 191252 kb
Host smart-1d2b8047-bb02-4001-9e58-9fef67218240
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26660748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.26660748
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2698513926
Short name T875
Test name
Test status
Simulation time 47118016 ps
CPU time 1.24 seconds
Started Aug 14 04:28:01 PM PDT 24
Finished Aug 14 04:28:02 PM PDT 24
Peak memory 191148 kb
Host smart-cfd876e2-1fa4-4699-ac38-0e9a161b2680
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2698513926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2698513926
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.743541256
Short name T916
Test name
Test status
Simulation time 47066336 ps
CPU time 0.8 seconds
Started Aug 14 04:27:42 PM PDT 24
Finished Aug 14 04:27:43 PM PDT 24
Peak memory 191036 kb
Host smart-07c76557-463c-467c-823f-d2c2c4170077
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743541256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.743541256
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1307576534
Short name T927
Test name
Test status
Simulation time 197399950 ps
CPU time 1.13 seconds
Started Aug 14 04:27:36 PM PDT 24
Finished Aug 14 04:27:37 PM PDT 24
Peak memory 197548 kb
Host smart-9520c302-f9c3-42bb-a717-866ff2ddf81d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1307576534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1307576534
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1767364085
Short name T936
Test name
Test status
Simulation time 259675469 ps
CPU time 1.13 seconds
Started Aug 14 04:27:32 PM PDT 24
Finished Aug 14 04:27:33 PM PDT 24
Peak memory 197560 kb
Host smart-a2751628-7119-4ad0-8173-60f9205bf503
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767364085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1767364085
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3698711313
Short name T898
Test name
Test status
Simulation time 232251995 ps
CPU time 0.99 seconds
Started Aug 14 04:27:47 PM PDT 24
Finished Aug 14 04:27:49 PM PDT 24
Peak memory 191264 kb
Host smart-0a679aed-9c5c-4fbb-805b-6341a8652356
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3698711313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3698711313
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3684793584
Short name T933
Test name
Test status
Simulation time 51049180 ps
CPU time 0.99 seconds
Started Aug 14 04:27:33 PM PDT 24
Finished Aug 14 04:27:34 PM PDT 24
Peak memory 195776 kb
Host smart-42359a3b-9c62-4550-8d90-1456882433fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684793584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3684793584
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.916775920
Short name T937
Test name
Test status
Simulation time 135435253 ps
CPU time 0.82 seconds
Started Aug 14 04:27:36 PM PDT 24
Finished Aug 14 04:27:37 PM PDT 24
Peak memory 191000 kb
Host smart-f6df2dc1-c064-4543-b671-c11ca4787b9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=916775920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.916775920
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2099551134
Short name T870
Test name
Test status
Simulation time 64395588 ps
CPU time 1.24 seconds
Started Aug 14 04:27:29 PM PDT 24
Finished Aug 14 04:27:30 PM PDT 24
Peak memory 196648 kb
Host smart-d8422855-b429-4724-b249-6194407f31ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099551134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2099551134
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3235005038
Short name T860
Test name
Test status
Simulation time 56067091 ps
CPU time 1.09 seconds
Started Aug 14 04:27:27 PM PDT 24
Finished Aug 14 04:27:28 PM PDT 24
Peak memory 197476 kb
Host smart-08cc22fb-f317-43ff-9943-43d8bb9912e0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3235005038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3235005038
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3172139088
Short name T851
Test name
Test status
Simulation time 377725491 ps
CPU time 1.45 seconds
Started Aug 14 04:27:22 PM PDT 24
Finished Aug 14 04:27:24 PM PDT 24
Peak memory 190320 kb
Host smart-13f320a3-3b59-4ee7-b14b-27811ae16cb7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172139088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3172139088
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.657378298
Short name T894
Test name
Test status
Simulation time 43510730 ps
CPU time 0.87 seconds
Started Aug 14 04:27:46 PM PDT 24
Finished Aug 14 04:27:47 PM PDT 24
Peak memory 195552 kb
Host smart-8eff6fe2-751b-4b2d-a3f1-620f5ff13913
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=657378298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.657378298
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2208587178
Short name T905
Test name
Test status
Simulation time 208513819 ps
CPU time 0.88 seconds
Started Aug 14 04:27:41 PM PDT 24
Finished Aug 14 04:27:42 PM PDT 24
Peak memory 191180 kb
Host smart-c49b62ed-203b-4334-ba42-06c394f46cfc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208587178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2208587178
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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