Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1398050	1			T19	764		T20	1		T21	1
all_pins[1]	1398050	1			T19	764		T20	1		T21	1
all_pins[2]	1398050	1			T19	764		T20	1		T21	1
all_pins[3]	1398050	1			T19	764		T20	1		T21	1
all_pins[4]	1398050	1			T19	764		T20	1		T21	1
all_pins[5]	1398050	1			T19	764		T20	1		T21	1
all_pins[6]	1398050	1			T19	764		T20	1		T21	1
all_pins[7]	1398050	1			T19	764		T20	1		T21	1
all_pins[8]	1398050	1			T19	764		T20	1		T21	1
all_pins[9]	1398050	1			T19	764		T20	1		T21	1
all_pins[10]	1398050	1			T19	764		T20	1		T21	1
all_pins[11]	1398050	1			T19	764		T20	1		T21	1
all_pins[12]	1398050	1			T19	764		T20	1		T21	1
all_pins[13]	1398050	1			T19	764		T20	1		T21	1
all_pins[14]	1398050	1			T19	764		T20	1		T21	1
all_pins[15]	1398050	1			T19	764		T20	1		T21	1
all_pins[16]	1398050	1			T19	764		T20	1		T21	1
all_pins[17]	1398050	1			T19	764		T20	1		T21	1
all_pins[18]	1398050	1			T19	764		T20	1		T21	1
all_pins[19]	1398050	1			T19	764		T20	1		T21	1
all_pins[20]	1398050	1			T19	764		T20	1		T21	1
all_pins[21]	1398050	1			T19	764		T20	1		T21	1
all_pins[22]	1398050	1			T19	764		T20	1		T21	1
all_pins[23]	1398050	1			T19	764		T20	1		T21	1
all_pins[24]	1398050	1			T19	764		T20	1		T21	1
all_pins[25]	1398050	1			T19	764		T20	1		T21	1
all_pins[26]	1398050	1			T19	764		T20	1		T21	1
all_pins[27]	1398050	1			T19	764		T20	1		T21	1
all_pins[28]	1398050	1			T19	764		T20	1		T21	1
all_pins[29]	1398050	1			T19	764		T20	1		T21	1
all_pins[30]	1398050	1			T19	764		T20	1		T21	1
all_pins[31]	1398050	1			T19	764		T20	1		T21	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	27831510	1			T19	15221		T20	32		T21	32
values[0x1]	16906090	1			T19	9227		T22	35		T27	1248
transitions[0x0=>0x1]	10118618	1			T19	5598		T22	29		T27	674
transitions[0x1=>0x0]	10118465	1			T19	5598		T22	29		T27	673

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	872126	1			T19	492		T20	1		T21	1
all_pins[0]	values[0x1]	525924	1			T19	272		T27	41		T31	41
all_pins[0]	transitions[0x0=>0x1]	326733	1			T19	172		T27	23		T31	23
all_pins[0]	transitions[0x1=>0x0]	326360	1			T19	156		T22	2		T27	21
all_pins[1]	values[0x0]	872532	1			T19	471		T20	1		T21	1
all_pins[1]	values[0x1]	525518	1			T19	293		T27	40		T31	36
all_pins[1]	transitions[0x0=>0x1]	315082	1			T19	196		T27	20		T31	21
all_pins[1]	transitions[0x1=>0x0]	315488	1			T19	175		T27	21		T31	26
all_pins[2]	values[0x0]	867920	1			T19	486		T20	1		T21	1
all_pins[2]	values[0x1]	530130	1			T19	278		T22	2		T27	38
all_pins[2]	transitions[0x0=>0x1]	318233	1			T19	125		T22	2		T27	18
all_pins[2]	transitions[0x1=>0x0]	313621	1			T19	140		T27	20		T31	16
all_pins[3]	values[0x0]	866311	1			T19	497		T20	1		T21	1
all_pins[3]	values[0x1]	531739	1			T19	267		T27	49		T31	34
all_pins[3]	transitions[0x0=>0x1]	316262	1			T19	180		T27	31		T31	12
all_pins[3]	transitions[0x1=>0x0]	314653	1			T19	191		T22	2		T27	20
all_pins[4]	values[0x0]	868339	1			T19	499		T20	1		T21	1
all_pins[4]	values[0x1]	529711	1			T19	265		T27	44		T31	32
all_pins[4]	transitions[0x0=>0x1]	315377	1			T19	165		T27	24		T31	14
all_pins[4]	transitions[0x1=>0x0]	317405	1			T19	167		T27	29		T31	16
all_pins[5]	values[0x0]	869872	1			T19	415		T20	1		T21	1
all_pins[5]	values[0x1]	528178	1			T19	349		T27	41		T31	36
all_pins[5]	transitions[0x0=>0x1]	316664	1			T19	226		T27	22		T31	17
all_pins[5]	transitions[0x1=>0x0]	318197	1			T19	142		T27	25		T31	13
all_pins[6]	values[0x0]	873737	1			T19	502		T20	1		T21	1
all_pins[6]	values[0x1]	524313	1			T19	262		T27	32		T31	47
all_pins[6]	transitions[0x0=>0x1]	313543	1			T19	151		T27	13		T31	28
all_pins[6]	transitions[0x1=>0x0]	317408	1			T19	238		T27	22		T31	17
all_pins[7]	values[0x0]	867514	1			T19	382		T20	1		T21	1
all_pins[7]	values[0x1]	530536	1			T19	382		T22	3		T27	46
all_pins[7]	transitions[0x0=>0x1]	318150	1			T19	257		T22	3		T27	27
all_pins[7]	transitions[0x1=>0x0]	311927	1			T19	137		T27	13		T31	24
all_pins[8]	values[0x0]	870801	1			T19	521		T20	1		T21	1
all_pins[8]	values[0x1]	527249	1			T19	243		T27	41		T31	41
all_pins[8]	transitions[0x0=>0x1]	315206	1			T19	118		T27	16		T31	18
all_pins[8]	transitions[0x1=>0x0]	318493	1			T19	257		T22	3		T27	21
all_pins[9]	values[0x0]	867592	1			T19	532		T20	1		T21	1
all_pins[9]	values[0x1]	530458	1			T19	232		T22	1		T27	32
all_pins[9]	transitions[0x0=>0x1]	318334	1			T19	138		T22	1		T27	18
all_pins[9]	transitions[0x1=>0x0]	315125	1			T19	149		T27	27		T31	21
all_pins[10]	values[0x0]	868641	1			T19	491		T20	1		T21	1
all_pins[10]	values[0x1]	529409	1			T19	273		T27	39		T31	48
all_pins[10]	transitions[0x0=>0x1]	316611	1			T19	197		T27	27		T31	26
all_pins[10]	transitions[0x1=>0x0]	317660	1			T19	156		T22	1		T27	20
all_pins[11]	values[0x0]	868730	1			T19	473		T20	1		T21	1
all_pins[11]	values[0x1]	529320	1			T19	291		T22	2		T27	36
all_pins[11]	transitions[0x0=>0x1]	315803	1			T19	174		T22	2		T27	19
all_pins[11]	transitions[0x1=>0x0]	315892	1			T19	156		T27	22		T31	24
all_pins[12]	values[0x0]	870159	1			T19	404		T20	1		T21	1
all_pins[12]	values[0x1]	527891	1			T19	360		T27	35		T31	28
all_pins[12]	transitions[0x0=>0x1]	314008	1			T19	205		T27	17		T31	14
all_pins[12]	transitions[0x1=>0x0]	315437	1			T19	136		T22	2		T27	18
all_pins[13]	values[0x0]	870734	1			T19	389		T20	1		T21	1
all_pins[13]	values[0x1]	527316	1			T19	375		T27	42		T31	32
all_pins[13]	transitions[0x0=>0x1]	315129	1			T19	196		T27	28		T31	22
all_pins[13]	transitions[0x1=>0x0]	315704	1			T19	181		T27	21		T31	18
all_pins[14]	values[0x0]	868260	1			T19	524		T20	1		T21	1
all_pins[14]	values[0x1]	529790	1			T19	240		T22	2		T27	31
all_pins[14]	transitions[0x0=>0x1]	317119	1			T19	115		T22	2		T27	15
all_pins[14]	transitions[0x1=>0x0]	314645	1			T19	250		T27	26		T31	13
all_pins[15]	values[0x0]	867715	1			T19	445		T20	1		T21	1
all_pins[15]	values[0x1]	530335	1			T19	319		T27	38		T31	38
all_pins[15]	transitions[0x0=>0x1]	316693	1			T19	228		T27	24		T31	21
all_pins[15]	transitions[0x1=>0x0]	316148	1			T19	149		T22	2		T27	17
all_pins[16]	values[0x0]	870977	1			T19	513		T20	1		T21	1
all_pins[16]	values[0x1]	527073	1			T19	251		T22	2		T27	35
all_pins[16]	transitions[0x0=>0x1]	314301	1			T19	149		T22	2		T27	19
all_pins[16]	transitions[0x1=>0x0]	317563	1			T19	217		T27	22		T31	26
all_pins[17]	values[0x0]	870159	1			T19	457		T20	1		T21	1
all_pins[17]	values[0x1]	527891	1			T19	307		T27	47		T31	37
all_pins[17]	transitions[0x0=>0x1]	315526	1			T19	168		T27	26		T31	22
all_pins[17]	transitions[0x1=>0x0]	314708	1			T19	112		T22	2		T27	14
all_pins[18]	values[0x0]	870954	1			T19	428		T20	1		T21	1
all_pins[18]	values[0x1]	527096	1			T19	336		T27	35		T31	35
all_pins[18]	transitions[0x0=>0x1]	314948	1			T19	208		T27	16		T31	14
all_pins[18]	transitions[0x1=>0x0]	315743	1			T19	179		T27	28		T31	16
all_pins[19]	values[0x0]	872976	1			T19	484		T20	1		T21	1
all_pins[19]	values[0x1]	525074	1			T19	280		T27	42		T31	36
all_pins[19]	transitions[0x0=>0x1]	313737	1			T19	149		T27	24		T31	15
all_pins[19]	transitions[0x1=>0x0]	315759	1			T19	205		T27	17		T31	14
all_pins[20]	values[0x0]	869044	1			T19	483		T20	1		T21	1
all_pins[20]	values[0x1]	529006	1			T19	281		T22	2		T27	30
all_pins[20]	transitions[0x0=>0x1]	318185	1			T19	187		T22	2		T27	14
all_pins[20]	transitions[0x1=>0x0]	314253	1			T19	186		T27	26		T31	19
all_pins[21]	values[0x0]	872240	1			T19	509		T20	1		T21	1
all_pins[21]	values[0x1]	525810	1			T19	255		T22	1		T27	34
all_pins[21]	transitions[0x0=>0x1]	313440	1			T19	175		T27	20		T31	17
all_pins[21]	transitions[0x1=>0x0]	316636	1			T19	201		T22	1		T27	16
all_pins[22]	values[0x0]	867981	1			T19	431		T20	1		T21	1
all_pins[22]	values[0x1]	530069	1			T19	333		T22	4		T27	47
all_pins[22]	transitions[0x0=>0x1]	317537	1			T19	215		T22	3		T27	29
all_pins[22]	transitions[0x1=>0x0]	313278	1			T19	137		T27	16		T31	14
all_pins[23]	values[0x0]	868916	1			T19	469		T20	1		T21	1
all_pins[23]	values[0x1]	529134	1			T19	295		T27	30		T31	44
all_pins[23]	transitions[0x0=>0x1]	315702	1			T19	174		T27	18		T31	22
all_pins[23]	transitions[0x1=>0x0]	316637	1			T19	212		T22	4		T27	35
all_pins[24]	values[0x0]	868234	1			T19	492		T20	1		T21	1
all_pins[24]	values[0x1]	529816	1			T19	272		T22	3		T27	54
all_pins[24]	transitions[0x0=>0x1]	318042	1			T19	161		T22	3		T27	37
all_pins[24]	transitions[0x1=>0x0]	317360	1			T19	184		T27	13		T31	25
all_pins[25]	values[0x0]	870874	1			T19	529		T20	1		T21	1
all_pins[25]	values[0x1]	527176	1			T19	235		T22	4		T27	42
all_pins[25]	transitions[0x0=>0x1]	312755	1			T19	152		T22	2		T27	18
all_pins[25]	transitions[0x1=>0x0]	315395	1			T19	189		T22	1		T27	30
all_pins[26]	values[0x0]	870989	1			T19	437		T20	1		T21	1
all_pins[26]	values[0x1]	527061	1			T19	327		T27	36		T31	40
all_pins[26]	transitions[0x0=>0x1]	316833	1			T19	225		T27	17		T31	19
all_pins[26]	transitions[0x1=>0x0]	316948	1			T19	133		T22	4		T27	23
all_pins[27]	values[0x0]	868387	1			T19	527		T20	1		T21	1
all_pins[27]	values[0x1]	529663	1			T19	237		T22	1		T27	37
all_pins[27]	transitions[0x0=>0x1]	318286	1			T19	144		T22	1		T27	18
all_pins[27]	transitions[0x1=>0x0]	315684	1			T19	234		T27	17		T31	15
all_pins[28]	values[0x0]	869676	1			T19	572		T20	1		T21	1
all_pins[28]	values[0x1]	528374	1			T19	192		T22	3		T27	41
all_pins[28]	transitions[0x0=>0x1]	314516	1			T19	111		T22	2		T27	22
all_pins[28]	transitions[0x1=>0x0]	315805	1			T19	156		T27	18		T31	25
all_pins[29]	values[0x0]	867778	1			T19	429		T20	1		T21	1
all_pins[29]	values[0x1]	530272	1			T19	335		T27	41		T31	39
all_pins[29]	transitions[0x0=>0x1]	316132	1			T19	243		T27	17		T31	23
all_pins[29]	transitions[0x1=>0x0]	314234	1			T19	100		T22	3		T27	17
all_pins[30]	values[0x0]	868996	1			T19	430		T20	1		T21	1
all_pins[30]	values[0x1]	529054	1			T19	334		T22	3		T27	32
all_pins[30]	transitions[0x0=>0x1]	315694	1			T19	155		T22	3		T27	14
all_pins[30]	transitions[0x1=>0x0]	316912	1			T19	156		T27	23		T31	14
all_pins[31]	values[0x0]	872346	1			T19	508		T20	1		T21	1
all_pins[31]	values[0x1]	525704	1			T19	256		T22	2		T27	40
all_pins[31]	transitions[0x0=>0x1]	314037	1			T19	139		T22	1		T27	23
all_pins[31]	transitions[0x1=>0x0]	317387	1			T19	217		T22	2		T27	15