Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[1]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[2]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[3]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[4]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[5]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[6]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[7]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[8]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[9]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[10]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[11]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[12]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[13]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[14]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[15]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[16]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[17]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[18]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[19]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[20]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[21]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[22]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[23]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[24]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[25]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[26]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[27]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[28]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[29]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[30]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[31]	5596739	1			T19	1954		T20	1		T21	300

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91809185

1

T19

15045

T20

32

T21

7565

auto[1]

87286463

1

T19

47483

T21

2035

T22

250

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

146922213

1

T19

34678

T20

32

T21

7265

auto[1]

32173435

1

T19

27850

T21

2335

T22

9

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137744794

1

T19

31055

T20

32

T21

4792

auto[1]

41350854

1

T19

31473

T21

4808

T22

188

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	1931945	1			T19	11		T20	1		T21	55
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	1862864	1			T19	510		T21	13		T22	9
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	503927	1			T19	345		T21	26		T23	133
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	431895	1			T19	29		T21	135		T22	2
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	362205	1			T19	614		T21	20		T23	15
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	503903	1			T19	445		T21	51		T23	53
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	1929113	1			T19	24		T20	1		T21	89
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	1869963	1			T19	506		T21	12		T22	5
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	510826	1			T19	434		T21	18		T23	75
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	429031	1			T19	9		T21	122		T22	4
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	356630	1			T19	495		T21	9		T23	17
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	501176	1			T19	486		T21	50		T23	57
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	1941093	1			T19	30		T20	1		T21	79
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	1860998	1			T19	503		T21	11		T22	3
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	508045	1			T19	467		T21	40		T23	99
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	425888	1			T19	22		T21	112		T22	3
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	360126	1			T19	497		T21	13		T22	6
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	500589	1			T19	435		T21	45		T22	2
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	1928501	1			T19	17		T20	1		T21	82
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	1871380	1			T19	629		T21	12		T22	9
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	507121	1			T19	453		T21	21		T23	66
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	431429	1			T19	10		T21	129		T22	4
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	357047	1			T19	448		T21	11		T23	33
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	501261	1			T19	397		T21	45		T23	76
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	1925586	1			T19	21		T20	1		T21	169
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	1871205	1			T19	561		T21	18		T22	5
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	506292	1			T19	468		T21	52		T23	87
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	432343	1			T19	22		T21	39		T22	4
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	361082	1			T19	433		T21	6		T23	23
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	500231	1			T19	449		T21	16		T23	64
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	1933118	1			T19	30		T20	1		T21	114
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	1867307	1			T19	593		T21	16		T22	11
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	504070	1			T19	315		T21	28		T23	78
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	430879	1			T19	6		T21	102		T23	182
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	360040	1			T19	603		T21	12		T23	23
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	501325	1			T19	407		T21	28		T23	102
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	1936265	1			T19	15		T20	1		T21	159
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	1862975	1			T19	496		T21	17		T22	9
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	503462	1			T19	468		T21	76		T23	69
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	430284	1			T19	24		T21	32		T22	3
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	362405	1			T19	489		T21	4		T23	22
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	501348	1			T19	462		T21	12		T22	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	1935480	1			T19	20		T20	1		T21	148
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	1858962	1			T19	575		T21	19		T22	7
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	506361	1			T19	337		T21	33		T23	107
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	433138	1			T19	20		T21	86		T22	6
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	361328	1			T19	573		T21	4		T23	23
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	501470	1			T19	429		T21	10		T23	76
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	1938599	1			T19	10		T20	1		T21	97
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	1863935	1			T19	514		T21	12		T22	2
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	506310	1			T19	459		T21	36		T23	100
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	430326	1			T19	26		T21	83		T22	7
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	359958	1			T19	524		T21	12		T22	4
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	497611	1			T19	421		T21	60		T23	83
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	1932155	1			T19	10		T20	1		T21	131
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	1863581	1			T19	548		T21	7		T22	7
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	505125	1			T19	410		T21	22		T23	79
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	432368	1			T19	24		T21	101		T23	177
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	361749	1			T19	526		T21	6		T23	14
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	501761	1			T19	436		T21	33		T23	77
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	1936355	1			T19	39		T20	1		T21	103
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	1863720	1			T19	572		T21	9		T22	4
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	507289	1			T19	548		T21	42		T23	116
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	430546	1			T19	1		T21	82		T22	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	359752	1			T19	461		T21	20		T22	9
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	499077	1			T19	333		T21	44		T23	73
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	1926926	1			T19	28		T20	1		T21	99
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	1869209	1			T19	578		T21	17		T22	8
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	506256	1			T19	435		T21	27		T23	87
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	431436	1			T19	14		T21	120		T22	3
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	359608	1			T19	503		T21	12		T23	27
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	503304	1			T19	396		T21	25		T22	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	1923625	1			T19	28		T20	1		T21	60
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	1869915	1			T19	566		T21	15		T22	4
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	506654	1			T19	440		T21	32		T23	98
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	434814	1			T19	16		T21	137		T22	5
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	360824	1			T19	480		T21	19		T22	6
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	500907	1			T19	424		T21	37		T23	83
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	1928435	1			T19	24		T20	1		T21	71
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	1871588	1			T19	595		T21	6		T22	4
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	507083	1			T19	379		T21	24		T23	85
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	430467	1			T19	13		T21	124		T22	7
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	360451	1			T19	461		T21	15		T22	6
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	498715	1			T19	482		T21	60		T23	69
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	1924967	1			T19	25		T20	1		T21	127
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	1868077	1			T19	505		T21	15		T22	2
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	506758	1			T19	425		T21	37		T23	78
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	432805	1			T19	18		T21	77		T23	148
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	360403	1			T19	573		T21	4		T23	32
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	503729	1			T19	408		T21	40		T23	67
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	1935614	1			T19	16		T20	1		T21	104
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	1866947	1			T19	437		T21	18		T22	4
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	506836	1			T19	521		T21	56		T23	41
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	430036	1			T19	30		T21	88		T22	7
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	357830	1			T19	459		T21	8		T22	4
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	499476	1			T19	491		T21	26		T23	102
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	1930191	1			T19	17		T20	1		T21	95
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	1871456	1			T19	513		T21	23		T22	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	503228	1			T19	398		T21	72		T22	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	430479	1			T19	21		T21	74		T22	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	360571	1			T19	553		T21	4		T22	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	500814	1			T19	452		T21	32		T23	99
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	1927088	1			T19	17		T20	1		T21	117
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	1870242	1			T19	509		T21	11		T23	18
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	500522	1			T19	413		T21	26		T23	100
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	436617	1			T19	11		T21	92		T22	7
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	362403	1			T19	580		T21	19		T23	30
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	499867	1			T19	424		T21	35		T23	50
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	1937879	1			T19	14		T20	1		T21	76
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	1866897	1			T19	500		T21	6		T22	13
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	502815	1			T19	422		T21	26		T23	44
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	429130	1			T19	30		T21	117		T23	217
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	361465	1			T19	554		T21	19		T23	31
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	498553	1			T19	434		T21	56		T23	137
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	1932217	1			T19	19		T20	1		T21	70
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	1870384	1			T19	588		T21	10		T22	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	507046	1			T19	371		T21	31		T23	65
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	429133	1			T19	27		T21	143		T22	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	360274	1			T19	571		T21	17		T22	8
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	497685	1			T19	378		T21	29		T23	118
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	1933752	1			T19	22		T20	1		T21	94
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	1863297	1			T19	484		T21	10		T22	6
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	501724	1			T19	387		T21	10		T22	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	432514	1			T19	18		T21	143		T23	156
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	361388	1			T19	500		T21	16		T23	24
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	504064	1			T19	543		T21	27		T23	78
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	1928922	1			T19	29		T20	1		T21	176
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	1867562	1			T19	540		T21	18		T22	2
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	505777	1			T19	454		T21	40		T23	62
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	433077	1			T19	17		T21	50		T23	194
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	360978	1			T19	520		T21	2		T22	11
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	500423	1			T19	394		T21	14		T23	63
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	1931341	1			T19	11		T20	1		T21	137
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	1867709	1			T19	389		T21	18		T22	6
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	505484	1			T19	459		T21	47		T23	98
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	429478	1			T19	25		T21	47		T22	4
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	359917	1			T19	644		T21	11		T23	30
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	502810	1			T19	426		T21	40		T23	57
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	1929824	1			T19	24		T20	1		T21	109
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	1869584	1			T19	442		T21	13		T22	2
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	500936	1			T19	423		T21	28		T22	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	434807	1			T19	20		T21	97		T23	183
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	363111	1			T19	577		T21	16		T23	27
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	498477	1			T19	468		T21	37		T23	64
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	1943648	1			T19	14		T20	1		T21	106
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	1858137	1			T19	466		T21	19		T22	2
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	507132	1			T19	397		T21	32		T23	92
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	429066	1			T19	26		T21	94		T22	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	358142	1			T19	553		T21	11		T22	2
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	500614	1			T19	498		T21	38		T23	77
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	1940974	1			T19	21		T20	1		T21	71
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	1860997	1			T19	552		T21	7		T22	7
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	502307	1			T19	337		T21	28		T22	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	432872	1			T19	21		T21	138		T22	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	361928	1			T19	523		T21	13		T22	3
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	497661	1			T19	500		T21	43		T23	98
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	1934217	1			T19	29		T20	1		T21	61
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	1866681	1			T19	488		T21	7		T22	9
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	506362	1			T19	447		T21	38		T23	60
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	430193	1			T19	9		T21	113		T22	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	360656	1			T19	507		T21	22		T23	29
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	498630	1			T19	474		T21	59		T23	74
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	1932303	1			T19	12		T20	1		T21	104
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	1869294	1			T19	460		T21	16		T22	2
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	503493	1			T19	589		T21	39		T23	91
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	430662	1			T19	29		T21	95		T22	4
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	361210	1			T19	472		T21	10		T22	11
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	499777	1			T19	392		T21	36		T23	89
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	1929162	1			T19	31		T20	1		T21	68
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	1870913	1			T19	467		T21	9		T22	10
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	502066	1			T19	460		T21	28		T23	82
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	432268	1			T19	21		T21	122		T22	1
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	361936	1			T19	510		T21	20		T23	18
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	500394	1			T19	465		T21	53		T23	95
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	1938724	1			T19	16		T20	1		T21	89
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	1863097	1			T19	480		T21	17		T22	3
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	502494	1			T19	375		T21	21		T22	1
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	430218	1			T19	17		T21	111		T22	9
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	362830	1			T19	531		T21	13		T22	3
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	499376	1			T19	535		T21	49		T23	74
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	1930319	1			T19	20		T20	1		T21	95
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	1871757	1			T19	566		T21	8		T22	8
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	502797	1			T19	483		T21	58		T23	134
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	434841	1			T19	15		T21	79		T22	4
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	359400	1			T19	513		T21	12		T22	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	497625	1			T19	357		T21	48		T23	78
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	1935144	1			T19	23		T20	1		T21	96
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	1868383	1			T19	494		T21	15		T22	6
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	505698	1			T19	443		T21	23		T23	86
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	430367	1			T19	25		T21	113		T22	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	358661	1			T19	522		T21	13		T23	23
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	498486	1			T19	447		T21	40		T23	63

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal