Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[1]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[2]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[3]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[4]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[5]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[6]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[7]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[8]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[9]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[10]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[11]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[12]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[13]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[14]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[15]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[16]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[17]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[18]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[19]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[20]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[21]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[22]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[23]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[24]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[25]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[26]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[27]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[28]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[29]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[30]	5596739	1			T19	1954		T20	1		T21	300
bins_for_gpio_bits[31]	5596739	1			T19	1954		T20	1		T21	300

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91809185

1

T19

15045

T20

32

T21

7565

auto[1]

87286463

1

T19

47483

T21

2035

T22

250

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91802805

1

T19

15054

T20

32

T21

7559

auto[1]

87292843

1

T19

47474

T21

2041

T22

252

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	2776704	1			T19	336		T20	1		T21	206
bins_for_gpio_bits[0]	auto[0]	auto[1]	90870	1			T19	50		T21	10		T23	7
bins_for_gpio_bits[0]	auto[1]	auto[0]	91063	1			T19	49		T21	10		T23	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	2638102	1			T19	1519		T21	74		T22	9
bins_for_gpio_bits[1]	auto[0]	auto[0]	2777324	1			T19	407		T20	1		T21	221
bins_for_gpio_bits[1]	auto[0]	auto[1]	91449	1			T19	61		T21	7		T23	10
bins_for_gpio_bits[1]	auto[1]	auto[0]	91646	1			T19	60		T21	8		T23	10
bins_for_gpio_bits[1]	auto[1]	auto[1]	2636320	1			T19	1426		T21	64		T22	5
bins_for_gpio_bits[2]	auto[0]	auto[0]	2784558	1			T19	450		T20	1		T21	222
bins_for_gpio_bits[2]	auto[0]	auto[1]	90287	1			T19	69		T21	9		T23	11
bins_for_gpio_bits[2]	auto[1]	auto[0]	90468	1			T19	69		T21	9		T23	11
bins_for_gpio_bits[2]	auto[1]	auto[1]	2631426	1			T19	1366		T21	60		T22	11
bins_for_gpio_bits[3]	auto[0]	auto[0]	2775884	1			T19	419		T20	1		T21	224
bins_for_gpio_bits[3]	auto[0]	auto[1]	90980	1			T19	61		T21	8		T23	13
bins_for_gpio_bits[3]	auto[1]	auto[0]	91167	1			T19	61		T21	8		T23	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	2638708	1			T19	1413		T21	60		T22	9
bins_for_gpio_bits[4]	auto[0]	auto[0]	2773355	1			T19	445		T20	1		T21	256
bins_for_gpio_bits[4]	auto[0]	auto[1]	90659	1			T19	66		T21	4		T23	13
bins_for_gpio_bits[4]	auto[1]	auto[0]	90866	1			T19	66		T21	4		T23	13
bins_for_gpio_bits[4]	auto[1]	auto[1]	2641859	1			T19	1377		T21	36		T22	5
bins_for_gpio_bits[5]	auto[0]	auto[0]	2777011	1			T19	291		T20	1		T21	237
bins_for_gpio_bits[5]	auto[0]	auto[1]	90867	1			T19	61		T21	7		T23	18
bins_for_gpio_bits[5]	auto[1]	auto[0]	91056	1			T19	60		T21	7		T23	18
bins_for_gpio_bits[5]	auto[1]	auto[1]	2637805	1			T19	1542		T21	49		T22	11
bins_for_gpio_bits[6]	auto[0]	auto[0]	2779380	1			T19	443		T20	1		T21	264
bins_for_gpio_bits[6]	auto[0]	auto[1]	90382	1			T19	64		T21	3		T23	13
bins_for_gpio_bits[6]	auto[1]	auto[0]	90631	1			T19	64		T21	3		T22	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	2636346	1			T19	1383		T21	30		T22	10
bins_for_gpio_bits[7]	auto[0]	auto[0]	2783962	1			T19	325		T20	1		T21	264
bins_for_gpio_bits[7]	auto[0]	auto[1]	90811	1			T19	52		T21	3		T23	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	91017	1			T19	52		T21	3		T23	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	2630949	1			T19	1525		T21	30		T22	7
bins_for_gpio_bits[8]	auto[0]	auto[0]	2784589	1			T19	435		T20	1		T21	208
bins_for_gpio_bits[8]	auto[0]	auto[1]	90442	1			T19	61		T21	8		T23	14
bins_for_gpio_bits[8]	auto[1]	auto[0]	90646	1			T19	60		T21	8		T23	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	2631062	1			T19	1398		T21	76		T22	6
bins_for_gpio_bits[9]	auto[0]	auto[0]	2778548	1			T19	389		T20	1		T21	248
bins_for_gpio_bits[9]	auto[0]	auto[1]	90865	1			T19	55		T21	6		T23	10
bins_for_gpio_bits[9]	auto[1]	auto[0]	91100	1			T19	55		T21	6		T23	10
bins_for_gpio_bits[9]	auto[1]	auto[1]	2636226	1			T19	1455		T21	40		T22	7
bins_for_gpio_bits[10]	auto[0]	auto[0]	2783122	1			T19	518		T20	1		T21	219
bins_for_gpio_bits[10]	auto[0]	auto[1]	90898	1			T19	71		T21	8		T23	14
bins_for_gpio_bits[10]	auto[1]	auto[0]	91068	1			T19	70		T21	8		T23	14
bins_for_gpio_bits[10]	auto[1]	auto[1]	2631651	1			T19	1295		T21	65		T22	13
bins_for_gpio_bits[11]	auto[0]	auto[0]	2773576	1			T19	416		T20	1		T21	243
bins_for_gpio_bits[11]	auto[0]	auto[1]	90828	1			T19	61		T21	3		T23	16
bins_for_gpio_bits[11]	auto[1]	auto[0]	91042	1			T19	61		T21	3		T22	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	2641293	1			T19	1416		T21	51		T22	9
bins_for_gpio_bits[12]	auto[0]	auto[0]	2773619	1			T19	418		T20	1		T21	220
bins_for_gpio_bits[12]	auto[0]	auto[1]	91242	1			T19	66		T21	9		T23	14
bins_for_gpio_bits[12]	auto[1]	auto[0]	91474	1			T19	66		T21	9		T23	14
bins_for_gpio_bits[12]	auto[1]	auto[1]	2640404	1			T19	1404		T21	62		T22	10
bins_for_gpio_bits[13]	auto[0]	auto[0]	2774982	1			T19	353		T20	1		T21	207
bins_for_gpio_bits[13]	auto[0]	auto[1]	90795	1			T19	63		T21	12		T23	12
bins_for_gpio_bits[13]	auto[1]	auto[0]	91003	1			T19	63		T21	12		T23	12
bins_for_gpio_bits[13]	auto[1]	auto[1]	2639959	1			T19	1475		T21	69		T22	10
bins_for_gpio_bits[14]	auto[0]	auto[0]	2773611	1			T19	418		T20	1		T21	232
bins_for_gpio_bits[14]	auto[0]	auto[1]	90755	1			T19	50		T21	8		T23	15
bins_for_gpio_bits[14]	auto[1]	auto[0]	90919	1			T19	50		T21	9		T23	15
bins_for_gpio_bits[14]	auto[1]	auto[1]	2641454	1			T19	1436		T21	51		T22	2
bins_for_gpio_bits[15]	auto[0]	auto[0]	2781223	1			T19	495		T20	1		T21	242
bins_for_gpio_bits[15]	auto[0]	auto[1]	91048	1			T19	72		T21	6		T23	17
bins_for_gpio_bits[15]	auto[1]	auto[0]	91263	1			T19	72		T21	6		T23	17
bins_for_gpio_bits[15]	auto[1]	auto[1]	2633205	1			T19	1315		T21	46		T22	8
bins_for_gpio_bits[16]	auto[0]	auto[0]	2772941	1			T19	376		T20	1		T21	237
bins_for_gpio_bits[16]	auto[0]	auto[1]	90726	1			T19	61		T21	3		T23	16
bins_for_gpio_bits[16]	auto[1]	auto[0]	90957	1			T19	60		T21	4		T23	16
bins_for_gpio_bits[16]	auto[1]	auto[1]	2642115	1			T19	1457		T21	56		T22	2
bins_for_gpio_bits[17]	auto[0]	auto[0]	2773050	1			T19	377		T20	1		T21	229
bins_for_gpio_bits[17]	auto[0]	auto[1]	91017	1			T19	64		T21	6		T23	13
bins_for_gpio_bits[17]	auto[1]	auto[0]	91177	1			T19	64		T21	6		T23	13
bins_for_gpio_bits[17]	auto[1]	auto[1]	2641495	1			T19	1449		T21	59		T23	85
bins_for_gpio_bits[18]	auto[0]	auto[0]	2778934	1			T19	406		T20	1		T21	210
bins_for_gpio_bits[18]	auto[0]	auto[1]	90703	1			T19	60		T21	9		T23	17
bins_for_gpio_bits[18]	auto[1]	auto[0]	90890	1			T19	60		T21	9		T23	17
bins_for_gpio_bits[18]	auto[1]	auto[1]	2636212	1			T19	1428		T21	72		T22	13
bins_for_gpio_bits[19]	auto[0]	auto[0]	2777630	1			T19	374		T20	1		T21	237
bins_for_gpio_bits[19]	auto[0]	auto[1]	90565	1			T19	44		T21	7		T23	15
bins_for_gpio_bits[19]	auto[1]	auto[0]	90766	1			T19	43		T21	7		T23	15
bins_for_gpio_bits[19]	auto[1]	auto[1]	2637778	1			T19	1493		T21	49		T22	9
bins_for_gpio_bits[20]	auto[0]	auto[0]	2776939	1			T19	370		T20	1		T21	241
bins_for_gpio_bits[20]	auto[0]	auto[1]	90886	1			T19	58		T21	6		T23	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	91051	1			T19	57		T21	6		T23	16
bins_for_gpio_bits[20]	auto[1]	auto[1]	2637863	1			T19	1469		T21	47		T22	6
bins_for_gpio_bits[21]	auto[0]	auto[0]	2776399	1			T19	447		T20	1		T21	263
bins_for_gpio_bits[21]	auto[0]	auto[1]	91182	1			T19	53		T21	3		T23	14
bins_for_gpio_bits[21]	auto[1]	auto[0]	91377	1			T19	53		T21	3		T23	14
bins_for_gpio_bits[21]	auto[1]	auto[1]	2637781	1			T19	1401		T21	31		T22	13
bins_for_gpio_bits[22]	auto[0]	auto[0]	2775242	1			T19	432		T20	1		T21	225
bins_for_gpio_bits[22]	auto[0]	auto[1]	90888	1			T19	63		T21	5		T23	15
bins_for_gpio_bits[22]	auto[1]	auto[0]	91061	1			T19	63		T21	6		T23	15
bins_for_gpio_bits[22]	auto[1]	auto[1]	2639548	1			T19	1396		T21	64		T22	6
bins_for_gpio_bits[23]	auto[0]	auto[0]	2774709	1			T19	410		T20	1		T21	227
bins_for_gpio_bits[23]	auto[0]	auto[1]	90672	1			T19	57		T21	6		T23	12
bins_for_gpio_bits[23]	auto[1]	auto[0]	90858	1			T19	57		T21	7		T23	12
bins_for_gpio_bits[23]	auto[1]	auto[1]	2640500	1			T19	1430		T21	60		T22	2
bins_for_gpio_bits[24]	auto[0]	auto[0]	2788832	1			T19	382		T20	1		T21	226
bins_for_gpio_bits[24]	auto[0]	auto[1]	90815	1			T19	55		T21	6		T23	13
bins_for_gpio_bits[24]	auto[1]	auto[0]	91014	1			T19	55		T21	6		T23	13
bins_for_gpio_bits[24]	auto[1]	auto[1]	2626078	1			T19	1462		T21	62		T22	4
bins_for_gpio_bits[25]	auto[0]	auto[0]	2785311	1			T19	333		T20	1		T21	230
bins_for_gpio_bits[25]	auto[0]	auto[1]	90621	1			T19	46		T21	7		T23	19
bins_for_gpio_bits[25]	auto[1]	auto[0]	90842	1			T19	46		T21	7		T23	19
bins_for_gpio_bits[25]	auto[1]	auto[1]	2629965	1			T19	1529		T21	56		T22	10
bins_for_gpio_bits[26]	auto[0]	auto[0]	2779887	1			T19	430		T20	1		T21	200
bins_for_gpio_bits[26]	auto[0]	auto[1]	90706	1			T19	55		T21	12		T23	14
bins_for_gpio_bits[26]	auto[1]	auto[0]	90885	1			T19	55		T21	12		T23	14
bins_for_gpio_bits[26]	auto[1]	auto[1]	2635261	1			T19	1414		T21	76		T22	9
bins_for_gpio_bits[27]	auto[0]	auto[0]	2775573	1			T19	563		T20	1		T21	231
bins_for_gpio_bits[27]	auto[0]	auto[1]	90677	1			T19	67		T21	6		T23	15
bins_for_gpio_bits[27]	auto[1]	auto[0]	90885	1			T19	67		T21	7		T23	15
bins_for_gpio_bits[27]	auto[1]	auto[1]	2639604	1			T19	1257		T21	56		T22	13
bins_for_gpio_bits[28]	auto[0]	auto[0]	2772459	1			T19	452		T20	1		T21	209
bins_for_gpio_bits[28]	auto[0]	auto[1]	90847	1			T19	60		T21	9		T23	15
bins_for_gpio_bits[28]	auto[1]	auto[0]	91037	1			T19	60		T21	9		T23	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	2642396	1			T19	1382		T21	73		T22	10
bins_for_gpio_bits[29]	auto[0]	auto[0]	2780503	1			T19	349		T20	1		T21	213
bins_for_gpio_bits[29]	auto[0]	auto[1]	90711	1			T19	60		T21	8		T23	16
bins_for_gpio_bits[29]	auto[1]	auto[0]	90933	1			T19	59		T21	8		T23	16
bins_for_gpio_bits[29]	auto[1]	auto[1]	2634592	1			T19	1486		T21	71		T22	6
bins_for_gpio_bits[30]	auto[0]	auto[0]	2776654	1			T19	465		T20	1		T21	225
bins_for_gpio_bits[30]	auto[0]	auto[1]	91119	1			T19	53		T21	7		T23	14
bins_for_gpio_bits[30]	auto[1]	auto[0]	91303	1			T19	53		T21	7		T23	14
bins_for_gpio_bits[30]	auto[1]	auto[1]	2637663	1			T19	1383		T21	61		T22	9
bins_for_gpio_bits[31]	auto[0]	auto[0]	2780424	1			T19	438		T20	1		T21	227
bins_for_gpio_bits[31]	auto[0]	auto[1]	90557	1			T19	53		T21	5		T23	13
bins_for_gpio_bits[31]	auto[1]	auto[0]	90785	1			T19	53		T21	5		T23	13
bins_for_gpio_bits[31]	auto[1]	auto[1]	2634973	1			T19	1410		T21	63		T22	6