Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3688729 |
1 |
|
|
T19 |
1000 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1907751 |
1 |
|
|
T19 |
1026 |
|
T22 |
5 |
|
T29 |
17289 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5361366 |
1 |
|
|
T19 |
1987 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
235114 |
1 |
|
|
T19 |
39 |
|
T29 |
1831 |
|
T100 |
180 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3691754 |
1 |
|
|
T19 |
1171 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1904726 |
1 |
|
|
T19 |
855 |
|
T22 |
4 |
|
T29 |
17026 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
841887 |
1 |
|
|
T19 |
413 |
|
T29 |
7707 |
|
T100 |
397 |
| auto[1] |
auto[0] |
auto[1] |
118740 |
1 |
|
|
T19 |
21 |
|
T29 |
895 |
|
T100 |
90 |
| auto[1] |
auto[1] |
auto[0] |
827725 |
1 |
|
|
T19 |
403 |
|
T22 |
4 |
|
T29 |
7488 |
| auto[1] |
auto[1] |
auto[1] |
116374 |
1 |
|
|
T19 |
18 |
|
T29 |
936 |
|
T100 |
90 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3677244 |
1 |
|
|
T19 |
1004 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1919236 |
1 |
|
|
T19 |
1022 |
|
T22 |
5 |
|
T29 |
17736 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5360267 |
1 |
|
|
T19 |
1985 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
236213 |
1 |
|
|
T19 |
41 |
|
T29 |
2182 |
|
T100 |
96 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3687838 |
1 |
|
|
T19 |
1074 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1908642 |
1 |
|
|
T19 |
952 |
|
T22 |
4 |
|
T29 |
18573 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
834411 |
1 |
|
|
T19 |
425 |
|
T29 |
8282 |
|
T100 |
224 |
| auto[1] |
auto[0] |
auto[1] |
118105 |
1 |
|
|
T19 |
15 |
|
T29 |
1169 |
|
T100 |
51 |
| auto[1] |
auto[1] |
auto[0] |
838018 |
1 |
|
|
T19 |
486 |
|
T22 |
4 |
|
T29 |
8109 |
| auto[1] |
auto[1] |
auto[1] |
118108 |
1 |
|
|
T19 |
26 |
|
T29 |
1013 |
|
T100 |
45 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3674404 |
1 |
|
|
T19 |
992 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1922076 |
1 |
|
|
T19 |
1034 |
|
T22 |
5 |
|
T29 |
17780 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5358149 |
1 |
|
|
T19 |
1986 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
238331 |
1 |
|
|
T19 |
40 |
|
T29 |
2137 |
|
T100 |
92 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3672523 |
1 |
|
|
T19 |
988 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1923957 |
1 |
|
|
T19 |
1038 |
|
T29 |
18298 |
|
T100 |
495 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
841176 |
1 |
|
|
T19 |
513 |
|
T29 |
7886 |
|
T100 |
195 |
| auto[1] |
auto[0] |
auto[1] |
118749 |
1 |
|
|
T19 |
19 |
|
T29 |
1054 |
|
T100 |
45 |
| auto[1] |
auto[1] |
auto[0] |
844450 |
1 |
|
|
T19 |
485 |
|
T29 |
8275 |
|
T100 |
208 |
| auto[1] |
auto[1] |
auto[1] |
119582 |
1 |
|
|
T19 |
21 |
|
T29 |
1083 |
|
T100 |
47 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3681842 |
1 |
|
|
T19 |
976 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1914638 |
1 |
|
|
T19 |
1050 |
|
T22 |
5 |
|
T29 |
18811 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5361263 |
1 |
|
|
T19 |
1985 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
235217 |
1 |
|
|
T19 |
41 |
|
T29 |
1877 |
|
T100 |
124 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3695394 |
1 |
|
|
T19 |
902 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1901086 |
1 |
|
|
T19 |
1124 |
|
T29 |
16720 |
|
T100 |
657 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
833814 |
1 |
|
|
T19 |
572 |
|
T29 |
6918 |
|
T100 |
316 |
| auto[1] |
auto[0] |
auto[1] |
117930 |
1 |
|
|
T19 |
25 |
|
T29 |
897 |
|
T100 |
73 |
| auto[1] |
auto[1] |
auto[0] |
832055 |
1 |
|
|
T19 |
511 |
|
T29 |
7925 |
|
T100 |
217 |
| auto[1] |
auto[1] |
auto[1] |
117287 |
1 |
|
|
T19 |
16 |
|
T29 |
980 |
|
T100 |
51 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3692544 |
1 |
|
|
T19 |
813 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1903936 |
1 |
|
|
T19 |
1213 |
|
T29 |
16414 |
|
T100 |
752 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5359736 |
1 |
|
|
T19 |
1985 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
236744 |
1 |
|
|
T19 |
41 |
|
T29 |
2002 |
|
T100 |
129 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3683762 |
1 |
|
|
T19 |
1013 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1912718 |
1 |
|
|
T19 |
1013 |
|
T29 |
17533 |
|
T100 |
726 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
846196 |
1 |
|
|
T19 |
343 |
|
T29 |
8499 |
|
T100 |
304 |
| auto[1] |
auto[0] |
auto[1] |
119843 |
1 |
|
|
T19 |
12 |
|
T29 |
1135 |
|
T100 |
64 |
| auto[1] |
auto[1] |
auto[0] |
829778 |
1 |
|
|
T19 |
629 |
|
T29 |
7032 |
|
T100 |
293 |
| auto[1] |
auto[1] |
auto[1] |
116901 |
1 |
|
|
T19 |
29 |
|
T29 |
867 |
|
T100 |
65 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3691341 |
1 |
|
|
T19 |
784 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1905139 |
1 |
|
|
T19 |
1242 |
|
T22 |
5 |
|
T29 |
19233 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5358775 |
1 |
|
|
T19 |
1974 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
237705 |
1 |
|
|
T19 |
52 |
|
T29 |
2080 |
|
T100 |
104 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3678225 |
1 |
|
|
T19 |
916 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1918255 |
1 |
|
|
T19 |
1110 |
|
T29 |
17745 |
|
T100 |
594 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
849655 |
1 |
|
|
T19 |
449 |
|
T29 |
7348 |
|
T100 |
247 |
| auto[1] |
auto[0] |
auto[1] |
120173 |
1 |
|
|
T19 |
19 |
|
T29 |
889 |
|
T100 |
54 |
| auto[1] |
auto[1] |
auto[0] |
830895 |
1 |
|
|
T19 |
609 |
|
T29 |
8317 |
|
T100 |
243 |
| auto[1] |
auto[1] |
auto[1] |
117532 |
1 |
|
|
T19 |
33 |
|
T29 |
1191 |
|
T100 |
50 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3679937 |
1 |
|
|
T19 |
1035 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1916543 |
1 |
|
|
T19 |
991 |
|
T22 |
5 |
|
T29 |
18393 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5358832 |
1 |
|
|
T19 |
1992 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
237648 |
1 |
|
|
T19 |
34 |
|
T29 |
1964 |
|
T100 |
165 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3673604 |
1 |
|
|
T19 |
1002 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1922876 |
1 |
|
|
T19 |
1024 |
|
T29 |
17508 |
|
T100 |
880 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
847324 |
1 |
|
|
T19 |
427 |
|
T29 |
7627 |
|
T100 |
219 |
| auto[1] |
auto[0] |
auto[1] |
119345 |
1 |
|
|
T19 |
10 |
|
T29 |
869 |
|
T100 |
49 |
| auto[1] |
auto[1] |
auto[0] |
837904 |
1 |
|
|
T19 |
563 |
|
T29 |
7917 |
|
T100 |
496 |
| auto[1] |
auto[1] |
auto[1] |
118303 |
1 |
|
|
T19 |
24 |
|
T29 |
1095 |
|
T100 |
116 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3683218 |
1 |
|
|
T19 |
935 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1913262 |
1 |
|
|
T19 |
1091 |
|
T22 |
4 |
|
T29 |
17479 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5360122 |
1 |
|
|
T19 |
1984 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
236358 |
1 |
|
|
T19 |
42 |
|
T29 |
2070 |
|
T100 |
133 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3691609 |
1 |
|
|
T19 |
1190 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1904871 |
1 |
|
|
T19 |
836 |
|
T29 |
17881 |
|
T100 |
733 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
838687 |
1 |
|
|
T19 |
329 |
|
T29 |
8309 |
|
T100 |
292 |
| auto[1] |
auto[0] |
auto[1] |
119687 |
1 |
|
|
T19 |
15 |
|
T29 |
1142 |
|
T100 |
62 |
| auto[1] |
auto[1] |
auto[0] |
829826 |
1 |
|
|
T19 |
465 |
|
T29 |
7502 |
|
T100 |
308 |
| auto[1] |
auto[1] |
auto[1] |
116671 |
1 |
|
|
T19 |
27 |
|
T29 |
928 |
|
T100 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3678737 |
1 |
|
|
T19 |
1077 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1917743 |
1 |
|
|
T19 |
949 |
|
T22 |
9 |
|
T29 |
17358 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5357855 |
1 |
|
|
T19 |
1978 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
238625 |
1 |
|
|
T19 |
48 |
|
T29 |
2019 |
|
T100 |
147 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3674667 |
1 |
|
|
T19 |
991 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1921813 |
1 |
|
|
T19 |
1035 |
|
T29 |
17934 |
|
T100 |
794 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
843597 |
1 |
|
|
T19 |
566 |
|
T29 |
8133 |
|
T100 |
290 |
| auto[1] |
auto[0] |
auto[1] |
120044 |
1 |
|
|
T19 |
30 |
|
T29 |
1036 |
|
T100 |
57 |
| auto[1] |
auto[1] |
auto[0] |
839591 |
1 |
|
|
T19 |
421 |
|
T29 |
7782 |
|
T100 |
357 |
| auto[1] |
auto[1] |
auto[1] |
118581 |
1 |
|
|
T19 |
18 |
|
T29 |
983 |
|
T100 |
90 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3669123 |
1 |
|
|
T19 |
904 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1927357 |
1 |
|
|
T19 |
1122 |
|
T29 |
18018 |
|
T100 |
892 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5360688 |
1 |
|
|
T19 |
1989 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
235792 |
1 |
|
|
T19 |
37 |
|
T29 |
1955 |
|
T100 |
166 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3690899 |
1 |
|
|
T19 |
1070 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1905581 |
1 |
|
|
T19 |
956 |
|
T22 |
4 |
|
T29 |
17545 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
827845 |
1 |
|
|
T19 |
381 |
|
T22 |
4 |
|
T29 |
7442 |
| auto[1] |
auto[0] |
auto[1] |
116390 |
1 |
|
|
T19 |
15 |
|
T29 |
919 |
|
T100 |
72 |
| auto[1] |
auto[1] |
auto[0] |
841944 |
1 |
|
|
T19 |
538 |
|
T29 |
8148 |
|
T100 |
410 |
| auto[1] |
auto[1] |
auto[1] |
119402 |
1 |
|
|
T19 |
22 |
|
T29 |
1036 |
|
T100 |
94 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3685269 |
1 |
|
|
T19 |
926 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1911211 |
1 |
|
|
T19 |
1100 |
|
T29 |
17100 |
|
T100 |
1048 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5362811 |
1 |
|
|
T19 |
1999 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
233669 |
1 |
|
|
T19 |
27 |
|
T29 |
2002 |
|
T100 |
165 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3705672 |
1 |
|
|
T19 |
1158 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1890808 |
1 |
|
|
T19 |
868 |
|
T29 |
17199 |
|
T100 |
869 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
830699 |
1 |
|
|
T19 |
418 |
|
T29 |
8184 |
|
T100 |
211 |
| auto[1] |
auto[0] |
auto[1] |
117309 |
1 |
|
|
T19 |
12 |
|
T29 |
1077 |
|
T100 |
53 |
| auto[1] |
auto[1] |
auto[0] |
826440 |
1 |
|
|
T19 |
423 |
|
T29 |
7013 |
|
T100 |
493 |
| auto[1] |
auto[1] |
auto[1] |
116360 |
1 |
|
|
T19 |
15 |
|
T29 |
925 |
|
T100 |
112 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3699336 |
1 |
|
|
T19 |
912 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1897144 |
1 |
|
|
T19 |
1114 |
|
T22 |
4 |
|
T29 |
17072 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5358241 |
1 |
|
|
T19 |
1991 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
238239 |
1 |
|
|
T19 |
35 |
|
T29 |
2080 |
|
T100 |
131 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3681714 |
1 |
|
|
T19 |
1022 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1914766 |
1 |
|
|
T19 |
1004 |
|
T29 |
17550 |
|
T100 |
692 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
849000 |
1 |
|
|
T19 |
454 |
|
T29 |
7637 |
|
T100 |
159 |
| auto[1] |
auto[0] |
auto[1] |
121152 |
1 |
|
|
T19 |
15 |
|
T29 |
1074 |
|
T100 |
34 |
| auto[1] |
auto[1] |
auto[0] |
827527 |
1 |
|
|
T19 |
515 |
|
T29 |
7833 |
|
T100 |
402 |
| auto[1] |
auto[1] |
auto[1] |
117087 |
1 |
|
|
T19 |
20 |
|
T29 |
1006 |
|
T100 |
97 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3672826 |
1 |
|
|
T19 |
1020 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1923654 |
1 |
|
|
T19 |
1006 |
|
T22 |
9 |
|
T29 |
18356 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5359421 |
1 |
|
|
T19 |
1989 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
237059 |
1 |
|
|
T19 |
37 |
|
T29 |
2041 |
|
T100 |
137 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3688104 |
1 |
|
|
T19 |
1066 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1908376 |
1 |
|
|
T19 |
960 |
|
T29 |
18085 |
|
T100 |
676 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
826648 |
1 |
|
|
T19 |
505 |
|
T29 |
7609 |
|
T100 |
324 |
| auto[1] |
auto[0] |
auto[1] |
116762 |
1 |
|
|
T19 |
22 |
|
T29 |
922 |
|
T100 |
82 |
| auto[1] |
auto[1] |
auto[0] |
844669 |
1 |
|
|
T19 |
418 |
|
T29 |
8435 |
|
T100 |
215 |
| auto[1] |
auto[1] |
auto[1] |
120297 |
1 |
|
|
T19 |
15 |
|
T29 |
1119 |
|
T100 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3681353 |
1 |
|
|
T19 |
1004 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1915127 |
1 |
|
|
T19 |
1022 |
|
T22 |
5 |
|
T29 |
16930 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5358988 |
1 |
|
|
T19 |
1991 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
237492 |
1 |
|
|
T19 |
35 |
|
T29 |
2054 |
|
T100 |
110 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3678023 |
1 |
|
|
T19 |
1112 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1918457 |
1 |
|
|
T19 |
914 |
|
T29 |
17986 |
|
T100 |
608 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
838110 |
1 |
|
|
T19 |
455 |
|
T29 |
8496 |
|
T100 |
268 |
| auto[1] |
auto[0] |
auto[1] |
118486 |
1 |
|
|
T19 |
18 |
|
T29 |
1138 |
|
T100 |
66 |
| auto[1] |
auto[1] |
auto[0] |
842855 |
1 |
|
|
T19 |
424 |
|
T29 |
7436 |
|
T100 |
230 |
| auto[1] |
auto[1] |
auto[1] |
119006 |
1 |
|
|
T19 |
17 |
|
T29 |
916 |
|
T100 |
44 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3687654 |
1 |
|
|
T19 |
1033 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1908826 |
1 |
|
|
T19 |
993 |
|
T22 |
9 |
|
T29 |
18403 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5361694 |
1 |
|
|
T19 |
1977 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
234786 |
1 |
|
|
T19 |
49 |
|
T29 |
1984 |
|
T100 |
167 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3695827 |
1 |
|
|
T19 |
775 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1900653 |
1 |
|
|
T19 |
1251 |
|
T22 |
4 |
|
T29 |
17373 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
840779 |
1 |
|
|
T19 |
618 |
|
T29 |
7553 |
|
T100 |
432 |
| auto[1] |
auto[0] |
auto[1] |
119066 |
1 |
|
|
T19 |
25 |
|
T29 |
961 |
|
T100 |
102 |
| auto[1] |
auto[1] |
auto[0] |
825088 |
1 |
|
|
T19 |
584 |
|
T22 |
4 |
|
T29 |
7836 |
| auto[1] |
auto[1] |
auto[1] |
115720 |
1 |
|
|
T19 |
24 |
|
T29 |
1023 |
|
T100 |
65 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3683096 |
1 |
|
|
T19 |
846 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1913384 |
1 |
|
|
T19 |
1180 |
|
T22 |
9 |
|
T29 |
17385 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5359451 |
1 |
|
|
T19 |
1990 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
237029 |
1 |
|
|
T19 |
36 |
|
T29 |
2030 |
|
T100 |
138 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3683990 |
1 |
|
|
T19 |
1155 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1912490 |
1 |
|
|
T19 |
871 |
|
T22 |
4 |
|
T29 |
17693 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
843086 |
1 |
|
|
T19 |
267 |
|
T29 |
8000 |
|
T100 |
274 |
| auto[1] |
auto[0] |
auto[1] |
119104 |
1 |
|
|
T19 |
12 |
|
T29 |
1035 |
|
T100 |
67 |
| auto[1] |
auto[1] |
auto[0] |
832375 |
1 |
|
|
T19 |
568 |
|
T22 |
4 |
|
T29 |
7663 |
| auto[1] |
auto[1] |
auto[1] |
117925 |
1 |
|
|
T19 |
24 |
|
T29 |
995 |
|
T100 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3683038 |
1 |
|
|
T19 |
1177 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1913442 |
1 |
|
|
T19 |
849 |
|
T22 |
9 |
|
T29 |
18032 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5360627 |
1 |
|
|
T19 |
1993 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
235853 |
1 |
|
|
T19 |
33 |
|
T29 |
2005 |
|
T100 |
112 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3689264 |
1 |
|
|
T19 |
1019 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1907216 |
1 |
|
|
T19 |
1007 |
|
T22 |
4 |
|
T29 |
17215 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
836849 |
1 |
|
|
T19 |
572 |
|
T29 |
7515 |
|
T100 |
287 |
| auto[1] |
auto[0] |
auto[1] |
117860 |
1 |
|
|
T19 |
20 |
|
T29 |
1013 |
|
T100 |
59 |
| auto[1] |
auto[1] |
auto[0] |
834514 |
1 |
|
|
T19 |
402 |
|
T22 |
4 |
|
T29 |
7695 |
| auto[1] |
auto[1] |
auto[1] |
117993 |
1 |
|
|
T19 |
13 |
|
T29 |
992 |
|
T100 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3677437 |
1 |
|
|
T19 |
1048 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1919043 |
1 |
|
|
T19 |
978 |
|
T22 |
5 |
|
T29 |
16428 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5359107 |
1 |
|
|
T19 |
1996 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
237373 |
1 |
|
|
T19 |
30 |
|
T29 |
1959 |
|
T100 |
164 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3680887 |
1 |
|
|
T19 |
1158 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1915593 |
1 |
|
|
T19 |
868 |
|
T22 |
4 |
|
T29 |
17491 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
842211 |
1 |
|
|
T19 |
403 |
|
T29 |
8220 |
|
T100 |
424 |
| auto[1] |
auto[0] |
auto[1] |
119394 |
1 |
|
|
T19 |
15 |
|
T29 |
1032 |
|
T100 |
91 |
| auto[1] |
auto[1] |
auto[0] |
836009 |
1 |
|
|
T19 |
435 |
|
T22 |
4 |
|
T29 |
7312 |
| auto[1] |
auto[1] |
auto[1] |
117979 |
1 |
|
|
T19 |
15 |
|
T29 |
927 |
|
T100 |
73 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3700236 |
1 |
|
|
T19 |
1222 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1896244 |
1 |
|
|
T19 |
804 |
|
T22 |
9 |
|
T29 |
17119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5359653 |
1 |
|
|
T19 |
1997 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
236827 |
1 |
|
|
T19 |
29 |
|
T29 |
1936 |
|
T100 |
173 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3678150 |
1 |
|
|
T19 |
1034 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1918330 |
1 |
|
|
T19 |
992 |
|
T22 |
4 |
|
T29 |
17328 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
847637 |
1 |
|
|
T19 |
595 |
|
T29 |
7683 |
|
T100 |
472 |
| auto[1] |
auto[0] |
auto[1] |
120072 |
1 |
|
|
T19 |
22 |
|
T29 |
1004 |
|
T100 |
113 |
| auto[1] |
auto[1] |
auto[0] |
833866 |
1 |
|
|
T19 |
368 |
|
T22 |
4 |
|
T29 |
7709 |
| auto[1] |
auto[1] |
auto[1] |
116755 |
1 |
|
|
T19 |
7 |
|
T29 |
932 |
|
T100 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |