Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3668966 |
1 |
|
|
T19 |
1090 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1927514 |
1 |
|
|
T19 |
936 |
|
T22 |
9 |
|
T29 |
18574 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5361319 |
1 |
|
|
T19 |
1982 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
235161 |
1 |
|
|
T19 |
44 |
|
T29 |
1964 |
|
T100 |
112 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3696019 |
1 |
|
|
T19 |
998 |
|
T20 |
1 |
|
T21 |
155 |
| auto[1] |
1900461 |
1 |
|
|
T19 |
1028 |
|
T29 |
17312 |
|
T100 |
569 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
831139 |
1 |
|
|
T19 |
472 |
|
T29 |
7108 |
|
T100 |
172 |
| auto[1] |
auto[0] |
auto[1] |
117046 |
1 |
|
|
T19 |
21 |
|
T29 |
892 |
|
T100 |
40 |
| auto[1] |
auto[1] |
auto[0] |
834161 |
1 |
|
|
T19 |
512 |
|
T29 |
8240 |
|
T100 |
285 |
| auto[1] |
auto[1] |
auto[1] |
118115 |
1 |
|
|
T19 |
23 |
|
T29 |
1072 |
|
T100 |
72 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |