Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 940
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T95 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3007652568 Aug 15 06:05:33 PM PDT 24 Aug 15 06:05:34 PM PDT 24 228963578 ps
T760 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.4228415165 Aug 15 06:05:35 PM PDT 24 Aug 15 06:05:36 PM PDT 24 99638913 ps
T49 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3900268278 Aug 15 06:05:35 PM PDT 24 Aug 15 06:05:37 PM PDT 24 451846781 ps
T761 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1686657318 Aug 15 06:05:41 PM PDT 24 Aug 15 06:05:42 PM PDT 24 139765209 ps
T762 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2791123199 Aug 15 06:05:46 PM PDT 24 Aug 15 06:05:47 PM PDT 24 52886889 ps
T84 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3510981667 Aug 15 06:05:53 PM PDT 24 Aug 15 06:05:53 PM PDT 24 33636138 ps
T763 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.292571201 Aug 15 06:05:29 PM PDT 24 Aug 15 06:05:32 PM PDT 24 308430183 ps
T85 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4194273297 Aug 15 06:05:58 PM PDT 24 Aug 15 06:05:59 PM PDT 24 17430440 ps
T764 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3376291728 Aug 15 06:05:40 PM PDT 24 Aug 15 06:05:41 PM PDT 24 31706163 ps
T765 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1764951685 Aug 15 06:05:53 PM PDT 24 Aug 15 06:05:54 PM PDT 24 47766162 ps
T766 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2344123347 Aug 15 06:05:30 PM PDT 24 Aug 15 06:05:31 PM PDT 24 34411648 ps
T767 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3274235156 Aug 15 06:05:30 PM PDT 24 Aug 15 06:05:34 PM PDT 24 251732937 ps
T768 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2346977790 Aug 15 06:06:00 PM PDT 24 Aug 15 06:06:01 PM PDT 24 36246145 ps
T769 /workspace/coverage/cover_reg_top/15.gpio_intr_test.4112573400 Aug 15 06:05:53 PM PDT 24 Aug 15 06:05:54 PM PDT 24 16422055 ps
T770 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1975790771 Aug 15 06:05:31 PM PDT 24 Aug 15 06:05:32 PM PDT 24 14260642 ps
T771 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2855341926 Aug 15 06:05:39 PM PDT 24 Aug 15 06:05:40 PM PDT 24 74965298 ps
T772 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.665917735 Aug 15 06:05:48 PM PDT 24 Aug 15 06:05:49 PM PDT 24 71409227 ps
T773 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1752942140 Aug 15 06:05:30 PM PDT 24 Aug 15 06:05:31 PM PDT 24 11691150 ps
T774 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.656978138 Aug 15 06:05:35 PM PDT 24 Aug 15 06:05:36 PM PDT 24 20359486 ps
T775 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2702881768 Aug 15 06:06:01 PM PDT 24 Aug 15 06:06:03 PM PDT 24 538155511 ps
T776 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3122003810 Aug 15 06:05:47 PM PDT 24 Aug 15 06:05:48 PM PDT 24 11599226 ps
T777 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3819789772 Aug 15 06:05:39 PM PDT 24 Aug 15 06:05:40 PM PDT 24 13647580 ps
T778 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2695423993 Aug 15 06:05:43 PM PDT 24 Aug 15 06:05:45 PM PDT 24 71751767 ps
T779 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3663974384 Aug 15 06:05:34 PM PDT 24 Aug 15 06:05:35 PM PDT 24 62883900 ps
T780 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.343216632 Aug 15 06:05:51 PM PDT 24 Aug 15 06:05:52 PM PDT 24 75406396 ps
T781 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3878682967 Aug 15 06:05:58 PM PDT 24 Aug 15 06:05:59 PM PDT 24 53783246 ps
T782 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1959650294 Aug 15 06:05:53 PM PDT 24 Aug 15 06:05:54 PM PDT 24 14204606 ps
T783 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.636268353 Aug 15 06:05:43 PM PDT 24 Aug 15 06:05:44 PM PDT 24 126019753 ps
T784 /workspace/coverage/cover_reg_top/32.gpio_intr_test.314981649 Aug 15 06:05:57 PM PDT 24 Aug 15 06:05:58 PM PDT 24 15187832 ps
T785 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3166587948 Aug 15 06:05:59 PM PDT 24 Aug 15 06:06:00 PM PDT 24 31028723 ps
T786 /workspace/coverage/cover_reg_top/47.gpio_intr_test.4166499811 Aug 15 06:05:52 PM PDT 24 Aug 15 06:05:52 PM PDT 24 13195042 ps
T787 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.959892440 Aug 15 06:05:51 PM PDT 24 Aug 15 06:05:51 PM PDT 24 14732577 ps
T788 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1593203336 Aug 15 06:05:47 PM PDT 24 Aug 15 06:05:48 PM PDT 24 365660352 ps
T789 /workspace/coverage/cover_reg_top/30.gpio_intr_test.631240319 Aug 15 06:06:06 PM PDT 24 Aug 15 06:06:07 PM PDT 24 25750189 ps
T790 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.135344928 Aug 15 06:05:21 PM PDT 24 Aug 15 06:05:22 PM PDT 24 22346586 ps
T791 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3785932606 Aug 15 06:05:49 PM PDT 24 Aug 15 06:05:50 PM PDT 24 16094099 ps
T792 /workspace/coverage/cover_reg_top/5.gpio_intr_test.341609140 Aug 15 06:05:34 PM PDT 24 Aug 15 06:05:35 PM PDT 24 14968191 ps
T793 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3903857147 Aug 15 06:05:32 PM PDT 24 Aug 15 06:05:34 PM PDT 24 117496303 ps
T794 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.925411219 Aug 15 06:05:30 PM PDT 24 Aug 15 06:05:32 PM PDT 24 87261273 ps
T795 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1238087349 Aug 15 06:06:04 PM PDT 24 Aug 15 06:06:05 PM PDT 24 20423330 ps
T796 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2893009148 Aug 15 06:05:58 PM PDT 24 Aug 15 06:06:03 PM PDT 24 38930983 ps
T797 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2441279921 Aug 15 06:05:56 PM PDT 24 Aug 15 06:05:57 PM PDT 24 40787863 ps
T798 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3803387942 Aug 15 06:05:37 PM PDT 24 Aug 15 06:05:38 PM PDT 24 136990048 ps
T799 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.186902184 Aug 15 06:05:47 PM PDT 24 Aug 15 06:05:48 PM PDT 24 29302781 ps
T800 /workspace/coverage/cover_reg_top/0.gpio_intr_test.216714685 Aug 15 06:05:26 PM PDT 24 Aug 15 06:05:27 PM PDT 24 11965519 ps
T801 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3655600365 Aug 15 06:05:37 PM PDT 24 Aug 15 06:05:37 PM PDT 24 56208413 ps
T802 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1037757258 Aug 15 06:05:51 PM PDT 24 Aug 15 06:05:52 PM PDT 24 13917602 ps
T803 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3439179971 Aug 15 06:05:50 PM PDT 24 Aug 15 06:05:50 PM PDT 24 19745729 ps
T90 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2060757498 Aug 15 06:05:32 PM PDT 24 Aug 15 06:05:35 PM PDT 24 409912864 ps
T804 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1421127428 Aug 15 06:05:34 PM PDT 24 Aug 15 06:05:35 PM PDT 24 19258803 ps
T805 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3330081029 Aug 15 06:05:53 PM PDT 24 Aug 15 06:05:55 PM PDT 24 286609611 ps
T806 /workspace/coverage/cover_reg_top/49.gpio_intr_test.1706871241 Aug 15 06:05:54 PM PDT 24 Aug 15 06:05:55 PM PDT 24 17041245 ps
T807 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.239568291 Aug 15 06:05:35 PM PDT 24 Aug 15 06:05:37 PM PDT 24 431659337 ps
T808 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.4260162949 Aug 15 06:05:45 PM PDT 24 Aug 15 06:05:45 PM PDT 24 14214786 ps
T809 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.820398982 Aug 15 06:05:52 PM PDT 24 Aug 15 06:05:53 PM PDT 24 24307300 ps
T810 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3335041464 Aug 15 06:05:30 PM PDT 24 Aug 15 06:05:31 PM PDT 24 31231494 ps
T811 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2378913739 Aug 15 06:05:37 PM PDT 24 Aug 15 06:05:38 PM PDT 24 105650648 ps
T812 /workspace/coverage/cover_reg_top/38.gpio_intr_test.593047327 Aug 15 06:06:15 PM PDT 24 Aug 15 06:06:16 PM PDT 24 40459469 ps
T86 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.566424498 Aug 15 06:05:57 PM PDT 24 Aug 15 06:05:58 PM PDT 24 106817606 ps
T813 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2281137818 Aug 15 06:05:41 PM PDT 24 Aug 15 06:05:43 PM PDT 24 121870377 ps
T814 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.914644598 Aug 15 06:05:44 PM PDT 24 Aug 15 06:05:47 PM PDT 24 129424529 ps
T815 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.826043386 Aug 15 06:06:01 PM PDT 24 Aug 15 06:06:02 PM PDT 24 498569120 ps
T816 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3767228455 Aug 15 06:05:59 PM PDT 24 Aug 15 06:06:01 PM PDT 24 225417170 ps
T817 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4117350460 Aug 15 06:05:32 PM PDT 24 Aug 15 06:05:33 PM PDT 24 41288792 ps
T818 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2392821613 Aug 15 06:05:34 PM PDT 24 Aug 15 06:05:35 PM PDT 24 38278294 ps
T819 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1571576358 Aug 15 06:05:51 PM PDT 24 Aug 15 06:05:51 PM PDT 24 13418839 ps
T820 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3096144516 Aug 15 06:05:39 PM PDT 24 Aug 15 06:05:40 PM PDT 24 145573815 ps
T821 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.345777008 Aug 15 06:05:47 PM PDT 24 Aug 15 06:05:49 PM PDT 24 68857361 ps
T822 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3008550827 Aug 15 06:05:36 PM PDT 24 Aug 15 06:05:37 PM PDT 24 30980791 ps
T87 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.688191918 Aug 15 06:05:29 PM PDT 24 Aug 15 06:05:30 PM PDT 24 21187361 ps
T823 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1038368299 Aug 15 06:05:53 PM PDT 24 Aug 15 06:05:58 PM PDT 24 34608818 ps
T824 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.524228471 Aug 15 06:05:33 PM PDT 24 Aug 15 06:05:33 PM PDT 24 25310698 ps
T825 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3350986918 Aug 15 06:05:55 PM PDT 24 Aug 15 06:05:56 PM PDT 24 24116413 ps
T826 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.307627181 Aug 15 06:05:33 PM PDT 24 Aug 15 06:05:34 PM PDT 24 383737621 ps
T827 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1516750414 Aug 15 06:05:42 PM PDT 24 Aug 15 06:05:43 PM PDT 24 29077081 ps
T88 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1892197556 Aug 15 06:05:45 PM PDT 24 Aug 15 06:05:46 PM PDT 24 118973255 ps
T89 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2046693542 Aug 15 06:05:45 PM PDT 24 Aug 15 06:05:46 PM PDT 24 27069029 ps
T828 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1285719599 Aug 15 06:05:35 PM PDT 24 Aug 15 06:05:36 PM PDT 24 19720746 ps
T829 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1302443842 Aug 15 06:05:54 PM PDT 24 Aug 15 06:05:55 PM PDT 24 15967340 ps
T830 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1743835194 Aug 15 06:05:30 PM PDT 24 Aug 15 06:05:31 PM PDT 24 312185464 ps
T831 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2829795694 Aug 15 06:05:52 PM PDT 24 Aug 15 06:05:53 PM PDT 24 23676750 ps
T832 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2262014684 Aug 15 06:05:43 PM PDT 24 Aug 15 06:05:44 PM PDT 24 22999848 ps
T833 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1992089145 Aug 15 06:05:34 PM PDT 24 Aug 15 06:05:35 PM PDT 24 41177841 ps
T834 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1804468399 Aug 15 06:05:33 PM PDT 24 Aug 15 06:05:34 PM PDT 24 28063428 ps
T835 /workspace/coverage/cover_reg_top/23.gpio_intr_test.373874004 Aug 15 06:05:42 PM PDT 24 Aug 15 06:05:43 PM PDT 24 11724327 ps
T836 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.660375943 Aug 15 06:05:51 PM PDT 24 Aug 15 06:05:53 PM PDT 24 140477899 ps
T837 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3028310022 Aug 15 06:05:54 PM PDT 24 Aug 15 06:05:55 PM PDT 24 75568758 ps
T838 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3018260630 Aug 15 06:05:39 PM PDT 24 Aug 15 06:05:40 PM PDT 24 52176969 ps
T839 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.973199044 Aug 15 06:05:28 PM PDT 24 Aug 15 06:05:30 PM PDT 24 144462129 ps
T840 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2535315891 Aug 15 06:05:31 PM PDT 24 Aug 15 06:05:33 PM PDT 24 47397785 ps
T841 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.32958469 Aug 15 05:25:01 PM PDT 24 Aug 15 05:25:03 PM PDT 24 43105908 ps
T842 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.33235215 Aug 15 05:25:00 PM PDT 24 Aug 15 05:25:02 PM PDT 24 145479895 ps
T843 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4066394298 Aug 15 05:24:53 PM PDT 24 Aug 15 05:24:55 PM PDT 24 95757259 ps
T844 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2767256752 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:52 PM PDT 24 209954790 ps
T845 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.750021926 Aug 15 05:25:05 PM PDT 24 Aug 15 05:25:06 PM PDT 24 126225853 ps
T846 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1067042912 Aug 15 05:25:06 PM PDT 24 Aug 15 05:25:07 PM PDT 24 153225834 ps
T847 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3418562599 Aug 15 05:24:51 PM PDT 24 Aug 15 05:24:53 PM PDT 24 161115556 ps
T848 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4253591203 Aug 15 05:25:05 PM PDT 24 Aug 15 05:25:06 PM PDT 24 62144607 ps
T849 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3143334907 Aug 15 05:24:54 PM PDT 24 Aug 15 05:24:55 PM PDT 24 84382740 ps
T850 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2467846787 Aug 15 05:25:01 PM PDT 24 Aug 15 05:25:02 PM PDT 24 55190428 ps
T851 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.866078084 Aug 15 05:25:06 PM PDT 24 Aug 15 05:25:08 PM PDT 24 89285924 ps
T852 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1714747337 Aug 15 05:25:06 PM PDT 24 Aug 15 05:25:07 PM PDT 24 134726234 ps
T853 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3387731081 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:51 PM PDT 24 162994499 ps
T854 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1430599245 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:51 PM PDT 24 166100256 ps
T855 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2777105719 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:50 PM PDT 24 300704302 ps
T856 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.28557931 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:51 PM PDT 24 63721660 ps
T857 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3266375631 Aug 15 05:25:05 PM PDT 24 Aug 15 05:25:07 PM PDT 24 161734164 ps
T858 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2219068386 Aug 15 05:24:58 PM PDT 24 Aug 15 05:24:59 PM PDT 24 157697225 ps
T859 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.684148884 Aug 15 05:25:01 PM PDT 24 Aug 15 05:25:02 PM PDT 24 356765089 ps
T860 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.563995448 Aug 15 05:25:04 PM PDT 24 Aug 15 05:25:05 PM PDT 24 40577138 ps
T861 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.773736660 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:50 PM PDT 24 19135132 ps
T862 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4293467854 Aug 15 05:25:02 PM PDT 24 Aug 15 05:25:03 PM PDT 24 188447189 ps
T863 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3471735980 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:50 PM PDT 24 36087403 ps
T864 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.796467069 Aug 15 05:24:58 PM PDT 24 Aug 15 05:24:59 PM PDT 24 27755621 ps
T865 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3311657336 Aug 15 05:25:01 PM PDT 24 Aug 15 05:25:03 PM PDT 24 50525274 ps
T866 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.910400807 Aug 15 05:24:56 PM PDT 24 Aug 15 05:24:58 PM PDT 24 303112540 ps
T867 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1435399098 Aug 15 05:24:54 PM PDT 24 Aug 15 05:24:55 PM PDT 24 44222965 ps
T868 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3338865058 Aug 15 05:25:04 PM PDT 24 Aug 15 05:25:05 PM PDT 24 46333464 ps
T869 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.86113057 Aug 15 05:25:05 PM PDT 24 Aug 15 05:25:06 PM PDT 24 59095951 ps
T870 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.655839179 Aug 15 05:25:02 PM PDT 24 Aug 15 05:25:04 PM PDT 24 98575847 ps
T871 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3494384707 Aug 15 05:24:55 PM PDT 24 Aug 15 05:24:56 PM PDT 24 189386327 ps
T872 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3751698289 Aug 15 05:25:07 PM PDT 24 Aug 15 05:25:08 PM PDT 24 47451599 ps
T873 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.49190903 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:50 PM PDT 24 30993971 ps
T874 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2308416908 Aug 15 05:25:03 PM PDT 24 Aug 15 05:25:05 PM PDT 24 117796836 ps
T875 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3771542114 Aug 15 05:24:48 PM PDT 24 Aug 15 05:24:49 PM PDT 24 275522447 ps
T876 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1603083656 Aug 15 05:25:07 PM PDT 24 Aug 15 05:25:08 PM PDT 24 119662140 ps
T877 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1600871000 Aug 15 05:24:48 PM PDT 24 Aug 15 05:24:50 PM PDT 24 50793444 ps
T878 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2596854259 Aug 15 05:24:52 PM PDT 24 Aug 15 05:24:54 PM PDT 24 280452672 ps
T879 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1390685339 Aug 15 05:25:02 PM PDT 24 Aug 15 05:25:03 PM PDT 24 75791063 ps
T880 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3253470582 Aug 15 05:25:05 PM PDT 24 Aug 15 05:25:06 PM PDT 24 37704917 ps
T881 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3679151722 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:51 PM PDT 24 89249667 ps
T882 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3563481212 Aug 15 05:24:51 PM PDT 24 Aug 15 05:24:52 PM PDT 24 159058632 ps
T883 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4002673976 Aug 15 05:25:02 PM PDT 24 Aug 15 05:25:04 PM PDT 24 238150855 ps
T884 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2124431008 Aug 15 05:25:19 PM PDT 24 Aug 15 05:25:21 PM PDT 24 73569171 ps
T885 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1847194453 Aug 15 05:25:05 PM PDT 24 Aug 15 05:25:06 PM PDT 24 211978182 ps
T886 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3537164158 Aug 15 05:25:03 PM PDT 24 Aug 15 05:25:04 PM PDT 24 1296992798 ps
T887 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1799549800 Aug 15 05:25:02 PM PDT 24 Aug 15 05:25:03 PM PDT 24 180939710 ps
T888 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1617584374 Aug 15 05:24:57 PM PDT 24 Aug 15 05:24:58 PM PDT 24 49446771 ps
T889 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.853753144 Aug 15 05:25:03 PM PDT 24 Aug 15 05:25:04 PM PDT 24 41830789 ps
T890 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2406071438 Aug 15 05:25:01 PM PDT 24 Aug 15 05:25:03 PM PDT 24 132569576 ps
T891 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2412299094 Aug 15 05:25:05 PM PDT 24 Aug 15 05:25:06 PM PDT 24 357250281 ps
T892 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2682085483 Aug 15 05:25:00 PM PDT 24 Aug 15 05:25:01 PM PDT 24 162032229 ps
T893 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1989542777 Aug 15 05:24:56 PM PDT 24 Aug 15 05:24:58 PM PDT 24 141352744 ps
T894 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3181452713 Aug 15 05:24:51 PM PDT 24 Aug 15 05:24:52 PM PDT 24 39634050 ps
T895 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.461193612 Aug 15 05:25:05 PM PDT 24 Aug 15 05:25:07 PM PDT 24 230255203 ps
T896 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1225844560 Aug 15 05:25:03 PM PDT 24 Aug 15 05:25:04 PM PDT 24 90162374 ps
T897 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1556900957 Aug 15 05:24:58 PM PDT 24 Aug 15 05:25:00 PM PDT 24 65791418 ps
T898 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2095050349 Aug 15 05:24:58 PM PDT 24 Aug 15 05:24:59 PM PDT 24 65403817 ps
T899 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.595752339 Aug 15 05:25:05 PM PDT 24 Aug 15 05:25:06 PM PDT 24 48259222 ps
T900 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2600071237 Aug 15 05:25:00 PM PDT 24 Aug 15 05:25:01 PM PDT 24 488334402 ps
T901 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1644422382 Aug 15 05:25:02 PM PDT 24 Aug 15 05:25:04 PM PDT 24 70795380 ps
T902 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1150027990 Aug 15 05:24:53 PM PDT 24 Aug 15 05:24:55 PM PDT 24 293098055 ps
T903 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3941250835 Aug 15 05:24:55 PM PDT 24 Aug 15 05:24:56 PM PDT 24 66725190 ps
T904 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.291830186 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:51 PM PDT 24 622656609 ps
T905 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2113596502 Aug 15 05:25:09 PM PDT 24 Aug 15 05:25:10 PM PDT 24 89290955 ps
T906 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4097845955 Aug 15 05:25:03 PM PDT 24 Aug 15 05:25:05 PM PDT 24 285480615 ps
T907 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2808701490 Aug 15 05:24:52 PM PDT 24 Aug 15 05:24:53 PM PDT 24 48705098 ps
T908 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2647948414 Aug 15 05:25:01 PM PDT 24 Aug 15 05:25:02 PM PDT 24 382638588 ps
T909 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3601514593 Aug 15 05:25:01 PM PDT 24 Aug 15 05:25:03 PM PDT 24 525356948 ps
T910 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.4072803778 Aug 15 05:24:57 PM PDT 24 Aug 15 05:24:58 PM PDT 24 28660684 ps
T911 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3036223446 Aug 15 05:24:55 PM PDT 24 Aug 15 05:24:56 PM PDT 24 42393970 ps
T912 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3912662829 Aug 15 05:24:51 PM PDT 24 Aug 15 05:24:53 PM PDT 24 889707107 ps
T913 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3604949857 Aug 15 05:24:48 PM PDT 24 Aug 15 05:24:50 PM PDT 24 141039618 ps
T914 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2329768812 Aug 15 05:24:49 PM PDT 24 Aug 15 05:24:50 PM PDT 24 134841244 ps
T915 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.7202334 Aug 15 05:24:51 PM PDT 24 Aug 15 05:24:53 PM PDT 24 43333847 ps
T916 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.542534622 Aug 15 05:25:02 PM PDT 24 Aug 15 05:25:03 PM PDT 24 44915478 ps
T917 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.575633479 Aug 15 05:24:58 PM PDT 24 Aug 15 05:24:59 PM PDT 24 70204309 ps
T918 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.523581943 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:52 PM PDT 24 389675569 ps
T919 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3376678847 Aug 15 05:25:01 PM PDT 24 Aug 15 05:25:02 PM PDT 24 139313391 ps
T920 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2887100134 Aug 15 05:25:01 PM PDT 24 Aug 15 05:25:03 PM PDT 24 75784086 ps
T921 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2923197882 Aug 15 05:25:01 PM PDT 24 Aug 15 05:25:03 PM PDT 24 541154153 ps
T922 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3389154875 Aug 15 05:25:03 PM PDT 24 Aug 15 05:25:04 PM PDT 24 126700099 ps
T923 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.769000176 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:51 PM PDT 24 148246493 ps
T924 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1039634672 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:51 PM PDT 24 334585243 ps
T925 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2750235543 Aug 15 05:25:00 PM PDT 24 Aug 15 05:25:01 PM PDT 24 131770294 ps
T926 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.912677717 Aug 15 05:24:58 PM PDT 24 Aug 15 05:24:59 PM PDT 24 202367593 ps
T927 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1418952622 Aug 15 05:25:08 PM PDT 24 Aug 15 05:25:09 PM PDT 24 203242319 ps
T928 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.883963775 Aug 15 05:24:54 PM PDT 24 Aug 15 05:24:55 PM PDT 24 204766433 ps
T929 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3050540308 Aug 15 05:25:05 PM PDT 24 Aug 15 05:25:07 PM PDT 24 49279661 ps
T930 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3486102013 Aug 15 05:25:05 PM PDT 24 Aug 15 05:25:06 PM PDT 24 19602537 ps
T931 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2440972709 Aug 15 05:25:03 PM PDT 24 Aug 15 05:25:04 PM PDT 24 43554540 ps
T932 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2272042883 Aug 15 05:25:02 PM PDT 24 Aug 15 05:25:04 PM PDT 24 1478681628 ps
T933 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2031283916 Aug 15 05:24:55 PM PDT 24 Aug 15 05:24:56 PM PDT 24 40523477 ps
T934 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.559721923 Aug 15 05:24:54 PM PDT 24 Aug 15 05:24:55 PM PDT 24 113909732 ps
T935 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2454434638 Aug 15 05:24:54 PM PDT 24 Aug 15 05:24:55 PM PDT 24 76806947 ps
T936 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.732764534 Aug 15 05:25:02 PM PDT 24 Aug 15 05:25:04 PM PDT 24 181640842 ps
T937 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1209339482 Aug 15 05:24:56 PM PDT 24 Aug 15 05:24:57 PM PDT 24 115901884 ps
T938 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3617926109 Aug 15 05:24:57 PM PDT 24 Aug 15 05:24:59 PM PDT 24 851439399 ps
T939 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.886006588 Aug 15 05:24:58 PM PDT 24 Aug 15 05:24:59 PM PDT 24 930997905 ps
T940 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1802708096 Aug 15 05:24:50 PM PDT 24 Aug 15 05:24:52 PM PDT 24 263896920 ps

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3506759101
Short name T19
Test name
Test status
Simulation time 99433216 ps
CPU time 4.25 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:56 PM PDT 24
Peak memory 198104 kb
Host smart-b779bb3d-5cc6-46b7-8e90-30e059eeb3e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506759101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3506759101
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.662875382
Short name T39
Test name
Test status
Simulation time 88456600 ps
CPU time 3.83 seconds
Started Aug 15 05:26:25 PM PDT 24
Finished Aug 15 05:26:29 PM PDT 24
Peak memory 198132 kb
Host smart-a23b202b-c73f-4af7-9656-5106ae3c0386
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662875382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.662875382
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3432601284
Short name T33
Test name
Test status
Simulation time 25396947823 ps
CPU time 176.72 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:28:54 PM PDT 24
Peak memory 198540 kb
Host smart-4115e1ed-19c3-4c74-b2ab-d8942bacaefc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3432601284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3432601284
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1456844449
Short name T41
Test name
Test status
Simulation time 617696429 ps
CPU time 0.98 seconds
Started Aug 15 05:25:44 PM PDT 24
Finished Aug 15 05:25:45 PM PDT 24
Peak memory 214968 kb
Host smart-c8b390fd-451b-478a-93e2-6d43081474d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456844449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1456844449
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3198291922
Short name T76
Test name
Test status
Simulation time 28933624 ps
CPU time 0.77 seconds
Started Aug 15 06:05:29 PM PDT 24
Finished Aug 15 06:05:30 PM PDT 24
Peak memory 196220 kb
Host smart-3f26afa7-557c-447b-ab55-0b9cfcdcff36
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198291922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3198291922
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/19.gpio_stress_all.871427377
Short name T1
Test name
Test status
Simulation time 18190386800 ps
CPU time 43.02 seconds
Started Aug 15 05:26:00 PM PDT 24
Finished Aug 15 05:26:44 PM PDT 24
Peak memory 198356 kb
Host smart-75287ac9-0a9d-4a14-b9b5-6d7edfb0f724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871427377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.871427377
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2625967571
Short name T51
Test name
Test status
Simulation time 99015149 ps
CPU time 1.37 seconds
Started Aug 15 06:05:25 PM PDT 24
Finished Aug 15 06:05:26 PM PDT 24
Peak memory 198516 kb
Host smart-b939139a-8511-4b81-aeed-948e317a6b1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625967571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2625967571
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/21.gpio_alert_test.4153542098
Short name T44
Test name
Test status
Simulation time 11252952 ps
CPU time 0.56 seconds
Started Aug 15 05:26:30 PM PDT 24
Finished Aug 15 05:26:31 PM PDT 24
Peak memory 194764 kb
Host smart-36416ec1-004b-4f40-a015-a41482924b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153542098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.4153542098
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3259997092
Short name T94
Test name
Test status
Simulation time 19912243 ps
CPU time 0.82 seconds
Started Aug 15 06:05:28 PM PDT 24
Finished Aug 15 06:05:34 PM PDT 24
Peak memory 197172 kb
Host smart-14166c6b-8475-4462-b935-2d73571a9b98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259997092 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3259997092
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3247061596
Short name T46
Test name
Test status
Simulation time 361902314 ps
CPU time 0.92 seconds
Started Aug 15 06:05:24 PM PDT 24
Finished Aug 15 06:05:25 PM PDT 24
Peak memory 197420 kb
Host smart-ae21816f-31d7-48c9-b9a2-e7b50ec04e7c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247061596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3247061596
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1825223689
Short name T82
Test name
Test status
Simulation time 127237480 ps
CPU time 1.4 seconds
Started Aug 15 06:05:29 PM PDT 24
Finished Aug 15 06:05:30 PM PDT 24
Peak memory 198484 kb
Host smart-29d123e5-c7e2-4cb3-853b-c263b2787420
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825223689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1825223689
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2344123347
Short name T766
Test name
Test status
Simulation time 34411648 ps
CPU time 0.69 seconds
Started Aug 15 06:05:30 PM PDT 24
Finished Aug 15 06:05:31 PM PDT 24
Peak memory 196044 kb
Host smart-737ae3aa-82d1-4657-a4b7-6295c791d1c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344123347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2344123347
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2046705603
Short name T742
Test name
Test status
Simulation time 29618243 ps
CPU time 1.4 seconds
Started Aug 15 06:05:19 PM PDT 24
Finished Aug 15 06:05:21 PM PDT 24
Peak memory 198624 kb
Host smart-0eae3d00-4d1f-45b9-970c-04c7f8f847a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046705603 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2046705603
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3695480262
Short name T730
Test name
Test status
Simulation time 23255213 ps
CPU time 0.59 seconds
Started Aug 15 06:05:38 PM PDT 24
Finished Aug 15 06:05:39 PM PDT 24
Peak memory 193756 kb
Host smart-75583d0b-1774-4ae8-a75b-6ff8e0df467f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695480262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3695480262
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.216714685
Short name T800
Test name
Test status
Simulation time 11965519 ps
CPU time 0.57 seconds
Started Aug 15 06:05:26 PM PDT 24
Finished Aug 15 06:05:27 PM PDT 24
Peak memory 194852 kb
Host smart-e23a4c1c-3ef4-4dc9-8a33-46c1cbe654e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216714685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.216714685
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2149687424
Short name T721
Test name
Test status
Simulation time 607127653 ps
CPU time 2.95 seconds
Started Aug 15 06:05:33 PM PDT 24
Finished Aug 15 06:05:36 PM PDT 24
Peak memory 198532 kb
Host smart-f320d198-0965-45b9-9a81-8da902df515c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149687424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2149687424
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.135344928
Short name T790
Test name
Test status
Simulation time 22346586 ps
CPU time 0.64 seconds
Started Aug 15 06:05:21 PM PDT 24
Finished Aug 15 06:05:22 PM PDT 24
Peak memory 195168 kb
Host smart-2e41b403-5eb8-4b54-a3e1-c64a5b16d99d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135344928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.135344928
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3274235156
Short name T767
Test name
Test status
Simulation time 251732937 ps
CPU time 3.19 seconds
Started Aug 15 06:05:30 PM PDT 24
Finished Aug 15 06:05:34 PM PDT 24
Peak memory 197672 kb
Host smart-e94610c4-fc2b-4c15-b14d-3bc9a21ff8ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274235156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3274235156
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.688191918
Short name T87
Test name
Test status
Simulation time 21187361 ps
CPU time 0.58 seconds
Started Aug 15 06:05:29 PM PDT 24
Finished Aug 15 06:05:30 PM PDT 24
Peak memory 194892 kb
Host smart-9c81a709-4c02-42f3-9054-10a64e3e0667
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688191918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.688191918
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.925411219
Short name T794
Test name
Test status
Simulation time 87261273 ps
CPU time 1.14 seconds
Started Aug 15 06:05:30 PM PDT 24
Finished Aug 15 06:05:32 PM PDT 24
Peak memory 198608 kb
Host smart-d34e44e7-efc2-40d6-97b7-9593544a8987
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925411219 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.925411219
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.524228471
Short name T824
Test name
Test status
Simulation time 25310698 ps
CPU time 0.59 seconds
Started Aug 15 06:05:33 PM PDT 24
Finished Aug 15 06:05:33 PM PDT 24
Peak memory 193708 kb
Host smart-c55cf498-57ae-4d8d-8cc8-744d85563862
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524228471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.524228471
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1496883831
Short name T749
Test name
Test status
Simulation time 13590615 ps
CPU time 0.63 seconds
Started Aug 15 06:05:29 PM PDT 24
Finished Aug 15 06:05:34 PM PDT 24
Peak memory 194168 kb
Host smart-df8d9f50-ce97-4ff8-afab-3d80572ca798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496883831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1496883831
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1421127428
Short name T804
Test name
Test status
Simulation time 19258803 ps
CPU time 0.75 seconds
Started Aug 15 06:05:34 PM PDT 24
Finished Aug 15 06:05:35 PM PDT 24
Peak memory 195052 kb
Host smart-141dbeb9-c3ae-4110-b03b-6e9f4f18f55e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421127428 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1421127428
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.973199044
Short name T839
Test name
Test status
Simulation time 144462129 ps
CPU time 1.96 seconds
Started Aug 15 06:05:28 PM PDT 24
Finished Aug 15 06:05:30 PM PDT 24
Peak memory 198512 kb
Host smart-699741ba-c1b3-4a10-b0ad-b186a7a45cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973199044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.973199044
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3246326830
Short name T737
Test name
Test status
Simulation time 106780323 ps
CPU time 0.79 seconds
Started Aug 15 06:05:36 PM PDT 24
Finished Aug 15 06:05:37 PM PDT 24
Peak memory 198392 kb
Host smart-e07bdfca-a8a4-47b8-8ea7-23a6722bb7a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246326830 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3246326830
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.4260162949
Short name T808
Test name
Test status
Simulation time 14214786 ps
CPU time 0.59 seconds
Started Aug 15 06:05:45 PM PDT 24
Finished Aug 15 06:05:45 PM PDT 24
Peak memory 194472 kb
Host smart-d4767d03-ecd7-4bb0-98eb-2d025ad7f920
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260162949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.4260162949
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1959650294
Short name T782
Test name
Test status
Simulation time 14204606 ps
CPU time 0.58 seconds
Started Aug 15 06:05:53 PM PDT 24
Finished Aug 15 06:05:54 PM PDT 24
Peak memory 194172 kb
Host smart-16ee567d-a475-44b5-97e1-e2dc618e93fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959650294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1959650294
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3007652568
Short name T95
Test name
Test status
Simulation time 228963578 ps
CPU time 0.82 seconds
Started Aug 15 06:05:33 PM PDT 24
Finished Aug 15 06:05:34 PM PDT 24
Peak memory 196620 kb
Host smart-ba18db85-f466-4d80-9cc6-f4e37e11d3eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007652568 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3007652568
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3204006640
Short name T744
Test name
Test status
Simulation time 54292102 ps
CPU time 2.56 seconds
Started Aug 15 06:05:42 PM PDT 24
Finished Aug 15 06:05:44 PM PDT 24
Peak memory 198604 kb
Host smart-e257cf7c-fae9-4e15-ab3c-e7b27263ce66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204006640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3204006640
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.239568291
Short name T807
Test name
Test status
Simulation time 431659337 ps
CPU time 1.4 seconds
Started Aug 15 06:05:35 PM PDT 24
Finished Aug 15 06:05:37 PM PDT 24
Peak memory 198524 kb
Host smart-4cea843c-2f8e-4d4d-b8ea-7d4233a3020f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239568291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.239568291
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2796614689
Short name T720
Test name
Test status
Simulation time 16969041 ps
CPU time 0.67 seconds
Started Aug 15 06:05:43 PM PDT 24
Finished Aug 15 06:05:44 PM PDT 24
Peak memory 196932 kb
Host smart-dfd7993c-38a1-4271-89de-3a20e446eb34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796614689 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2796614689
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1752942140
Short name T773
Test name
Test status
Simulation time 11691150 ps
CPU time 0.61 seconds
Started Aug 15 06:05:30 PM PDT 24
Finished Aug 15 06:05:31 PM PDT 24
Peak memory 196012 kb
Host smart-228e3947-de83-4749-b185-e223aaa282ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752942140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1752942140
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1201861149
Short name T743
Test name
Test status
Simulation time 23523934 ps
CPU time 0.62 seconds
Started Aug 15 06:05:46 PM PDT 24
Finished Aug 15 06:05:46 PM PDT 24
Peak memory 194296 kb
Host smart-6d90ac67-ca62-4a6b-ac01-9ea7fab197ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201861149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1201861149
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1992089145
Short name T833
Test name
Test status
Simulation time 41177841 ps
CPU time 0.74 seconds
Started Aug 15 06:05:34 PM PDT 24
Finished Aug 15 06:05:35 PM PDT 24
Peak memory 196424 kb
Host smart-f22ea70a-7e82-40ab-b6ba-87398d96dd28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992089145 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1992089145
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.660375943
Short name T836
Test name
Test status
Simulation time 140477899 ps
CPU time 2.14 seconds
Started Aug 15 06:05:51 PM PDT 24
Finished Aug 15 06:05:53 PM PDT 24
Peak memory 198644 kb
Host smart-69fe70f0-c481-451e-bfe6-9c93ec0c7e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660375943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.660375943
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.699208976
Short name T40
Test name
Test status
Simulation time 261542438 ps
CPU time 1.44 seconds
Started Aug 15 06:05:44 PM PDT 24
Finished Aug 15 06:05:46 PM PDT 24
Peak memory 198424 kb
Host smart-c50b7714-67f1-4708-8dec-c1c4b7097984
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699208976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.699208976
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.820398982
Short name T809
Test name
Test status
Simulation time 24307300 ps
CPU time 0.79 seconds
Started Aug 15 06:05:52 PM PDT 24
Finished Aug 15 06:05:53 PM PDT 24
Peak memory 198384 kb
Host smart-7ab1b4ba-6d29-4988-81da-c309a001e2b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820398982 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.820398982
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2682450274
Short name T80
Test name
Test status
Simulation time 15310993 ps
CPU time 0.62 seconds
Started Aug 15 06:05:52 PM PDT 24
Finished Aug 15 06:05:53 PM PDT 24
Peak memory 195208 kb
Host smart-eaa4e597-c156-4ba0-87b5-64e66f648627
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682450274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2682450274
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1302443842
Short name T829
Test name
Test status
Simulation time 15967340 ps
CPU time 0.59 seconds
Started Aug 15 06:05:54 PM PDT 24
Finished Aug 15 06:05:55 PM PDT 24
Peak memory 194164 kb
Host smart-9ab32a0d-c56c-49a9-b9b6-49b555d4bf00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302443842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1302443842
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2291566073
Short name T92
Test name
Test status
Simulation time 40469886 ps
CPU time 0.88 seconds
Started Aug 15 06:05:48 PM PDT 24
Finished Aug 15 06:05:49 PM PDT 24
Peak memory 196676 kb
Host smart-3de7eed6-429e-4de8-a054-d5466b052b8a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291566073 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2291566073
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.914644598
Short name T814
Test name
Test status
Simulation time 129424529 ps
CPU time 2.38 seconds
Started Aug 15 06:05:44 PM PDT 24
Finished Aug 15 06:05:47 PM PDT 24
Peak memory 198512 kb
Host smart-72df2682-ba4c-435d-a0f6-3d83459fc5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914644598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.914644598
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.827961053
Short name T35
Test name
Test status
Simulation time 127922785 ps
CPU time 1.07 seconds
Started Aug 15 06:05:47 PM PDT 24
Finished Aug 15 06:05:48 PM PDT 24
Peak memory 198116 kb
Host smart-847f0d5b-f0b8-45d4-bf21-ae7dbac4f368
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827961053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.827961053
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1564281637
Short name T723
Test name
Test status
Simulation time 48684284 ps
CPU time 0.77 seconds
Started Aug 15 06:05:45 PM PDT 24
Finished Aug 15 06:05:46 PM PDT 24
Peak memory 198376 kb
Host smart-131c56c9-2663-4f79-a669-788ef21002e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564281637 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1564281637
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3510981667
Short name T84
Test name
Test status
Simulation time 33636138 ps
CPU time 0.56 seconds
Started Aug 15 06:05:53 PM PDT 24
Finished Aug 15 06:05:53 PM PDT 24
Peak memory 193784 kb
Host smart-baae9f98-a1d0-47d4-8220-0b069ca536ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510981667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3510981667
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3439179971
Short name T803
Test name
Test status
Simulation time 19745729 ps
CPU time 0.62 seconds
Started Aug 15 06:05:50 PM PDT 24
Finished Aug 15 06:05:50 PM PDT 24
Peak memory 194244 kb
Host smart-91dade54-9653-4ec4-93e5-ef1f9e2fe483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439179971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3439179971
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1018201395
Short name T93
Test name
Test status
Simulation time 42702595 ps
CPU time 0.62 seconds
Started Aug 15 06:05:34 PM PDT 24
Finished Aug 15 06:05:35 PM PDT 24
Peak memory 195180 kb
Host smart-5032da18-f864-4350-a81e-db449502cfa9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018201395 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1018201395
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.339190424
Short name T740
Test name
Test status
Simulation time 134840631 ps
CPU time 2.29 seconds
Started Aug 15 06:05:40 PM PDT 24
Finished Aug 15 06:05:42 PM PDT 24
Peak memory 198548 kb
Host smart-dc220653-9956-48a8-a357-0bf44d5aac39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339190424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.339190424
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.636268353
Short name T783
Test name
Test status
Simulation time 126019753 ps
CPU time 1.46 seconds
Started Aug 15 06:05:43 PM PDT 24
Finished Aug 15 06:05:44 PM PDT 24
Peak memory 198556 kb
Host smart-acac46eb-dac5-43d4-8e99-77d6797d1a2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636268353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.636268353
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.343216632
Short name T780
Test name
Test status
Simulation time 75406396 ps
CPU time 0.74 seconds
Started Aug 15 06:05:51 PM PDT 24
Finished Aug 15 06:05:52 PM PDT 24
Peak memory 198400 kb
Host smart-89634422-61cc-46f9-aa19-eb9aa888d7f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343216632 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.343216632
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1144697417
Short name T753
Test name
Test status
Simulation time 47137874 ps
CPU time 0.58 seconds
Started Aug 15 06:05:52 PM PDT 24
Finished Aug 15 06:05:52 PM PDT 24
Peak memory 193812 kb
Host smart-7238ffcb-d24e-4afa-9163-dcbb3703ad1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144697417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1144697417
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2723265704
Short name T750
Test name
Test status
Simulation time 15539512 ps
CPU time 0.58 seconds
Started Aug 15 06:05:42 PM PDT 24
Finished Aug 15 06:05:43 PM PDT 24
Peak memory 194204 kb
Host smart-8dbeeb0a-63c1-48b3-9d7f-a4fcdbd148f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723265704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2723265704
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3028310022
Short name T837
Test name
Test status
Simulation time 75568758 ps
CPU time 0.67 seconds
Started Aug 15 06:05:54 PM PDT 24
Finished Aug 15 06:05:55 PM PDT 24
Peak memory 196016 kb
Host smart-3a469c54-6593-4600-bf08-09492c29b2c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028310022 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3028310022
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4146202177
Short name T729
Test name
Test status
Simulation time 53004597 ps
CPU time 2.66 seconds
Started Aug 15 06:05:34 PM PDT 24
Finished Aug 15 06:05:37 PM PDT 24
Peak memory 198604 kb
Host smart-3ad8eb21-b770-41d8-87f9-21b862b4e984
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146202177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4146202177
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.804320882
Short name T45
Test name
Test status
Simulation time 60834091 ps
CPU time 0.89 seconds
Started Aug 15 06:05:56 PM PDT 24
Finished Aug 15 06:05:57 PM PDT 24
Peak memory 197544 kb
Host smart-3fd92d28-6cd9-422f-a94d-b833cb128caa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804320882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.804320882
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.665917735
Short name T772
Test name
Test status
Simulation time 71409227 ps
CPU time 0.93 seconds
Started Aug 15 06:05:48 PM PDT 24
Finished Aug 15 06:05:49 PM PDT 24
Peak memory 198416 kb
Host smart-42091e0c-0182-431e-ab4d-e86a65cd0c78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665917735 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.665917735
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2046693542
Short name T89
Test name
Test status
Simulation time 27069029 ps
CPU time 0.6 seconds
Started Aug 15 06:05:45 PM PDT 24
Finished Aug 15 06:05:46 PM PDT 24
Peak memory 195788 kb
Host smart-8cb35231-5c86-4d46-ab48-b350407e9430
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046693542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2046693542
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4112573400
Short name T769
Test name
Test status
Simulation time 16422055 ps
CPU time 0.62 seconds
Started Aug 15 06:05:53 PM PDT 24
Finished Aug 15 06:05:54 PM PDT 24
Peak memory 194924 kb
Host smart-91ffb278-bd67-4a00-94fb-7062fc7606de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112573400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4112573400
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3008550827
Short name T822
Test name
Test status
Simulation time 30980791 ps
CPU time 0.71 seconds
Started Aug 15 06:05:36 PM PDT 24
Finished Aug 15 06:05:37 PM PDT 24
Peak memory 195028 kb
Host smart-2aeaf1c0-1bdf-4637-adc8-6add08b5b91f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008550827 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3008550827
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3330081029
Short name T805
Test name
Test status
Simulation time 286609611 ps
CPU time 1.67 seconds
Started Aug 15 06:05:53 PM PDT 24
Finished Aug 15 06:05:55 PM PDT 24
Peak memory 198596 kb
Host smart-307022f3-7612-4494-9e36-a71f4747357d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330081029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3330081029
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.826043386
Short name T815
Test name
Test status
Simulation time 498569120 ps
CPU time 0.89 seconds
Started Aug 15 06:06:01 PM PDT 24
Finished Aug 15 06:06:02 PM PDT 24
Peak memory 197660 kb
Host smart-9996f3eb-b62d-4d29-af4c-2b168de37300
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826043386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.826043386
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.186902184
Short name T799
Test name
Test status
Simulation time 29302781 ps
CPU time 0.66 seconds
Started Aug 15 06:05:47 PM PDT 24
Finished Aug 15 06:05:48 PM PDT 24
Peak memory 197584 kb
Host smart-0db37934-d83b-430c-8be5-299382745a02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186902184 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.186902184
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2346977790
Short name T768
Test name
Test status
Simulation time 36246145 ps
CPU time 0.57 seconds
Started Aug 15 06:06:00 PM PDT 24
Finished Aug 15 06:06:01 PM PDT 24
Peak memory 194928 kb
Host smart-282f456f-1679-448a-ad4c-2929a16eb397
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346977790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2346977790
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.416435314
Short name T728
Test name
Test status
Simulation time 18664739 ps
CPU time 0.58 seconds
Started Aug 15 06:05:47 PM PDT 24
Finished Aug 15 06:05:47 PM PDT 24
Peak memory 194124 kb
Host smart-bb9eec98-b53f-46e5-b2b2-8a27c051954a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416435314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.416435314
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3376291728
Short name T764
Test name
Test status
Simulation time 31706163 ps
CPU time 0.85 seconds
Started Aug 15 06:05:40 PM PDT 24
Finished Aug 15 06:05:41 PM PDT 24
Peak memory 196596 kb
Host smart-6bb5dcdf-925b-47c8-82e4-2a32d76c834f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376291728 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3376291728
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1537369359
Short name T717
Test name
Test status
Simulation time 116200514 ps
CPU time 1.97 seconds
Started Aug 15 06:05:46 PM PDT 24
Finished Aug 15 06:05:48 PM PDT 24
Peak memory 198568 kb
Host smart-db89a9d2-62ee-4904-ad11-09035e56d693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537369359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1537369359
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.586400230
Short name T36
Test name
Test status
Simulation time 502090350 ps
CPU time 1.44 seconds
Started Aug 15 06:06:03 PM PDT 24
Finished Aug 15 06:06:05 PM PDT 24
Peak memory 198472 kb
Host smart-824197b8-6940-4ca7-9857-0b85e9fd9965
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586400230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.586400230
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.156181493
Short name T716
Test name
Test status
Simulation time 181843006 ps
CPU time 0.85 seconds
Started Aug 15 06:05:43 PM PDT 24
Finished Aug 15 06:05:43 PM PDT 24
Peak memory 198372 kb
Host smart-0695bd11-5586-4f02-b536-5d79d61fbe9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156181493 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.156181493
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.575379602
Short name T751
Test name
Test status
Simulation time 20415839 ps
CPU time 0.58 seconds
Started Aug 15 06:05:54 PM PDT 24
Finished Aug 15 06:05:55 PM PDT 24
Peak memory 193760 kb
Host smart-1edcfa77-ca69-4644-8667-0381b9ca8c0d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575379602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.575379602
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1899469648
Short name T726
Test name
Test status
Simulation time 33472732 ps
CPU time 0.58 seconds
Started Aug 15 06:05:44 PM PDT 24
Finished Aug 15 06:05:44 PM PDT 24
Peak memory 194788 kb
Host smart-e7c7a0be-db7e-46d3-abc3-3bc096da3e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899469648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1899469648
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1285719599
Short name T828
Test name
Test status
Simulation time 19720746 ps
CPU time 0.7 seconds
Started Aug 15 06:05:35 PM PDT 24
Finished Aug 15 06:05:36 PM PDT 24
Peak memory 194764 kb
Host smart-48621425-20dd-42a9-b354-d4dea75b8e38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285719599 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1285719599
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2695423993
Short name T778
Test name
Test status
Simulation time 71751767 ps
CPU time 1.62 seconds
Started Aug 15 06:05:43 PM PDT 24
Finished Aug 15 06:05:45 PM PDT 24
Peak memory 198536 kb
Host smart-ac8cdd81-b393-4522-8f95-a9630532b9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695423993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2695423993
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3018260630
Short name T838
Test name
Test status
Simulation time 52176969 ps
CPU time 0.87 seconds
Started Aug 15 06:05:39 PM PDT 24
Finished Aug 15 06:05:40 PM PDT 24
Peak memory 197616 kb
Host smart-ff8b36de-f542-4227-9ca9-69caf46def1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018260630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3018260630
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1238087349
Short name T795
Test name
Test status
Simulation time 20423330 ps
CPU time 0.97 seconds
Started Aug 15 06:06:04 PM PDT 24
Finished Aug 15 06:06:05 PM PDT 24
Peak memory 198364 kb
Host smart-baf3eca9-1933-441b-a2c6-9d64a8c03fa2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238087349 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1238087349
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3819789772
Short name T777
Test name
Test status
Simulation time 13647580 ps
CPU time 0.62 seconds
Started Aug 15 06:05:39 PM PDT 24
Finished Aug 15 06:05:40 PM PDT 24
Peak memory 195880 kb
Host smart-5f64a6c1-9eb7-4573-a7e6-9fc920a8a91a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819789772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3819789772
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1571576358
Short name T819
Test name
Test status
Simulation time 13418839 ps
CPU time 0.57 seconds
Started Aug 15 06:05:51 PM PDT 24
Finished Aug 15 06:05:51 PM PDT 24
Peak memory 194200 kb
Host smart-e325d2bc-54b3-44e5-b4ba-7ea3cdc1b17b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571576358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1571576358
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.298117440
Short name T81
Test name
Test status
Simulation time 13990271 ps
CPU time 0.62 seconds
Started Aug 15 06:05:45 PM PDT 24
Finished Aug 15 06:05:46 PM PDT 24
Peak memory 194956 kb
Host smart-4b309a32-bbef-47fa-950f-dd37000485af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298117440 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.298117440
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3767228455
Short name T816
Test name
Test status
Simulation time 225417170 ps
CPU time 1.45 seconds
Started Aug 15 06:05:59 PM PDT 24
Finished Aug 15 06:06:01 PM PDT 24
Peak memory 198560 kb
Host smart-3d88746c-27e2-4dd7-b024-b08f478ed80a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767228455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3767228455
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2563617080
Short name T37
Test name
Test status
Simulation time 1234296674 ps
CPU time 1.16 seconds
Started Aug 15 06:05:46 PM PDT 24
Finished Aug 15 06:05:47 PM PDT 24
Peak memory 198536 kb
Host smart-5a2db919-1561-4014-9607-989cab0ee614
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563617080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2563617080
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2565101093
Short name T752
Test name
Test status
Simulation time 22030217 ps
CPU time 0.79 seconds
Started Aug 15 06:05:41 PM PDT 24
Finished Aug 15 06:05:42 PM PDT 24
Peak memory 198380 kb
Host smart-28ed4d6c-0a25-4be9-a0e7-b74e756b958d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565101093 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2565101093
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.959892440
Short name T787
Test name
Test status
Simulation time 14732577 ps
CPU time 0.59 seconds
Started Aug 15 06:05:51 PM PDT 24
Finished Aug 15 06:05:51 PM PDT 24
Peak memory 195232 kb
Host smart-bf103c90-ca40-42a7-8b36-3db660027664
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959892440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.959892440
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3878682967
Short name T781
Test name
Test status
Simulation time 53783246 ps
CPU time 0.65 seconds
Started Aug 15 06:05:58 PM PDT 24
Finished Aug 15 06:05:59 PM PDT 24
Peak memory 194868 kb
Host smart-82a64a9d-2b20-4794-bb83-db572404e334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878682967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3878682967
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.656978138
Short name T774
Test name
Test status
Simulation time 20359486 ps
CPU time 0.81 seconds
Started Aug 15 06:05:35 PM PDT 24
Finished Aug 15 06:05:36 PM PDT 24
Peak memory 196852 kb
Host smart-3dad0b30-6085-43d2-b695-3bb793153104
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656978138 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.656978138
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2702881768
Short name T775
Test name
Test status
Simulation time 538155511 ps
CPU time 1.18 seconds
Started Aug 15 06:06:01 PM PDT 24
Finished Aug 15 06:06:03 PM PDT 24
Peak memory 198632 kb
Host smart-c2e2c083-ad35-4f45-bda1-eafc573cce87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702881768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2702881768
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3870181190
Short name T47
Test name
Test status
Simulation time 814268828 ps
CPU time 1.43 seconds
Started Aug 15 06:05:35 PM PDT 24
Finished Aug 15 06:05:37 PM PDT 24
Peak memory 198540 kb
Host smart-620205ac-7ddf-4d9e-a4b5-c91bfea2814e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870181190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3870181190
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3458465530
Short name T96
Test name
Test status
Simulation time 68041670 ps
CPU time 0.67 seconds
Started Aug 15 06:05:31 PM PDT 24
Finished Aug 15 06:05:32 PM PDT 24
Peak memory 195016 kb
Host smart-0d6f6bf3-49f1-4ad1-a03f-4655df8908b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458465530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3458465530
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1738060846
Short name T78
Test name
Test status
Simulation time 131905552 ps
CPU time 1.34 seconds
Started Aug 15 06:05:33 PM PDT 24
Finished Aug 15 06:05:35 PM PDT 24
Peak memory 197264 kb
Host smart-d83e9c02-395c-42d6-a0a4-e586f97ee8b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738060846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1738060846
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3335041464
Short name T810
Test name
Test status
Simulation time 31231494 ps
CPU time 0.64 seconds
Started Aug 15 06:05:30 PM PDT 24
Finished Aug 15 06:05:31 PM PDT 24
Peak memory 195260 kb
Host smart-37e85ac9-0e39-46cb-86c3-027e4f7637ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335041464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3335041464
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1128408286
Short name T736
Test name
Test status
Simulation time 124004146 ps
CPU time 0.92 seconds
Started Aug 15 06:05:45 PM PDT 24
Finished Aug 15 06:05:46 PM PDT 24
Peak memory 198584 kb
Host smart-7fac8fb6-3135-4a9c-b806-86e1a9be734e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128408286 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1128408286
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2683869366
Short name T98
Test name
Test status
Simulation time 23433266 ps
CPU time 0.59 seconds
Started Aug 15 06:05:30 PM PDT 24
Finished Aug 15 06:05:31 PM PDT 24
Peak memory 195076 kb
Host smart-f29616ff-f6b1-4596-8eab-88814c02b8f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683869366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2683869366
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1402103186
Short name T758
Test name
Test status
Simulation time 12227208 ps
CPU time 0.61 seconds
Started Aug 15 06:05:31 PM PDT 24
Finished Aug 15 06:05:32 PM PDT 24
Peak memory 194152 kb
Host smart-a96f344d-32cf-4976-af09-05bc60f29540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402103186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1402103186
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3663974384
Short name T779
Test name
Test status
Simulation time 62883900 ps
CPU time 0.68 seconds
Started Aug 15 06:05:34 PM PDT 24
Finished Aug 15 06:05:35 PM PDT 24
Peak memory 194804 kb
Host smart-d4870419-6bcc-4840-9cab-9dac3f60cc16
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663974384 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3663974384
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.292571201
Short name T763
Test name
Test status
Simulation time 308430183 ps
CPU time 2.36 seconds
Started Aug 15 06:05:29 PM PDT 24
Finished Aug 15 06:05:32 PM PDT 24
Peak memory 198528 kb
Host smart-7545e356-9d36-49a9-8984-f179232f3d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292571201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.292571201
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1743835194
Short name T830
Test name
Test status
Simulation time 312185464 ps
CPU time 1.14 seconds
Started Aug 15 06:05:30 PM PDT 24
Finished Aug 15 06:05:31 PM PDT 24
Peak memory 198560 kb
Host smart-bfcdc7ab-6c76-4a34-a06b-036ca124cae4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743835194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1743835194
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3616183868
Short name T748
Test name
Test status
Simulation time 18407871 ps
CPU time 0.59 seconds
Started Aug 15 06:05:46 PM PDT 24
Finished Aug 15 06:05:47 PM PDT 24
Peak memory 194160 kb
Host smart-5c1f101d-4d9e-4a76-87f2-da9212ebab36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616183868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3616183868
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3923239170
Short name T715
Test name
Test status
Simulation time 36976901 ps
CPU time 0.6 seconds
Started Aug 15 06:05:46 PM PDT 24
Finished Aug 15 06:05:47 PM PDT 24
Peak memory 194144 kb
Host smart-001910be-a8bf-497a-979e-7f23cc042469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923239170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3923239170
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.138519692
Short name T759
Test name
Test status
Simulation time 13050763 ps
CPU time 0.61 seconds
Started Aug 15 06:05:57 PM PDT 24
Finished Aug 15 06:05:58 PM PDT 24
Peak memory 194304 kb
Host smart-e3abbe20-3dbd-40b8-a1ac-12bf2318554c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138519692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.138519692
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.373874004
Short name T835
Test name
Test status
Simulation time 11724327 ps
CPU time 0.56 seconds
Started Aug 15 06:05:42 PM PDT 24
Finished Aug 15 06:05:43 PM PDT 24
Peak memory 194808 kb
Host smart-5a3cf8a9-ad9a-44bd-8781-c54f4900860c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373874004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.373874004
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1172983828
Short name T724
Test name
Test status
Simulation time 25288917 ps
CPU time 0.57 seconds
Started Aug 15 06:05:52 PM PDT 24
Finished Aug 15 06:05:53 PM PDT 24
Peak memory 194172 kb
Host smart-39493d25-ba60-4b24-9d6a-8b24d7d01fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172983828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1172983828
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2829795694
Short name T831
Test name
Test status
Simulation time 23676750 ps
CPU time 0.59 seconds
Started Aug 15 06:05:52 PM PDT 24
Finished Aug 15 06:05:53 PM PDT 24
Peak memory 194172 kb
Host smart-584cd07e-75b2-4191-affc-6d5af5a896e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829795694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2829795694
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2485186867
Short name T725
Test name
Test status
Simulation time 24272080 ps
CPU time 0.63 seconds
Started Aug 15 06:06:00 PM PDT 24
Finished Aug 15 06:06:01 PM PDT 24
Peak memory 194272 kb
Host smart-222e4cef-4074-43c5-bace-a4e308f55cd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485186867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2485186867
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1407171836
Short name T739
Test name
Test status
Simulation time 34267440 ps
CPU time 0.62 seconds
Started Aug 15 06:05:52 PM PDT 24
Finished Aug 15 06:05:53 PM PDT 24
Peak memory 194940 kb
Host smart-c6c05ca4-3530-4d1d-81b4-56f54c1e732e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407171836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1407171836
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1037757258
Short name T802
Test name
Test status
Simulation time 13917602 ps
CPU time 0.58 seconds
Started Aug 15 06:05:51 PM PDT 24
Finished Aug 15 06:05:52 PM PDT 24
Peak memory 194188 kb
Host smart-90edff3b-56ff-4ec1-8344-0683420333cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037757258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1037757258
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2441279921
Short name T797
Test name
Test status
Simulation time 40787863 ps
CPU time 0.57 seconds
Started Aug 15 06:05:56 PM PDT 24
Finished Aug 15 06:05:57 PM PDT 24
Peak memory 194140 kb
Host smart-f964e748-0758-4ff1-a77b-39a353c99632
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441279921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2441279921
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.4228415165
Short name T760
Test name
Test status
Simulation time 99638913 ps
CPU time 0.84 seconds
Started Aug 15 06:05:35 PM PDT 24
Finished Aug 15 06:05:36 PM PDT 24
Peak memory 196912 kb
Host smart-16925279-de37-4ee8-a3f0-2e92d917d750
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228415165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.4228415165
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3702932142
Short name T99
Test name
Test status
Simulation time 76223022 ps
CPU time 1.47 seconds
Started Aug 15 06:05:31 PM PDT 24
Finished Aug 15 06:05:33 PM PDT 24
Peak memory 197704 kb
Host smart-6c364975-5093-4d93-b718-259434812957
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702932142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3702932142
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1892197556
Short name T88
Test name
Test status
Simulation time 118973255 ps
CPU time 0.67 seconds
Started Aug 15 06:05:45 PM PDT 24
Finished Aug 15 06:05:46 PM PDT 24
Peak memory 195348 kb
Host smart-86f39b9b-6b8b-42c0-a80a-29099497ca01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892197556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1892197556
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3903857147
Short name T793
Test name
Test status
Simulation time 117496303 ps
CPU time 1.47 seconds
Started Aug 15 06:05:32 PM PDT 24
Finished Aug 15 06:05:34 PM PDT 24
Peak memory 198600 kb
Host smart-4c05c04e-de9e-488f-b71d-414793da0b65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903857147 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3903857147
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.447035954
Short name T734
Test name
Test status
Simulation time 40047761 ps
CPU time 0.62 seconds
Started Aug 15 06:05:30 PM PDT 24
Finished Aug 15 06:05:30 PM PDT 24
Peak memory 195224 kb
Host smart-d3fcbe46-60bd-4ecf-b8c9-b2d0bbba4f4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447035954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.447035954
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2320871901
Short name T732
Test name
Test status
Simulation time 41875492 ps
CPU time 0.6 seconds
Started Aug 15 06:05:30 PM PDT 24
Finished Aug 15 06:05:31 PM PDT 24
Peak memory 194836 kb
Host smart-4ba19e84-ceef-4589-8461-c085dd98ed1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320871901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2320871901
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1516750414
Short name T827
Test name
Test status
Simulation time 29077081 ps
CPU time 0.73 seconds
Started Aug 15 06:05:42 PM PDT 24
Finished Aug 15 06:05:43 PM PDT 24
Peak memory 195964 kb
Host smart-fb284f04-14db-448e-960f-d7ff77330b3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516750414 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1516750414
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2535315891
Short name T840
Test name
Test status
Simulation time 47397785 ps
CPU time 1.25 seconds
Started Aug 15 06:05:31 PM PDT 24
Finished Aug 15 06:05:33 PM PDT 24
Peak memory 198676 kb
Host smart-88c22371-b171-4354-9308-305baa34c01a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535315891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2535315891
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2804578559
Short name T756
Test name
Test status
Simulation time 88795499 ps
CPU time 1.15 seconds
Started Aug 15 06:05:30 PM PDT 24
Finished Aug 15 06:05:32 PM PDT 24
Peak memory 198452 kb
Host smart-9bc0e3a8-97e1-4a43-99c3-481b43f66f41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804578559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2804578559
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.631240319
Short name T789
Test name
Test status
Simulation time 25750189 ps
CPU time 0.57 seconds
Started Aug 15 06:06:06 PM PDT 24
Finished Aug 15 06:06:07 PM PDT 24
Peak memory 194852 kb
Host smart-c7cca4c6-04f8-4d0f-9ca4-29fc3ed27353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631240319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.631240319
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2262014684
Short name T832
Test name
Test status
Simulation time 22999848 ps
CPU time 0.56 seconds
Started Aug 15 06:05:43 PM PDT 24
Finished Aug 15 06:05:44 PM PDT 24
Peak memory 194192 kb
Host smart-9fc8c95c-1bc0-465a-a231-9c4e1a4b24c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262014684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2262014684
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.314981649
Short name T784
Test name
Test status
Simulation time 15187832 ps
CPU time 0.59 seconds
Started Aug 15 06:05:57 PM PDT 24
Finished Aug 15 06:05:58 PM PDT 24
Peak memory 194164 kb
Host smart-cc25a668-253c-4915-8719-a5c57cb01434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314981649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.314981649
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3166587948
Short name T785
Test name
Test status
Simulation time 31028723 ps
CPU time 0.57 seconds
Started Aug 15 06:05:59 PM PDT 24
Finished Aug 15 06:06:00 PM PDT 24
Peak memory 194244 kb
Host smart-d728c91c-948d-4e97-9165-ebd75810e101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166587948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3166587948
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.947033132
Short name T733
Test name
Test status
Simulation time 33203260 ps
CPU time 0.59 seconds
Started Aug 15 06:05:50 PM PDT 24
Finished Aug 15 06:05:51 PM PDT 24
Peak memory 193376 kb
Host smart-7aca7e76-66d3-44d3-be76-6a254f3c5fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947033132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.947033132
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2893009148
Short name T796
Test name
Test status
Simulation time 38930983 ps
CPU time 0.6 seconds
Started Aug 15 06:05:58 PM PDT 24
Finished Aug 15 06:06:03 PM PDT 24
Peak memory 194824 kb
Host smart-a1bec68c-e14f-4a33-aeb6-c38aaeb13876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893009148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2893009148
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1032813107
Short name T718
Test name
Test status
Simulation time 12997802 ps
CPU time 0.58 seconds
Started Aug 15 06:05:51 PM PDT 24
Finished Aug 15 06:05:51 PM PDT 24
Peak memory 194384 kb
Host smart-dfb15019-52ef-4100-ad2b-1e741c711e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032813107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1032813107
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3785932606
Short name T791
Test name
Test status
Simulation time 16094099 ps
CPU time 0.61 seconds
Started Aug 15 06:05:49 PM PDT 24
Finished Aug 15 06:05:50 PM PDT 24
Peak memory 194196 kb
Host smart-b97de561-8adb-4421-8d32-cbc8cc738731
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785932606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3785932606
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.593047327
Short name T812
Test name
Test status
Simulation time 40459469 ps
CPU time 0.57 seconds
Started Aug 15 06:06:15 PM PDT 24
Finished Aug 15 06:06:16 PM PDT 24
Peak memory 194196 kb
Host smart-ea707c4a-7b9b-4cd1-8d9c-e5f968ff64c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593047327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.593047327
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2791123199
Short name T762
Test name
Test status
Simulation time 52886889 ps
CPU time 0.6 seconds
Started Aug 15 06:05:46 PM PDT 24
Finished Aug 15 06:05:47 PM PDT 24
Peak memory 194888 kb
Host smart-82abfa98-8e10-4b4e-8b37-b62d128b305f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791123199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2791123199
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.566424498
Short name T86
Test name
Test status
Simulation time 106817606 ps
CPU time 0.72 seconds
Started Aug 15 06:05:57 PM PDT 24
Finished Aug 15 06:05:58 PM PDT 24
Peak memory 196088 kb
Host smart-35ca65a7-c565-4438-b822-ddf9fc3289f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566424498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.566424498
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2060757498
Short name T90
Test name
Test status
Simulation time 409912864 ps
CPU time 2.92 seconds
Started Aug 15 06:05:32 PM PDT 24
Finished Aug 15 06:05:35 PM PDT 24
Peak memory 196908 kb
Host smart-01a3a7f0-5963-4e01-a4d9-60840fe97fc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060757498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2060757498
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3655600365
Short name T801
Test name
Test status
Simulation time 56208413 ps
CPU time 0.64 seconds
Started Aug 15 06:05:37 PM PDT 24
Finished Aug 15 06:05:37 PM PDT 24
Peak memory 195404 kb
Host smart-ffed0ebc-9672-48c5-931f-8f3019824024
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655600365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3655600365
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4068684489
Short name T757
Test name
Test status
Simulation time 56650309 ps
CPU time 0.73 seconds
Started Aug 15 06:05:30 PM PDT 24
Finished Aug 15 06:05:31 PM PDT 24
Peak memory 197680 kb
Host smart-9d04d6a3-c8d0-4f52-ba10-23b6ab511807
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068684489 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.4068684489
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.946722373
Short name T755
Test name
Test status
Simulation time 38170203 ps
CPU time 0.64 seconds
Started Aug 15 06:05:34 PM PDT 24
Finished Aug 15 06:05:35 PM PDT 24
Peak memory 195872 kb
Host smart-1c427a07-5be8-4dbe-98f0-ac2eeb9966f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946722373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.946722373
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.669290883
Short name T731
Test name
Test status
Simulation time 30463848 ps
CPU time 0.58 seconds
Started Aug 15 06:05:27 PM PDT 24
Finished Aug 15 06:05:28 PM PDT 24
Peak memory 194876 kb
Host smart-3e247045-e828-4edd-ae83-527abd51a8ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669290883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.669290883
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1799073989
Short name T75
Test name
Test status
Simulation time 153189732 ps
CPU time 0.89 seconds
Started Aug 15 06:05:31 PM PDT 24
Finished Aug 15 06:05:32 PM PDT 24
Peak memory 197488 kb
Host smart-aa74b26c-f015-4791-ab95-110ce87dd10c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799073989 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1799073989
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1752631631
Short name T745
Test name
Test status
Simulation time 364345858 ps
CPU time 1.12 seconds
Started Aug 15 06:05:31 PM PDT 24
Finished Aug 15 06:05:33 PM PDT 24
Peak memory 198336 kb
Host smart-f6c2905f-ab8d-44cb-aa62-c4598d46c94d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752631631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1752631631
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3900268278
Short name T49
Test name
Test status
Simulation time 451846781 ps
CPU time 1.36 seconds
Started Aug 15 06:05:35 PM PDT 24
Finished Aug 15 06:05:37 PM PDT 24
Peak memory 198492 kb
Host smart-fc88f543-cf6c-402f-b528-ae8c0e4e2ee9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900268278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3900268278
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3122003810
Short name T776
Test name
Test status
Simulation time 11599226 ps
CPU time 0.62 seconds
Started Aug 15 06:05:47 PM PDT 24
Finished Aug 15 06:05:48 PM PDT 24
Peak memory 194884 kb
Host smart-a1302148-14d8-4ae0-ae6f-19b87b902272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122003810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3122003810
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3350986918
Short name T825
Test name
Test status
Simulation time 24116413 ps
CPU time 0.6 seconds
Started Aug 15 06:05:55 PM PDT 24
Finished Aug 15 06:05:56 PM PDT 24
Peak memory 194860 kb
Host smart-b8185198-0a80-4aef-a80a-98ec416ad923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350986918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3350986918
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.411053751
Short name T722
Test name
Test status
Simulation time 33849655 ps
CPU time 0.57 seconds
Started Aug 15 06:05:44 PM PDT 24
Finished Aug 15 06:05:45 PM PDT 24
Peak memory 194904 kb
Host smart-ba797424-e8c4-4072-b885-b1fb45f0f39d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411053751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.411053751
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.457561951
Short name T735
Test name
Test status
Simulation time 13973738 ps
CPU time 0.55 seconds
Started Aug 15 06:05:48 PM PDT 24
Finished Aug 15 06:05:48 PM PDT 24
Peak memory 194160 kb
Host smart-fca12bf6-4643-4b6e-ba33-bdff1f856854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457561951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.457561951
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1764951685
Short name T765
Test name
Test status
Simulation time 47766162 ps
CPU time 0.6 seconds
Started Aug 15 06:05:53 PM PDT 24
Finished Aug 15 06:05:54 PM PDT 24
Peak memory 194228 kb
Host smart-28978f1b-2387-465a-84ef-54ea6ffe24ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764951685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1764951685
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1325243291
Short name T719
Test name
Test status
Simulation time 46800665 ps
CPU time 0.63 seconds
Started Aug 15 06:05:53 PM PDT 24
Finished Aug 15 06:05:54 PM PDT 24
Peak memory 194316 kb
Host smart-d811f727-2ea5-4f40-bdd5-6d950674b3e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325243291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1325243291
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1038368299
Short name T823
Test name
Test status
Simulation time 34608818 ps
CPU time 0.6 seconds
Started Aug 15 06:05:53 PM PDT 24
Finished Aug 15 06:05:58 PM PDT 24
Peak memory 194196 kb
Host smart-9be87be6-a5dd-47ae-9d91-6aae5fd8e0ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038368299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1038368299
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4166499811
Short name T786
Test name
Test status
Simulation time 13195042 ps
CPU time 0.63 seconds
Started Aug 15 06:05:52 PM PDT 24
Finished Aug 15 06:05:52 PM PDT 24
Peak memory 194196 kb
Host smart-9478090b-5669-401e-ad59-afb812f5780e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166499811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4166499811
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.160791839
Short name T747
Test name
Test status
Simulation time 40522670 ps
CPU time 0.57 seconds
Started Aug 15 06:05:58 PM PDT 24
Finished Aug 15 06:05:59 PM PDT 24
Peak memory 194284 kb
Host smart-2aad64e4-4f1c-4a8f-b587-e14535847e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160791839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.160791839
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1706871241
Short name T806
Test name
Test status
Simulation time 17041245 ps
CPU time 0.61 seconds
Started Aug 15 06:05:54 PM PDT 24
Finished Aug 15 06:05:55 PM PDT 24
Peak memory 194908 kb
Host smart-f335da8a-ca71-4fce-a7dc-8baecbf4cae6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706871241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1706871241
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1686657318
Short name T761
Test name
Test status
Simulation time 139765209 ps
CPU time 1.05 seconds
Started Aug 15 06:05:41 PM PDT 24
Finished Aug 15 06:05:42 PM PDT 24
Peak memory 198436 kb
Host smart-d86484df-739e-490f-97e2-f81fdc43229d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686657318 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1686657318
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4194273297
Short name T85
Test name
Test status
Simulation time 17430440 ps
CPU time 0.61 seconds
Started Aug 15 06:05:58 PM PDT 24
Finished Aug 15 06:05:59 PM PDT 24
Peak memory 195360 kb
Host smart-a639ee2e-6b49-4752-ad09-6ee5e302be35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194273297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.4194273297
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.341609140
Short name T792
Test name
Test status
Simulation time 14968191 ps
CPU time 0.59 seconds
Started Aug 15 06:05:34 PM PDT 24
Finished Aug 15 06:05:35 PM PDT 24
Peak memory 194252 kb
Host smart-82bbf903-e96b-4ca4-955c-bd97b26b0d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341609140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.341609140
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.55906787
Short name T74
Test name
Test status
Simulation time 36819430 ps
CPU time 0.86 seconds
Started Aug 15 06:05:36 PM PDT 24
Finished Aug 15 06:05:37 PM PDT 24
Peak memory 197624 kb
Host smart-f5fba543-b017-4fcf-b354-94595bff85f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55906787 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.gpio_same_csr_outstanding.55906787
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2855341926
Short name T771
Test name
Test status
Simulation time 74965298 ps
CPU time 1.1 seconds
Started Aug 15 06:05:39 PM PDT 24
Finished Aug 15 06:05:40 PM PDT 24
Peak memory 198368 kb
Host smart-e421be7a-d744-4e5d-91ad-1e064e1288df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855341926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2855341926
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.327491063
Short name T48
Test name
Test status
Simulation time 70800045 ps
CPU time 1.08 seconds
Started Aug 15 06:05:46 PM PDT 24
Finished Aug 15 06:05:48 PM PDT 24
Peak memory 198524 kb
Host smart-19cf29e8-902b-4688-99f8-4cf3dc720b69
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327491063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.327491063
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3439463649
Short name T754
Test name
Test status
Simulation time 501319893 ps
CPU time 0.81 seconds
Started Aug 15 06:05:32 PM PDT 24
Finished Aug 15 06:05:33 PM PDT 24
Peak memory 198340 kb
Host smart-97ccbc5f-2e25-430d-8b17-395cf07eecf0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439463649 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3439463649
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1804468399
Short name T834
Test name
Test status
Simulation time 28063428 ps
CPU time 0.63 seconds
Started Aug 15 06:05:33 PM PDT 24
Finished Aug 15 06:05:34 PM PDT 24
Peak memory 195788 kb
Host smart-77a77cd9-6abf-4c42-af3a-4d3b1752513e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804468399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1804468399
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1508961849
Short name T738
Test name
Test status
Simulation time 120060600 ps
CPU time 0.58 seconds
Started Aug 15 06:05:36 PM PDT 24
Finished Aug 15 06:05:37 PM PDT 24
Peak memory 194828 kb
Host smart-1a125b7f-d7cd-43a7-b896-8ad44f5c77d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508961849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1508961849
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4039771389
Short name T91
Test name
Test status
Simulation time 51604658 ps
CPU time 0.62 seconds
Started Aug 15 06:05:29 PM PDT 24
Finished Aug 15 06:05:30 PM PDT 24
Peak memory 194928 kb
Host smart-8f8afd0a-4c1f-4a75-a75d-8a87da063c7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039771389 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.4039771389
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2612482185
Short name T713
Test name
Test status
Simulation time 103582428 ps
CPU time 2.12 seconds
Started Aug 15 06:05:31 PM PDT 24
Finished Aug 15 06:05:34 PM PDT 24
Peak memory 198596 kb
Host smart-e23f31eb-54fc-47fb-b900-ea7ed4144093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612482185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2612482185
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1593203336
Short name T788
Test name
Test status
Simulation time 365660352 ps
CPU time 0.91 seconds
Started Aug 15 06:05:47 PM PDT 24
Finished Aug 15 06:05:48 PM PDT 24
Peak memory 198272 kb
Host smart-07b1cda5-af21-41f0-aa7f-b31e8cd4e4bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593203336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1593203336
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1676718290
Short name T741
Test name
Test status
Simulation time 20501455 ps
CPU time 1.1 seconds
Started Aug 15 06:05:31 PM PDT 24
Finished Aug 15 06:05:33 PM PDT 24
Peak memory 198416 kb
Host smart-15c1d4b2-1f2e-4c4a-a7f4-104c86178cfb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676718290 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1676718290
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1497383733
Short name T79
Test name
Test status
Simulation time 64769285 ps
CPU time 0.64 seconds
Started Aug 15 06:05:35 PM PDT 24
Finished Aug 15 06:05:36 PM PDT 24
Peak memory 195032 kb
Host smart-09aa865a-5347-48ce-89d5-1a18c94d8f49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497383733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1497383733
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2117529351
Short name T727
Test name
Test status
Simulation time 37103413 ps
CPU time 0.59 seconds
Started Aug 15 06:05:29 PM PDT 24
Finished Aug 15 06:05:30 PM PDT 24
Peak memory 194224 kb
Host smart-4df16fd1-ebb4-47e3-a030-70695abe6cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117529351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2117529351
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.4117350460
Short name T817
Test name
Test status
Simulation time 41288792 ps
CPU time 0.67 seconds
Started Aug 15 06:05:32 PM PDT 24
Finished Aug 15 06:05:33 PM PDT 24
Peak memory 194936 kb
Host smart-abb6b696-2de6-4897-8a16-f13db1b53a1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117350460 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.4117350460
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2281137818
Short name T813
Test name
Test status
Simulation time 121870377 ps
CPU time 2.12 seconds
Started Aug 15 06:05:41 PM PDT 24
Finished Aug 15 06:05:43 PM PDT 24
Peak memory 198508 kb
Host smart-25ff41cc-0126-41be-adad-5c6e2fcc9390
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281137818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2281137818
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1243004322
Short name T50
Test name
Test status
Simulation time 153299287 ps
CPU time 1.08 seconds
Started Aug 15 06:05:31 PM PDT 24
Finished Aug 15 06:05:32 PM PDT 24
Peak memory 198192 kb
Host smart-b94bc954-fa91-488e-98f5-82d7ac0fb8af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243004322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1243004322
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3803387942
Short name T798
Test name
Test status
Simulation time 136990048 ps
CPU time 0.79 seconds
Started Aug 15 06:05:37 PM PDT 24
Finished Aug 15 06:05:38 PM PDT 24
Peak memory 198420 kb
Host smart-eb0613e7-f142-45a2-8f9a-aa900bbb6044
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803387942 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3803387942
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1975790771
Short name T770
Test name
Test status
Simulation time 14260642 ps
CPU time 0.62 seconds
Started Aug 15 06:05:31 PM PDT 24
Finished Aug 15 06:05:32 PM PDT 24
Peak memory 195760 kb
Host smart-144606fd-87c7-4cca-84b4-a9a711304cbd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975790771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1975790771
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2392821613
Short name T818
Test name
Test status
Simulation time 38278294 ps
CPU time 0.57 seconds
Started Aug 15 06:05:34 PM PDT 24
Finished Aug 15 06:05:35 PM PDT 24
Peak memory 194824 kb
Host smart-9d896460-50a7-4185-8f1f-050cdbd5eeb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392821613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2392821613
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3076870595
Short name T77
Test name
Test status
Simulation time 45716303 ps
CPU time 0.73 seconds
Started Aug 15 06:05:34 PM PDT 24
Finished Aug 15 06:05:35 PM PDT 24
Peak memory 196428 kb
Host smart-2caabf8f-bd2b-4687-9aa3-554f3b1e9f99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076870595 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3076870595
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.345777008
Short name T821
Test name
Test status
Simulation time 68857361 ps
CPU time 1.37 seconds
Started Aug 15 06:05:47 PM PDT 24
Finished Aug 15 06:05:49 PM PDT 24
Peak memory 198620 kb
Host smart-65a0e1c5-0343-4fa9-8ca6-d3c1f8426569
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345777008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.345777008
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.307627181
Short name T826
Test name
Test status
Simulation time 383737621 ps
CPU time 1.35 seconds
Started Aug 15 06:05:33 PM PDT 24
Finished Aug 15 06:05:34 PM PDT 24
Peak memory 198508 kb
Host smart-7cb5b53f-78e7-4b32-9ef9-a4c75812c697
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307627181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.307627181
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3096144516
Short name T820
Test name
Test status
Simulation time 145573815 ps
CPU time 1.06 seconds
Started Aug 15 06:05:39 PM PDT 24
Finished Aug 15 06:05:40 PM PDT 24
Peak memory 198300 kb
Host smart-1b23e227-d816-4d8f-ba2e-cb3081ea2e82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096144516 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3096144516
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4240005721
Short name T97
Test name
Test status
Simulation time 53080445 ps
CPU time 0.58 seconds
Started Aug 15 06:05:37 PM PDT 24
Finished Aug 15 06:05:37 PM PDT 24
Peak memory 193764 kb
Host smart-da079cad-32ee-40aa-a94a-e4d48cdab054
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240005721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.4240005721
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1846088436
Short name T746
Test name
Test status
Simulation time 127614301 ps
CPU time 0.58 seconds
Started Aug 15 06:05:39 PM PDT 24
Finished Aug 15 06:05:39 PM PDT 24
Peak memory 194872 kb
Host smart-3e273685-a5dc-4266-8c60-b788669083a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846088436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1846088436
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1904891884
Short name T83
Test name
Test status
Simulation time 20291954 ps
CPU time 0.79 seconds
Started Aug 15 06:05:33 PM PDT 24
Finished Aug 15 06:05:34 PM PDT 24
Peak memory 196552 kb
Host smart-4dcf056d-a59c-4f20-a396-bc8a56c19a65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904891884 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1904891884
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2926236220
Short name T714
Test name
Test status
Simulation time 352202875 ps
CPU time 2.87 seconds
Started Aug 15 06:05:39 PM PDT 24
Finished Aug 15 06:05:42 PM PDT 24
Peak memory 198636 kb
Host smart-b9252979-bd60-4ad8-838f-78beaeac74be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926236220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2926236220
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2378913739
Short name T811
Test name
Test status
Simulation time 105650648 ps
CPU time 0.9 seconds
Started Aug 15 06:05:37 PM PDT 24
Finished Aug 15 06:05:38 PM PDT 24
Peak memory 197616 kb
Host smart-7c478f79-c016-4573-a227-2e2d6201252d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378913739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2378913739
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1537490465
Short name T522
Test name
Test status
Simulation time 14065766 ps
CPU time 0.56 seconds
Started Aug 15 05:25:51 PM PDT 24
Finished Aug 15 05:25:52 PM PDT 24
Peak memory 194020 kb
Host smart-8ce1900b-2f85-4913-a499-bb6e1a76c2be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537490465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1537490465
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.848872777
Short name T15
Test name
Test status
Simulation time 103972607 ps
CPU time 0.81 seconds
Started Aug 15 05:25:35 PM PDT 24
Finished Aug 15 05:25:35 PM PDT 24
Peak memory 196424 kb
Host smart-fcb41536-63f0-415f-816b-83aa9fbb403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848872777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.848872777
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.796891718
Short name T219
Test name
Test status
Simulation time 550796249 ps
CPU time 15.77 seconds
Started Aug 15 05:25:28 PM PDT 24
Finished Aug 15 05:25:44 PM PDT 24
Peak memory 196416 kb
Host smart-330cb404-f56f-4c5f-9ace-7898ab9260db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796891718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.796891718
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2608518581
Short name T658
Test name
Test status
Simulation time 260278560 ps
CPU time 0.91 seconds
Started Aug 15 05:25:28 PM PDT 24
Finished Aug 15 05:25:29 PM PDT 24
Peak memory 195992 kb
Host smart-749f0ed3-83f0-4f74-82fe-fe163563e4ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608518581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2608518581
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.4103787919
Short name T497
Test name
Test status
Simulation time 72808729 ps
CPU time 1.04 seconds
Started Aug 15 05:25:35 PM PDT 24
Finished Aug 15 05:25:36 PM PDT 24
Peak memory 196180 kb
Host smart-7871228b-5220-4777-a3b5-13be8791c804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103787919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.4103787919
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.375515223
Short name T379
Test name
Test status
Simulation time 1164146909 ps
CPU time 3.18 seconds
Started Aug 15 05:25:32 PM PDT 24
Finished Aug 15 05:25:35 PM PDT 24
Peak memory 198008 kb
Host smart-1209eed9-60f9-4b9c-9aa1-af4efb50f075
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375515223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.375515223
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.623263014
Short name T626
Test name
Test status
Simulation time 88159071 ps
CPU time 1.31 seconds
Started Aug 15 05:26:47 PM PDT 24
Finished Aug 15 05:26:49 PM PDT 24
Peak memory 195796 kb
Host smart-bd409513-2b8c-4a88-b966-53c407fe3710
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623263014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.623263014
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3145092002
Short name T103
Test name
Test status
Simulation time 184907733 ps
CPU time 0.99 seconds
Started Aug 15 05:25:40 PM PDT 24
Finished Aug 15 05:25:42 PM PDT 24
Peak memory 196104 kb
Host smart-a30691ed-d41e-4601-99c6-548cf3732a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145092002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3145092002
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2404607568
Short name T688
Test name
Test status
Simulation time 232339913 ps
CPU time 1.41 seconds
Started Aug 15 05:25:46 PM PDT 24
Finished Aug 15 05:25:48 PM PDT 24
Peak memory 198184 kb
Host smart-6fb3dbca-acb3-4cf1-b2c6-c865422fedc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404607568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2404607568
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1638919935
Short name T218
Test name
Test status
Simulation time 134873830 ps
CPU time 3.09 seconds
Started Aug 15 05:25:34 PM PDT 24
Finished Aug 15 05:25:37 PM PDT 24
Peak memory 198116 kb
Host smart-e8d1953f-81fc-4dcb-b3f5-18714b7cd3e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638919935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1638919935
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.4220425970
Short name T43
Test name
Test status
Simulation time 230488766 ps
CPU time 0.86 seconds
Started Aug 15 05:25:38 PM PDT 24
Finished Aug 15 05:25:39 PM PDT 24
Peak memory 213976 kb
Host smart-c2fb22a4-65a1-414e-8ce5-9fdc23390541
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220425970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.4220425970
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.590403027
Short name T215
Test name
Test status
Simulation time 51603471 ps
CPU time 1.39 seconds
Started Aug 15 05:25:51 PM PDT 24
Finished Aug 15 05:25:52 PM PDT 24
Peak memory 195612 kb
Host smart-13ee0ab2-739a-49a8-a781-aad85e940ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590403027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.590403027
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.70888860
Short name T467
Test name
Test status
Simulation time 375014593 ps
CPU time 1 seconds
Started Aug 15 05:25:48 PM PDT 24
Finished Aug 15 05:25:49 PM PDT 24
Peak memory 196504 kb
Host smart-c45e6130-3c7a-4cd6-89f3-8aadcb138001
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70888860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.70888860
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3232485332
Short name T224
Test name
Test status
Simulation time 6774085825 ps
CPU time 84.54 seconds
Started Aug 15 05:25:34 PM PDT 24
Finished Aug 15 05:26:59 PM PDT 24
Peak memory 198280 kb
Host smart-d653ef74-3150-4ce2-9a23-a75a6ab8b95c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232485332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3232485332
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3920332204
Short name T612
Test name
Test status
Simulation time 2683080207 ps
CPU time 87.91 seconds
Started Aug 15 05:26:31 PM PDT 24
Finished Aug 15 05:27:59 PM PDT 24
Peak memory 197548 kb
Host smart-741409fb-093a-458c-b56c-01e7d5237acd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3920332204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3920332204
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4209240983
Short name T513
Test name
Test status
Simulation time 35708476 ps
CPU time 0.55 seconds
Started Aug 15 05:25:39 PM PDT 24
Finished Aug 15 05:25:40 PM PDT 24
Peak memory 193920 kb
Host smart-5e035fa8-c332-4287-81a9-2dff919e151c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209240983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4209240983
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1357852523
Short name T645
Test name
Test status
Simulation time 174661282 ps
CPU time 0.73 seconds
Started Aug 15 05:25:41 PM PDT 24
Finished Aug 15 05:25:42 PM PDT 24
Peak memory 194324 kb
Host smart-cee096e2-a1de-40d1-8d07-267b9b88bc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357852523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1357852523
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.909935996
Short name T395
Test name
Test status
Simulation time 226413136 ps
CPU time 12.01 seconds
Started Aug 15 05:25:27 PM PDT 24
Finished Aug 15 05:25:39 PM PDT 24
Peak memory 197040 kb
Host smart-b7c7b9e4-6c11-4fc5-a6ff-7e0f0a4085c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909935996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.909935996
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2845759838
Short name T382
Test name
Test status
Simulation time 81048083 ps
CPU time 0.73 seconds
Started Aug 15 05:25:30 PM PDT 24
Finished Aug 15 05:25:31 PM PDT 24
Peak memory 194892 kb
Host smart-4094b3b3-35f4-4514-8c9f-18ca2b3fb886
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845759838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2845759838
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.477489816
Short name T669
Test name
Test status
Simulation time 694954527 ps
CPU time 0.93 seconds
Started Aug 15 05:25:31 PM PDT 24
Finished Aug 15 05:25:32 PM PDT 24
Peak memory 197680 kb
Host smart-eec21f47-73de-4b25-887a-82a93e12f200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477489816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.477489816
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2261620710
Short name T509
Test name
Test status
Simulation time 24118627 ps
CPU time 1.04 seconds
Started Aug 15 05:25:34 PM PDT 24
Finished Aug 15 05:25:35 PM PDT 24
Peak memory 196364 kb
Host smart-b055db6f-5a47-4d9e-857a-538a15838b73
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261620710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2261620710
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.523292336
Short name T422
Test name
Test status
Simulation time 842888091 ps
CPU time 2.98 seconds
Started Aug 15 05:25:34 PM PDT 24
Finished Aug 15 05:25:37 PM PDT 24
Peak memory 198200 kb
Host smart-66348b8a-1784-4f35-9030-8c5163015804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523292336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.523292336
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.4236528434
Short name T667
Test name
Test status
Simulation time 116518872 ps
CPU time 1.15 seconds
Started Aug 15 05:25:30 PM PDT 24
Finished Aug 15 05:25:31 PM PDT 24
Peak memory 197000 kb
Host smart-29008fb9-b26b-425e-a902-6c7deedddae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236528434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.4236528434
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.374656189
Short name T668
Test name
Test status
Simulation time 66600722 ps
CPU time 0.92 seconds
Started Aug 15 05:25:40 PM PDT 24
Finished Aug 15 05:25:41 PM PDT 24
Peak memory 196128 kb
Host smart-9f77ed42-1309-44eb-a8fb-15f0fe52e0ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374656189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.374656189
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.4279066641
Short name T655
Test name
Test status
Simulation time 411326506 ps
CPU time 4.61 seconds
Started Aug 15 05:25:46 PM PDT 24
Finished Aug 15 05:25:51 PM PDT 24
Peak memory 198028 kb
Host smart-32336d64-0b49-4e7c-9310-18e8a426a0df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279066641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.4279066641
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2576201446
Short name T42
Test name
Test status
Simulation time 396521561 ps
CPU time 0.94 seconds
Started Aug 15 05:25:29 PM PDT 24
Finished Aug 15 05:25:30 PM PDT 24
Peak memory 215064 kb
Host smart-18962eb2-e808-4d32-a286-78a3722ea810
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576201446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2576201446
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.275260726
Short name T300
Test name
Test status
Simulation time 56469725 ps
CPU time 1.04 seconds
Started Aug 15 05:25:39 PM PDT 24
Finished Aug 15 05:25:40 PM PDT 24
Peak memory 196636 kb
Host smart-177d0579-2d52-4cca-9cc4-5ac41450f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275260726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.275260726
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2716428202
Short name T205
Test name
Test status
Simulation time 57354084 ps
CPU time 1.15 seconds
Started Aug 15 05:25:35 PM PDT 24
Finished Aug 15 05:25:37 PM PDT 24
Peak memory 195976 kb
Host smart-eed9b028-8c6a-49e0-b639-363c4fcce4ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716428202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2716428202
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.779265909
Short name T650
Test name
Test status
Simulation time 4530954899 ps
CPU time 41.63 seconds
Started Aug 15 05:25:53 PM PDT 24
Finished Aug 15 05:26:35 PM PDT 24
Peak memory 198360 kb
Host smart-493d14ad-df09-4bfb-aa36-bebff49ff49b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779265909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.779265909
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3481086093
Short name T469
Test name
Test status
Simulation time 9022924036 ps
CPU time 78.42 seconds
Started Aug 15 05:25:33 PM PDT 24
Finished Aug 15 05:26:51 PM PDT 24
Peak memory 198524 kb
Host smart-3682184a-8a1b-48dd-b447-e07fefcc5afd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3481086093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3481086093
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.317714020
Short name T303
Test name
Test status
Simulation time 11027989 ps
CPU time 0.56 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 194048 kb
Host smart-8c26d23b-8578-4200-b952-6f3c3eb4ddcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317714020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.317714020
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.249886448
Short name T24
Test name
Test status
Simulation time 48123700 ps
CPU time 0.65 seconds
Started Aug 15 05:25:51 PM PDT 24
Finished Aug 15 05:25:51 PM PDT 24
Peak memory 194136 kb
Host smart-bcf4d3d4-dd89-4304-91e9-50b256acf524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249886448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.249886448
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1853668792
Short name T535
Test name
Test status
Simulation time 2550144147 ps
CPU time 18.34 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:17 PM PDT 24
Peak memory 197636 kb
Host smart-9971cde6-493c-415e-99ef-d103042314e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853668792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1853668792
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1529459101
Short name T583
Test name
Test status
Simulation time 76354334 ps
CPU time 0.93 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:55 PM PDT 24
Peak memory 197012 kb
Host smart-f75c4b9d-4442-4cc0-a4f0-aa0b9a5b2e06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529459101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1529459101
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4016388424
Short name T495
Test name
Test status
Simulation time 42932471 ps
CPU time 1.25 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 198216 kb
Host smart-10094132-f1ac-4905-99f7-3ed6340e14d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016388424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4016388424
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3653221559
Short name T402
Test name
Test status
Simulation time 287743879 ps
CPU time 3.14 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 198160 kb
Host smart-1af34a97-20f2-4421-90da-148ce6213587
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653221559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3653221559
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.4197039899
Short name T408
Test name
Test status
Simulation time 135195030 ps
CPU time 2.48 seconds
Started Aug 15 05:25:51 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 197216 kb
Host smart-890c3e65-02dc-418e-bc91-95cd8242c05c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197039899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.4197039899
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2293980413
Short name T472
Test name
Test status
Simulation time 29352864 ps
CPU time 0.82 seconds
Started Aug 15 05:26:01 PM PDT 24
Finished Aug 15 05:26:02 PM PDT 24
Peak memory 195656 kb
Host smart-8c12e4aa-a6aa-4a08-9f57-9cf38ae1cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293980413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2293980413
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3559277393
Short name T474
Test name
Test status
Simulation time 18022048 ps
CPU time 0.73 seconds
Started Aug 15 05:25:53 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 195564 kb
Host smart-3cc3cdea-cbb8-4785-a325-f56149f77030
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559277393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3559277393
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2879827054
Short name T683
Test name
Test status
Simulation time 52878654 ps
CPU time 2.48 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 198080 kb
Host smart-7f98015a-722f-4600-9f6b-13596ea2b723
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879827054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2879827054
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3422054497
Short name T106
Test name
Test status
Simulation time 36650999 ps
CPU time 0.8 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 196000 kb
Host smart-792a0134-2b41-4762-98e1-90756adbab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422054497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3422054497
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1079096483
Short name T356
Test name
Test status
Simulation time 117908382 ps
CPU time 1.1 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:25:53 PM PDT 24
Peak memory 195668 kb
Host smart-136183ba-f361-467b-9a8c-c23b0132f12a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079096483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1079096483
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.174021753
Short name T419
Test name
Test status
Simulation time 66656254109 ps
CPU time 122.49 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:27:57 PM PDT 24
Peak memory 198344 kb
Host smart-c43ceb89-a54a-40ef-a6cf-cccbb7bfcceb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174021753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.174021753
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.216169005
Short name T636
Test name
Test status
Simulation time 46872160 ps
CPU time 0.59 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 194748 kb
Host smart-974d38b2-2b0c-4a29-afba-4539b522ceb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216169005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.216169005
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2789873885
Short name T231
Test name
Test status
Simulation time 32029826 ps
CPU time 0.77 seconds
Started Aug 15 05:25:45 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 195456 kb
Host smart-7e9bfe7a-8023-499e-9f25-ea3b711758cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789873885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2789873885
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3756117309
Short name T267
Test name
Test status
Simulation time 1131184039 ps
CPU time 15.4 seconds
Started Aug 15 05:25:51 PM PDT 24
Finished Aug 15 05:26:06 PM PDT 24
Peak memory 198108 kb
Host smart-165b4823-518b-4449-8bde-3d3b2f80cc20
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756117309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3756117309
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.677742323
Short name T295
Test name
Test status
Simulation time 109193464 ps
CPU time 0.67 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 194788 kb
Host smart-64728c88-17db-469e-a0ff-3f5d381fc44b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677742323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.677742323
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2007142409
Short name T530
Test name
Test status
Simulation time 27212302 ps
CPU time 0.78 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 196200 kb
Host smart-5ef952a1-2a56-464a-84af-6714715613b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007142409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2007142409
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.252852753
Short name T109
Test name
Test status
Simulation time 97859952 ps
CPU time 2.03 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:26:00 PM PDT 24
Peak memory 198144 kb
Host smart-b307e320-2664-4f74-9952-8f0da0ba3a4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252852753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.252852753
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2366897793
Short name T529
Test name
Test status
Simulation time 63780453 ps
CPU time 0.89 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 194652 kb
Host smart-842c4c55-2ce0-4c69-95b8-0e44f383adaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366897793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2366897793
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2785022745
Short name T489
Test name
Test status
Simulation time 22149235 ps
CPU time 0.77 seconds
Started Aug 15 05:25:49 PM PDT 24
Finished Aug 15 05:25:50 PM PDT 24
Peak memory 196304 kb
Host smart-0682bf95-973c-49c8-8af9-ef29ee03eb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785022745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2785022745
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2516983868
Short name T193
Test name
Test status
Simulation time 29904520 ps
CPU time 1 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 196040 kb
Host smart-cee8c4a0-6afb-4dc7-8867-f60e7aa83f7f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516983868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2516983868
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.652783612
Short name T646
Test name
Test status
Simulation time 187924838 ps
CPU time 2.59 seconds
Started Aug 15 05:25:53 PM PDT 24
Finished Aug 15 05:25:55 PM PDT 24
Peak memory 198084 kb
Host smart-6bd75469-8f4b-46dc-9609-480ea55e41da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652783612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.652783612
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.4130384439
Short name T610
Test name
Test status
Simulation time 143837406 ps
CPU time 1.1 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:55 PM PDT 24
Peak memory 195724 kb
Host smart-fe7f6806-b60b-4e07-80fb-e79730260dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130384439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.4130384439
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2120757481
Short name T414
Test name
Test status
Simulation time 43158737 ps
CPU time 1.02 seconds
Started Aug 15 05:26:06 PM PDT 24
Finished Aug 15 05:26:07 PM PDT 24
Peak memory 195792 kb
Host smart-2aae38a3-b4e6-478c-9e81-336c796ba52b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120757481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2120757481
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.514743264
Short name T321
Test name
Test status
Simulation time 15420655131 ps
CPU time 101.46 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:27:40 PM PDT 24
Peak memory 198372 kb
Host smart-29065143-9a18-43cf-9b79-3e597809466d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514743264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.514743264
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.4010319747
Short name T60
Test name
Test status
Simulation time 4566246493 ps
CPU time 154.76 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:28:27 PM PDT 24
Peak memory 198540 kb
Host smart-97bf572e-0e4e-44d4-9432-d509c81ce1fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4010319747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.4010319747
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.286168343
Short name T416
Test name
Test status
Simulation time 42123707 ps
CPU time 0.57 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 194736 kb
Host smart-46eda405-ebdf-4379-bb73-980ecbc33418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286168343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.286168343
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3355752301
Short name T283
Test name
Test status
Simulation time 37457651 ps
CPU time 0.78 seconds
Started Aug 15 05:25:49 PM PDT 24
Finished Aug 15 05:25:50 PM PDT 24
Peak memory 195932 kb
Host smart-36b7d82e-d514-43fc-b6d4-71097fb37108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355752301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3355752301
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.104746071
Short name T284
Test name
Test status
Simulation time 115702492 ps
CPU time 5.91 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:26:00 PM PDT 24
Peak memory 196960 kb
Host smart-621131e8-cad9-4d20-b9de-c2228cb23c09
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104746071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.104746071
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1581463965
Short name T157
Test name
Test status
Simulation time 66631909 ps
CPU time 0.93 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 197828 kb
Host smart-888aee43-ab33-4e1d-9558-f0a42e0c4b13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581463965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1581463965
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.125332420
Short name T640
Test name
Test status
Simulation time 71118258 ps
CPU time 1.04 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 196988 kb
Host smart-0e44614a-ecd4-449c-9941-7a93917523ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125332420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.125332420
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1634433126
Short name T505
Test name
Test status
Simulation time 111052653 ps
CPU time 2.16 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 198116 kb
Host smart-24502145-b4cc-4476-8616-6d2b1d06068f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634433126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1634433126
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2231678466
Short name T391
Test name
Test status
Simulation time 266530848 ps
CPU time 1.96 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 197116 kb
Host smart-a722c2d0-df54-4cf4-801f-6a5297f1429a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231678466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2231678466
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2612105879
Short name T701
Test name
Test status
Simulation time 117207050 ps
CPU time 1.17 seconds
Started Aug 15 05:25:53 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 197232 kb
Host smart-e1412ec7-950a-41b1-bb5c-167c53a91e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612105879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2612105879
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1059826252
Short name T340
Test name
Test status
Simulation time 96356216 ps
CPU time 0.77 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:25:53 PM PDT 24
Peak memory 196268 kb
Host smart-eaae2c1c-3d4c-4aa0-bd1e-7ee6eb85b940
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059826252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1059826252
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.4235780899
Short name T525
Test name
Test status
Simulation time 96957014 ps
CPU time 1.78 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 198108 kb
Host smart-d5d7c9b8-63ec-4ef3-8aef-6ec6db752260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235780899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.4235780899
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2726098792
Short name T206
Test name
Test status
Simulation time 136875322 ps
CPU time 0.97 seconds
Started Aug 15 05:25:49 PM PDT 24
Finished Aug 15 05:25:50 PM PDT 24
Peak memory 196016 kb
Host smart-0d8dab5b-a671-4bf9-a6d6-08346eb07803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726098792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2726098792
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1763295414
Short name T16
Test name
Test status
Simulation time 91198444 ps
CPU time 1.36 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:01 PM PDT 24
Peak memory 196864 kb
Host smart-dac64536-c78d-4d70-89d7-12ef391b345f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763295414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1763295414
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4030027340
Short name T9
Test name
Test status
Simulation time 42556415253 ps
CPU time 109.23 seconds
Started Aug 15 05:26:04 PM PDT 24
Finished Aug 15 05:27:53 PM PDT 24
Peak memory 198336 kb
Host smart-b5f254da-6e33-41f7-aced-5aa95d11de96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030027340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4030027340
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1167976589
Short name T499
Test name
Test status
Simulation time 40320329 ps
CPU time 0.58 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 194712 kb
Host smart-50603c17-e57a-4192-9453-9275e95b0ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167976589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1167976589
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.750563461
Short name T292
Test name
Test status
Simulation time 128488618 ps
CPU time 0.92 seconds
Started Aug 15 05:26:05 PM PDT 24
Finished Aug 15 05:26:06 PM PDT 24
Peak memory 196044 kb
Host smart-2d798893-2320-466c-be5a-c9431b364c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750563461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.750563461
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2889628987
Short name T387
Test name
Test status
Simulation time 2483374881 ps
CPU time 9.94 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:26:05 PM PDT 24
Peak memory 196852 kb
Host smart-8ef8a4cd-066f-4586-ad8f-54a567abad6d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889628987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2889628987
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.466364684
Short name T320
Test name
Test status
Simulation time 125969825 ps
CPU time 0.67 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:55 PM PDT 24
Peak memory 195612 kb
Host smart-fbc5c78d-29de-4ccf-8657-79bd425acf34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466364684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.466364684
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1514055276
Short name T543
Test name
Test status
Simulation time 184404249 ps
CPU time 1.45 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 196892 kb
Host smart-b6a2d2d9-4909-4e0f-bbf3-6daf809df762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514055276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1514055276
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3456882827
Short name T390
Test name
Test status
Simulation time 1020571776 ps
CPU time 3.02 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:26:00 PM PDT 24
Peak memory 197348 kb
Host smart-304a4900-0b25-4013-9597-67dd1d74a9c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456882827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3456882827
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2413550539
Short name T334
Test name
Test status
Simulation time 104704620 ps
CPU time 1.37 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 195912 kb
Host smart-12a1de9d-d37a-445e-8f42-7bd50b41ea63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413550539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2413550539
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3729237806
Short name T638
Test name
Test status
Simulation time 259881667 ps
CPU time 1.21 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 198148 kb
Host smart-fc8e5972-f40f-4737-a6c0-c2191649491f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729237806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3729237806
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3240382568
Short name T396
Test name
Test status
Simulation time 173902631 ps
CPU time 0.96 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 196032 kb
Host smart-766e3cd8-f8a3-4afb-9782-3256e2a672e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240382568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3240382568
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.312740062
Short name T234
Test name
Test status
Simulation time 940763685 ps
CPU time 5.17 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:26:02 PM PDT 24
Peak memory 198108 kb
Host smart-3144c1f8-c6e6-47cc-b259-92361d10045e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312740062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.312740062
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3556549107
Short name T652
Test name
Test status
Simulation time 121578252 ps
CPU time 1.01 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:26:00 PM PDT 24
Peak memory 195684 kb
Host smart-0597a2b9-dc9c-4cd7-a24b-f59cfab92e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556549107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3556549107
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3604908006
Short name T693
Test name
Test status
Simulation time 90473846 ps
CPU time 1.04 seconds
Started Aug 15 05:26:06 PM PDT 24
Finished Aug 15 05:26:07 PM PDT 24
Peak memory 196488 kb
Host smart-ecf95331-2f7d-49f8-bdf6-49f2bf70c76f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604908006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3604908006
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1192875646
Short name T6
Test name
Test status
Simulation time 27769439308 ps
CPU time 169.66 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:28:46 PM PDT 24
Peak memory 198512 kb
Host smart-c49e2660-a2de-4f98-bc49-87da9f1b0190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192875646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1192875646
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.4077031327
Short name T418
Test name
Test status
Simulation time 49503902 ps
CPU time 0.56 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 194956 kb
Host smart-e9894fa9-5102-4de0-930b-1d25e0628ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077031327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.4077031327
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3181879377
Short name T450
Test name
Test status
Simulation time 25763101 ps
CPU time 0.83 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 196412 kb
Host smart-298e8143-4338-49e8-9595-fec7d5da87d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181879377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3181879377
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.174052794
Short name T448
Test name
Test status
Simulation time 349902984 ps
CPU time 12.26 seconds
Started Aug 15 05:26:03 PM PDT 24
Finished Aug 15 05:26:15 PM PDT 24
Peak memory 197152 kb
Host smart-2475f1db-338c-460c-9e3d-9c149b3204fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174052794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.174052794
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1204625772
Short name T227
Test name
Test status
Simulation time 256452652 ps
CPU time 0.98 seconds
Started Aug 15 05:25:53 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 198072 kb
Host smart-259352f1-53c3-4bfd-9356-2caf0a26d7a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204625772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1204625772
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4027675381
Short name T703
Test name
Test status
Simulation time 366920464 ps
CPU time 1.39 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 197312 kb
Host smart-d34c5e00-7c26-40ed-a0a9-9a37f795d345
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027675381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4027675381
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.352446682
Short name T213
Test name
Test status
Simulation time 45868941 ps
CPU time 1.89 seconds
Started Aug 15 05:26:09 PM PDT 24
Finished Aug 15 05:26:11 PM PDT 24
Peak memory 198104 kb
Host smart-df6c1f94-1e34-4325-9b16-155b34aae07f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352446682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.352446682
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3381226336
Short name T363
Test name
Test status
Simulation time 62701411 ps
CPU time 1.46 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 196192 kb
Host smart-a99a390e-900b-4995-a5cc-8bcd3f973cf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381226336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3381226336
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2523638654
Short name T406
Test name
Test status
Simulation time 30344154 ps
CPU time 0.91 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 196212 kb
Host smart-3761fe7b-1fcf-4cdd-a1d3-c3eaa1936efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523638654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2523638654
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.228363078
Short name T662
Test name
Test status
Simulation time 18803888 ps
CPU time 0.72 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 196196 kb
Host smart-6a5b4c45-e6ee-4456-8eea-4c58a39bbc1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228363078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.228363078
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1632360002
Short name T697
Test name
Test status
Simulation time 387902935 ps
CPU time 6.23 seconds
Started Aug 15 05:26:01 PM PDT 24
Finished Aug 15 05:26:07 PM PDT 24
Peak memory 198024 kb
Host smart-77a4d467-fc5e-42d4-a792-febf03228ca7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632360002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1632360002
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2030481986
Short name T473
Test name
Test status
Simulation time 424798297 ps
CPU time 1.34 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 196836 kb
Host smart-72685cb4-f6fe-43fb-be68-6610c360e146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030481986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2030481986
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.98263726
Short name T526
Test name
Test status
Simulation time 35683436 ps
CPU time 0.91 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 195648 kb
Host smart-63edc643-1d9f-48db-a4fb-6ba4f502328b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98263726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.98263726
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2001140605
Short name T5
Test name
Test status
Simulation time 18971625750 ps
CPU time 151.87 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:28:26 PM PDT 24
Peak memory 198340 kb
Host smart-3a646cbb-a97b-4617-9f47-3e576ab8f6cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001140605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2001140605
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.4049611395
Short name T637
Test name
Test status
Simulation time 40302851 ps
CPU time 0.57 seconds
Started Aug 15 05:26:06 PM PDT 24
Finished Aug 15 05:26:06 PM PDT 24
Peak memory 194020 kb
Host smart-bd552aaf-8539-4902-abed-a5d7ab6edc8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049611395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.4049611395
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1219091664
Short name T249
Test name
Test status
Simulation time 32893378 ps
CPU time 0.82 seconds
Started Aug 15 05:26:09 PM PDT 24
Finished Aug 15 05:26:10 PM PDT 24
Peak memory 195352 kb
Host smart-0ed6982e-f9ab-4db9-bdcc-4ca2bc2da1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219091664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1219091664
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1968755120
Short name T177
Test name
Test status
Simulation time 591734089 ps
CPU time 2.8 seconds
Started Aug 15 05:26:00 PM PDT 24
Finished Aug 15 05:26:03 PM PDT 24
Peak memory 196728 kb
Host smart-58134e5f-1c89-470a-9ba8-e7037531d46e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968755120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1968755120
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.128390358
Short name T214
Test name
Test status
Simulation time 60910713 ps
CPU time 1.05 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 196840 kb
Host smart-2f8f0846-d414-4f50-85c9-45a78128a1aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128390358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.128390358
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.613044644
Short name T169
Test name
Test status
Simulation time 129206039 ps
CPU time 0.77 seconds
Started Aug 15 05:26:11 PM PDT 24
Finished Aug 15 05:26:12 PM PDT 24
Peak memory 195628 kb
Host smart-cbfc3ebb-adcf-423b-8cf5-576328f13c77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613044644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.613044644
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.4087122212
Short name T240
Test name
Test status
Simulation time 292710054 ps
CPU time 2.94 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 198212 kb
Host smart-c90b4525-730d-4d3d-a1a4-b317f0266b29
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087122212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.4087122212
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.961282010
Short name T329
Test name
Test status
Simulation time 144082240 ps
CPU time 0.93 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 196284 kb
Host smart-70fa21c3-7900-414f-9786-a99e17bcd661
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961282010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
961282010
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2001061416
Short name T562
Test name
Test status
Simulation time 214926054 ps
CPU time 0.98 seconds
Started Aug 15 05:26:05 PM PDT 24
Finished Aug 15 05:26:07 PM PDT 24
Peak memory 196136 kb
Host smart-545d8e66-cb9f-432f-bfe4-26b79d13bf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001061416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2001061416
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3923348868
Short name T202
Test name
Test status
Simulation time 58001543 ps
CPU time 1.05 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:55 PM PDT 24
Peak memory 196836 kb
Host smart-27020adb-152d-4b27-8a2e-ce3e9c324e83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923348868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3923348868
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2444300467
Short name T307
Test name
Test status
Simulation time 586005432 ps
CPU time 3.83 seconds
Started Aug 15 05:26:01 PM PDT 24
Finished Aug 15 05:26:06 PM PDT 24
Peak memory 198124 kb
Host smart-c96098d9-f314-4d3d-9357-48c34d6ff505
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444300467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2444300467
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3139268155
Short name T492
Test name
Test status
Simulation time 81834908 ps
CPU time 0.69 seconds
Started Aug 15 05:26:05 PM PDT 24
Finished Aug 15 05:26:06 PM PDT 24
Peak memory 194984 kb
Host smart-c978cb93-d38c-468a-9d4a-74d910fd26cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139268155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3139268155
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2795924571
Short name T635
Test name
Test status
Simulation time 165577258 ps
CPU time 1.24 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 195856 kb
Host smart-8231ef3b-3d75-4024-8e77-f8c7c2c0821b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795924571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2795924571
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1026942154
Short name T477
Test name
Test status
Simulation time 9310391026 ps
CPU time 52.88 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:52 PM PDT 24
Peak memory 198332 kb
Host smart-67e24bee-70e3-4667-a7e8-470263323cc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026942154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1026942154
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3325916803
Short name T376
Test name
Test status
Simulation time 11263006 ps
CPU time 0.57 seconds
Started Aug 15 05:26:03 PM PDT 24
Finished Aug 15 05:26:04 PM PDT 24
Peak memory 193900 kb
Host smart-f4e292a3-69e1-4e0c-bbae-df6748f3aedd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325916803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3325916803
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3140457184
Short name T189
Test name
Test status
Simulation time 59960760 ps
CPU time 0.6 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 194044 kb
Host smart-e2d94f18-73aa-4c09-8c5d-f8e3d200d990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140457184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3140457184
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.51799056
Short name T180
Test name
Test status
Simulation time 2861675099 ps
CPU time 27.47 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:27 PM PDT 24
Peak memory 198292 kb
Host smart-673e4137-ad06-44d8-8eab-bd7649585f01
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51799056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stress
.51799056
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1452510782
Short name T624
Test name
Test status
Simulation time 90013490 ps
CPU time 0.98 seconds
Started Aug 15 05:26:10 PM PDT 24
Finished Aug 15 05:26:11 PM PDT 24
Peak memory 197768 kb
Host smart-0d2da842-4dba-4870-b84f-7b7c9d96a777
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452510782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1452510782
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3887227821
Short name T365
Test name
Test status
Simulation time 193772155 ps
CPU time 1.4 seconds
Started Aug 15 05:26:06 PM PDT 24
Finished Aug 15 05:26:07 PM PDT 24
Peak memory 197128 kb
Host smart-8f64e4d0-71e5-4df3-a05d-adf01af12cde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887227821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3887227821
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2218379133
Short name T531
Test name
Test status
Simulation time 76822477 ps
CPU time 1.68 seconds
Started Aug 15 05:26:05 PM PDT 24
Finished Aug 15 05:26:07 PM PDT 24
Peak memory 197012 kb
Host smart-3a970c58-c4c4-402b-b5c3-60668ea46cca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218379133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2218379133
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1720045120
Short name T181
Test name
Test status
Simulation time 99382898 ps
CPU time 1.28 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 195868 kb
Host smart-8fe08761-66f5-4990-95c8-ebedeb3fef3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720045120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1720045120
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.641422852
Short name T114
Test name
Test status
Simulation time 49096268 ps
CPU time 1.14 seconds
Started Aug 15 05:26:01 PM PDT 24
Finished Aug 15 05:26:02 PM PDT 24
Peak memory 196224 kb
Host smart-7c61b81b-6b36-46ee-8e15-698afe826fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641422852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.641422852
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.380781133
Short name T151
Test name
Test status
Simulation time 197413733 ps
CPU time 1 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:00 PM PDT 24
Peak memory 195920 kb
Host smart-da60ffc2-67d9-4e91-99e2-1bf913eb192c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380781133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.380781133
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2635363376
Short name T453
Test name
Test status
Simulation time 83896593 ps
CPU time 3.61 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:03 PM PDT 24
Peak memory 198124 kb
Host smart-5ac14f47-5eab-46fd-8f9c-1a40ae99dba6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635363376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2635363376
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1963820510
Short name T121
Test name
Test status
Simulation time 35980409 ps
CPU time 1.2 seconds
Started Aug 15 05:26:05 PM PDT 24
Finished Aug 15 05:26:06 PM PDT 24
Peak memory 198176 kb
Host smart-aa71eb00-d1a8-4f9d-993a-ec05c1759b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963820510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1963820510
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.882463009
Short name T682
Test name
Test status
Simulation time 47463076 ps
CPU time 1.01 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 196376 kb
Host smart-ecbe6905-2660-48a3-8c3a-149734093076
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882463009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.882463009
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1202519514
Short name T278
Test name
Test status
Simulation time 4735495452 ps
CPU time 52.76 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:52 PM PDT 24
Peak memory 198320 kb
Host smart-7320218e-006c-427e-b2bc-97dbb102a155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202519514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1202519514
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3045593300
Short name T576
Test name
Test status
Simulation time 3414201638 ps
CPU time 124.25 seconds
Started Aug 15 05:26:12 PM PDT 24
Finished Aug 15 05:28:17 PM PDT 24
Peak memory 198416 kb
Host smart-328d5090-1f72-4c8d-8932-58347ed5310e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3045593300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3045593300
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2663256910
Short name T204
Test name
Test status
Simulation time 39373882 ps
CPU time 0.65 seconds
Started Aug 15 05:26:09 PM PDT 24
Finished Aug 15 05:26:09 PM PDT 24
Peak memory 194052 kb
Host smart-9bc1ca6b-9608-46d5-bbd9-babb7bf72539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663256910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2663256910
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2794730199
Short name T289
Test name
Test status
Simulation time 92422667 ps
CPU time 0.86 seconds
Started Aug 15 05:26:01 PM PDT 24
Finished Aug 15 05:26:02 PM PDT 24
Peak memory 196468 kb
Host smart-99392c30-a364-47e1-b48a-a2a2724d1ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794730199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2794730199
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3325180108
Short name T471
Test name
Test status
Simulation time 625740240 ps
CPU time 16.93 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:26:13 PM PDT 24
Peak memory 196864 kb
Host smart-db1c607c-8e35-4ff6-b65d-24bb0ed6c93b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325180108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3325180108
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3594453663
Short name T647
Test name
Test status
Simulation time 183561501 ps
CPU time 0.67 seconds
Started Aug 15 05:26:10 PM PDT 24
Finished Aug 15 05:26:11 PM PDT 24
Peak memory 194648 kb
Host smart-beff3de2-f094-48de-89d9-f90a506c210f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594453663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3594453663
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.673517147
Short name T455
Test name
Test status
Simulation time 60503823 ps
CPU time 1.14 seconds
Started Aug 15 05:26:04 PM PDT 24
Finished Aug 15 05:26:05 PM PDT 24
Peak memory 196276 kb
Host smart-481c10cc-4112-47bd-b72f-d3bbbd94503a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673517147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.673517147
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3604628429
Short name T388
Test name
Test status
Simulation time 81722277 ps
CPU time 0.99 seconds
Started Aug 15 05:26:07 PM PDT 24
Finished Aug 15 05:26:08 PM PDT 24
Peak memory 196872 kb
Host smart-794f6004-a9ff-4311-8314-409a7ffab450
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604628429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3604628429
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2309930356
Short name T100
Test name
Test status
Simulation time 130967075 ps
CPU time 2.07 seconds
Started Aug 15 05:26:01 PM PDT 24
Finished Aug 15 05:26:04 PM PDT 24
Peak memory 198192 kb
Host smart-17d5d745-5d0c-4c41-800e-8dd473a504fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309930356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2309930356
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1948170330
Short name T26
Test name
Test status
Simulation time 20868737 ps
CPU time 0.65 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 194320 kb
Host smart-119dcf72-481b-4f98-9689-cfeb00ec1b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948170330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1948170330
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1823025596
Short name T551
Test name
Test status
Simulation time 57018666 ps
CPU time 1.07 seconds
Started Aug 15 05:26:16 PM PDT 24
Finished Aug 15 05:26:17 PM PDT 24
Peak memory 196100 kb
Host smart-4f0287ca-daac-461f-a434-c442793ba03b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823025596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1823025596
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3781797305
Short name T71
Test name
Test status
Simulation time 1439452308 ps
CPU time 5.13 seconds
Started Aug 15 05:26:17 PM PDT 24
Finished Aug 15 05:26:23 PM PDT 24
Peak memory 198076 kb
Host smart-0225962e-62da-4137-a9e3-37c7b971cd63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781797305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3781797305
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3425415966
Short name T59
Test name
Test status
Simulation time 80027011 ps
CPU time 0.82 seconds
Started Aug 15 05:26:17 PM PDT 24
Finished Aug 15 05:26:18 PM PDT 24
Peak memory 195412 kb
Host smart-0e06ea35-183f-4351-b677-b1e98d426220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425415966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3425415966
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1763813085
Short name T601
Test name
Test status
Simulation time 434532039 ps
CPU time 1.34 seconds
Started Aug 15 05:26:11 PM PDT 24
Finished Aug 15 05:26:13 PM PDT 24
Peak memory 196408 kb
Host smart-b084253e-06de-474d-ac7f-66ed91f28478
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763813085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1763813085
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1706871084
Short name T476
Test name
Test status
Simulation time 7765115130 ps
CPU time 82.19 seconds
Started Aug 15 05:26:01 PM PDT 24
Finished Aug 15 05:27:24 PM PDT 24
Peak memory 192340 kb
Host smart-b96f20d5-4ac5-4ac2-9e8e-fa339d6b1bc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706871084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1706871084
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1278384747
Short name T335
Test name
Test status
Simulation time 13842077 ps
CPU time 0.58 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 194728 kb
Host smart-80e6474f-18d2-4df5-bb7d-b3a82a80b635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278384747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1278384747
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2760204816
Short name T111
Test name
Test status
Simulation time 43294127 ps
CPU time 0.64 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 194856 kb
Host smart-9acd0a2f-e173-4ed8-9f9e-f2226f27d8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760204816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2760204816
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1581316327
Short name T596
Test name
Test status
Simulation time 424743353 ps
CPU time 22.24 seconds
Started Aug 15 05:26:09 PM PDT 24
Finished Aug 15 05:26:31 PM PDT 24
Peak memory 197196 kb
Host smart-03ccd99b-16cd-4a91-9192-53ddc4b43787
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581316327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1581316327
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.556629483
Short name T166
Test name
Test status
Simulation time 274192988 ps
CPU time 1.08 seconds
Started Aug 15 05:26:22 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 196520 kb
Host smart-6595964f-a0cd-4148-9c3f-716fe6cd5881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556629483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.556629483
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2700676007
Short name T196
Test name
Test status
Simulation time 39964452 ps
CPU time 0.76 seconds
Started Aug 15 05:26:10 PM PDT 24
Finished Aug 15 05:26:11 PM PDT 24
Peak memory 195564 kb
Host smart-07b82eaa-8cf0-4afc-a47b-a315489e5dfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700676007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2700676007
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2341353276
Short name T251
Test name
Test status
Simulation time 445643318 ps
CPU time 1.61 seconds
Started Aug 15 05:26:09 PM PDT 24
Finished Aug 15 05:26:11 PM PDT 24
Peak memory 196772 kb
Host smart-3b7e8fac-91bc-43fe-bd1e-0ab24d937c68
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341353276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2341353276
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.4207465457
Short name T605
Test name
Test status
Simulation time 50092547 ps
CPU time 1.57 seconds
Started Aug 15 05:26:27 PM PDT 24
Finished Aug 15 05:26:28 PM PDT 24
Peak memory 196560 kb
Host smart-64481ad6-23a6-4e29-aa2c-20fab3aa101b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207465457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.4207465457
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1708624182
Short name T512
Test name
Test status
Simulation time 267276453 ps
CPU time 1.42 seconds
Started Aug 15 05:26:02 PM PDT 24
Finished Aug 15 05:26:04 PM PDT 24
Peak memory 195940 kb
Host smart-9e1b6144-90f0-4bee-9050-ddf5be7e56f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708624182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1708624182
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1764589885
Short name T399
Test name
Test status
Simulation time 65480109 ps
CPU time 1.23 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:01 PM PDT 24
Peak memory 198220 kb
Host smart-6802e2f6-1366-40a0-9f6c-fe388d653334
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764589885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1764589885
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1105513111
Short name T124
Test name
Test status
Simulation time 825234068 ps
CPU time 1.97 seconds
Started Aug 15 05:26:03 PM PDT 24
Finished Aug 15 05:26:05 PM PDT 24
Peak memory 198092 kb
Host smart-fab12a5f-68da-4bef-8f18-17566d9997ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105513111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1105513111
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2428957550
Short name T135
Test name
Test status
Simulation time 295365695 ps
CPU time 1.01 seconds
Started Aug 15 05:26:11 PM PDT 24
Finished Aug 15 05:26:13 PM PDT 24
Peak memory 196436 kb
Host smart-a0a8841b-4798-4f2e-b6bd-09b0d8013139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428957550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2428957550
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2835693138
Short name T502
Test name
Test status
Simulation time 102367462 ps
CPU time 0.76 seconds
Started Aug 15 05:26:02 PM PDT 24
Finished Aug 15 05:26:03 PM PDT 24
Peak memory 195120 kb
Host smart-f839472b-9ffc-47bd-8009-0d60976a869c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835693138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2835693138
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.293728355
Short name T328
Test name
Test status
Simulation time 9146738447 ps
CPU time 40.69 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:26:36 PM PDT 24
Peak memory 198320 kb
Host smart-d12b76e3-db3b-4ed1-89c8-4f95f1c30576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293728355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.293728355
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2015664472
Short name T34
Test name
Test status
Simulation time 8036070589 ps
CPU time 66.68 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:27:04 PM PDT 24
Peak memory 206652 kb
Host smart-4070507a-8bf3-40f4-82b9-0dae2b5a9c97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2015664472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2015664472
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3392946629
Short name T128
Test name
Test status
Simulation time 14451489 ps
CPU time 0.57 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 194152 kb
Host smart-82e1fea2-423a-4ef3-943a-254de47c5912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392946629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3392946629
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4183310564
Short name T152
Test name
Test status
Simulation time 33090597 ps
CPU time 0.72 seconds
Started Aug 15 05:26:00 PM PDT 24
Finished Aug 15 05:26:01 PM PDT 24
Peak memory 195436 kb
Host smart-66098233-0616-4b78-ac49-8f9352ca0a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183310564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4183310564
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2626037556
Short name T230
Test name
Test status
Simulation time 284421525 ps
CPU time 8.53 seconds
Started Aug 15 05:26:17 PM PDT 24
Finished Aug 15 05:26:26 PM PDT 24
Peak memory 195628 kb
Host smart-7f46f112-b6ad-4fae-9fb6-5a625672c390
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626037556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2626037556
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2412531585
Short name T604
Test name
Test status
Simulation time 119917585 ps
CPU time 0.83 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:00 PM PDT 24
Peak memory 196004 kb
Host smart-f99c70c5-c73d-41c6-abdb-b8b8b0a2bcb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412531585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2412531585
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2809917159
Short name T56
Test name
Test status
Simulation time 28024435 ps
CPU time 0.75 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 196288 kb
Host smart-930d78d3-3841-4cae-b2d3-5eb7fa7bfd60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809917159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2809917159
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1361174221
Short name T217
Test name
Test status
Simulation time 90353715 ps
CPU time 2.8 seconds
Started Aug 15 05:26:01 PM PDT 24
Finished Aug 15 05:26:04 PM PDT 24
Peak memory 196628 kb
Host smart-03d96b52-4069-4e7e-bb7a-0d5ab9bf975d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361174221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1361174221
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3058600545
Short name T413
Test name
Test status
Simulation time 474976659 ps
CPU time 2.74 seconds
Started Aug 15 05:26:05 PM PDT 24
Finished Aug 15 05:26:08 PM PDT 24
Peak memory 198228 kb
Host smart-715a1838-0d73-4116-adfa-9388e194b7eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058600545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3058600545
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1545862143
Short name T168
Test name
Test status
Simulation time 120481463 ps
CPU time 1.28 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:26:00 PM PDT 24
Peak memory 197108 kb
Host smart-f99b727e-7143-4bd7-9d2a-a20bafd18345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545862143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1545862143
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.4208897627
Short name T208
Test name
Test status
Simulation time 23845397 ps
CPU time 0.84 seconds
Started Aug 15 05:26:00 PM PDT 24
Finished Aug 15 05:26:01 PM PDT 24
Peak memory 196932 kb
Host smart-bb686320-fde8-4e5a-95a6-4fad36e3a776
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208897627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.4208897627
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.803552784
Short name T178
Test name
Test status
Simulation time 213763045 ps
CPU time 4.72 seconds
Started Aug 15 05:26:28 PM PDT 24
Finished Aug 15 05:26:33 PM PDT 24
Peak memory 197988 kb
Host smart-d341c22b-5515-4ca0-90d3-e94e72b93b26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803552784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.803552784
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.4187626663
Short name T173
Test name
Test status
Simulation time 274987908 ps
CPU time 0.79 seconds
Started Aug 15 05:26:11 PM PDT 24
Finished Aug 15 05:26:12 PM PDT 24
Peak memory 195388 kb
Host smart-8266c763-a74a-4a23-8d80-d88a3ab00848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187626663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.4187626663
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.442995023
Short name T447
Test name
Test status
Simulation time 129431616 ps
CPU time 0.95 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:00 PM PDT 24
Peak memory 195788 kb
Host smart-22e7e990-7c9a-4b65-a42f-82a2cbd6f33d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442995023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.442995023
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2230244677
Short name T375
Test name
Test status
Simulation time 26617163 ps
CPU time 0.54 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 194748 kb
Host smart-069e0c3a-b3c9-4e01-a100-47d7e1816bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230244677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2230244677
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1052042702
Short name T245
Test name
Test status
Simulation time 66116936 ps
CPU time 0.7 seconds
Started Aug 15 05:25:32 PM PDT 24
Finished Aug 15 05:25:33 PM PDT 24
Peak memory 194144 kb
Host smart-a3110570-10ed-4ea7-8e68-a68c5d96e13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052042702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1052042702
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1084750000
Short name T588
Test name
Test status
Simulation time 471272385 ps
CPU time 12.1 seconds
Started Aug 15 05:25:33 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 197292 kb
Host smart-3d7c6900-be38-4438-9221-ad2567e6f10b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084750000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1084750000
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3548989947
Short name T580
Test name
Test status
Simulation time 66119279 ps
CPU time 0.84 seconds
Started Aug 15 05:25:45 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 197156 kb
Host smart-29628812-a5b7-4a9b-a74b-74d01f519f1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548989947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3548989947
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3500536345
Short name T698
Test name
Test status
Simulation time 995071463 ps
CPU time 1.39 seconds
Started Aug 15 05:25:44 PM PDT 24
Finished Aug 15 05:25:45 PM PDT 24
Peak memory 198180 kb
Host smart-7eafe210-22be-4458-b1b8-923f61122986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500536345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3500536345
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.737365104
Short name T554
Test name
Test status
Simulation time 45142705 ps
CPU time 1.77 seconds
Started Aug 15 05:25:39 PM PDT 24
Finished Aug 15 05:25:41 PM PDT 24
Peak memory 198216 kb
Host smart-c0a005b3-c9b6-49b4-9daa-4deea3f1cb98
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737365104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.737365104
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.450112674
Short name T260
Test name
Test status
Simulation time 432056634 ps
CPU time 3.41 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 198248 kb
Host smart-7772dae4-30fa-4048-bd18-75ea6158be2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450112674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.450112674
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1332236983
Short name T609
Test name
Test status
Simulation time 181467954 ps
CPU time 1.2 seconds
Started Aug 15 05:25:43 PM PDT 24
Finished Aug 15 05:25:45 PM PDT 24
Peak memory 197080 kb
Host smart-679f7406-cf7b-4bea-81a3-6fbb667fdcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332236983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1332236983
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2757293168
Short name T706
Test name
Test status
Simulation time 33125041 ps
CPU time 0.76 seconds
Started Aug 15 05:25:46 PM PDT 24
Finished Aug 15 05:25:47 PM PDT 24
Peak memory 195604 kb
Host smart-cdcd2c9b-8893-4797-aaed-5385d1069647
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757293168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2757293168
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2941492384
Short name T575
Test name
Test status
Simulation time 849076266 ps
CPU time 1.52 seconds
Started Aug 15 05:25:44 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 198108 kb
Host smart-3f2fc3ef-15b0-4b34-96d4-5c637e8c59c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941492384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2941492384
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.613315847
Short name T53
Test name
Test status
Simulation time 59109394 ps
CPU time 0.87 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:25:53 PM PDT 24
Peak memory 214028 kb
Host smart-b90646bf-8f65-4a55-b0d5-ff6e599fbe2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613315847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.613315847
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3748444878
Short name T117
Test name
Test status
Simulation time 108983685 ps
CPU time 0.98 seconds
Started Aug 15 05:25:45 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 195844 kb
Host smart-3fc7376b-eec6-45b5-9c2e-2159d2d513e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748444878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3748444878
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3354225751
Short name T630
Test name
Test status
Simulation time 31088325 ps
CPU time 0.91 seconds
Started Aug 15 05:25:35 PM PDT 24
Finished Aug 15 05:25:36 PM PDT 24
Peak memory 196416 kb
Host smart-e4bb36d0-6bc1-4c77-afe7-625d5ddba586
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354225751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3354225751
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.673775361
Short name T30
Test name
Test status
Simulation time 10242240893 ps
CPU time 69.33 seconds
Started Aug 15 05:25:37 PM PDT 24
Finished Aug 15 05:26:47 PM PDT 24
Peak memory 198352 kb
Host smart-e6805351-4d0e-41cc-a40a-a823709337e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673775361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.673775361
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1523500872
Short name T62
Test name
Test status
Simulation time 6699796283 ps
CPU time 28.05 seconds
Started Aug 15 05:25:51 PM PDT 24
Finished Aug 15 05:26:19 PM PDT 24
Peak memory 198496 kb
Host smart-bf0bbc12-f21d-4802-938d-bec41a4136d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1523500872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1523500872
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2312258612
Short name T579
Test name
Test status
Simulation time 35353720 ps
CPU time 0.56 seconds
Started Aug 15 05:26:23 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 194732 kb
Host smart-735bb60c-9672-4596-a445-ba56142a40d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312258612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2312258612
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2262633094
Short name T578
Test name
Test status
Simulation time 29397666 ps
CPU time 0.66 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:00 PM PDT 24
Peak memory 195064 kb
Host smart-b03839d9-8905-4c4e-aa47-6c76cea0d79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262633094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2262633094
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1202732486
Short name T394
Test name
Test status
Simulation time 1486614201 ps
CPU time 8.67 seconds
Started Aug 15 05:26:06 PM PDT 24
Finished Aug 15 05:26:15 PM PDT 24
Peak memory 197096 kb
Host smart-45e824bf-35a9-4268-8dee-bf754dffff96
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202732486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1202732486
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.4284424399
Short name T296
Test name
Test status
Simulation time 182480287 ps
CPU time 1.06 seconds
Started Aug 15 05:26:32 PM PDT 24
Finished Aug 15 05:26:33 PM PDT 24
Peak memory 196656 kb
Host smart-b87d1956-5f77-48b8-b04d-83b8fa5bae0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284424399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.4284424399
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2669349696
Short name T102
Test name
Test status
Simulation time 118157229 ps
CPU time 1.15 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:26:00 PM PDT 24
Peak memory 196608 kb
Host smart-6f827e5d-01ad-4af0-a46e-baac577ac007
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669349696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2669349696
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2159679885
Short name T244
Test name
Test status
Simulation time 76504214 ps
CPU time 1.55 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 196892 kb
Host smart-7f8b44ec-94cb-4670-bdcb-29c42eea1c75
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159679885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2159679885
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1452423048
Short name T323
Test name
Test status
Simulation time 237813981 ps
CPU time 2.54 seconds
Started Aug 15 05:26:05 PM PDT 24
Finished Aug 15 05:26:07 PM PDT 24
Peak memory 195916 kb
Host smart-7ac7339f-037f-45e2-abff-501feba3d1d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452423048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1452423048
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3435177376
Short name T201
Test name
Test status
Simulation time 108860968 ps
CPU time 1.12 seconds
Started Aug 15 05:26:13 PM PDT 24
Finished Aug 15 05:26:14 PM PDT 24
Peak memory 195960 kb
Host smart-7eced875-9f7e-4d64-ab83-dfe6a68679e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435177376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3435177376
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1452993503
Short name T237
Test name
Test status
Simulation time 54223916 ps
CPU time 1.13 seconds
Started Aug 15 05:26:13 PM PDT 24
Finished Aug 15 05:26:14 PM PDT 24
Peak memory 195960 kb
Host smart-8a9fa615-2f6f-4de2-a087-434d70b37b35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452993503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1452993503
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1349872287
Short name T437
Test name
Test status
Simulation time 855427460 ps
CPU time 4.27 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:26:03 PM PDT 24
Peak memory 198116 kb
Host smart-f54b267c-5983-42ee-9466-2d2c81318159
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349872287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1349872287
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3945665791
Short name T589
Test name
Test status
Simulation time 173285291 ps
CPU time 1.02 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:26:00 PM PDT 24
Peak memory 196672 kb
Host smart-92e616f9-195b-411b-b127-2e83b6aa0eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945665791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3945665791
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.436685017
Short name T559
Test name
Test status
Simulation time 52656074 ps
CPU time 1.42 seconds
Started Aug 15 05:26:03 PM PDT 24
Finished Aug 15 05:26:05 PM PDT 24
Peak memory 196400 kb
Host smart-5ffc4007-32cd-4625-bfba-7b5b6a516c68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436685017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.436685017
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3858329345
Short name T699
Test name
Test status
Simulation time 19227148613 ps
CPU time 182.63 seconds
Started Aug 15 05:26:33 PM PDT 24
Finished Aug 15 05:29:36 PM PDT 24
Peak memory 198352 kb
Host smart-c307d95f-bac7-4811-97f5-8d063f432cc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858329345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3858329345
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2985477237
Short name T611
Test name
Test status
Simulation time 5966412803 ps
CPU time 198.97 seconds
Started Aug 15 05:26:23 PM PDT 24
Finished Aug 15 05:29:42 PM PDT 24
Peak memory 198540 kb
Host smart-05310223-89a5-41fc-97e8-489d2ce0e56f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2985477237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2985477237
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2410641675
Short name T352
Test name
Test status
Simulation time 38212464 ps
CPU time 0.84 seconds
Started Aug 15 05:26:30 PM PDT 24
Finished Aug 15 05:26:31 PM PDT 24
Peak memory 195540 kb
Host smart-c0b84799-c723-4871-8522-874d20d7c51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410641675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2410641675
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1914642976
Short name T671
Test name
Test status
Simulation time 1076897867 ps
CPU time 17.59 seconds
Started Aug 15 05:26:31 PM PDT 24
Finished Aug 15 05:26:49 PM PDT 24
Peak memory 197016 kb
Host smart-74fc87ed-3709-451c-b938-0823724692c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914642976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1914642976
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3115669842
Short name T330
Test name
Test status
Simulation time 249791711 ps
CPU time 1.04 seconds
Started Aug 15 05:26:24 PM PDT 24
Finished Aug 15 05:26:25 PM PDT 24
Peak memory 198184 kb
Host smart-cae9df28-a49e-453b-894e-286b9cfd3b34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115669842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3115669842
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.301013300
Short name T427
Test name
Test status
Simulation time 57912118 ps
CPU time 0.69 seconds
Started Aug 15 05:26:31 PM PDT 24
Finished Aug 15 05:26:32 PM PDT 24
Peak memory 195584 kb
Host smart-66c6b25d-cc0e-4300-9a57-53f3941f08b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301013300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.301013300
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.999063671
Short name T272
Test name
Test status
Simulation time 201714629 ps
CPU time 1.19 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 195732 kb
Host smart-62be5b83-bfe1-46fd-8b47-4bbf264d7f43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999063671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
999063671
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1068608988
Short name T239
Test name
Test status
Simulation time 32857617 ps
CPU time 0.71 seconds
Started Aug 15 05:26:23 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 195140 kb
Host smart-59b7ca2e-0cf8-4fca-bb05-a226eda1c56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068608988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1068608988
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1234051066
Short name T393
Test name
Test status
Simulation time 423972006 ps
CPU time 1.29 seconds
Started Aug 15 05:26:23 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 196000 kb
Host smart-8017fbda-14ef-419f-b382-c55b9b65646d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234051066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1234051066
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1154333105
Short name T346
Test name
Test status
Simulation time 219280406 ps
CPU time 2.93 seconds
Started Aug 15 05:26:31 PM PDT 24
Finished Aug 15 05:26:34 PM PDT 24
Peak memory 198120 kb
Host smart-92a885f9-392e-4292-8d2f-761758912646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154333105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1154333105
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3082036953
Short name T55
Test name
Test status
Simulation time 33796368 ps
CPU time 0.97 seconds
Started Aug 15 05:26:22 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 196208 kb
Host smart-2a84d4aa-ae93-493e-9546-f0b2c0e7fb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082036953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3082036953
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1955442934
Short name T674
Test name
Test status
Simulation time 33082607 ps
CPU time 1.08 seconds
Started Aug 15 05:26:33 PM PDT 24
Finished Aug 15 05:26:34 PM PDT 24
Peak memory 195724 kb
Host smart-a6d486af-d5bf-4f27-a1ab-df687f00f726
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955442934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1955442934
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.116768015
Short name T8
Test name
Test status
Simulation time 32364021271 ps
CPU time 184.85 seconds
Started Aug 15 05:26:21 PM PDT 24
Finished Aug 15 05:29:26 PM PDT 24
Peak memory 198312 kb
Host smart-8ebdf124-1f5e-4559-a5ee-8aaa64be603b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116768015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.116768015
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3243415008
Short name T627
Test name
Test status
Simulation time 16338338 ps
CPU time 0.55 seconds
Started Aug 15 05:26:22 PM PDT 24
Finished Aug 15 05:26:23 PM PDT 24
Peak memory 193996 kb
Host smart-77972b17-1623-4aee-8e86-d8d7dac06f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243415008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3243415008
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3341694873
Short name T433
Test name
Test status
Simulation time 31188209 ps
CPU time 0.98 seconds
Started Aug 15 05:26:24 PM PDT 24
Finished Aug 15 05:26:25 PM PDT 24
Peak memory 195840 kb
Host smart-7430631d-dd72-478e-89e2-32b7ac166364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341694873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3341694873
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2050370266
Short name T702
Test name
Test status
Simulation time 649243942 ps
CPU time 6.32 seconds
Started Aug 15 05:26:28 PM PDT 24
Finished Aug 15 05:26:35 PM PDT 24
Peak memory 197104 kb
Host smart-24f49cca-f3f2-4958-9f3f-48a2544c9de8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050370266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2050370266
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2687256885
Short name T506
Test name
Test status
Simulation time 189107695 ps
CPU time 0.85 seconds
Started Aug 15 05:26:23 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 195940 kb
Host smart-f22709bf-661a-49f0-8f71-91b9cf5b4d6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687256885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2687256885
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1548677336
Short name T331
Test name
Test status
Simulation time 55234275 ps
CPU time 0.99 seconds
Started Aug 15 05:26:33 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 195912 kb
Host smart-b0b2ea3d-a3fd-490d-bfd8-f10386262a31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548677336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1548677336
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3824758777
Short name T326
Test name
Test status
Simulation time 303127058 ps
CPU time 2.91 seconds
Started Aug 15 05:26:29 PM PDT 24
Finished Aug 15 05:26:32 PM PDT 24
Peak memory 196416 kb
Host smart-211cd72c-de97-4207-994a-442eb6bfa27e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824758777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3824758777
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.182342704
Short name T203
Test name
Test status
Simulation time 394975437 ps
CPU time 1.08 seconds
Started Aug 15 05:26:30 PM PDT 24
Finished Aug 15 05:26:32 PM PDT 24
Peak memory 195780 kb
Host smart-6606c8e6-7448-4140-a748-c60d2e100caa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182342704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
182342704
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3070829333
Short name T324
Test name
Test status
Simulation time 23758905 ps
CPU time 0.97 seconds
Started Aug 15 05:26:32 PM PDT 24
Finished Aug 15 05:26:33 PM PDT 24
Peak memory 196192 kb
Host smart-75677b87-aa88-40ec-8eb2-7243be5ae263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070829333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3070829333
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1929339993
Short name T617
Test name
Test status
Simulation time 34039184 ps
CPU time 1.31 seconds
Started Aug 15 05:26:23 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 198180 kb
Host smart-7554c548-2b11-4b90-a29d-9bd75fff8b38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929339993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1929339993
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3193029485
Short name T364
Test name
Test status
Simulation time 66114152 ps
CPU time 1.41 seconds
Started Aug 15 05:26:22 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 198112 kb
Host smart-53ed12fc-737a-488f-99e4-d6803cb4a578
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193029485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3193029485
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.960562518
Short name T198
Test name
Test status
Simulation time 27198091 ps
CPU time 0.76 seconds
Started Aug 15 05:26:28 PM PDT 24
Finished Aug 15 05:26:29 PM PDT 24
Peak memory 195388 kb
Host smart-09e609fd-2663-4f44-8047-fa9916c82e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960562518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.960562518
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2347244441
Short name T389
Test name
Test status
Simulation time 69117075 ps
CPU time 0.75 seconds
Started Aug 15 05:26:32 PM PDT 24
Finished Aug 15 05:26:32 PM PDT 24
Peak memory 194956 kb
Host smart-c5d4505f-34b5-4c15-898b-aa9553243baa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347244441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2347244441
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2863852994
Short name T401
Test name
Test status
Simulation time 43471466724 ps
CPU time 145.37 seconds
Started Aug 15 05:26:31 PM PDT 24
Finished Aug 15 05:28:57 PM PDT 24
Peak memory 198368 kb
Host smart-e8b6d3e8-178f-4a09-8876-5a7df8650cba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863852994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2863852994
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.918848538
Short name T20
Test name
Test status
Simulation time 32893034 ps
CPU time 0.62 seconds
Started Aug 15 05:26:24 PM PDT 24
Finished Aug 15 05:26:25 PM PDT 24
Peak memory 194220 kb
Host smart-1fdad577-4a39-41b4-b92c-2cefb7ea6934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918848538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.918848538
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3270179950
Short name T615
Test name
Test status
Simulation time 19762333 ps
CPU time 0.71 seconds
Started Aug 15 05:26:23 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 194860 kb
Host smart-78a26937-9912-47e6-a13a-b56e8eddc18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270179950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3270179950
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1331902888
Short name T150
Test name
Test status
Simulation time 570972133 ps
CPU time 6.47 seconds
Started Aug 15 05:26:24 PM PDT 24
Finished Aug 15 05:26:31 PM PDT 24
Peak memory 197128 kb
Host smart-eaf166ff-c711-4cec-8541-b479339d5d7d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331902888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1331902888
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.842899937
Short name T417
Test name
Test status
Simulation time 93901445 ps
CPU time 1.05 seconds
Started Aug 15 05:26:24 PM PDT 24
Finished Aug 15 05:26:26 PM PDT 24
Peak memory 198024 kb
Host smart-a1371e35-3a17-413f-bd8e-61c08923d450
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842899937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.842899937
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1096697814
Short name T710
Test name
Test status
Simulation time 82107131 ps
CPU time 1.18 seconds
Started Aug 15 05:26:23 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 195892 kb
Host smart-3cd35091-cd9c-409a-a44e-26091068ce22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096697814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1096697814
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1584363922
Short name T67
Test name
Test status
Simulation time 41681881 ps
CPU time 1.78 seconds
Started Aug 15 05:26:33 PM PDT 24
Finished Aug 15 05:26:35 PM PDT 24
Peak memory 198216 kb
Host smart-c8a09cbf-9129-46fa-811f-f6827627808d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584363922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1584363922
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3514771299
Short name T424
Test name
Test status
Simulation time 200780260 ps
CPU time 2.05 seconds
Started Aug 15 05:26:30 PM PDT 24
Finished Aug 15 05:26:32 PM PDT 24
Peak memory 196496 kb
Host smart-6ebd6656-88c9-4fa5-b951-634874ebe1c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514771299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3514771299
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2407592101
Short name T247
Test name
Test status
Simulation time 205375944 ps
CPU time 1.37 seconds
Started Aug 15 05:26:24 PM PDT 24
Finished Aug 15 05:26:25 PM PDT 24
Peak memory 197028 kb
Host smart-8def8a89-459c-4a85-9cd3-75a3dbcbb1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407592101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2407592101
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.772096834
Short name T351
Test name
Test status
Simulation time 78021582 ps
CPU time 1.13 seconds
Started Aug 15 05:26:25 PM PDT 24
Finished Aug 15 05:26:26 PM PDT 24
Peak memory 196684 kb
Host smart-16758aa1-b0d0-4935-8c6c-b25b322dd0c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772096834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.772096834
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.119970109
Short name T545
Test name
Test status
Simulation time 606344897 ps
CPU time 5.8 seconds
Started Aug 15 05:26:25 PM PDT 24
Finished Aug 15 05:26:30 PM PDT 24
Peak memory 198148 kb
Host smart-efd696e5-7d25-40f9-8099-f6b6f65dae2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119970109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.119970109
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3748584789
Short name T593
Test name
Test status
Simulation time 27876838 ps
CPU time 0.98 seconds
Started Aug 15 05:26:23 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 195700 kb
Host smart-e7aafed8-e7b6-44ff-a508-684c6f5bfd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748584789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3748584789
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3852792896
Short name T316
Test name
Test status
Simulation time 53900832 ps
CPU time 0.85 seconds
Started Aug 15 05:26:32 PM PDT 24
Finished Aug 15 05:26:33 PM PDT 24
Peak memory 195596 kb
Host smart-df3e5552-8176-4819-bbc6-e2358464b948
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852792896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3852792896
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3020194528
Short name T461
Test name
Test status
Simulation time 3775241775 ps
CPU time 44.67 seconds
Started Aug 15 05:26:25 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 198304 kb
Host smart-8d8871ea-1dc7-4c15-b97e-0aff4f15c05b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020194528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3020194528
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.707073477
Short name T66
Test name
Test status
Simulation time 2040989672 ps
CPU time 67.67 seconds
Started Aug 15 05:26:23 PM PDT 24
Finished Aug 15 05:27:31 PM PDT 24
Peak memory 198364 kb
Host smart-390faee1-593c-431f-8c86-96b19964d0f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=707073477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.707073477
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.648389833
Short name T435
Test name
Test status
Simulation time 14169896 ps
CPU time 0.56 seconds
Started Aug 15 05:26:39 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 194224 kb
Host smart-89ce7d68-5f5a-458b-a858-5f430992321f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648389833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.648389833
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2782170017
Short name T141
Test name
Test status
Simulation time 46556977 ps
CPU time 0.73 seconds
Started Aug 15 05:26:34 PM PDT 24
Finished Aug 15 05:26:35 PM PDT 24
Peak memory 195380 kb
Host smart-eeaa20c8-92e6-4e10-b104-f68a73faebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782170017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2782170017
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2798255161
Short name T603
Test name
Test status
Simulation time 5419104510 ps
CPU time 18.83 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:55 PM PDT 24
Peak memory 197556 kb
Host smart-e8ba0a8b-bd44-4fd3-b2c6-d214d7b21a26
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798255161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2798255161
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1991657430
Short name T220
Test name
Test status
Simulation time 36942825 ps
CPU time 0.76 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 195908 kb
Host smart-64001d27-27c4-4008-bd31-caedda441a8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991657430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1991657430
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3522462348
Short name T113
Test name
Test status
Simulation time 44715111 ps
CPU time 1.3 seconds
Started Aug 15 05:26:34 PM PDT 24
Finished Aug 15 05:26:35 PM PDT 24
Peak memory 197268 kb
Host smart-0620068e-ef8b-4dd6-b444-6082ca0953bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522462348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3522462348
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2394860668
Short name T344
Test name
Test status
Simulation time 32288926 ps
CPU time 1.23 seconds
Started Aug 15 05:26:35 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 196756 kb
Host smart-23da5b1e-7066-4cb7-b621-d7a3593f2ac8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394860668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2394860668
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2878890690
Short name T704
Test name
Test status
Simulation time 188460166 ps
CPU time 1.15 seconds
Started Aug 15 05:26:35 PM PDT 24
Finished Aug 15 05:26:36 PM PDT 24
Peak memory 195740 kb
Host smart-68d8205c-5cb0-42ad-b2f8-9ea4aa66c5b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878890690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2878890690
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1738164149
Short name T439
Test name
Test status
Simulation time 33337943 ps
CPU time 0.84 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 196436 kb
Host smart-0e36882b-0310-4616-9d77-fee0517644bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738164149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1738164149
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.272853185
Short name T400
Test name
Test status
Simulation time 27399896 ps
CPU time 1.07 seconds
Started Aug 15 05:26:35 PM PDT 24
Finished Aug 15 05:26:36 PM PDT 24
Peak memory 195992 kb
Host smart-34af8dd6-54e3-4956-b405-8061df6717cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272853185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.272853185
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3127242381
Short name T274
Test name
Test status
Simulation time 612758888 ps
CPU time 1.73 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 197840 kb
Host smart-a52eb1a6-f940-43ca-bd73-a986716f6c45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127242381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3127242381
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2143249434
Short name T211
Test name
Test status
Simulation time 38350452 ps
CPU time 0.98 seconds
Started Aug 15 05:26:29 PM PDT 24
Finished Aug 15 05:26:30 PM PDT 24
Peak memory 196540 kb
Host smart-de1979f0-5d43-4b04-bf0d-e0705a94289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143249434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2143249434
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2148488149
Short name T156
Test name
Test status
Simulation time 34593790 ps
CPU time 1.03 seconds
Started Aug 15 05:26:23 PM PDT 24
Finished Aug 15 05:26:24 PM PDT 24
Peak memory 195740 kb
Host smart-6baee7e1-7e1b-4a63-8362-242c66b4b85f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148488149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2148488149
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1566506230
Short name T560
Test name
Test status
Simulation time 19099819983 ps
CPU time 69.43 seconds
Started Aug 15 05:26:33 PM PDT 24
Finished Aug 15 05:27:43 PM PDT 24
Peak memory 198240 kb
Host smart-97174a42-bf5a-4dbe-849f-81e2f9eca20f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566506230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1566506230
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3242331312
Short name T314
Test name
Test status
Simulation time 12663063 ps
CPU time 0.56 seconds
Started Aug 15 05:26:44 PM PDT 24
Finished Aug 15 05:26:45 PM PDT 24
Peak memory 194748 kb
Host smart-b647e064-349e-4cf1-a59e-ef50522d00c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242331312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3242331312
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2820852701
Short name T463
Test name
Test status
Simulation time 30947666 ps
CPU time 0.89 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 195184 kb
Host smart-1001dd99-3686-4749-b846-518079424508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820852701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2820852701
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2660278730
Short name T258
Test name
Test status
Simulation time 186623993 ps
CPU time 8.95 seconds
Started Aug 15 05:26:51 PM PDT 24
Finished Aug 15 05:27:00 PM PDT 24
Peak memory 197096 kb
Host smart-6f06aacb-f925-48bb-b384-037fda928dae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660278730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2660278730
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.4076186439
Short name T223
Test name
Test status
Simulation time 26380543 ps
CPU time 0.65 seconds
Started Aug 15 05:26:41 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 195324 kb
Host smart-e61035db-f0ac-4ee4-b0e0-605bdba89995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076186439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.4076186439
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2199474659
Short name T434
Test name
Test status
Simulation time 45974775 ps
CPU time 1.18 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 196248 kb
Host smart-18ffded3-c450-445e-951b-0e6f2d50a88b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199474659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2199474659
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3063125096
Short name T368
Test name
Test status
Simulation time 353254453 ps
CPU time 3.04 seconds
Started Aug 15 05:26:47 PM PDT 24
Finished Aug 15 05:26:50 PM PDT 24
Peak memory 198168 kb
Host smart-e993212d-fdf6-44ac-a9a9-50c18c672723
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063125096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3063125096
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2977902114
Short name T137
Test name
Test status
Simulation time 54689572 ps
CPU time 1.92 seconds
Started Aug 15 05:26:34 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 197032 kb
Host smart-298d71c4-821d-43ee-b6f5-f88d65402b5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977902114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2977902114
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3744953505
Short name T226
Test name
Test status
Simulation time 210749153 ps
CPU time 1.27 seconds
Started Aug 15 05:26:41 PM PDT 24
Finished Aug 15 05:26:43 PM PDT 24
Peak memory 197088 kb
Host smart-04177ecf-08cd-4235-bcd7-315a6e17373c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744953505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3744953505
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3009204166
Short name T57
Test name
Test status
Simulation time 119185148 ps
CPU time 0.88 seconds
Started Aug 15 05:26:35 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 195940 kb
Host smart-e9a72b1f-8df9-4d77-9135-245a600d3a7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009204166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3009204166
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2597862028
Short name T591
Test name
Test status
Simulation time 383726405 ps
CPU time 2.74 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 197752 kb
Host smart-701502b1-710f-441a-8fe6-f5c70bdda6cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597862028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2597862028
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1059605940
Short name T254
Test name
Test status
Simulation time 147443439 ps
CPU time 1.04 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 195768 kb
Host smart-e72ed8fe-e9ec-4562-8c29-ac741498e9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059605940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1059605940
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.4255660382
Short name T238
Test name
Test status
Simulation time 209128702 ps
CPU time 1.15 seconds
Started Aug 15 05:26:34 PM PDT 24
Finished Aug 15 05:26:36 PM PDT 24
Peak memory 195648 kb
Host smart-a989cc5b-6411-41b0-a85a-1db3be764fda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255660382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.4255660382
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.922488754
Short name T3
Test name
Test status
Simulation time 12982781444 ps
CPU time 70.03 seconds
Started Aug 15 05:26:35 PM PDT 24
Finished Aug 15 05:27:46 PM PDT 24
Peak memory 198340 kb
Host smart-d133dbdc-c9ea-4456-a3e4-7d4493c9a928
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922488754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.922488754
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.646548934
Short name T61
Test name
Test status
Simulation time 14653598546 ps
CPU time 120.44 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:28:37 PM PDT 24
Peak memory 198532 kb
Host smart-8e0b4ad8-675c-43e0-872d-615ac8acc7be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=646548934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.646548934
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3144376030
Short name T281
Test name
Test status
Simulation time 46253512 ps
CPU time 0.58 seconds
Started Aug 15 05:26:34 PM PDT 24
Finished Aug 15 05:26:35 PM PDT 24
Peak memory 194712 kb
Host smart-a5dda6b8-0fe2-45c1-a11b-04fa0b531b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144376030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3144376030
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.735517351
Short name T195
Test name
Test status
Simulation time 31778904 ps
CPU time 0.91 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 196824 kb
Host smart-72208237-b21e-4ed0-b4ac-7fe311d0b38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735517351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.735517351
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.392137425
Short name T187
Test name
Test status
Simulation time 476098212 ps
CPU time 12.94 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:26:50 PM PDT 24
Peak memory 197224 kb
Host smart-d3a01b7b-e4f2-48df-8443-949ef2997344
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392137425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.392137425
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1658769573
Short name T299
Test name
Test status
Simulation time 59599568 ps
CPU time 0.88 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 196836 kb
Host smart-f8278303-ece8-4576-9272-d03ccb0a03a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658769573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1658769573
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1824710156
Short name T120
Test name
Test status
Simulation time 38232421 ps
CPU time 0.97 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 196172 kb
Host smart-38f4d6e7-60e1-481c-af3d-c4cba25a7c26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824710156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1824710156
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.780879762
Short name T171
Test name
Test status
Simulation time 303093167 ps
CPU time 2.83 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 198148 kb
Host smart-2287bca2-2438-49af-afb4-6f59871f4cf9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780879762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.780879762
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1161758274
Short name T517
Test name
Test status
Simulation time 348579626 ps
CPU time 2.81 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 198188 kb
Host smart-b0d39d3c-ced1-419d-a625-f4e7237bef39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161758274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1161758274
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1520690710
Short name T661
Test name
Test status
Simulation time 170601216 ps
CPU time 0.97 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 196872 kb
Host smart-9eb979df-dff9-4742-b96f-2c014e2f69d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520690710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1520690710
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.866896522
Short name T232
Test name
Test status
Simulation time 33895445 ps
CPU time 1.08 seconds
Started Aug 15 05:26:34 PM PDT 24
Finished Aug 15 05:26:35 PM PDT 24
Peak memory 196708 kb
Host smart-c8ee16e3-c564-4b3b-8f09-9784c078583d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866896522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.866896522
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2761262015
Short name T250
Test name
Test status
Simulation time 119327728 ps
CPU time 4.79 seconds
Started Aug 15 05:26:34 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 198060 kb
Host smart-e8546fe2-0933-42bf-a5fb-03b9186447ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761262015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2761262015
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.68030980
Short name T207
Test name
Test status
Simulation time 64929078 ps
CPU time 1.24 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 198124 kb
Host smart-9906f0c2-9fc1-4c78-a67f-bc71c954f8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68030980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.68030980
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3672031593
Short name T361
Test name
Test status
Simulation time 104343684 ps
CPU time 0.85 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 197272 kb
Host smart-f4387b89-eecf-4ad5-b52c-0f1bda937bc1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672031593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3672031593
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2976377515
Short name T10
Test name
Test status
Simulation time 19131908444 ps
CPU time 45.91 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:27:24 PM PDT 24
Peak memory 198252 kb
Host smart-ebca05e4-1c1e-458e-b429-e3c80cb14b8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976377515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2976377515
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.522762399
Short name T585
Test name
Test status
Simulation time 34846682 ps
CPU time 0.58 seconds
Started Aug 15 05:26:43 PM PDT 24
Finished Aug 15 05:26:43 PM PDT 24
Peak memory 193988 kb
Host smart-05fd41bb-3419-4e03-b1b8-e383d73eefe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522762399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.522762399
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2383554642
Short name T276
Test name
Test status
Simulation time 37932620 ps
CPU time 0.88 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 195992 kb
Host smart-750f0863-1099-4256-bc12-6b895693e56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383554642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2383554642
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.4252610997
Short name T374
Test name
Test status
Simulation time 414681077 ps
CPU time 3.75 seconds
Started Aug 15 05:26:35 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 196416 kb
Host smart-e079a78c-e070-4775-9e5c-facec65fd63b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252610997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.4252610997
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.41936655
Short name T411
Test name
Test status
Simulation time 153061309 ps
CPU time 0.8 seconds
Started Aug 15 05:26:34 PM PDT 24
Finished Aug 15 05:26:35 PM PDT 24
Peak memory 196016 kb
Host smart-48c19267-1fe7-4bba-a685-ef995c3f5a1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41936655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.41936655
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2511312571
Short name T185
Test name
Test status
Simulation time 18777425 ps
CPU time 0.69 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:52 PM PDT 24
Peak memory 194484 kb
Host smart-4f8997e0-417a-4cd6-a929-c627e0f67352
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511312571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2511312571
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1512258458
Short name T31
Test name
Test status
Simulation time 673402855 ps
CPU time 2.62 seconds
Started Aug 15 05:26:35 PM PDT 24
Finished Aug 15 05:26:38 PM PDT 24
Peak memory 198160 kb
Host smart-3ece43d6-f3fd-4f87-a3cc-a409148adb86
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512258458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1512258458
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.148218873
Short name T358
Test name
Test status
Simulation time 429102978 ps
CPU time 3.19 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 197228 kb
Host smart-35c234a6-79a9-46e4-80da-c4d2074a9338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148218873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
148218873
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3682428736
Short name T429
Test name
Test status
Simulation time 39401202 ps
CPU time 0.9 seconds
Started Aug 15 05:26:33 PM PDT 24
Finished Aug 15 05:26:35 PM PDT 24
Peak memory 195964 kb
Host smart-a7a036c9-f148-4676-855b-62d1e40b5119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682428736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3682428736
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.621497308
Short name T690
Test name
Test status
Simulation time 207502339 ps
CPU time 1.23 seconds
Started Aug 15 05:26:46 PM PDT 24
Finished Aug 15 05:26:47 PM PDT 24
Peak memory 197072 kb
Host smart-450f615c-05dd-4596-bdc0-0d9166b9c200
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621497308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.621497308
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1210808077
Short name T538
Test name
Test status
Simulation time 443144681 ps
CPU time 2.15 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 198116 kb
Host smart-3bf22d80-2fb9-49de-b444-74bd5bc32385
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210808077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1210808077
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1145060059
Short name T520
Test name
Test status
Simulation time 136571068 ps
CPU time 1.28 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 196868 kb
Host smart-26ab1089-cc66-4e81-b7fe-3283a6b31d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145060059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1145060059
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.940886504
Short name T397
Test name
Test status
Simulation time 111674879 ps
CPU time 1.12 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:26:38 PM PDT 24
Peak memory 196632 kb
Host smart-348a47fb-428e-4d00-86d9-a78b2968f538
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940886504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.940886504
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2120422687
Short name T280
Test name
Test status
Simulation time 1702099686 ps
CPU time 16.57 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 198180 kb
Host smart-0b19de78-b91b-4303-97ec-40ec73ac1942
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120422687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2120422687
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3703445008
Short name T507
Test name
Test status
Simulation time 50954685 ps
CPU time 0.58 seconds
Started Aug 15 05:26:47 PM PDT 24
Finished Aug 15 05:26:48 PM PDT 24
Peak memory 194272 kb
Host smart-4cec3b20-f7b8-4f47-bc50-9607a5a5f406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703445008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3703445008
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1755049873
Short name T38
Test name
Test status
Simulation time 22683753 ps
CPU time 0.69 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 194868 kb
Host smart-f9ae65f9-489c-4ced-b5b0-e3fc64d3bf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755049873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1755049873
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.566060040
Short name T694
Test name
Test status
Simulation time 179910083 ps
CPU time 4.21 seconds
Started Aug 15 05:26:48 PM PDT 24
Finished Aug 15 05:26:52 PM PDT 24
Peak memory 195932 kb
Host smart-4fc66f99-356f-46c7-8f8e-efdb4f9d0e74
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566060040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.566060040
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2468192145
Short name T319
Test name
Test status
Simulation time 387071074 ps
CPU time 1.1 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 196512 kb
Host smart-cfeb25f1-4951-4c31-87fd-3c551de87222
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468192145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2468192145
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.198112191
Short name T222
Test name
Test status
Simulation time 189381447 ps
CPU time 1.38 seconds
Started Aug 15 05:26:46 PM PDT 24
Finished Aug 15 05:26:48 PM PDT 24
Peak memory 198228 kb
Host smart-d95eec3c-6f8e-4e5b-9b04-2aebeaf3ddd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198112191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.198112191
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3163282107
Short name T565
Test name
Test status
Simulation time 113791191 ps
CPU time 1.52 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 198028 kb
Host smart-b240bfc1-0c0c-4c40-84ad-d2b10765c276
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163282107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3163282107
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3910366927
Short name T532
Test name
Test status
Simulation time 77295236 ps
CPU time 1.33 seconds
Started Aug 15 05:26:47 PM PDT 24
Finished Aug 15 05:26:49 PM PDT 24
Peak memory 196912 kb
Host smart-7bc3d9cb-6273-4971-b31e-7d0528ef0035
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910366927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3910366927
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1150321918
Short name T285
Test name
Test status
Simulation time 113479425 ps
CPU time 1.29 seconds
Started Aug 15 05:26:35 PM PDT 24
Finished Aug 15 05:26:36 PM PDT 24
Peak memory 198140 kb
Host smart-d925f4be-81ca-40a1-9af1-b836eebf5198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150321918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1150321918
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.599138826
Short name T656
Test name
Test status
Simulation time 48951207 ps
CPU time 0.81 seconds
Started Aug 15 05:26:35 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 195616 kb
Host smart-5f9ad614-efbb-4006-ba92-3694f53e46c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599138826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.599138826
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3156895500
Short name T378
Test name
Test status
Simulation time 272523558 ps
CPU time 3.4 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 198124 kb
Host smart-c58eac7f-fc64-4e35-aa61-99e7596051ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156895500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3156895500
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3392167445
Short name T381
Test name
Test status
Simulation time 87072608 ps
CPU time 1.33 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 195692 kb
Host smart-f4e81332-8062-4f78-ba9f-bfc827d1c0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392167445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3392167445
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3502139221
Short name T678
Test name
Test status
Simulation time 508393075 ps
CPU time 1.29 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 196404 kb
Host smart-070d8133-21df-435a-aa6d-12cebb90132b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502139221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3502139221
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.497632109
Short name T548
Test name
Test status
Simulation time 34101379120 ps
CPU time 129.2 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:28:48 PM PDT 24
Peak memory 197940 kb
Host smart-b1af065f-7e5d-44b0-8be7-6fb217f847c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497632109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.497632109
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3319272736
Short name T633
Test name
Test status
Simulation time 5227271421 ps
CPU time 170.95 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:29:28 PM PDT 24
Peak memory 198500 kb
Host smart-e25d2b86-ea77-40fb-af64-196d83feef73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3319272736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3319272736
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1694521417
Short name T386
Test name
Test status
Simulation time 40234062 ps
CPU time 0.61 seconds
Started Aug 15 05:26:48 PM PDT 24
Finished Aug 15 05:26:48 PM PDT 24
Peak memory 194016 kb
Host smart-54512a8f-d67f-4906-85c3-b40608fa63c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694521417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1694521417
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2050568610
Short name T159
Test name
Test status
Simulation time 39609555 ps
CPU time 0.75 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:26:51 PM PDT 24
Peak memory 195332 kb
Host smart-73716cb5-04e8-4ee9-9f0c-016e22212deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050568610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2050568610
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.385206304
Short name T145
Test name
Test status
Simulation time 2343247708 ps
CPU time 25.3 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:27:06 PM PDT 24
Peak memory 198328 kb
Host smart-b7015372-8682-49d2-90d6-8063735cffec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385206304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.385206304
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.130278466
Short name T252
Test name
Test status
Simulation time 114163821 ps
CPU time 0.86 seconds
Started Aug 15 05:26:41 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 198024 kb
Host smart-ec934d2f-f4bd-4367-8e08-676a5ca1d1c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130278466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.130278466
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3445803939
Short name T338
Test name
Test status
Simulation time 108130751 ps
CPU time 1.14 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:38 PM PDT 24
Peak memory 196200 kb
Host smart-7835295b-80a2-4391-afa7-1542ed7f714b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445803939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3445803939
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1463535665
Short name T188
Test name
Test status
Simulation time 304597817 ps
CPU time 3 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 198064 kb
Host smart-baef5934-b4df-4224-8cad-fc50fdcfebc7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463535665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1463535665
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1184965386
Short name T582
Test name
Test status
Simulation time 100072245 ps
CPU time 1.51 seconds
Started Aug 15 05:26:42 PM PDT 24
Finished Aug 15 05:26:44 PM PDT 24
Peak memory 196232 kb
Host smart-76d40707-6db7-4356-90d8-169500199fa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184965386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1184965386
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1445918295
Short name T160
Test name
Test status
Simulation time 70781815 ps
CPU time 1.29 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 197044 kb
Host smart-cfa901c1-dfcd-47c7-8128-7a644c241abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445918295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1445918295
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2824529738
Short name T709
Test name
Test status
Simulation time 43163492 ps
CPU time 0.85 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:38 PM PDT 24
Peak memory 197472 kb
Host smart-9fb737b9-d116-436a-9702-be01b5da792a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824529738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2824529738
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3887314376
Short name T456
Test name
Test status
Simulation time 247936152 ps
CPU time 6.16 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:45 PM PDT 24
Peak memory 197868 kb
Host smart-e4920106-5e04-488a-a979-093fdb69a8be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887314376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3887314376
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2953040791
Short name T304
Test name
Test status
Simulation time 55403949 ps
CPU time 1 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 195800 kb
Host smart-e6150b2a-d70d-4f0c-980f-73f62b1d47c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953040791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2953040791
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.569198297
Short name T503
Test name
Test status
Simulation time 128101531 ps
CPU time 1.22 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 195688 kb
Host smart-a5df3a1d-37d9-4b10-ad0b-093eb0d0cf1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569198297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.569198297
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.891413677
Short name T345
Test name
Test status
Simulation time 90896578679 ps
CPU time 207.92 seconds
Started Aug 15 05:26:43 PM PDT 24
Finished Aug 15 05:30:12 PM PDT 24
Peak memory 198292 kb
Host smart-847f0444-a682-4ce5-99eb-1660f66d87ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891413677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.891413677
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.873890096
Short name T700
Test name
Test status
Simulation time 688852223 ps
CPU time 24.17 seconds
Started Aug 15 05:26:48 PM PDT 24
Finished Aug 15 05:27:12 PM PDT 24
Peak memory 197720 kb
Host smart-acf1bf11-dd2e-4f16-89ce-8c3c2688a68a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=873890096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.873890096
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1717972595
Short name T705
Test name
Test status
Simulation time 13794800 ps
CPU time 0.59 seconds
Started Aug 15 05:25:47 PM PDT 24
Finished Aug 15 05:25:48 PM PDT 24
Peak memory 194008 kb
Host smart-af704b17-c6c7-4c3a-8d62-a36a794b60cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717972595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1717972595
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2383982818
Short name T127
Test name
Test status
Simulation time 76256429 ps
CPU time 0.64 seconds
Started Aug 15 05:25:53 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 194132 kb
Host smart-bb738637-1082-443b-96f0-89e5b3c1ddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383982818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2383982818
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1273069150
Short name T383
Test name
Test status
Simulation time 292294044 ps
CPU time 15.32 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:26:10 PM PDT 24
Peak memory 196832 kb
Host smart-cd6d25d2-30a5-4e3f-a4e3-67d509f14d1d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273069150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1273069150
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3571053209
Short name T464
Test name
Test status
Simulation time 34209396 ps
CPU time 0.72 seconds
Started Aug 15 05:25:45 PM PDT 24
Finished Aug 15 05:25:45 PM PDT 24
Peak memory 194708 kb
Host smart-e3d238a2-457e-4481-9685-ad11921a423b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571053209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3571053209
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2877718889
Short name T322
Test name
Test status
Simulation time 87066011 ps
CPU time 0.67 seconds
Started Aug 15 05:25:51 PM PDT 24
Finished Aug 15 05:25:52 PM PDT 24
Peak memory 194340 kb
Host smart-e5085470-ae00-4574-b129-f9da455d8aa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877718889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2877718889
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.201968672
Short name T68
Test name
Test status
Simulation time 176976542 ps
CPU time 3.66 seconds
Started Aug 15 05:25:44 PM PDT 24
Finished Aug 15 05:25:48 PM PDT 24
Peak memory 198240 kb
Host smart-23b5b93f-3678-4f2c-8e6a-3816f755a441
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201968672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.201968672
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1097624901
Short name T606
Test name
Test status
Simulation time 50450549 ps
CPU time 1.22 seconds
Started Aug 15 05:25:47 PM PDT 24
Finished Aug 15 05:25:49 PM PDT 24
Peak memory 196888 kb
Host smart-f7989242-3234-4a54-8c77-cf2834972535
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097624901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1097624901
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3742274253
Short name T452
Test name
Test status
Simulation time 43801338 ps
CPU time 0.93 seconds
Started Aug 15 05:25:39 PM PDT 24
Finished Aug 15 05:25:40 PM PDT 24
Peak memory 196648 kb
Host smart-73f5fa34-b1c4-4d84-a43d-8a415d3e7e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742274253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3742274253
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1978561083
Short name T619
Test name
Test status
Simulation time 197371544 ps
CPU time 0.82 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:25:53 PM PDT 24
Peak memory 196568 kb
Host smart-e5e52085-e3a7-488f-87f8-864396850c45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978561083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1978561083
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.581177525
Short name T275
Test name
Test status
Simulation time 179553187 ps
CPU time 1.71 seconds
Started Aug 15 05:25:46 PM PDT 24
Finished Aug 15 05:25:48 PM PDT 24
Peak memory 198156 kb
Host smart-4f50e0f1-7a63-434e-a7ba-a542317cfdd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581177525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.581177525
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.765423320
Short name T480
Test name
Test status
Simulation time 148664164 ps
CPU time 1.28 seconds
Started Aug 15 05:25:51 PM PDT 24
Finished Aug 15 05:25:52 PM PDT 24
Peak memory 196308 kb
Host smart-0f4e4a62-33e5-473d-8564-3d56f7597ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765423320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.765423320
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.4008285407
Short name T537
Test name
Test status
Simulation time 95432327 ps
CPU time 1.47 seconds
Started Aug 15 05:25:43 PM PDT 24
Finished Aug 15 05:25:45 PM PDT 24
Peak memory 198104 kb
Host smart-10c2779e-7efa-4cdb-9394-5d5c2e9e8dfc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008285407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.4008285407
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.69407241
Short name T592
Test name
Test status
Simulation time 54664631952 ps
CPU time 149.93 seconds
Started Aug 15 05:25:37 PM PDT 24
Finished Aug 15 05:28:07 PM PDT 24
Peak memory 198360 kb
Host smart-30415f42-9fd4-4dd3-9d2f-7cab413a7e80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69407241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpi
o_stress_all.69407241
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2001728278
Short name T32
Test name
Test status
Simulation time 3017555725 ps
CPU time 114.38 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:27:47 PM PDT 24
Peak memory 198516 kb
Host smart-f6c4a52d-65f6-41f5-8ff8-4aa1ddd9fa5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2001728278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2001728278
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.384724953
Short name T541
Test name
Test status
Simulation time 13619760 ps
CPU time 0.56 seconds
Started Aug 15 05:26:46 PM PDT 24
Finished Aug 15 05:26:47 PM PDT 24
Peak memory 194048 kb
Host smart-de390c3d-3919-442f-be7f-2f8cab7d12b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384724953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.384724953
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.584714298
Short name T711
Test name
Test status
Simulation time 14997887 ps
CPU time 0.76 seconds
Started Aug 15 05:26:39 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 194224 kb
Host smart-6113954a-f000-45cf-9f51-c93af92a68e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584714298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.584714298
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2102330502
Short name T266
Test name
Test status
Simulation time 625257540 ps
CPU time 10.74 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:27:00 PM PDT 24
Peak memory 196404 kb
Host smart-69a3ed7c-374b-44b2-9608-795b379b987e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102330502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2102330502
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2773016849
Short name T279
Test name
Test status
Simulation time 124913099 ps
CPU time 0.76 seconds
Started Aug 15 05:26:49 PM PDT 24
Finished Aug 15 05:26:50 PM PDT 24
Peak memory 195936 kb
Host smart-8ef2186f-1bbc-48bf-86c0-1e4a6d0ffdf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773016849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2773016849
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1520006858
Short name T691
Test name
Test status
Simulation time 285586969 ps
CPU time 0.93 seconds
Started Aug 15 05:26:49 PM PDT 24
Finished Aug 15 05:26:50 PM PDT 24
Peak memory 196744 kb
Host smart-77de7de6-ca0a-45e4-b11c-dda19958b16a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520006858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1520006858
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1461679677
Short name T273
Test name
Test status
Simulation time 47378578 ps
CPU time 1.99 seconds
Started Aug 15 05:26:57 PM PDT 24
Finished Aug 15 05:26:59 PM PDT 24
Peak memory 198240 kb
Host smart-dc569366-8e05-4fbb-b605-117841a6fca3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461679677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1461679677
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3243905367
Short name T257
Test name
Test status
Simulation time 408141286 ps
CPU time 2.27 seconds
Started Aug 15 05:26:39 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 197432 kb
Host smart-cd232255-b7f5-4162-9e0e-f8266ff0c6dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243905367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3243905367
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1539158996
Short name T140
Test name
Test status
Simulation time 170087176 ps
CPU time 1.11 seconds
Started Aug 15 05:26:54 PM PDT 24
Finished Aug 15 05:26:56 PM PDT 24
Peak memory 196144 kb
Host smart-5d9137c0-74b5-4a30-b416-5dc1cf57a02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539158996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1539158996
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2504788711
Short name T288
Test name
Test status
Simulation time 632731454 ps
CPU time 0.9 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 197468 kb
Host smart-3e67b967-7bf6-414d-8efd-ff2182e2deed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504788711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2504788711
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.4171875351
Short name T146
Test name
Test status
Simulation time 104207105 ps
CPU time 2.74 seconds
Started Aug 15 05:26:49 PM PDT 24
Finished Aug 15 05:26:52 PM PDT 24
Peak memory 198144 kb
Host smart-95426357-b1db-4c71-af6d-94b138056d50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171875351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.4171875351
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1399152938
Short name T210
Test name
Test status
Simulation time 180616725 ps
CPU time 1.27 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 195684 kb
Host smart-f95fab43-9ad2-4c50-92cc-44dd973c3729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399152938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1399152938
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3386622141
Short name T595
Test name
Test status
Simulation time 42548938 ps
CPU time 1.05 seconds
Started Aug 15 05:26:41 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 195692 kb
Host smart-379ed115-1ee2-4bb0-b0a3-1a5657c96637
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386622141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3386622141
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2743727261
Short name T287
Test name
Test status
Simulation time 15141004664 ps
CPU time 174.61 seconds
Started Aug 15 05:26:47 PM PDT 24
Finished Aug 15 05:29:42 PM PDT 24
Peak memory 198288 kb
Host smart-6c530810-1213-4c2a-92f6-466b173e0ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743727261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2743727261
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3720553998
Short name T312
Test name
Test status
Simulation time 16752278 ps
CPU time 0.59 seconds
Started Aug 15 05:26:53 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 194840 kb
Host smart-9ceed384-e104-4845-add8-8dc509617928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720553998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3720553998
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.311494943
Short name T138
Test name
Test status
Simulation time 84282009 ps
CPU time 0.79 seconds
Started Aug 15 05:26:48 PM PDT 24
Finished Aug 15 05:26:49 PM PDT 24
Peak memory 195556 kb
Host smart-e90953c5-f056-47d5-9c37-7282688be1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311494943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.311494943
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3328483451
Short name T225
Test name
Test status
Simulation time 391218713 ps
CPU time 10.33 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:49 PM PDT 24
Peak memory 197180 kb
Host smart-71017ff2-a784-4cff-820d-2c5d0c714dca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328483451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3328483451
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1655544088
Short name T425
Test name
Test status
Simulation time 227737218 ps
CPU time 0.86 seconds
Started Aug 15 05:26:41 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 196776 kb
Host smart-6e207475-8b27-49f7-ab3f-344de39f3558
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655544088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1655544088
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1872800028
Short name T290
Test name
Test status
Simulation time 175543867 ps
CPU time 1.02 seconds
Started Aug 15 05:26:45 PM PDT 24
Finished Aug 15 05:26:46 PM PDT 24
Peak memory 196212 kb
Host smart-b04c40bb-c0fb-4e16-b19a-695245922763
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872800028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1872800028
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2845518367
Short name T533
Test name
Test status
Simulation time 58148277 ps
CPU time 2.32 seconds
Started Aug 15 05:26:39 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 198224 kb
Host smart-910426f7-bdf4-42ac-a8cc-1c0cc85672f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845518367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2845518367
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1224713926
Short name T692
Test name
Test status
Simulation time 92218175 ps
CPU time 2.66 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:55 PM PDT 24
Peak memory 197232 kb
Host smart-808d70e8-21bc-46bf-98c7-cc5511304afc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224713926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1224713926
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2160658045
Short name T521
Test name
Test status
Simulation time 28558359 ps
CPU time 1.14 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 196040 kb
Host smart-2618ca73-f822-4d75-8cf1-fd811ec390c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160658045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2160658045
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2007133942
Short name T478
Test name
Test status
Simulation time 47717638 ps
CPU time 0.96 seconds
Started Aug 15 05:26:35 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 196168 kb
Host smart-ffcde646-2d67-4092-ac88-5188e0395011
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007133942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2007133942
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2780268681
Short name T154
Test name
Test status
Simulation time 606128397 ps
CPU time 4.85 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:44 PM PDT 24
Peak memory 198136 kb
Host smart-e1db7077-09bf-4081-9685-691887d78dd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780268681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2780268681
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3194638177
Short name T569
Test name
Test status
Simulation time 155844792 ps
CPU time 1.06 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 195672 kb
Host smart-278965ff-10a5-45d8-99b3-020fd92e285e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194638177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3194638177
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3744850918
Short name T445
Test name
Test status
Simulation time 230846084 ps
CPU time 1.25 seconds
Started Aug 15 05:26:49 PM PDT 24
Finished Aug 15 05:26:50 PM PDT 24
Peak memory 195692 kb
Host smart-8889a8e8-8774-4d93-922e-8d3d621c5c37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744850918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3744850918
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1499738607
Short name T163
Test name
Test status
Simulation time 19805423173 ps
CPU time 168.78 seconds
Started Aug 15 05:26:48 PM PDT 24
Finished Aug 15 05:29:37 PM PDT 24
Peak memory 198200 kb
Host smart-74a2c91d-84f1-4e74-af5f-40deacbe258e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499738607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1499738607
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.4153030024
Short name T672
Test name
Test status
Simulation time 76644463 ps
CPU time 0.56 seconds
Started Aug 15 05:26:42 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 194892 kb
Host smart-4287feca-3912-4f98-a007-e49a7bb8722d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153030024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.4153030024
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.9422925
Short name T242
Test name
Test status
Simulation time 41475765 ps
CPU time 0.75 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 196140 kb
Host smart-a0bcf4e5-1c7d-4759-9eb2-eb40e459f20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9422925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.9422925
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1818515210
Short name T684
Test name
Test status
Simulation time 117965419 ps
CPU time 6.14 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:46 PM PDT 24
Peak memory 196952 kb
Host smart-6a0befc6-c6a4-4515-98b3-fe3e08b831d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818515210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1818515210
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.34456166
Short name T197
Test name
Test status
Simulation time 33286262 ps
CPU time 0.76 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 196592 kb
Host smart-d9b7b1bb-fdb0-4129-bff4-9c94931bb586
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34456166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.34456166
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2693481660
Short name T486
Test name
Test status
Simulation time 170842215 ps
CPU time 1.28 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 197212 kb
Host smart-8e08d36a-17a7-417b-a663-5d608e17434e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693481660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2693481660
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2201579092
Short name T665
Test name
Test status
Simulation time 494967465 ps
CPU time 3.51 seconds
Started Aug 15 05:26:46 PM PDT 24
Finished Aug 15 05:26:49 PM PDT 24
Peak memory 198132 kb
Host smart-454c47e8-4669-4cec-a77f-4e7ac4b28b81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201579092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2201579092
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1982843457
Short name T228
Test name
Test status
Simulation time 82817729 ps
CPU time 1.18 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 195664 kb
Host smart-d46c09dc-b571-4ade-ab9d-47937d929b04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982843457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1982843457
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1625530798
Short name T313
Test name
Test status
Simulation time 61435028 ps
CPU time 1.21 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 196144 kb
Host smart-e18b800c-7017-4503-acf3-2c85c20ea469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625530798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1625530798
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3101876544
Short name T130
Test name
Test status
Simulation time 36103541 ps
CPU time 0.86 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:26:51 PM PDT 24
Peak memory 196076 kb
Host smart-e4f7f042-6529-4d31-99a1-a402ed301c4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101876544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3101876544
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.831540385
Short name T442
Test name
Test status
Simulation time 126720045 ps
CPU time 5.39 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:44 PM PDT 24
Peak memory 198000 kb
Host smart-c61e62b6-149e-4938-bfe8-d14adcb8e5d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831540385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.831540385
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2762853863
Short name T348
Test name
Test status
Simulation time 81202988 ps
CPU time 0.83 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:37 PM PDT 24
Peak memory 195244 kb
Host smart-5bed37ae-e278-49f2-9442-a45b0bbe2012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762853863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2762853863
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.835666033
Short name T58
Test name
Test status
Simulation time 27830398 ps
CPU time 0.87 seconds
Started Aug 15 05:26:41 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 195500 kb
Host smart-ecef90d3-0c2d-46f2-8d66-2e381935b6d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835666033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.835666033
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1916581727
Short name T659
Test name
Test status
Simulation time 44544936853 ps
CPU time 146.53 seconds
Started Aug 15 05:26:43 PM PDT 24
Finished Aug 15 05:29:09 PM PDT 24
Peak memory 192140 kb
Host smart-c4414249-9372-476d-8cdc-b459f6eefc5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916581727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1916581727
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1896234993
Short name T628
Test name
Test status
Simulation time 21697440 ps
CPU time 0.57 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:39 PM PDT 24
Peak memory 194776 kb
Host smart-d4f27f4c-fa32-4961-b546-a4b209eb63a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896234993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1896234993
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3597150872
Short name T675
Test name
Test status
Simulation time 139048077 ps
CPU time 0.85 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 195624 kb
Host smart-802e537c-d1a3-4dd6-8a8f-4b369d88d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597150872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3597150872
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2174907017
Short name T298
Test name
Test status
Simulation time 1165268141 ps
CPU time 17.07 seconds
Started Aug 15 05:26:48 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 195604 kb
Host smart-2896a4cb-90fd-4f47-bb01-bdee177653eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174907017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2174907017
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3558208080
Short name T22
Test name
Test status
Simulation time 23080127 ps
CPU time 0.61 seconds
Started Aug 15 05:26:38 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 194144 kb
Host smart-0071c946-3ed8-4d65-8a63-9e51b048a9d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558208080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3558208080
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2290249029
Short name T12
Test name
Test status
Simulation time 77918172 ps
CPU time 1.28 seconds
Started Aug 15 05:26:41 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 197016 kb
Host smart-fc2e2504-5c19-4c50-8ff1-c22cc110d7d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290249029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2290249029
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2785424579
Short name T460
Test name
Test status
Simulation time 92124289 ps
CPU time 3.52 seconds
Started Aug 15 05:26:51 PM PDT 24
Finished Aug 15 05:26:55 PM PDT 24
Peak memory 198248 kb
Host smart-a6ede1bf-0403-4a3c-8a4b-de12778309cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785424579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2785424579
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.55025332
Short name T293
Test name
Test status
Simulation time 24117180 ps
CPU time 0.81 seconds
Started Aug 15 05:26:39 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 194544 kb
Host smart-3289436e-cfea-4d4a-9ce7-c82dc1472852
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55025332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.55025332
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1725794400
Short name T620
Test name
Test status
Simulation time 14184639 ps
CPU time 0.67 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 195060 kb
Host smart-5b1101f7-5eeb-43c0-8f2b-accfbfcaf031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725794400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1725794400
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3409062006
Short name T139
Test name
Test status
Simulation time 26153299 ps
CPU time 0.96 seconds
Started Aug 15 05:26:41 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 195956 kb
Host smart-d0f9265f-ec7a-4f3f-bca4-3a4e5cab5305
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409062006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3409062006
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2805753742
Short name T444
Test name
Test status
Simulation time 660046540 ps
CPU time 5.52 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:46 PM PDT 24
Peak memory 198144 kb
Host smart-cb66b1d4-d3a5-4084-8fab-f54f4d195f93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805753742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2805753742
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3006260480
Short name T318
Test name
Test status
Simulation time 242566748 ps
CPU time 1.56 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:42 PM PDT 24
Peak memory 196780 kb
Host smart-077b390c-4458-4eb1-976a-376f9f2fef97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006260480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3006260480
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3832819638
Short name T174
Test name
Test status
Simulation time 128988562 ps
CPU time 1.29 seconds
Started Aug 15 05:26:46 PM PDT 24
Finished Aug 15 05:26:48 PM PDT 24
Peak memory 195872 kb
Host smart-7b4d0628-54eb-471e-af93-3a3a5299ab65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832819638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3832819638
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1538535775
Short name T29
Test name
Test status
Simulation time 5174320492 ps
CPU time 71.1 seconds
Started Aug 15 05:26:45 PM PDT 24
Finished Aug 15 05:27:56 PM PDT 24
Peak memory 198332 kb
Host smart-8bb00d8b-d241-45fd-87a5-83aad6a6fc44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538535775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1538535775
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.174337037
Short name T310
Test name
Test status
Simulation time 34033170 ps
CPU time 0.58 seconds
Started Aug 15 05:26:39 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 194048 kb
Host smart-6a599c26-36f5-4ef5-a51c-f1376f5585fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174337037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.174337037
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1776096195
Short name T504
Test name
Test status
Simulation time 34007183 ps
CPU time 0.64 seconds
Started Aug 15 05:26:53 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 194736 kb
Host smart-40130206-4055-408d-b3c5-e6f182b89665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776096195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1776096195
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3038552041
Short name T518
Test name
Test status
Simulation time 605522593 ps
CPU time 4.53 seconds
Started Aug 15 05:26:51 PM PDT 24
Finished Aug 15 05:26:55 PM PDT 24
Peak memory 195952 kb
Host smart-3c81e8df-7c8d-4a8b-94a9-50af8d373663
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038552041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3038552041
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3103430366
Short name T269
Test name
Test status
Simulation time 409724269 ps
CPU time 0.71 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:26:51 PM PDT 24
Peak memory 194708 kb
Host smart-bba970c3-5701-478e-9943-374033a39cf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103430366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3103430366
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1566941149
Short name T527
Test name
Test status
Simulation time 332047180 ps
CPU time 1.27 seconds
Started Aug 15 05:26:54 PM PDT 24
Finished Aug 15 05:26:55 PM PDT 24
Peak memory 198244 kb
Host smart-534745ca-726c-4dc7-bdbc-3260611794b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566941149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1566941149
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1725537813
Short name T125
Test name
Test status
Simulation time 826192907 ps
CPU time 2.85 seconds
Started Aug 15 05:26:48 PM PDT 24
Finished Aug 15 05:26:51 PM PDT 24
Peak memory 197996 kb
Host smart-f6b7ccb5-aaad-4795-8fe2-4b1bd7ed312b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725537813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1725537813
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2030705460
Short name T349
Test name
Test status
Simulation time 607009147 ps
CPU time 3.22 seconds
Started Aug 15 05:26:37 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 195940 kb
Host smart-efb4e2cd-94c7-4f0c-8183-4f905b823de5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030705460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2030705460
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2350864081
Short name T179
Test name
Test status
Simulation time 65468965 ps
CPU time 1.33 seconds
Started Aug 15 05:26:39 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 198248 kb
Host smart-61c03b2a-ebdb-43c1-b39c-43a7fbcaab01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350864081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2350864081
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2901681334
Short name T462
Test name
Test status
Simulation time 154158480 ps
CPU time 1.07 seconds
Started Aug 15 05:26:46 PM PDT 24
Finished Aug 15 05:26:47 PM PDT 24
Peak memory 196864 kb
Host smart-848d4b51-6780-4990-9b63-f2366341d4d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901681334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2901681334
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2798358050
Short name T263
Test name
Test status
Simulation time 284208385 ps
CPU time 1.69 seconds
Started Aug 15 05:26:41 PM PDT 24
Finished Aug 15 05:26:43 PM PDT 24
Peak memory 198088 kb
Host smart-90e02c02-fb44-4788-a767-303f1692ca2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798358050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2798358050
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.551307592
Short name T190
Test name
Test status
Simulation time 30357351 ps
CPU time 0.92 seconds
Started Aug 15 05:26:57 PM PDT 24
Finished Aug 15 05:26:58 PM PDT 24
Peak memory 195912 kb
Host smart-6c92c6f1-649c-4404-8857-f29e5b1e451f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551307592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.551307592
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2280327442
Short name T131
Test name
Test status
Simulation time 112791383 ps
CPU time 0.75 seconds
Started Aug 15 05:26:43 PM PDT 24
Finished Aug 15 05:26:44 PM PDT 24
Peak memory 195352 kb
Host smart-aa9fd1b7-251f-480f-ab33-6ab2ecfc8c68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280327442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2280327442
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2021548102
Short name T268
Test name
Test status
Simulation time 7487892511 ps
CPU time 94.2 seconds
Started Aug 15 05:26:39 PM PDT 24
Finished Aug 15 05:28:14 PM PDT 24
Peak memory 198336 kb
Host smart-932b89f5-4f5d-4da9-9474-6cdbfe3293d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021548102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2021548102
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.196886416
Short name T680
Test name
Test status
Simulation time 11960704 ps
CPU time 0.56 seconds
Started Aug 15 05:26:58 PM PDT 24
Finished Aug 15 05:26:59 PM PDT 24
Peak memory 194772 kb
Host smart-8eeb770d-3d6c-4734-8047-cc1c6a015faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196886416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.196886416
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2261288244
Short name T491
Test name
Test status
Simulation time 476650117 ps
CPU time 0.87 seconds
Started Aug 15 05:26:40 PM PDT 24
Finished Aug 15 05:26:41 PM PDT 24
Peak memory 196412 kb
Host smart-30055468-4b06-4fb5-9836-40d83c2bfaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261288244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2261288244
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2325959343
Short name T438
Test name
Test status
Simulation time 950240697 ps
CPU time 5.23 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:26:55 PM PDT 24
Peak memory 196544 kb
Host smart-57c65909-3371-46bd-8a9d-d0059b273511
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325959343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2325959343
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3369062686
Short name T488
Test name
Test status
Simulation time 448307319 ps
CPU time 0.92 seconds
Started Aug 15 05:26:48 PM PDT 24
Finished Aug 15 05:26:49 PM PDT 24
Peak memory 196520 kb
Host smart-b5ae1b84-1592-43df-9fea-1fff3145538a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369062686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3369062686
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.752205727
Short name T259
Test name
Test status
Simulation time 76052022 ps
CPU time 1.26 seconds
Started Aug 15 05:26:49 PM PDT 24
Finished Aug 15 05:26:51 PM PDT 24
Peak memory 197320 kb
Host smart-d5e9ef30-1c87-4e66-b1ca-cd448e4677f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752205727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.752205727
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1628150250
Short name T440
Test name
Test status
Simulation time 45833598 ps
CPU time 1.7 seconds
Started Aug 15 05:27:08 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 197216 kb
Host smart-6c71cfd4-1236-4024-a4b7-5c91a262a50e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628150250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1628150250
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1481785277
Short name T468
Test name
Test status
Simulation time 448297640 ps
CPU time 2.42 seconds
Started Aug 15 05:26:53 PM PDT 24
Finished Aug 15 05:26:55 PM PDT 24
Peak memory 195940 kb
Host smart-e7dfe2fe-520a-4a64-b61d-938030cefd51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481785277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1481785277
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.622037505
Short name T550
Test name
Test status
Simulation time 28094921 ps
CPU time 0.84 seconds
Started Aug 15 05:26:45 PM PDT 24
Finished Aug 15 05:26:46 PM PDT 24
Peak memory 196208 kb
Host smart-1273a148-642e-47dd-9bd8-fd1d40d4d7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622037505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.622037505
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1988596347
Short name T184
Test name
Test status
Simulation time 18468802 ps
CPU time 0.68 seconds
Started Aug 15 05:26:39 PM PDT 24
Finished Aug 15 05:26:40 PM PDT 24
Peak memory 194392 kb
Host smart-7f375309-f02e-45c9-bb36-54c2613d5227
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988596347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1988596347
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2064981194
Short name T191
Test name
Test status
Simulation time 175237451 ps
CPU time 1.72 seconds
Started Aug 15 05:26:49 PM PDT 24
Finished Aug 15 05:26:51 PM PDT 24
Peak memory 198100 kb
Host smart-23026498-b423-4ff9-affa-5f603fec6578
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064981194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2064981194
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2486484537
Short name T200
Test name
Test status
Simulation time 181560391 ps
CPU time 1.43 seconds
Started Aug 15 05:26:36 PM PDT 24
Finished Aug 15 05:26:38 PM PDT 24
Peak memory 196820 kb
Host smart-16434add-5d51-48d9-82ff-6f4f45c85cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486484537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2486484537
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1844645036
Short name T479
Test name
Test status
Simulation time 28750649 ps
CPU time 0.88 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 196452 kb
Host smart-27825adb-a81f-454e-8ea9-3ff02b7f3b12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844645036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1844645036
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.118026152
Short name T367
Test name
Test status
Simulation time 19401956739 ps
CPU time 23.02 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:27:13 PM PDT 24
Peak memory 198336 kb
Host smart-67eca887-76a5-4510-bc3f-0f6d562fcc7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118026152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.118026152
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.4121161776
Short name T63
Test name
Test status
Simulation time 18227015909 ps
CPU time 278.11 seconds
Started Aug 15 05:26:51 PM PDT 24
Finished Aug 15 05:31:30 PM PDT 24
Peak memory 198476 kb
Host smart-bf1b2670-b415-4a92-84a6-b2eaf7d196d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4121161776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.4121161776
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1866197524
Short name T494
Test name
Test status
Simulation time 11920512 ps
CPU time 0.56 seconds
Started Aug 15 05:26:56 PM PDT 24
Finished Aug 15 05:26:56 PM PDT 24
Peak memory 194048 kb
Host smart-74fab68d-c18e-4f80-9b14-f349d123f686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866197524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1866197524
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3288240043
Short name T443
Test name
Test status
Simulation time 65579954 ps
CPU time 0.83 seconds
Started Aug 15 05:26:59 PM PDT 24
Finished Aug 15 05:27:00 PM PDT 24
Peak memory 195508 kb
Host smart-3ab15efa-81a8-4c36-aaae-7d3fa80a4f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288240043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3288240043
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1769640332
Short name T426
Test name
Test status
Simulation time 349090827 ps
CPU time 18.79 seconds
Started Aug 15 05:26:48 PM PDT 24
Finished Aug 15 05:27:07 PM PDT 24
Peak memory 198160 kb
Host smart-ad3479c1-13fe-4ff1-ae13-9f77ab4fa2b4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769640332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1769640332
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2062155141
Short name T236
Test name
Test status
Simulation time 49759674 ps
CPU time 0.83 seconds
Started Aug 15 05:26:53 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 196744 kb
Host smart-6f999ea4-fcb7-4dc9-9df0-321b8e63419a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062155141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2062155141
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2993563957
Short name T192
Test name
Test status
Simulation time 294639483 ps
CPU time 1.1 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:26:51 PM PDT 24
Peak memory 195936 kb
Host smart-64b106e5-7737-4f56-960c-ca0694e5053f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993563957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2993563957
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.518552152
Short name T69
Test name
Test status
Simulation time 170283640 ps
CPU time 2.63 seconds
Started Aug 15 05:26:55 PM PDT 24
Finished Aug 15 05:26:58 PM PDT 24
Peak memory 198228 kb
Host smart-27b7a3c0-cc63-44b4-833c-a1c5dcca1e5d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518552152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.518552152
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1523028840
Short name T175
Test name
Test status
Simulation time 122444783 ps
CPU time 1.17 seconds
Started Aug 15 05:26:56 PM PDT 24
Finished Aug 15 05:26:57 PM PDT 24
Peak memory 195652 kb
Host smart-811c5555-31ff-4369-a390-7781737095c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523028840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1523028840
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.969034306
Short name T567
Test name
Test status
Simulation time 37382043 ps
CPU time 0.96 seconds
Started Aug 15 05:26:57 PM PDT 24
Finished Aug 15 05:26:58 PM PDT 24
Peak memory 196692 kb
Host smart-eaf3ca33-d921-4315-80a7-a6de176be74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969034306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.969034306
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.139062417
Short name T372
Test name
Test status
Simulation time 20188056 ps
CPU time 0.66 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 194388 kb
Host smart-23350511-f394-4eca-8039-e3caf52b86bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139062417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.139062417
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1320220739
Short name T306
Test name
Test status
Simulation time 1143813611 ps
CPU time 3.8 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 198160 kb
Host smart-4fc72bd1-120f-4459-833c-f8aef0830979
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320220739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1320220739
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2520546053
Short name T511
Test name
Test status
Simulation time 101971699 ps
CPU time 1.27 seconds
Started Aug 15 05:26:57 PM PDT 24
Finished Aug 15 05:26:59 PM PDT 24
Peak memory 196420 kb
Host smart-92703cb8-ab7b-4629-af4a-56a3413a3d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520546053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2520546053
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3754652250
Short name T101
Test name
Test status
Simulation time 56727098 ps
CPU time 0.96 seconds
Started Aug 15 05:26:53 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 195916 kb
Host smart-5278f3f1-e9d1-4a83-acae-e247414b08d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754652250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3754652250
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.187241175
Short name T625
Test name
Test status
Simulation time 30801718295 ps
CPU time 94.74 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:28:27 PM PDT 24
Peak memory 198292 kb
Host smart-b25ec56a-2e64-4aad-bf0a-044caf54bca3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187241175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.187241175
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.195499171
Short name T350
Test name
Test status
Simulation time 19963214 ps
CPU time 0.56 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 194772 kb
Host smart-f4a5179d-0da6-40df-bfa8-9a2a5cf7a9c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195499171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.195499171
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3567549041
Short name T261
Test name
Test status
Simulation time 47189605 ps
CPU time 0.72 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 195232 kb
Host smart-612a9d2d-d939-4497-8a75-300dcc53d27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567549041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3567549041
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2155674219
Short name T277
Test name
Test status
Simulation time 860174053 ps
CPU time 6.5 seconds
Started Aug 15 05:26:56 PM PDT 24
Finished Aug 15 05:27:03 PM PDT 24
Peak memory 195636 kb
Host smart-3cd46d9f-2487-4eb1-8767-9035c0ebb12a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155674219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2155674219
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1564473977
Short name T4
Test name
Test status
Simulation time 269566524 ps
CPU time 0.89 seconds
Started Aug 15 05:26:56 PM PDT 24
Finished Aug 15 05:26:57 PM PDT 24
Peak memory 196044 kb
Host smart-85b17320-2b93-400c-ba72-a087bf347b1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564473977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1564473977
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1070482199
Short name T598
Test name
Test status
Simulation time 305219036 ps
CPU time 0.94 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 195768 kb
Host smart-c8c531a3-13f7-4724-8033-17a3ff605aae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070482199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1070482199
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.641114519
Short name T27
Test name
Test status
Simulation time 311298691 ps
CPU time 2.93 seconds
Started Aug 15 05:27:09 PM PDT 24
Finished Aug 15 05:27:12 PM PDT 24
Peak memory 197376 kb
Host smart-8d5cadd1-8a9e-4223-84fa-0995d4a45903
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641114519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.641114519
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.4274826804
Short name T549
Test name
Test status
Simulation time 102304876 ps
CPU time 2.3 seconds
Started Aug 15 05:26:48 PM PDT 24
Finished Aug 15 05:26:50 PM PDT 24
Peak memory 196932 kb
Host smart-7cf8016d-1fcb-4af2-8d28-c6986dfaf84b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274826804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.4274826804
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.4263566750
Short name T707
Test name
Test status
Simulation time 59220137 ps
CPU time 0.76 seconds
Started Aug 15 05:26:51 PM PDT 24
Finished Aug 15 05:26:52 PM PDT 24
Peak memory 196380 kb
Host smart-6acf2cde-d1bd-4982-b686-7c1a5c413383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263566750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.4263566750
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3301749909
Short name T112
Test name
Test status
Simulation time 93768323 ps
CPU time 1.21 seconds
Started Aug 15 05:26:56 PM PDT 24
Finished Aug 15 05:26:57 PM PDT 24
Peak memory 196776 kb
Host smart-df4b0918-fe20-4eb9-96eb-69690d6d81d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301749909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3301749909
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3663432012
Short name T248
Test name
Test status
Simulation time 45016686 ps
CPU time 1.19 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:26:51 PM PDT 24
Peak memory 197988 kb
Host smart-d3060396-ee65-4b65-a48e-c5a2fbf3474f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663432012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3663432012
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3379473972
Short name T246
Test name
Test status
Simulation time 23803596 ps
CPU time 0.74 seconds
Started Aug 15 05:26:53 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 195132 kb
Host smart-1c069d30-aae5-449c-8b90-0604ec018175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379473972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3379473972
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.419903984
Short name T241
Test name
Test status
Simulation time 52031605 ps
CPU time 0.92 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 196540 kb
Host smart-05f63d0a-a220-4b58-b04f-f95b11e90e9d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419903984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.419903984
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3961790075
Short name T110
Test name
Test status
Simulation time 25608008123 ps
CPU time 151.77 seconds
Started Aug 15 05:26:59 PM PDT 24
Finished Aug 15 05:29:31 PM PDT 24
Peak memory 198372 kb
Host smart-2ba8a5a3-77ec-4b9d-ae06-9fcb40a8d26c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961790075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3961790075
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1004628890
Short name T64
Test name
Test status
Simulation time 8963496603 ps
CPU time 82.3 seconds
Started Aug 15 05:26:57 PM PDT 24
Finished Aug 15 05:28:20 PM PDT 24
Peak memory 198532 kb
Host smart-b3c333d1-cab2-4456-8478-fc81c96a70d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1004628890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1004628890
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.611257781
Short name T291
Test name
Test status
Simulation time 20216462 ps
CPU time 0.57 seconds
Started Aug 15 05:27:11 PM PDT 24
Finished Aug 15 05:27:12 PM PDT 24
Peak memory 194056 kb
Host smart-81331e3e-025c-48da-8ab6-22842fc65ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611257781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.611257781
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.553944845
Short name T642
Test name
Test status
Simulation time 158783174 ps
CPU time 0.95 seconds
Started Aug 15 05:27:13 PM PDT 24
Finished Aug 15 05:27:14 PM PDT 24
Peak memory 196028 kb
Host smart-062ff115-d66b-49f3-a3a3-5a1f6ef2ae76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553944845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.553944845
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1989895097
Short name T623
Test name
Test status
Simulation time 174437894 ps
CPU time 5.19 seconds
Started Aug 15 05:26:55 PM PDT 24
Finished Aug 15 05:27:00 PM PDT 24
Peak memory 197156 kb
Host smart-4f5a4fd7-ec65-4548-b775-9d2c43228cac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989895097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1989895097
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3455227900
Short name T2
Test name
Test status
Simulation time 91910607 ps
CPU time 1.06 seconds
Started Aug 15 05:26:55 PM PDT 24
Finished Aug 15 05:26:57 PM PDT 24
Peak memory 196764 kb
Host smart-0c304c13-7a4e-435b-aa76-4477c5c96c06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455227900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3455227900
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3467672337
Short name T648
Test name
Test status
Simulation time 136076336 ps
CPU time 0.71 seconds
Started Aug 15 05:26:53 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 195424 kb
Host smart-27217638-ff7a-4f17-84ea-d31f51fe6e36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467672337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3467672337
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1647024941
Short name T104
Test name
Test status
Simulation time 70406238 ps
CPU time 1.51 seconds
Started Aug 15 05:27:08 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 196700 kb
Host smart-79f21e72-1531-4f39-8498-cd3f2212efe6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647024941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1647024941
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3878004914
Short name T353
Test name
Test status
Simulation time 191751098 ps
CPU time 1.68 seconds
Started Aug 15 05:26:56 PM PDT 24
Finished Aug 15 05:26:58 PM PDT 24
Peak memory 196128 kb
Host smart-5a2a122a-25f6-48eb-87c7-b7d04bfa07b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878004914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3878004914
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3584802813
Short name T571
Test name
Test status
Simulation time 56563386 ps
CPU time 0.8 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 196548 kb
Host smart-85d80af3-9ce6-47c1-8e72-eff00082d274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584802813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3584802813
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.4260377591
Short name T500
Test name
Test status
Simulation time 242272555 ps
CPU time 0.89 seconds
Started Aug 15 05:26:56 PM PDT 24
Finished Aug 15 05:26:58 PM PDT 24
Peak memory 196796 kb
Host smart-9c7dc404-1c47-4fc6-869f-5657aec7e216
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260377591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.4260377591
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1183643508
Short name T597
Test name
Test status
Simulation time 1414593560 ps
CPU time 4.49 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 198136 kb
Host smart-c986ca74-cd9b-428a-910b-9d50818919a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183643508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1183643508
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3324843229
Short name T515
Test name
Test status
Simulation time 88151149 ps
CPU time 1.36 seconds
Started Aug 15 05:26:55 PM PDT 24
Finished Aug 15 05:26:56 PM PDT 24
Peak memory 196960 kb
Host smart-1a99c7c2-b3d9-4a05-a7fc-759d1fdd3be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324843229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3324843229
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3059121945
Short name T398
Test name
Test status
Simulation time 267187451 ps
CPU time 1.11 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 195944 kb
Host smart-09b6a2ae-5056-4986-bdc4-15b389765108
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059121945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3059121945
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2295903506
Short name T132
Test name
Test status
Simulation time 10364264714 ps
CPU time 96.66 seconds
Started Aug 15 05:26:59 PM PDT 24
Finished Aug 15 05:28:36 PM PDT 24
Peak memory 198364 kb
Host smart-e2d4c459-6252-4d3f-83f5-26317710d8be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295903506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2295903506
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3957006499
Short name T147
Test name
Test status
Simulation time 34871560 ps
CPU time 0.62 seconds
Started Aug 15 05:27:01 PM PDT 24
Finished Aug 15 05:27:02 PM PDT 24
Peak memory 193996 kb
Host smart-cfc3f5d6-dbd9-4427-9501-fb3e4ab6bf6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957006499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3957006499
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2181269198
Short name T420
Test name
Test status
Simulation time 117506763 ps
CPU time 0.73 seconds
Started Aug 15 05:27:09 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 195308 kb
Host smart-b55fad0f-5b72-47ff-8ba6-637541b20af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181269198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2181269198
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3756892765
Short name T475
Test name
Test status
Simulation time 1272076731 ps
CPU time 17.95 seconds
Started Aug 15 05:27:02 PM PDT 24
Finished Aug 15 05:27:20 PM PDT 24
Peak memory 195904 kb
Host smart-8d194e29-2e08-42cb-936b-e2b4b9d55bde
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756892765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3756892765
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.4145122430
Short name T70
Test name
Test status
Simulation time 253249607 ps
CPU time 0.94 seconds
Started Aug 15 05:26:55 PM PDT 24
Finished Aug 15 05:26:56 PM PDT 24
Peak memory 198052 kb
Host smart-63f24de5-7f2c-4b45-963e-61619b5c8b44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145122430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.4145122430
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3957686993
Short name T446
Test name
Test status
Simulation time 403463108 ps
CPU time 1.52 seconds
Started Aug 15 05:27:18 PM PDT 24
Finished Aug 15 05:27:20 PM PDT 24
Peak memory 198224 kb
Host smart-05a8a124-25b3-434e-a88e-68a6c5780eb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957686993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3957686993
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1548312053
Short name T339
Test name
Test status
Simulation time 103742038 ps
CPU time 2.29 seconds
Started Aug 15 05:26:55 PM PDT 24
Finished Aug 15 05:26:57 PM PDT 24
Peak memory 198300 kb
Host smart-375c6f7a-2463-4cb9-a35c-80ae9d0156e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548312053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1548312053
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.209110617
Short name T264
Test name
Test status
Simulation time 646666534 ps
CPU time 2.26 seconds
Started Aug 15 05:26:57 PM PDT 24
Finished Aug 15 05:26:59 PM PDT 24
Peak memory 197232 kb
Host smart-0be251f8-3475-4af5-93be-0647bbe169aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209110617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
209110617
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.4292412226
Short name T405
Test name
Test status
Simulation time 30267168 ps
CPU time 0.84 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 196312 kb
Host smart-c280cd30-87af-41b4-8b57-0c6a24ac0b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292412226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.4292412226
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3662236694
Short name T587
Test name
Test status
Simulation time 426124034 ps
CPU time 1.34 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:26:51 PM PDT 24
Peak memory 196728 kb
Host smart-7588a65b-9901-46ad-977b-68ba8f95e8a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662236694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3662236694
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.564999246
Short name T449
Test name
Test status
Simulation time 531628670 ps
CPU time 1.88 seconds
Started Aug 15 05:27:08 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 197416 kb
Host smart-9ee0bf65-5845-4ccb-812c-69863157068a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564999246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.564999246
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.4129512533
Short name T369
Test name
Test status
Simulation time 71061249 ps
CPU time 1.25 seconds
Started Aug 15 05:26:48 PM PDT 24
Finished Aug 15 05:26:49 PM PDT 24
Peak memory 196972 kb
Host smart-53572d71-7d0d-4ca7-aa9e-bb08613892a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129512533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.4129512533
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.422617962
Short name T136
Test name
Test status
Simulation time 187979457 ps
CPU time 1.15 seconds
Started Aug 15 05:26:50 PM PDT 24
Finished Aug 15 05:26:51 PM PDT 24
Peak memory 195864 kb
Host smart-f6dc7543-1325-4f3c-9e9c-7223d8dc996f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422617962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.422617962
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.260780754
Short name T428
Test name
Test status
Simulation time 8973190399 ps
CPU time 77.96 seconds
Started Aug 15 05:26:58 PM PDT 24
Finished Aug 15 05:28:17 PM PDT 24
Peak memory 198376 kb
Host smart-5539721f-b6c1-43c1-9012-35c1819660ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260780754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.260780754
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.786857864
Short name T172
Test name
Test status
Simulation time 44933801 ps
CPU time 0.56 seconds
Started Aug 15 05:25:50 PM PDT 24
Finished Aug 15 05:25:51 PM PDT 24
Peak memory 194032 kb
Host smart-3d013bac-bb3c-44f2-928b-ff19a7390d3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786857864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.786857864
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2678393729
Short name T552
Test name
Test status
Simulation time 52842672 ps
CPU time 0.61 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:55 PM PDT 24
Peak memory 194072 kb
Host smart-5761142e-37c8-468d-befa-35840c75221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678393729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2678393729
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3212665728
Short name T651
Test name
Test status
Simulation time 266041609 ps
CPU time 13.67 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:26:06 PM PDT 24
Peak memory 197052 kb
Host smart-353b60d9-8863-4bbe-8697-56840d9dc3db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212665728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3212665728
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.954904387
Short name T144
Test name
Test status
Simulation time 142476185 ps
CPU time 1 seconds
Started Aug 15 05:25:43 PM PDT 24
Finished Aug 15 05:25:44 PM PDT 24
Peak memory 196796 kb
Host smart-fcd9566e-0bfa-4a5b-be38-758b3d3052c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954904387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.954904387
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2019770179
Short name T501
Test name
Test status
Simulation time 92131794 ps
CPU time 1.02 seconds
Started Aug 15 05:25:49 PM PDT 24
Finished Aug 15 05:25:50 PM PDT 24
Peak memory 196772 kb
Host smart-e2d30223-d050-44b4-bfc6-5a5753927eca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019770179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2019770179
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2558881915
Short name T233
Test name
Test status
Simulation time 115147512 ps
CPU time 1.33 seconds
Started Aug 15 05:25:45 PM PDT 24
Finished Aug 15 05:25:47 PM PDT 24
Peak memory 198268 kb
Host smart-a9a1abcc-39a9-4f36-bbb0-387253a49059
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558881915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2558881915
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3311483334
Short name T256
Test name
Test status
Simulation time 384037845 ps
CPU time 2.78 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 197080 kb
Host smart-31364873-1194-41fb-a1fc-337a8eec379b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311483334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3311483334
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.257579730
Short name T302
Test name
Test status
Simulation time 32420987 ps
CPU time 1.06 seconds
Started Aug 15 05:25:47 PM PDT 24
Finished Aug 15 05:25:48 PM PDT 24
Peak memory 196680 kb
Host smart-f7db67e6-319a-487d-a8fc-d2e2809123ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257579730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.257579730
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2971494417
Short name T243
Test name
Test status
Simulation time 17948137 ps
CPU time 0.68 seconds
Started Aug 15 05:25:44 PM PDT 24
Finished Aug 15 05:25:45 PM PDT 24
Peak memory 195528 kb
Host smart-1042e2d7-758b-40a1-9e1f-e2acdb5c1720
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971494417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2971494417
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3957953344
Short name T423
Test name
Test status
Simulation time 598475124 ps
CPU time 5.24 seconds
Started Aug 15 05:25:47 PM PDT 24
Finished Aug 15 05:25:52 PM PDT 24
Peak memory 198136 kb
Host smart-100ad36f-5214-4cd7-928f-1139df71c938
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957953344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3957953344
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1492752997
Short name T52
Test name
Test status
Simulation time 55392546 ps
CPU time 0.87 seconds
Started Aug 15 05:25:35 PM PDT 24
Finished Aug 15 05:25:36 PM PDT 24
Peak memory 214828 kb
Host smart-fa086f96-54ce-455f-90ef-6be7493ae554
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492752997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1492752997
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1414583367
Short name T148
Test name
Test status
Simulation time 75197239 ps
CPU time 1.15 seconds
Started Aug 15 05:25:44 PM PDT 24
Finished Aug 15 05:25:45 PM PDT 24
Peak memory 196016 kb
Host smart-6b3d4e3a-a478-42dd-a5e8-71c71d1f2441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414583367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1414583367
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1695814315
Short name T105
Test name
Test status
Simulation time 44436662 ps
CPU time 1.17 seconds
Started Aug 15 05:25:40 PM PDT 24
Finished Aug 15 05:25:41 PM PDT 24
Peak memory 196704 kb
Host smart-bc2df132-73d8-437b-94a3-4507398aaf33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695814315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1695814315
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3516982298
Short name T126
Test name
Test status
Simulation time 16811070617 ps
CPU time 228.49 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:29:43 PM PDT 24
Peak memory 198368 kb
Host smart-32bf8a82-e2bf-442f-80db-967b95fa37f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516982298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3516982298
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.319033825
Short name T65
Test name
Test status
Simulation time 10844814487 ps
CPU time 207.77 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:29:20 PM PDT 24
Peak memory 198508 kb
Host smart-82452a22-4f80-46d3-b6bb-1e8bbc28c2f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=319033825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.319033825
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3000753858
Short name T590
Test name
Test status
Simulation time 14265927 ps
CPU time 0.58 seconds
Started Aug 15 05:27:00 PM PDT 24
Finished Aug 15 05:27:01 PM PDT 24
Peak memory 194756 kb
Host smart-117f40cc-b134-4385-89ff-f240a88661c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000753858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3000753858
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.518691598
Short name T362
Test name
Test status
Simulation time 102352625 ps
CPU time 0.83 seconds
Started Aug 15 05:26:55 PM PDT 24
Finished Aug 15 05:26:56 PM PDT 24
Peak memory 196612 kb
Host smart-e662c0f4-98e8-40b3-85ef-26eee66c0ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518691598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.518691598
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.757377330
Short name T409
Test name
Test status
Simulation time 624636999 ps
CPU time 18.23 seconds
Started Aug 15 05:27:01 PM PDT 24
Finished Aug 15 05:27:19 PM PDT 24
Peak memory 197276 kb
Host smart-6b50c9dc-5d6a-4630-9e0d-6e9116b54f11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757377330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.757377330
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3076844502
Short name T209
Test name
Test status
Simulation time 28621859 ps
CPU time 0.65 seconds
Started Aug 15 05:27:05 PM PDT 24
Finished Aug 15 05:27:06 PM PDT 24
Peak memory 195344 kb
Host smart-e58f3a06-b2e4-4377-b308-4a6f4a7a90f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076844502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3076844502
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.4251892429
Short name T673
Test name
Test status
Simulation time 97378887 ps
CPU time 1.35 seconds
Started Aug 15 05:27:12 PM PDT 24
Finished Aug 15 05:27:13 PM PDT 24
Peak memory 196684 kb
Host smart-4ba51e3c-e3c5-43be-bc44-d185c8fc2918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251892429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.4251892429
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3792897005
Short name T282
Test name
Test status
Simulation time 59638515 ps
CPU time 2.3 seconds
Started Aug 15 05:27:15 PM PDT 24
Finished Aug 15 05:27:17 PM PDT 24
Peak memory 198160 kb
Host smart-5ff7f5f3-43e3-4ad1-8277-ca48547e6794
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792897005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3792897005
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3515627174
Short name T327
Test name
Test status
Simulation time 169928076 ps
CPU time 3.23 seconds
Started Aug 15 05:27:00 PM PDT 24
Finished Aug 15 05:27:04 PM PDT 24
Peak memory 196672 kb
Host smart-811d5b91-6a27-47a3-bb98-3efb290cc07c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515627174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3515627174
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3176662684
Short name T23
Test name
Test status
Simulation time 186208150 ps
CPU time 1.1 seconds
Started Aug 15 05:27:01 PM PDT 24
Finished Aug 15 05:27:02 PM PDT 24
Peak memory 195932 kb
Host smart-22858ec2-b92e-4ffb-8422-25afb02112c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176662684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3176662684
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1684090924
Short name T13
Test name
Test status
Simulation time 93614320 ps
CPU time 0.82 seconds
Started Aug 15 05:27:08 PM PDT 24
Finished Aug 15 05:27:09 PM PDT 24
Peak memory 195476 kb
Host smart-7c4300ef-1a8c-4b5a-97f5-2a59d2575b55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684090924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1684090924
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_smoke.276699489
Short name T654
Test name
Test status
Simulation time 143386675 ps
CPU time 1 seconds
Started Aug 15 05:26:55 PM PDT 24
Finished Aug 15 05:26:56 PM PDT 24
Peak memory 195608 kb
Host smart-3ffab3f9-c98c-4031-86b4-08fcbc076e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276699489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.276699489
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2857210139
Short name T482
Test name
Test status
Simulation time 213710639 ps
CPU time 1.29 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 198140 kb
Host smart-b0160646-d528-4697-bec8-b96a17170bfa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857210139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2857210139
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3753691340
Short name T534
Test name
Test status
Simulation time 24346802696 ps
CPU time 130.77 seconds
Started Aug 15 05:26:59 PM PDT 24
Finished Aug 15 05:29:10 PM PDT 24
Peak memory 198284 kb
Host smart-59e29306-16b5-446b-a0df-91220bf5c5a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753691340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3753691340
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2412361595
Short name T415
Test name
Test status
Simulation time 21702819 ps
CPU time 0.56 seconds
Started Aug 15 05:27:09 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 194072 kb
Host smart-1808d339-eefc-4be5-bf5d-8eee5b4f234f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412361595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2412361595
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2671629958
Short name T133
Test name
Test status
Simulation time 159418520 ps
CPU time 0.83 seconds
Started Aug 15 05:27:18 PM PDT 24
Finished Aug 15 05:27:19 PM PDT 24
Peak memory 195596 kb
Host smart-1171cbf0-0f0c-416e-9f9b-00ba8f4b26b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671629958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2671629958
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3281656839
Short name T373
Test name
Test status
Simulation time 126007554 ps
CPU time 5.01 seconds
Started Aug 15 05:27:01 PM PDT 24
Finished Aug 15 05:27:07 PM PDT 24
Peak memory 196724 kb
Host smart-8fe8e0d8-8580-4f54-a7bd-4743b4570a56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281656839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3281656839
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1765001366
Short name T311
Test name
Test status
Simulation time 239168183 ps
CPU time 0.83 seconds
Started Aug 15 05:27:20 PM PDT 24
Finished Aug 15 05:27:21 PM PDT 24
Peak memory 196192 kb
Host smart-9f4e55f7-b430-485a-869e-62ae836cc2c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765001366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1765001366
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1297172563
Short name T685
Test name
Test status
Simulation time 81398677 ps
CPU time 1.23 seconds
Started Aug 15 05:27:18 PM PDT 24
Finished Aug 15 05:27:19 PM PDT 24
Peak memory 197264 kb
Host smart-ef60e7c0-82e0-4554-9d54-471a47f7277a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297172563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1297172563
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1787103242
Short name T547
Test name
Test status
Simulation time 135293783 ps
CPU time 3.18 seconds
Started Aug 15 05:27:07 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 196620 kb
Host smart-e8466418-e45e-4dd9-a6d9-38ac0da7ba84
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787103242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1787103242
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1296965805
Short name T493
Test name
Test status
Simulation time 264023800 ps
CPU time 2.84 seconds
Started Aug 15 05:27:18 PM PDT 24
Finished Aug 15 05:27:21 PM PDT 24
Peak memory 197424 kb
Host smart-356d6f65-97a0-4d54-b16d-0a61f9d2bc4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296965805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1296965805
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.931198908
Short name T664
Test name
Test status
Simulation time 58755636 ps
CPU time 0.77 seconds
Started Aug 15 05:27:13 PM PDT 24
Finished Aug 15 05:27:14 PM PDT 24
Peak memory 195576 kb
Host smart-56e35f53-0047-4e27-bb8d-c143f8c9754e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931198908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.931198908
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3778093059
Short name T347
Test name
Test status
Simulation time 27631278 ps
CPU time 0.78 seconds
Started Aug 15 05:27:11 PM PDT 24
Finished Aug 15 05:27:12 PM PDT 24
Peak memory 195528 kb
Host smart-6d464804-ebda-439f-966d-5f39a0c1e0a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778093059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3778093059
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.4128362167
Short name T632
Test name
Test status
Simulation time 259705767 ps
CPU time 2.27 seconds
Started Aug 15 05:27:08 PM PDT 24
Finished Aug 15 05:27:11 PM PDT 24
Peak memory 198148 kb
Host smart-c2bd6e24-fb1d-4e7c-8213-6f67e5de6996
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128362167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.4128362167
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.720769733
Short name T309
Test name
Test status
Simulation time 63144534 ps
CPU time 0.98 seconds
Started Aug 15 05:27:15 PM PDT 24
Finished Aug 15 05:27:16 PM PDT 24
Peak memory 196336 kb
Host smart-6684eeb0-7203-4407-857c-550c2ee21623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720769733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.720769733
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1883847728
Short name T496
Test name
Test status
Simulation time 51201333 ps
CPU time 0.96 seconds
Started Aug 15 05:27:08 PM PDT 24
Finished Aug 15 05:27:09 PM PDT 24
Peak memory 196360 kb
Host smart-d966cc9d-d9c4-4f04-81e5-209a4e1b9add
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883847728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1883847728
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2015867096
Short name T366
Test name
Test status
Simulation time 33494760475 ps
CPU time 83.26 seconds
Started Aug 15 05:27:08 PM PDT 24
Finished Aug 15 05:28:32 PM PDT 24
Peak memory 198336 kb
Host smart-8dc9e903-c028-4e08-bd7e-7766d1832dd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015867096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2015867096
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3307695757
Short name T600
Test name
Test status
Simulation time 26068049 ps
CPU time 0.57 seconds
Started Aug 15 05:27:07 PM PDT 24
Finished Aug 15 05:27:08 PM PDT 24
Peak memory 194744 kb
Host smart-96d7b54c-f2c6-45ec-a38f-e09acfc20a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307695757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3307695757
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1787739480
Short name T354
Test name
Test status
Simulation time 27931318 ps
CPU time 0.69 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 194304 kb
Host smart-cbe67351-0537-448a-b206-5ad9a0a96ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787739480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1787739480
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.152688083
Short name T385
Test name
Test status
Simulation time 617691741 ps
CPU time 18.76 seconds
Started Aug 15 05:27:08 PM PDT 24
Finished Aug 15 05:27:27 PM PDT 24
Peak memory 198132 kb
Host smart-943852a8-d4fe-4abc-a8a4-a3fe569f99a8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152688083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.152688083
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2474228572
Short name T308
Test name
Test status
Simulation time 281553783 ps
CPU time 0.73 seconds
Started Aug 15 05:26:51 PM PDT 24
Finished Aug 15 05:26:52 PM PDT 24
Peak memory 194924 kb
Host smart-922d9019-e9a8-4230-8bdb-e5308f744397
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474228572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2474228572
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1718079598
Short name T490
Test name
Test status
Simulation time 102224903 ps
CPU time 1.53 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 197184 kb
Host smart-f75a5c79-59b2-4aed-956e-ecca05129b79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718079598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1718079598
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1450811375
Short name T357
Test name
Test status
Simulation time 87196603 ps
CPU time 3.45 seconds
Started Aug 15 05:27:07 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 198212 kb
Host smart-15e4cce0-936a-4aa4-9f7a-56d355d2051f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450811375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1450811375
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2164579805
Short name T404
Test name
Test status
Simulation time 221800617 ps
CPU time 1.27 seconds
Started Aug 15 05:26:53 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 197032 kb
Host smart-ae8f6b16-3113-4eb7-81ff-bc64f089bd36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164579805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2164579805
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.4114425253
Short name T25
Test name
Test status
Simulation time 182157939 ps
CPU time 1.19 seconds
Started Aug 15 05:26:58 PM PDT 24
Finished Aug 15 05:27:00 PM PDT 24
Peak memory 196808 kb
Host smart-39c9cc13-79a3-442e-aaf3-36714f2ba3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114425253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.4114425253
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.774563101
Short name T451
Test name
Test status
Simulation time 63652706 ps
CPU time 0.8 seconds
Started Aug 15 05:26:49 PM PDT 24
Finished Aug 15 05:26:50 PM PDT 24
Peak memory 196528 kb
Host smart-ffe40513-d207-4b63-937a-3d8fe4a09b3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774563101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.774563101
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.95957644
Short name T359
Test name
Test status
Simulation time 93878320 ps
CPU time 4.13 seconds
Started Aug 15 05:26:51 PM PDT 24
Finished Aug 15 05:26:56 PM PDT 24
Peak memory 198080 kb
Host smart-f018e879-bf3d-4408-945f-b223b1b6acdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95957644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand
om_long_reg_writes_reg_reads.95957644
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3581098353
Short name T212
Test name
Test status
Simulation time 29376641 ps
CPU time 0.71 seconds
Started Aug 15 05:26:49 PM PDT 24
Finished Aug 15 05:26:49 PM PDT 24
Peak memory 195212 kb
Host smart-adc9e89b-14f6-46a8-ae3f-ab1e1436ebe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581098353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3581098353
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1851947025
Short name T663
Test name
Test status
Simulation time 96939564 ps
CPU time 1.21 seconds
Started Aug 15 05:26:53 PM PDT 24
Finished Aug 15 05:26:57 PM PDT 24
Peak memory 195952 kb
Host smart-e5ec8c97-84d1-40f6-a923-be27a00e77a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851947025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1851947025
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3242948127
Short name T199
Test name
Test status
Simulation time 6508754481 ps
CPU time 82.08 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:28:15 PM PDT 24
Peak memory 192072 kb
Host smart-9c49296a-cb48-43fb-b922-122c507d2fd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242948127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3242948127
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.290945470
Short name T470
Test name
Test status
Simulation time 4602875624 ps
CPU time 67.16 seconds
Started Aug 15 05:27:02 PM PDT 24
Finished Aug 15 05:28:10 PM PDT 24
Peak memory 198552 kb
Host smart-a9fddd59-a711-4915-a24f-f2e07cf9dbc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=290945470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.290945470
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2413281356
Short name T384
Test name
Test status
Simulation time 28047197 ps
CPU time 0.57 seconds
Started Aug 15 05:26:59 PM PDT 24
Finished Aug 15 05:27:00 PM PDT 24
Peak memory 194244 kb
Host smart-821a04a3-3058-4f59-83ad-631e5ac5489a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413281356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2413281356
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.4131229093
Short name T574
Test name
Test status
Simulation time 34867528 ps
CPU time 0.68 seconds
Started Aug 15 05:26:56 PM PDT 24
Finished Aug 15 05:26:57 PM PDT 24
Peak memory 194284 kb
Host smart-e2d32a7e-9cd2-4568-8bf2-95fc361ea213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131229093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.4131229093
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3915213229
Short name T73
Test name
Test status
Simulation time 610678934 ps
CPU time 5.88 seconds
Started Aug 15 05:27:04 PM PDT 24
Finished Aug 15 05:27:10 PM PDT 24
Peak memory 197112 kb
Host smart-7b21e556-0e65-4678-8f8e-93723e61c437
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915213229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3915213229
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1003019505
Short name T164
Test name
Test status
Simulation time 189730193 ps
CPU time 0.68 seconds
Started Aug 15 05:27:01 PM PDT 24
Finished Aug 15 05:27:02 PM PDT 24
Peak memory 194000 kb
Host smart-ac26cfe7-465d-4616-9fd9-3ca7a025b88c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003019505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1003019505
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2983501706
Short name T466
Test name
Test status
Simulation time 81554567 ps
CPU time 0.83 seconds
Started Aug 15 05:27:02 PM PDT 24
Finished Aug 15 05:27:03 PM PDT 24
Peak memory 195004 kb
Host smart-df3f657c-1f04-4330-aa5c-81074e46c38f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983501706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2983501706
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.511253002
Short name T431
Test name
Test status
Simulation time 86222209 ps
CPU time 3.34 seconds
Started Aug 15 05:26:59 PM PDT 24
Finished Aug 15 05:27:03 PM PDT 24
Peak memory 198224 kb
Host smart-726e8b99-d998-492b-8a43-4859e2f46f30
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511253002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.511253002
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3339572614
Short name T360
Test name
Test status
Simulation time 120605062 ps
CPU time 1.26 seconds
Started Aug 15 05:27:01 PM PDT 24
Finished Aug 15 05:27:02 PM PDT 24
Peak memory 196880 kb
Host smart-2d153c85-b327-4853-bb97-10d136101bbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339572614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3339572614
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3601885206
Short name T403
Test name
Test status
Simulation time 130359330 ps
CPU time 0.78 seconds
Started Aug 15 05:26:55 PM PDT 24
Finished Aug 15 05:26:56 PM PDT 24
Peak memory 195532 kb
Host smart-d866e38e-7ad2-44c6-b314-0bc3e9ab9b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601885206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3601885206
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3596791961
Short name T653
Test name
Test status
Simulation time 36860857 ps
CPU time 0.94 seconds
Started Aug 15 05:26:58 PM PDT 24
Finished Aug 15 05:26:59 PM PDT 24
Peak memory 195984 kb
Host smart-f4ac5fd6-0029-49ba-8626-8bdac363b84f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596791961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3596791961
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2542026946
Short name T599
Test name
Test status
Simulation time 522433878 ps
CPU time 5.81 seconds
Started Aug 15 05:27:02 PM PDT 24
Finished Aug 15 05:27:08 PM PDT 24
Peak memory 198048 kb
Host smart-68395ddc-1b0c-41a6-ad8e-abe874ea5ddf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542026946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2542026946
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2041483319
Short name T614
Test name
Test status
Simulation time 94883700 ps
CPU time 1.45 seconds
Started Aug 15 05:26:56 PM PDT 24
Finished Aug 15 05:26:57 PM PDT 24
Peak memory 196972 kb
Host smart-ecef4a63-41e4-427d-b0d0-91633635bad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041483319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2041483319
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1960502687
Short name T498
Test name
Test status
Simulation time 53681127 ps
CPU time 1.1 seconds
Started Aug 15 05:27:01 PM PDT 24
Finished Aug 15 05:27:02 PM PDT 24
Peak memory 195716 kb
Host smart-80b5f3c7-e916-40bb-b3ce-53874be2047b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960502687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1960502687
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2740470984
Short name T649
Test name
Test status
Simulation time 6541329417 ps
CPU time 88.08 seconds
Started Aug 15 05:27:01 PM PDT 24
Finished Aug 15 05:28:29 PM PDT 24
Peak memory 197636 kb
Host smart-926e85c4-80c5-42af-9b65-b47b6a3e260d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740470984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2740470984
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2153203790
Short name T483
Test name
Test status
Simulation time 23813194 ps
CPU time 0.56 seconds
Started Aug 15 05:27:00 PM PDT 24
Finished Aug 15 05:27:01 PM PDT 24
Peak memory 194200 kb
Host smart-af59f8eb-bce0-4c83-b013-08a226ce5bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153203790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2153203790
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3866206442
Short name T563
Test name
Test status
Simulation time 29491873 ps
CPU time 0.8 seconds
Started Aug 15 05:27:14 PM PDT 24
Finished Aug 15 05:27:15 PM PDT 24
Peak memory 196396 kb
Host smart-f9bbb1ea-1e9c-4f26-83e9-f4a4f69021c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866206442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3866206442
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1237557040
Short name T162
Test name
Test status
Simulation time 1353713995 ps
CPU time 16.33 seconds
Started Aug 15 05:27:06 PM PDT 24
Finished Aug 15 05:27:23 PM PDT 24
Peak memory 197008 kb
Host smart-d96647a0-959e-49b0-8633-43550d4216e6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237557040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1237557040
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1079199397
Short name T297
Test name
Test status
Simulation time 247804646 ps
CPU time 0.86 seconds
Started Aug 15 05:27:13 PM PDT 24
Finished Aug 15 05:27:14 PM PDT 24
Peak memory 196188 kb
Host smart-fb3ee91c-9fd4-46ae-88c9-91d93a713d89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079199397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1079199397
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.465769020
Short name T265
Test name
Test status
Simulation time 109454731 ps
CPU time 0.9 seconds
Started Aug 15 05:27:07 PM PDT 24
Finished Aug 15 05:27:08 PM PDT 24
Peak memory 196280 kb
Host smart-d34a2165-08d0-4fc5-8f87-98cae0b770e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465769020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.465769020
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2855099569
Short name T143
Test name
Test status
Simulation time 27156848 ps
CPU time 1.05 seconds
Started Aug 15 05:27:12 PM PDT 24
Finished Aug 15 05:27:13 PM PDT 24
Peak memory 197240 kb
Host smart-62154bd6-eb85-4727-ba63-d1a73e938c47
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855099569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2855099569
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.897750058
Short name T176
Test name
Test status
Simulation time 274123210 ps
CPU time 1.55 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 196940 kb
Host smart-73b0ea8f-ef51-402c-8227-c4d876d16c8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897750058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
897750058
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4151567196
Short name T294
Test name
Test status
Simulation time 19992806 ps
CPU time 0.66 seconds
Started Aug 15 05:26:53 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 195104 kb
Host smart-54882755-d335-4fbc-8ce1-c2967c6e667f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151567196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4151567196
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.943870905
Short name T608
Test name
Test status
Simulation time 397052154 ps
CPU time 1.19 seconds
Started Aug 15 05:26:51 PM PDT 24
Finished Aug 15 05:26:53 PM PDT 24
Peak memory 197140 kb
Host smart-dba1f7ed-54db-462e-8cc6-b88a43cf4ad6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943870905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.943870905
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1813095124
Short name T7
Test name
Test status
Simulation time 366197219 ps
CPU time 4.29 seconds
Started Aug 15 05:27:12 PM PDT 24
Finished Aug 15 05:27:17 PM PDT 24
Peak memory 198176 kb
Host smart-0e93c4b0-a63f-44a5-a6b0-c3652189f558
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813095124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1813095124
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.764905256
Short name T546
Test name
Test status
Simulation time 49637056 ps
CPU time 1.06 seconds
Started Aug 15 05:27:00 PM PDT 24
Finished Aug 15 05:27:02 PM PDT 24
Peak memory 195700 kb
Host smart-bc4a0f09-6d27-43f2-8aaf-5e0879cf4797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764905256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.764905256
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3057883277
Short name T341
Test name
Test status
Simulation time 69634311 ps
CPU time 0.87 seconds
Started Aug 15 05:26:52 PM PDT 24
Finished Aug 15 05:26:54 PM PDT 24
Peak memory 196352 kb
Host smart-a5c42f92-562d-42c6-8044-1959f739e86f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057883277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3057883277
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3613657956
Short name T18
Test name
Test status
Simulation time 199913677869 ps
CPU time 186.87 seconds
Started Aug 15 05:27:09 PM PDT 24
Finished Aug 15 05:30:16 PM PDT 24
Peak memory 198344 kb
Host smart-99b71c75-5537-4890-b0c7-8b7723c76d66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613657956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3613657956
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2845884717
Short name T621
Test name
Test status
Simulation time 12076590 ps
CPU time 0.56 seconds
Started Aug 15 05:26:54 PM PDT 24
Finished Aug 15 05:26:55 PM PDT 24
Peak memory 194056 kb
Host smart-cde9a255-1607-4781-b527-8c92b41dd20a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845884717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2845884717
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.488020657
Short name T407
Test name
Test status
Simulation time 16146164 ps
CPU time 0.66 seconds
Started Aug 15 05:27:15 PM PDT 24
Finished Aug 15 05:27:15 PM PDT 24
Peak memory 193996 kb
Host smart-4b575a13-3823-43ae-a1fc-477451628042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488020657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.488020657
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2148467708
Short name T459
Test name
Test status
Simulation time 2223894341 ps
CPU time 15.37 seconds
Started Aug 15 05:27:18 PM PDT 24
Finished Aug 15 05:27:33 PM PDT 24
Peak memory 197252 kb
Host smart-b7a982d8-7626-488e-b468-12715b41e04c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148467708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2148467708
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1054470724
Short name T544
Test name
Test status
Simulation time 119551548 ps
CPU time 0.66 seconds
Started Aug 15 05:27:01 PM PDT 24
Finished Aug 15 05:27:02 PM PDT 24
Peak memory 195348 kb
Host smart-12c3b8b9-e3fb-4bbe-b28b-e99896196b39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054470724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1054470724
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1423739102
Short name T594
Test name
Test status
Simulation time 359803056 ps
CPU time 1.38 seconds
Started Aug 15 05:27:20 PM PDT 24
Finished Aug 15 05:27:22 PM PDT 24
Peak memory 197272 kb
Host smart-007e2f97-ab53-44bf-9ea6-d043e498dbde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423739102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1423739102
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1949627563
Short name T712
Test name
Test status
Simulation time 172831531 ps
CPU time 3.44 seconds
Started Aug 15 05:27:11 PM PDT 24
Finished Aug 15 05:27:15 PM PDT 24
Peak memory 198064 kb
Host smart-09438534-ad64-4186-97c8-32ef9e92b190
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949627563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1949627563
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1088503455
Short name T677
Test name
Test status
Simulation time 39186688 ps
CPU time 1.07 seconds
Started Aug 15 05:27:14 PM PDT 24
Finished Aug 15 05:27:15 PM PDT 24
Peak memory 196248 kb
Host smart-4e22b4fb-a229-4a46-9423-ba23cddf45c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088503455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1088503455
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3999512415
Short name T108
Test name
Test status
Simulation time 202520155 ps
CPU time 0.86 seconds
Started Aug 15 05:26:59 PM PDT 24
Finished Aug 15 05:27:00 PM PDT 24
Peak memory 196160 kb
Host smart-b08ec762-711b-4865-ad63-fcfd21b02eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999512415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3999512415
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.874999874
Short name T336
Test name
Test status
Simulation time 45057132 ps
CPU time 1.01 seconds
Started Aug 15 05:27:08 PM PDT 24
Finished Aug 15 05:27:09 PM PDT 24
Peak memory 195928 kb
Host smart-792009e4-d9a9-4157-8644-de1dc03b49c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874999874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.874999874
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3391022943
Short name T708
Test name
Test status
Simulation time 33068228 ps
CPU time 1.15 seconds
Started Aug 15 05:27:12 PM PDT 24
Finished Aug 15 05:27:14 PM PDT 24
Peak memory 197944 kb
Host smart-e61267a5-851a-4553-aab5-4bac6b65bb06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391022943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3391022943
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.586303545
Short name T519
Test name
Test status
Simulation time 1057745535 ps
CPU time 1.17 seconds
Started Aug 15 05:27:06 PM PDT 24
Finished Aug 15 05:27:07 PM PDT 24
Peak memory 196504 kb
Host smart-9281e215-63a5-4977-855e-0c0d21aa0eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586303545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.586303545
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1474146667
Short name T332
Test name
Test status
Simulation time 27275367 ps
CPU time 0.93 seconds
Started Aug 15 05:27:14 PM PDT 24
Finished Aug 15 05:27:15 PM PDT 24
Peak memory 195828 kb
Host smart-4093e658-edd8-458e-9059-9455f6fecc36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474146667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1474146667
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3486571422
Short name T410
Test name
Test status
Simulation time 1021939901 ps
CPU time 26.65 seconds
Started Aug 15 05:27:28 PM PDT 24
Finished Aug 15 05:27:54 PM PDT 24
Peak memory 198112 kb
Host smart-9ac5fd8a-2295-447b-864e-f01c9dd877e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486571422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3486571422
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1026286432
Short name T305
Test name
Test status
Simulation time 74368439 ps
CPU time 0.55 seconds
Started Aug 15 05:27:00 PM PDT 24
Finished Aug 15 05:27:01 PM PDT 24
Peak memory 194768 kb
Host smart-7f442c3b-e73d-44b4-93e3-52acc66530be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026286432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1026286432
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2914914103
Short name T687
Test name
Test status
Simulation time 29484046 ps
CPU time 0.83 seconds
Started Aug 15 05:27:13 PM PDT 24
Finished Aug 15 05:27:14 PM PDT 24
Peak memory 195556 kb
Host smart-80c5bba5-f184-4a8e-abbe-93f7b3883005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914914103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2914914103
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3116990736
Short name T516
Test name
Test status
Simulation time 532453113 ps
CPU time 27 seconds
Started Aug 15 05:27:09 PM PDT 24
Finished Aug 15 05:27:36 PM PDT 24
Peak memory 198180 kb
Host smart-60124d89-b676-4a43-b7d1-4796e186dff6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116990736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3116990736
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.520427233
Short name T315
Test name
Test status
Simulation time 208252094 ps
CPU time 0.81 seconds
Started Aug 15 05:27:13 PM PDT 24
Finished Aug 15 05:27:14 PM PDT 24
Peak memory 196028 kb
Host smart-a76dce36-ff12-4103-9f8d-baa69da98da9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520427233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.520427233
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3077447899
Short name T370
Test name
Test status
Simulation time 186826660 ps
CPU time 1.33 seconds
Started Aug 15 05:27:20 PM PDT 24
Finished Aug 15 05:27:21 PM PDT 24
Peak memory 196664 kb
Host smart-4957aca8-5b1f-4619-bcfd-74b74da39098
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077447899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3077447899
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3524632492
Short name T412
Test name
Test status
Simulation time 56471443 ps
CPU time 1.18 seconds
Started Aug 15 05:26:53 PM PDT 24
Finished Aug 15 05:26:59 PM PDT 24
Peak memory 196028 kb
Host smart-c2c463cf-2c9d-4b6a-9899-4c931a03fd02
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524632492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3524632492
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2007403013
Short name T540
Test name
Test status
Simulation time 105597423 ps
CPU time 1.6 seconds
Started Aug 15 05:27:13 PM PDT 24
Finished Aug 15 05:27:14 PM PDT 24
Peak memory 195968 kb
Host smart-f168de30-cdae-46cc-ad82-26cb93469c0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007403013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2007403013
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1237418661
Short name T325
Test name
Test status
Simulation time 94495663 ps
CPU time 0.85 seconds
Started Aug 15 05:27:20 PM PDT 24
Finished Aug 15 05:27:21 PM PDT 24
Peak memory 196568 kb
Host smart-c89de48c-1730-42d0-b7c0-6f0ba1fa96ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237418661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1237418661
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1538894754
Short name T21
Test name
Test status
Simulation time 19807871 ps
CPU time 0.8 seconds
Started Aug 15 05:27:13 PM PDT 24
Finished Aug 15 05:27:14 PM PDT 24
Peak memory 196740 kb
Host smart-910ea209-8df5-4985-947e-8df94812904c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538894754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1538894754
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4205460836
Short name T641
Test name
Test status
Simulation time 949666733 ps
CPU time 4.85 seconds
Started Aug 15 05:27:18 PM PDT 24
Finished Aug 15 05:27:23 PM PDT 24
Peak memory 198052 kb
Host smart-dcb78244-e412-4938-b4c9-e13e2dfcaa00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205460836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4205460836
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.4070224351
Short name T689
Test name
Test status
Simulation time 48777834 ps
CPU time 0.96 seconds
Started Aug 15 05:27:06 PM PDT 24
Finished Aug 15 05:27:07 PM PDT 24
Peak memory 195968 kb
Host smart-78f1e92d-c43c-4d7c-a79e-d01c8729933a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070224351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.4070224351
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2475503032
Short name T28
Test name
Test status
Simulation time 254613066 ps
CPU time 1.27 seconds
Started Aug 15 05:27:06 PM PDT 24
Finished Aug 15 05:27:07 PM PDT 24
Peak memory 195636 kb
Host smart-f60a8df6-6853-4eba-b054-b4045f4e04f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475503032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2475503032
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3874361391
Short name T153
Test name
Test status
Simulation time 3458845132 ps
CPU time 47.61 seconds
Started Aug 15 05:27:19 PM PDT 24
Finished Aug 15 05:28:06 PM PDT 24
Peak memory 198296 kb
Host smart-e765957e-3f70-4572-8568-757a36b1c3da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874361391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3874361391
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1350347802
Short name T14
Test name
Test status
Simulation time 32157925 ps
CPU time 0.57 seconds
Started Aug 15 05:27:18 PM PDT 24
Finished Aug 15 05:27:18 PM PDT 24
Peak memory 193980 kb
Host smart-138847b8-22cc-406d-954b-0c6d5218dc85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350347802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1350347802
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3237216628
Short name T644
Test name
Test status
Simulation time 33016698 ps
CPU time 0.75 seconds
Started Aug 15 05:27:08 PM PDT 24
Finished Aug 15 05:27:09 PM PDT 24
Peak memory 195168 kb
Host smart-d66c7507-e476-497a-8ca8-e6830a2e871c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237216628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3237216628
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1345225207
Short name T607
Test name
Test status
Simulation time 80488492 ps
CPU time 3.98 seconds
Started Aug 15 05:27:13 PM PDT 24
Finished Aug 15 05:27:17 PM PDT 24
Peak memory 195816 kb
Host smart-be979fbc-9048-4224-8e84-a91d9b56aa7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345225207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1345225207
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2546102515
Short name T564
Test name
Test status
Simulation time 32582143 ps
CPU time 0.74 seconds
Started Aug 15 05:26:54 PM PDT 24
Finished Aug 15 05:26:55 PM PDT 24
Peak memory 195048 kb
Host smart-a065f119-d8a2-4740-b104-1bc607614a25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546102515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2546102515
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1713984073
Short name T262
Test name
Test status
Simulation time 43448738 ps
CPU time 1.26 seconds
Started Aug 15 05:27:16 PM PDT 24
Finished Aug 15 05:27:17 PM PDT 24
Peak memory 197264 kb
Host smart-3afd9e82-2fe4-47a0-aa1e-966bc9c3c066
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713984073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1713984073
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1525743625
Short name T561
Test name
Test status
Simulation time 148287002 ps
CPU time 2.99 seconds
Started Aug 15 05:26:54 PM PDT 24
Finished Aug 15 05:26:57 PM PDT 24
Peak memory 195776 kb
Host smart-fcea6054-c868-4bd1-a08f-5e4fffe2fa00
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525743625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1525743625
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.4012951781
Short name T510
Test name
Test status
Simulation time 254437743 ps
CPU time 1.95 seconds
Started Aug 15 05:27:18 PM PDT 24
Finished Aug 15 05:27:20 PM PDT 24
Peak memory 197180 kb
Host smart-3d2a0ad3-d25d-4031-834a-527dafa44a06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012951781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.4012951781
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.4050744187
Short name T536
Test name
Test status
Simulation time 64924712 ps
CPU time 1.21 seconds
Started Aug 15 05:27:01 PM PDT 24
Finished Aug 15 05:27:02 PM PDT 24
Peak memory 196224 kb
Host smart-c716437c-7efc-4a1f-aa2c-ce13450b7cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050744187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.4050744187
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3459920164
Short name T465
Test name
Test status
Simulation time 196665819 ps
CPU time 0.94 seconds
Started Aug 15 05:26:51 PM PDT 24
Finished Aug 15 05:26:52 PM PDT 24
Peak memory 196640 kb
Host smart-5e061e4c-a0c4-4137-b2c5-947712cc700f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459920164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3459920164
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.470421086
Short name T421
Test name
Test status
Simulation time 126879526 ps
CPU time 2.87 seconds
Started Aug 15 05:27:17 PM PDT 24
Finished Aug 15 05:27:20 PM PDT 24
Peak memory 198048 kb
Host smart-788b069b-0f34-4250-b93b-cea3ba547653
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470421086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.470421086
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2582609490
Short name T155
Test name
Test status
Simulation time 80974737 ps
CPU time 0.79 seconds
Started Aug 15 05:27:00 PM PDT 24
Finished Aug 15 05:27:01 PM PDT 24
Peak memory 195408 kb
Host smart-e8e14179-62ba-4f09-8f27-d36b9d739513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582609490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2582609490
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2190077408
Short name T454
Test name
Test status
Simulation time 229103239 ps
CPU time 0.78 seconds
Started Aug 15 05:27:21 PM PDT 24
Finished Aug 15 05:27:22 PM PDT 24
Peak memory 195400 kb
Host smart-3febabcd-0b62-4bc6-9a0f-8c025df2f254
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190077408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2190077408
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2758531204
Short name T481
Test name
Test status
Simulation time 5285521902 ps
CPU time 140.69 seconds
Started Aug 15 05:27:11 PM PDT 24
Finished Aug 15 05:29:32 PM PDT 24
Peak memory 198344 kb
Host smart-d3e752d0-9c6e-486e-ad53-031d51fb813f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758531204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2758531204
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2073514032
Short name T676
Test name
Test status
Simulation time 81084886461 ps
CPU time 161.2 seconds
Started Aug 15 05:27:07 PM PDT 24
Finished Aug 15 05:29:49 PM PDT 24
Peak memory 198476 kb
Host smart-3cd8ea44-e2bb-48c0-b45e-20df9ff8001d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2073514032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2073514032
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1127871002
Short name T122
Test name
Test status
Simulation time 29312794 ps
CPU time 0.55 seconds
Started Aug 15 05:27:19 PM PDT 24
Finished Aug 15 05:27:20 PM PDT 24
Peak memory 194052 kb
Host smart-58965aa0-6853-4c47-982a-6a0fabb2519c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127871002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1127871002
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1905433392
Short name T528
Test name
Test status
Simulation time 39384501 ps
CPU time 0.9 seconds
Started Aug 15 05:27:15 PM PDT 24
Finished Aug 15 05:27:16 PM PDT 24
Peak memory 197448 kb
Host smart-6b77287c-6666-462b-ac4c-cf14db089aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905433392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1905433392
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3266158261
Short name T584
Test name
Test status
Simulation time 1823337072 ps
CPU time 11.29 seconds
Started Aug 15 05:27:09 PM PDT 24
Finished Aug 15 05:27:20 PM PDT 24
Peak memory 196788 kb
Host smart-d5c67946-27e6-411c-8c04-de3f9ca91c92
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266158261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3266158261
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3912666137
Short name T123
Test name
Test status
Simulation time 148506263 ps
CPU time 0.78 seconds
Started Aug 15 05:27:18 PM PDT 24
Finished Aug 15 05:27:19 PM PDT 24
Peak memory 196680 kb
Host smart-988b8ce5-9b01-4b51-a3ad-423d6adc3555
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912666137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3912666137
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1835682322
Short name T118
Test name
Test status
Simulation time 35002632 ps
CPU time 0.96 seconds
Started Aug 15 05:27:08 PM PDT 24
Finished Aug 15 05:27:09 PM PDT 24
Peak memory 195708 kb
Host smart-2545fa51-773e-473e-9a33-682001e07868
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835682322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1835682322
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.149319089
Short name T72
Test name
Test status
Simulation time 84889927 ps
CPU time 3.06 seconds
Started Aug 15 05:26:59 PM PDT 24
Finished Aug 15 05:27:02 PM PDT 24
Peak memory 197932 kb
Host smart-a2c6c13e-5280-4efa-ab0c-366502a0ff5d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149319089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.149319089
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1480930501
Short name T107
Test name
Test status
Simulation time 43191904 ps
CPU time 1.33 seconds
Started Aug 15 05:27:13 PM PDT 24
Finished Aug 15 05:27:15 PM PDT 24
Peak memory 196256 kb
Host smart-8d3e419c-7f61-40ed-af8c-1d33a2f57e30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480930501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1480930501
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1825616697
Short name T343
Test name
Test status
Simulation time 313319149 ps
CPU time 1.3 seconds
Started Aug 15 05:27:16 PM PDT 24
Finished Aug 15 05:27:17 PM PDT 24
Peak memory 195896 kb
Host smart-8310028e-efb2-4db4-9629-f0033fc5d288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825616697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1825616697
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3841538264
Short name T660
Test name
Test status
Simulation time 26333828 ps
CPU time 0.73 seconds
Started Aug 15 05:27:10 PM PDT 24
Finished Aug 15 05:27:11 PM PDT 24
Peak memory 196200 kb
Host smart-10b8d3e2-ed30-4d30-9c00-ffcd2b24d9ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841538264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3841538264
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2692921144
Short name T380
Test name
Test status
Simulation time 109903014 ps
CPU time 3.66 seconds
Started Aug 15 05:26:59 PM PDT 24
Finished Aug 15 05:27:02 PM PDT 24
Peak memory 198152 kb
Host smart-099ac5bb-3293-4b10-9c43-a7df9a7ed314
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692921144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2692921144
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1254230952
Short name T342
Test name
Test status
Simulation time 163640361 ps
CPU time 1.17 seconds
Started Aug 15 05:27:17 PM PDT 24
Finished Aug 15 05:27:18 PM PDT 24
Peak memory 196348 kb
Host smart-0ab6f052-0462-4bcf-bf7f-8ff0dc7da392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254230952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1254230952
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2176604957
Short name T371
Test name
Test status
Simulation time 63830840 ps
CPU time 1.13 seconds
Started Aug 15 05:27:20 PM PDT 24
Finished Aug 15 05:27:22 PM PDT 24
Peak memory 196516 kb
Host smart-0c97009d-2dd1-4bd0-ab3b-b0175d3ff2b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176604957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2176604957
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1917581612
Short name T286
Test name
Test status
Simulation time 4740355741 ps
CPU time 68.05 seconds
Started Aug 15 05:27:18 PM PDT 24
Finished Aug 15 05:28:26 PM PDT 24
Peak memory 198296 kb
Host smart-41662ee2-1ed2-4db0-81b0-b0454d7c0fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917581612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1917581612
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3705666115
Short name T186
Test name
Test status
Simulation time 14708995 ps
CPU time 0.59 seconds
Started Aug 15 05:27:27 PM PDT 24
Finished Aug 15 05:27:27 PM PDT 24
Peak memory 194020 kb
Host smart-b06ce9af-a81d-4f52-bfaf-be39debe526d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705666115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3705666115
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3025079332
Short name T666
Test name
Test status
Simulation time 171873583 ps
CPU time 0.84 seconds
Started Aug 15 05:27:15 PM PDT 24
Finished Aug 15 05:27:15 PM PDT 24
Peak memory 196340 kb
Host smart-3497f857-a97e-4173-8c58-f805d642cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025079332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3025079332
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.4012429385
Short name T221
Test name
Test status
Simulation time 933502575 ps
CPU time 14.76 seconds
Started Aug 15 05:27:23 PM PDT 24
Finished Aug 15 05:27:38 PM PDT 24
Peak memory 198116 kb
Host smart-76f5a3c3-f2d2-4138-9b61-31b975cc526d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012429385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.4012429385
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2265946809
Short name T573
Test name
Test status
Simulation time 52419266 ps
CPU time 0.83 seconds
Started Aug 15 05:27:24 PM PDT 24
Finished Aug 15 05:27:25 PM PDT 24
Peak memory 195948 kb
Host smart-f0d13d09-b801-4b58-a89b-47192027280e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265946809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2265946809
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1254662811
Short name T432
Test name
Test status
Simulation time 484702093 ps
CPU time 1.5 seconds
Started Aug 15 05:27:16 PM PDT 24
Finished Aug 15 05:27:17 PM PDT 24
Peak memory 197288 kb
Host smart-02b00575-3bd5-4e25-b84f-ff7b668fffd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254662811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1254662811
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.4026517963
Short name T458
Test name
Test status
Simulation time 67109645 ps
CPU time 0.92 seconds
Started Aug 15 05:27:02 PM PDT 24
Finished Aug 15 05:27:03 PM PDT 24
Peak memory 196016 kb
Host smart-d52bd632-4ac2-4390-ba9e-c7c69cf42785
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026517963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.4026517963
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3796983294
Short name T686
Test name
Test status
Simulation time 114695339 ps
CPU time 2.29 seconds
Started Aug 15 05:27:02 PM PDT 24
Finished Aug 15 05:27:04 PM PDT 24
Peak memory 197276 kb
Host smart-cb715046-d34a-461c-bd1f-fd7948c532b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796983294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3796983294
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2043185257
Short name T568
Test name
Test status
Simulation time 101688361 ps
CPU time 1.21 seconds
Started Aug 15 05:27:13 PM PDT 24
Finished Aug 15 05:27:14 PM PDT 24
Peak memory 196168 kb
Host smart-dc8b3a22-a643-44ed-9cf9-0f257bc880d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043185257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2043185257
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2481054771
Short name T116
Test name
Test status
Simulation time 43161149 ps
CPU time 0.66 seconds
Started Aug 15 05:27:16 PM PDT 24
Finished Aug 15 05:27:16 PM PDT 24
Peak memory 194356 kb
Host smart-5bdb60e4-a6f0-4371-a08d-a02a86dc6829
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481054771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2481054771
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2620161940
Short name T570
Test name
Test status
Simulation time 31559664 ps
CPU time 1.35 seconds
Started Aug 15 05:27:22 PM PDT 24
Finished Aug 15 05:27:23 PM PDT 24
Peak memory 198076 kb
Host smart-16c3f3ee-35a9-4a66-a44b-33c919dece23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620161940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2620161940
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1668061380
Short name T183
Test name
Test status
Simulation time 40217255 ps
CPU time 0.87 seconds
Started Aug 15 05:27:15 PM PDT 24
Finished Aug 15 05:27:16 PM PDT 24
Peak memory 195344 kb
Host smart-15a601bf-10b7-43f3-ba3b-2e178f8aeaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668061380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1668061380
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2847215143
Short name T194
Test name
Test status
Simulation time 238528704 ps
CPU time 1.39 seconds
Started Aug 15 05:26:58 PM PDT 24
Finished Aug 15 05:27:00 PM PDT 24
Peak memory 196840 kb
Host smart-74b6cc4c-fa05-4b53-86fa-19558978f48f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847215143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2847215143
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3562699143
Short name T333
Test name
Test status
Simulation time 1122314247 ps
CPU time 10.64 seconds
Started Aug 15 05:27:10 PM PDT 24
Finished Aug 15 05:27:21 PM PDT 24
Peak memory 198104 kb
Host smart-4b492d52-f371-4995-a1e9-8e2de591701d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562699143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3562699143
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1474948521
Short name T524
Test name
Test status
Simulation time 13848188992 ps
CPU time 124.23 seconds
Started Aug 15 05:27:28 PM PDT 24
Finished Aug 15 05:29:33 PM PDT 24
Peak memory 198568 kb
Host smart-c523f4ad-7c1a-4a97-be75-2e8960bc7109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1474948521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1474948521
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1293740249
Short name T553
Test name
Test status
Simulation time 44368592 ps
CPU time 0.56 seconds
Started Aug 15 05:25:44 PM PDT 24
Finished Aug 15 05:25:45 PM PDT 24
Peak memory 194956 kb
Host smart-58ee3710-99c8-4045-9d4d-1773aa5d8eda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293740249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1293740249
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.4241594967
Short name T337
Test name
Test status
Simulation time 42303256 ps
CPU time 0.87 seconds
Started Aug 15 05:25:45 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 195360 kb
Host smart-d98c2a0d-07ef-4095-9d37-7af9706e6ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241594967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.4241594967
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1525848436
Short name T170
Test name
Test status
Simulation time 6057962478 ps
CPU time 14.44 seconds
Started Aug 15 05:25:44 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 197124 kb
Host smart-39fd046d-736e-4362-b3c2-95a09ce04565
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525848436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1525848436
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3814010091
Short name T355
Test name
Test status
Simulation time 276660201 ps
CPU time 0.79 seconds
Started Aug 15 05:25:38 PM PDT 24
Finished Aug 15 05:25:39 PM PDT 24
Peak memory 195484 kb
Host smart-bd6eee75-a682-47d9-ae4e-3522816618ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814010091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3814010091
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.866435443
Short name T485
Test name
Test status
Simulation time 41287303 ps
CPU time 0.94 seconds
Started Aug 15 05:25:44 PM PDT 24
Finished Aug 15 05:25:45 PM PDT 24
Peak memory 197648 kb
Host smart-0fa1863b-4c35-4ee1-aedc-18ceee1e59f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866435443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.866435443
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2590080081
Short name T134
Test name
Test status
Simulation time 50839393 ps
CPU time 1.98 seconds
Started Aug 15 05:25:53 PM PDT 24
Finished Aug 15 05:25:55 PM PDT 24
Peak memory 198192 kb
Host smart-ab388075-80aa-4fb1-b95d-42ce7180adb3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590080081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2590080081
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3901441702
Short name T581
Test name
Test status
Simulation time 153888438 ps
CPU time 2.9 seconds
Started Aug 15 05:25:43 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 195944 kb
Host smart-d65633e1-3c0a-4f8d-852c-986bce8a2b03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901441702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3901441702
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1500636486
Short name T566
Test name
Test status
Simulation time 49878660 ps
CPU time 0.99 seconds
Started Aug 15 05:25:47 PM PDT 24
Finished Aug 15 05:25:48 PM PDT 24
Peak memory 196848 kb
Host smart-213402fa-7ca3-4e70-85e1-885f6590f83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500636486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1500636486
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3646525587
Short name T556
Test name
Test status
Simulation time 151686219 ps
CPU time 0.95 seconds
Started Aug 15 05:25:42 PM PDT 24
Finished Aug 15 05:25:43 PM PDT 24
Peak memory 195996 kb
Host smart-1f470692-4353-4f62-93ba-1f297710b98c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646525587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3646525587
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1064581443
Short name T572
Test name
Test status
Simulation time 68449777 ps
CPU time 2.82 seconds
Started Aug 15 05:25:49 PM PDT 24
Finished Aug 15 05:25:52 PM PDT 24
Peak memory 198128 kb
Host smart-f9d8a296-b786-4083-86f2-1945642000c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064581443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1064581443
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3477688284
Short name T618
Test name
Test status
Simulation time 72150998 ps
CPU time 1.18 seconds
Started Aug 15 05:25:46 PM PDT 24
Finished Aug 15 05:25:47 PM PDT 24
Peak memory 195968 kb
Host smart-2f90eea7-adfc-4322-991a-9051f1dce846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477688284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3477688284
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1921247224
Short name T255
Test name
Test status
Simulation time 38422767 ps
CPU time 0.85 seconds
Started Aug 15 05:25:43 PM PDT 24
Finished Aug 15 05:25:44 PM PDT 24
Peak memory 195468 kb
Host smart-f818c959-ec74-41f6-8385-452edc608496
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921247224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1921247224
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3450530376
Short name T392
Test name
Test status
Simulation time 10645917378 ps
CPU time 74.69 seconds
Started Aug 15 05:25:41 PM PDT 24
Finished Aug 15 05:26:56 PM PDT 24
Peak memory 198236 kb
Host smart-ebc3a37a-130f-4352-8ab6-cb5402098d9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450530376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3450530376
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.200777997
Short name T602
Test name
Test status
Simulation time 53108005 ps
CPU time 0.58 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 194988 kb
Host smart-d79b52ae-42a8-4488-82b4-880bac0ab581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200777997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.200777997
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3627186246
Short name T557
Test name
Test status
Simulation time 17916798 ps
CPU time 0.62 seconds
Started Aug 15 05:25:51 PM PDT 24
Finished Aug 15 05:25:52 PM PDT 24
Peak memory 194108 kb
Host smart-3fc97a4e-5d95-436d-ab30-79dfc5d098c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627186246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3627186246
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3016603464
Short name T54
Test name
Test status
Simulation time 781781845 ps
CPU time 23.59 seconds
Started Aug 15 05:25:49 PM PDT 24
Finished Aug 15 05:26:13 PM PDT 24
Peak memory 196972 kb
Host smart-cc98be8a-2533-4866-ba99-9609e78fb30a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016603464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3016603464
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2239098938
Short name T149
Test name
Test status
Simulation time 140769542 ps
CPU time 0.76 seconds
Started Aug 15 05:25:48 PM PDT 24
Finished Aug 15 05:25:49 PM PDT 24
Peak memory 195884 kb
Host smart-7a054dc0-7c0b-4fac-a669-bcd5799d7a5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239098938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2239098938
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.4183725851
Short name T158
Test name
Test status
Simulation time 68241965 ps
CPU time 1.1 seconds
Started Aug 15 05:25:49 PM PDT 24
Finished Aug 15 05:25:50 PM PDT 24
Peak memory 196988 kb
Host smart-1f9fe2b2-fcf8-438a-84cc-1ff2d01d548e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183725851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.4183725851
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.910262882
Short name T523
Test name
Test status
Simulation time 69618905 ps
CPU time 2.59 seconds
Started Aug 15 05:25:44 PM PDT 24
Finished Aug 15 05:25:47 PM PDT 24
Peak memory 196456 kb
Host smart-e5311166-8d93-4677-aa9f-adb18174b650
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910262882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.910262882
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3222423233
Short name T182
Test name
Test status
Simulation time 1162108519 ps
CPU time 3.52 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:25:55 PM PDT 24
Peak memory 197328 kb
Host smart-8f6046b3-3a7a-4a08-bcd5-aab772b6a01a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222423233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3222423233
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3465474505
Short name T487
Test name
Test status
Simulation time 121075286 ps
CPU time 0.97 seconds
Started Aug 15 05:25:44 PM PDT 24
Finished Aug 15 05:25:45 PM PDT 24
Peak memory 196020 kb
Host smart-729b6d03-b7df-42ef-8790-8d0ba1abfc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465474505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3465474505
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.414113350
Short name T629
Test name
Test status
Simulation time 136513516 ps
CPU time 0.92 seconds
Started Aug 15 05:25:50 PM PDT 24
Finished Aug 15 05:25:51 PM PDT 24
Peak memory 196660 kb
Host smart-9a2a9d44-2b09-4477-8a35-9c4c639bc5de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414113350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.414113350
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2229169369
Short name T555
Test name
Test status
Simulation time 626638455 ps
CPU time 5.28 seconds
Started Aug 15 05:25:41 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 198320 kb
Host smart-99fe7066-9168-4463-a04a-bb8acd0f9506
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229169369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2229169369
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3763354290
Short name T577
Test name
Test status
Simulation time 151636501 ps
CPU time 1.07 seconds
Started Aug 15 05:25:43 PM PDT 24
Finished Aug 15 05:25:44 PM PDT 24
Peak memory 195648 kb
Host smart-269f8a5a-859e-47d2-b4dc-7bf52a5151b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763354290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3763354290
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.533496120
Short name T270
Test name
Test status
Simulation time 183726834 ps
CPU time 1.44 seconds
Started Aug 15 05:25:45 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 198156 kb
Host smart-2eac0f0d-ef51-4fe3-a38f-db0d80d02f46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533496120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.533496120
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2327609651
Short name T115
Test name
Test status
Simulation time 20530477760 ps
CPU time 102.46 seconds
Started Aug 15 05:25:42 PM PDT 24
Finished Aug 15 05:27:25 PM PDT 24
Peak memory 198508 kb
Host smart-8188ebb3-74bf-4fde-910a-acd9c50c8dc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327609651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2327609651
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2792499012
Short name T622
Test name
Test status
Simulation time 17263366 ps
CPU time 0.57 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 194028 kb
Host smart-fa81fbf8-7688-4ce7-aa1e-2554711150a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792499012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2792499012
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1456364566
Short name T508
Test name
Test status
Simulation time 54984910 ps
CPU time 0.64 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 194216 kb
Host smart-e984b934-7e5f-4120-9ea5-733476ff1ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456364566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1456364566
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3918547645
Short name T670
Test name
Test status
Simulation time 98616648 ps
CPU time 5.02 seconds
Started Aug 15 05:25:48 PM PDT 24
Finished Aug 15 05:25:53 PM PDT 24
Peak memory 196172 kb
Host smart-9ffe2776-09f6-447a-a03b-47f192d980a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918547645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3918547645
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1595919947
Short name T436
Test name
Test status
Simulation time 200744847 ps
CPU time 0.89 seconds
Started Aug 15 05:25:47 PM PDT 24
Finished Aug 15 05:25:48 PM PDT 24
Peak memory 197316 kb
Host smart-860274de-699a-4d29-85a6-f7172d76e7df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595919947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1595919947
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.618235337
Short name T167
Test name
Test status
Simulation time 43835124 ps
CPU time 0.87 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 195888 kb
Host smart-fd9d0371-2c72-43b3-962c-9f667e1e1812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618235337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.618235337
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3422494808
Short name T643
Test name
Test status
Simulation time 93893217 ps
CPU time 2.77 seconds
Started Aug 15 05:25:43 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 196560 kb
Host smart-1822dd6b-9cec-448d-9bac-00edb223dc5e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422494808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3422494808
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.351846993
Short name T457
Test name
Test status
Simulation time 114773473 ps
CPU time 2.54 seconds
Started Aug 15 05:25:47 PM PDT 24
Finished Aug 15 05:25:50 PM PDT 24
Peak memory 196672 kb
Host smart-99db82d9-d45c-4af6-853c-6fa0576ce28e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351846993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.351846993
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3182250436
Short name T11
Test name
Test status
Simulation time 44005051 ps
CPU time 0.95 seconds
Started Aug 15 05:25:45 PM PDT 24
Finished Aug 15 05:25:46 PM PDT 24
Peak memory 196668 kb
Host smart-fa4e343b-4895-40e1-adb3-bce86269944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182250436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3182250436
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.789669086
Short name T430
Test name
Test status
Simulation time 27556910 ps
CPU time 0.79 seconds
Started Aug 15 05:25:50 PM PDT 24
Finished Aug 15 05:25:52 PM PDT 24
Peak memory 196344 kb
Host smart-617f9972-1fee-47f9-afbf-3e04209165f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789669086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.789669086
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4233970793
Short name T161
Test name
Test status
Simulation time 522159823 ps
CPU time 4.47 seconds
Started Aug 15 05:25:51 PM PDT 24
Finished Aug 15 05:25:55 PM PDT 24
Peak memory 198124 kb
Host smart-53105e89-1dfb-44b1-9c1c-aa0b55a6e6f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233970793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.4233970793
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.489084838
Short name T301
Test name
Test status
Simulation time 115615639 ps
CPU time 1.41 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 196844 kb
Host smart-8c1f43ad-7522-4552-af6d-e32d6db44487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489084838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.489084838
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3382387283
Short name T484
Test name
Test status
Simulation time 184299916 ps
CPU time 1.23 seconds
Started Aug 15 05:25:50 PM PDT 24
Finished Aug 15 05:25:52 PM PDT 24
Peak memory 195552 kb
Host smart-a878e7f8-9bed-4883-99fe-ce8ea8e7d3d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382387283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3382387283
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2798870120
Short name T165
Test name
Test status
Simulation time 28515678466 ps
CPU time 98.24 seconds
Started Aug 15 05:25:53 PM PDT 24
Finished Aug 15 05:27:32 PM PDT 24
Peak memory 198328 kb
Host smart-8b70b131-9130-4ad3-9b1f-48d033b56c2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798870120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2798870120
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.303363703
Short name T271
Test name
Test status
Simulation time 13127920 ps
CPU time 0.59 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 194004 kb
Host smart-c89a3e9e-1148-49ae-8f1b-2c6c868daa12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303363703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.303363703
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3026588327
Short name T586
Test name
Test status
Simulation time 33032472 ps
CPU time 0.65 seconds
Started Aug 15 05:25:47 PM PDT 24
Finished Aug 15 05:25:48 PM PDT 24
Peak memory 194888 kb
Host smart-75cf46b3-0544-4d37-8bf8-1009c28856c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026588327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3026588327
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1235935710
Short name T558
Test name
Test status
Simulation time 1884022189 ps
CPU time 5.73 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:26:02 PM PDT 24
Peak memory 198088 kb
Host smart-a5104c31-e883-4b5d-846c-2dd3dc2603bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235935710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1235935710
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.434229884
Short name T119
Test name
Test status
Simulation time 184968491 ps
CPU time 0.63 seconds
Started Aug 15 05:25:58 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 195240 kb
Host smart-388e1a00-7b49-4274-a109-fdbdd4b62cfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434229884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.434229884
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.4150832058
Short name T631
Test name
Test status
Simulation time 38864205 ps
CPU time 0.75 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 195560 kb
Host smart-09d801db-3231-4eb6-8ada-aa5707bd604d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150832058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.4150832058
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2061638438
Short name T142
Test name
Test status
Simulation time 145231232 ps
CPU time 2.78 seconds
Started Aug 15 05:25:51 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 198204 kb
Host smart-139f1042-7b88-4c6a-8d13-c0d7d0eb95e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061638438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2061638438
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.284129538
Short name T17
Test name
Test status
Simulation time 606478818 ps
CPU time 1.71 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 196088 kb
Host smart-bfdb737e-0bb7-4f0f-ad5f-dfcef9279b60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284129538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.284129538
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.963050182
Short name T639
Test name
Test status
Simulation time 36978365 ps
CPU time 0.89 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:55 PM PDT 24
Peak memory 196528 kb
Host smart-f5aa2a5f-7d9d-4c9b-b966-5fb20761a3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963050182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.963050182
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1346523697
Short name T129
Test name
Test status
Simulation time 92051867 ps
CPU time 0.83 seconds
Started Aug 15 05:25:47 PM PDT 24
Finished Aug 15 05:25:48 PM PDT 24
Peak memory 196144 kb
Host smart-6bb6ec19-3cb6-4de3-950f-6475e6d7cb32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346523697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1346523697
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1324322933
Short name T235
Test name
Test status
Simulation time 503391884 ps
CPU time 4.7 seconds
Started Aug 15 05:25:49 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 198128 kb
Host smart-e8e32f0b-af7a-41d0-93b8-a2bb6db0d4ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324322933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1324322933
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.4079904085
Short name T613
Test name
Test status
Simulation time 134746531 ps
CPU time 0.86 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:25:53 PM PDT 24
Peak memory 196376 kb
Host smart-4ac24a96-225c-443c-93be-691ff9b1d077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079904085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.4079904085
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1564778773
Short name T657
Test name
Test status
Simulation time 557483732 ps
CPU time 1.22 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 198160 kb
Host smart-47168a9e-5663-4b2a-8fa2-55027c8066fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564778773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1564778773
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1176239484
Short name T681
Test name
Test status
Simulation time 1500144447 ps
CPU time 19.73 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:26:15 PM PDT 24
Peak memory 198172 kb
Host smart-fec08a11-a599-4c88-b676-0e51bc2ed235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176239484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1176239484
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.974980183
Short name T317
Test name
Test status
Simulation time 39919033 ps
CPU time 0.54 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 192824 kb
Host smart-34f789d6-bd44-499a-9149-84b7d237b1cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974980183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.974980183
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3872413894
Short name T216
Test name
Test status
Simulation time 20525913 ps
CPU time 0.64 seconds
Started Aug 15 05:25:53 PM PDT 24
Finished Aug 15 05:25:53 PM PDT 24
Peak memory 194956 kb
Host smart-6c5af6d0-c22f-4ea1-b5be-18ac7edcc415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872413894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3872413894
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.669498618
Short name T695
Test name
Test status
Simulation time 420991023 ps
CPU time 13.53 seconds
Started Aug 15 05:25:53 PM PDT 24
Finished Aug 15 05:26:06 PM PDT 24
Peak memory 197372 kb
Host smart-34a57e29-2c2b-4d8e-8786-2063fbaa059e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669498618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.669498618
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2675667845
Short name T441
Test name
Test status
Simulation time 270657536 ps
CPU time 0.75 seconds
Started Aug 15 05:25:57 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 194740 kb
Host smart-48d856c6-249c-49cc-a9ee-858f65066ac7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675667845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2675667845
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4199303576
Short name T679
Test name
Test status
Simulation time 64519165 ps
CPU time 1.07 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 196256 kb
Host smart-3b7a3c71-0f32-42b0-8ba5-5bd0165edc7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199303576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4199303576
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3831223574
Short name T253
Test name
Test status
Simulation time 361526355 ps
CPU time 1.33 seconds
Started Aug 15 05:25:52 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 198052 kb
Host smart-6095ecf7-9d4a-4725-8eea-23bbbb5c6ab0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831223574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3831223574
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.4141036068
Short name T229
Test name
Test status
Simulation time 63274670 ps
CPU time 1.14 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:57 PM PDT 24
Peak memory 196896 kb
Host smart-63adcd28-837c-4551-8f18-1fd9ceb3a633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141036068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
4141036068
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1770295574
Short name T514
Test name
Test status
Simulation time 72122165 ps
CPU time 1 seconds
Started Aug 15 05:25:53 PM PDT 24
Finished Aug 15 05:25:54 PM PDT 24
Peak memory 196164 kb
Host smart-95222d24-7cbf-4374-b8f2-fff719c754f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770295574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1770295574
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1470514798
Short name T539
Test name
Test status
Simulation time 89970760 ps
CPU time 1.09 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 196248 kb
Host smart-3b0f0cc3-7172-4d78-999e-868042956f1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470514798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1470514798
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.48884942
Short name T616
Test name
Test status
Simulation time 230394071 ps
CPU time 2.33 seconds
Started Aug 15 05:25:56 PM PDT 24
Finished Aug 15 05:25:58 PM PDT 24
Peak memory 198168 kb
Host smart-6981dd36-1f24-41f8-a04b-8614064e1807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48884942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rando
m_long_reg_writes_reg_reads.48884942
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3971897585
Short name T634
Test name
Test status
Simulation time 110932805 ps
CPU time 0.97 seconds
Started Aug 15 05:25:54 PM PDT 24
Finished Aug 15 05:25:55 PM PDT 24
Peak memory 195740 kb
Host smart-e7fa659e-d4f9-4327-8e08-98d964d942ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971897585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3971897585
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.953868855
Short name T377
Test name
Test status
Simulation time 165985233 ps
CPU time 0.82 seconds
Started Aug 15 05:25:55 PM PDT 24
Finished Aug 15 05:25:56 PM PDT 24
Peak memory 195264 kb
Host smart-edeeaace-c6fd-430c-ae93-56a9e93a8a41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953868855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.953868855
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3598495042
Short name T696
Test name
Test status
Simulation time 10948583545 ps
CPU time 60.22 seconds
Started Aug 15 05:26:00 PM PDT 24
Finished Aug 15 05:27:00 PM PDT 24
Peak memory 198328 kb
Host smart-cc75632a-ed39-4309-b1eb-ba02df30e7a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598495042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3598495042
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2246897112
Short name T542
Test name
Test status
Simulation time 36226848311 ps
CPU time 193.32 seconds
Started Aug 15 05:25:59 PM PDT 24
Finished Aug 15 05:29:13 PM PDT 24
Peak memory 198504 kb
Host smart-7157628c-9315-499c-a1dd-48103db28b9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2246897112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2246897112
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3387731081
Short name T853
Test name
Test status
Simulation time 162994499 ps
CPU time 1 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 191280 kb
Host smart-cd3758e1-d1fd-49aa-a8ae-c1fdc928f6b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3387731081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3387731081
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.49190903
Short name T873
Test name
Test status
Simulation time 30993971 ps
CPU time 0.95 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 191308 kb
Host smart-6a169082-3178-4047-8914-3d2a5c745303
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49190903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.49190903
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3941250835
Short name T903
Test name
Test status
Simulation time 66725190 ps
CPU time 1.05 seconds
Started Aug 15 05:24:55 PM PDT 24
Finished Aug 15 05:24:56 PM PDT 24
Peak memory 191324 kb
Host smart-df165964-58a7-4655-8f32-d91c495f1082
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3941250835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3941250835
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.575633479
Short name T917
Test name
Test status
Simulation time 70204309 ps
CPU time 1.45 seconds
Started Aug 15 05:24:58 PM PDT 24
Finished Aug 15 05:24:59 PM PDT 24
Peak memory 191332 kb
Host smart-3861973f-a179-4b57-aca7-d4c5baa954ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575633479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.575633479
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3471735980
Short name T863
Test name
Test status
Simulation time 36087403 ps
CPU time 0.86 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 191088 kb
Host smart-fa33855b-6a4f-4da5-8ae0-4579eff95690
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3471735980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3471735980
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2808701490
Short name T907
Test name
Test status
Simulation time 48705098 ps
CPU time 1 seconds
Started Aug 15 05:24:52 PM PDT 24
Finished Aug 15 05:24:53 PM PDT 24
Peak memory 191360 kb
Host smart-1ec40fa5-1ea8-42b8-a028-7aa40e944d77
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808701490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2808701490
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1039634672
Short name T924
Test name
Test status
Simulation time 334585243 ps
CPU time 1.06 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 191232 kb
Host smart-e4330791-d714-4cd8-8865-3c5c91cf70f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1039634672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1039634672
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.7202334
Short name T915
Test name
Test status
Simulation time 43333847 ps
CPU time 1.34 seconds
Started Aug 15 05:24:51 PM PDT 24
Finished Aug 15 05:24:53 PM PDT 24
Peak memory 191624 kb
Host smart-d9c01d80-1590-4bbe-9448-7e81bfaaa081
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7202334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.7202334
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.563995448
Short name T860
Test name
Test status
Simulation time 40577138 ps
CPU time 1.27 seconds
Started Aug 15 05:25:04 PM PDT 24
Finished Aug 15 05:25:05 PM PDT 24
Peak memory 191352 kb
Host smart-7ba40fb5-aab9-461e-9c1a-99643a23cf9b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=563995448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.563995448
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.769000176
Short name T923
Test name
Test status
Simulation time 148246493 ps
CPU time 0.92 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 190984 kb
Host smart-7f53d724-0b94-4972-8450-e5b27433370c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769000176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.769000176
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.559721923
Short name T934
Test name
Test status
Simulation time 113909732 ps
CPU time 0.86 seconds
Started Aug 15 05:24:54 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 191108 kb
Host smart-99d75999-5003-4cdb-9398-9f14369f024f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=559721923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.559721923
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2777105719
Short name T855
Test name
Test status
Simulation time 300704302 ps
CPU time 1.07 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 196260 kb
Host smart-b7bd2284-8b47-47e3-b890-5992d5c72a01
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777105719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2777105719
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3771542114
Short name T875
Test name
Test status
Simulation time 275522447 ps
CPU time 1.25 seconds
Started Aug 15 05:24:48 PM PDT 24
Finished Aug 15 05:24:49 PM PDT 24
Peak memory 191296 kb
Host smart-59a66dd7-ac08-4e92-a174-9e2d86b0f730
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3771542114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3771542114
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2308416908
Short name T874
Test name
Test status
Simulation time 117796836 ps
CPU time 1.3 seconds
Started Aug 15 05:25:03 PM PDT 24
Finished Aug 15 05:25:05 PM PDT 24
Peak memory 191352 kb
Host smart-319e0ac1-e501-4c3e-ae00-9680c1fa6d52
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308416908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2308416908
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2767256752
Short name T844
Test name
Test status
Simulation time 209954790 ps
CPU time 0.9 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:52 PM PDT 24
Peak memory 191036 kb
Host smart-11e97781-9bdc-469a-ac4b-e36e47234dfe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2767256752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2767256752
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3486102013
Short name T930
Test name
Test status
Simulation time 19602537 ps
CPU time 0.81 seconds
Started Aug 15 05:25:05 PM PDT 24
Finished Aug 15 05:25:06 PM PDT 24
Peak memory 195640 kb
Host smart-dd88b2f5-4ba1-431b-abc8-d86b31bc4db7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486102013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3486102013
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.886006588
Short name T939
Test name
Test status
Simulation time 930997905 ps
CPU time 1.41 seconds
Started Aug 15 05:24:58 PM PDT 24
Finished Aug 15 05:24:59 PM PDT 24
Peak memory 191300 kb
Host smart-5e6535ca-074b-43df-bc19-b64674fd74a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=886006588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.886006588
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1150027990
Short name T902
Test name
Test status
Simulation time 293098055 ps
CPU time 1.32 seconds
Started Aug 15 05:24:53 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 191356 kb
Host smart-8701aab6-f056-4a97-a967-da23e4fd0df0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150027990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1150027990
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3912662829
Short name T912
Test name
Test status
Simulation time 889707107 ps
CPU time 1.52 seconds
Started Aug 15 05:24:51 PM PDT 24
Finished Aug 15 05:24:53 PM PDT 24
Peak memory 191392 kb
Host smart-35bafd78-3250-45ff-b476-18c89418f41d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3912662829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3912662829
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.33235215
Short name T842
Test name
Test status
Simulation time 145479895 ps
CPU time 1.39 seconds
Started Aug 15 05:25:00 PM PDT 24
Finished Aug 15 05:25:02 PM PDT 24
Peak memory 191240 kb
Host smart-b9eb1f9c-46d4-4188-81c7-27aeb9f0f694
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33235215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.33235215
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.28557931
Short name T856
Test name
Test status
Simulation time 63721660 ps
CPU time 1.27 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 191256 kb
Host smart-624cd6fa-2287-4f62-b841-aa86b75dc178
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=28557931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.28557931
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2412299094
Short name T891
Test name
Test status
Simulation time 357250281 ps
CPU time 1.44 seconds
Started Aug 15 05:25:05 PM PDT 24
Finished Aug 15 05:25:06 PM PDT 24
Peak memory 197592 kb
Host smart-e9a0a28f-08ba-4841-9ebf-ad309c03540e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412299094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2412299094
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.684148884
Short name T859
Test name
Test status
Simulation time 356765089 ps
CPU time 1.29 seconds
Started Aug 15 05:25:01 PM PDT 24
Finished Aug 15 05:25:02 PM PDT 24
Peak memory 191332 kb
Host smart-fd2b2548-d4bd-4b62-a6e2-3669b8d10c37
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=684148884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.684148884
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1556900957
Short name T897
Test name
Test status
Simulation time 65791418 ps
CPU time 1.06 seconds
Started Aug 15 05:24:58 PM PDT 24
Finished Aug 15 05:25:00 PM PDT 24
Peak memory 191184 kb
Host smart-57657c2c-b92f-49b0-a1ab-88948850158c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556900957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1556900957
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3563481212
Short name T882
Test name
Test status
Simulation time 159058632 ps
CPU time 0.96 seconds
Started Aug 15 05:24:51 PM PDT 24
Finished Aug 15 05:24:52 PM PDT 24
Peak memory 196156 kb
Host smart-67fc1b17-e2be-4252-81a5-1a4bb47cb0c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3563481212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3563481212
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3679151722
Short name T881
Test name
Test status
Simulation time 89249667 ps
CPU time 1.27 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 191324 kb
Host smart-e3f33813-4c4d-4652-a4e2-fc2dcf23c6fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679151722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3679151722
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2596854259
Short name T878
Test name
Test status
Simulation time 280452672 ps
CPU time 1.35 seconds
Started Aug 15 05:24:52 PM PDT 24
Finished Aug 15 05:24:54 PM PDT 24
Peak memory 191364 kb
Host smart-766985a1-4367-4886-9420-09850cdc1d31
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2596854259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2596854259
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2406071438
Short name T890
Test name
Test status
Simulation time 132569576 ps
CPU time 1.04 seconds
Started Aug 15 05:25:01 PM PDT 24
Finished Aug 15 05:25:03 PM PDT 24
Peak memory 191320 kb
Host smart-eab0bbcb-d13e-40cd-beed-e61c1e1fe82c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406071438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2406071438
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1435399098
Short name T867
Test name
Test status
Simulation time 44222965 ps
CPU time 1.29 seconds
Started Aug 15 05:24:54 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 191360 kb
Host smart-dde4804e-35ca-40bb-9e1d-48ce3c0528cc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1435399098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1435399098
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.32958469
Short name T841
Test name
Test status
Simulation time 43105908 ps
CPU time 0.98 seconds
Started Aug 15 05:25:01 PM PDT 24
Finished Aug 15 05:25:03 PM PDT 24
Peak memory 197000 kb
Host smart-689b9d68-deb3-44c1-9ad6-3da3bbb7243e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32958469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.32958469
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2923197882
Short name T921
Test name
Test status
Simulation time 541154153 ps
CPU time 1.13 seconds
Started Aug 15 05:25:01 PM PDT 24
Finished Aug 15 05:25:03 PM PDT 24
Peak memory 191304 kb
Host smart-d435aa9c-1766-485c-bb5f-0664f9fd6f6e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2923197882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2923197882
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3601514593
Short name T909
Test name
Test status
Simulation time 525356948 ps
CPU time 1.33 seconds
Started Aug 15 05:25:01 PM PDT 24
Finished Aug 15 05:25:03 PM PDT 24
Peak memory 191280 kb
Host smart-19ca0d09-19cb-4b0a-9005-dd84e34b8cc6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601514593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3601514593
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2467846787
Short name T850
Test name
Test status
Simulation time 55190428 ps
CPU time 1.09 seconds
Started Aug 15 05:25:01 PM PDT 24
Finished Aug 15 05:25:02 PM PDT 24
Peak memory 191360 kb
Host smart-bf88a9e0-8a0d-4bdc-ad18-8d66e968a347
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2467846787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2467846787
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4066394298
Short name T843
Test name
Test status
Simulation time 95757259 ps
CPU time 1.03 seconds
Started Aug 15 05:24:53 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 197688 kb
Host smart-ce28ace9-d85b-405a-8cd4-223622365f77
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066394298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4066394298
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2682085483
Short name T892
Test name
Test status
Simulation time 162032229 ps
CPU time 1.4 seconds
Started Aug 15 05:25:00 PM PDT 24
Finished Aug 15 05:25:01 PM PDT 24
Peak memory 197628 kb
Host smart-cbfa5db7-c128-44d6-97c5-c9d962be9c45
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2682085483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2682085483
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2272042883
Short name T932
Test name
Test status
Simulation time 1478681628 ps
CPU time 1.23 seconds
Started Aug 15 05:25:02 PM PDT 24
Finished Aug 15 05:25:04 PM PDT 24
Peak memory 191292 kb
Host smart-86ad72f4-f280-41bc-8336-c0a433ac2b9d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272042883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2272042883
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3036223446
Short name T911
Test name
Test status
Simulation time 42393970 ps
CPU time 0.88 seconds
Started Aug 15 05:24:55 PM PDT 24
Finished Aug 15 05:24:56 PM PDT 24
Peak memory 195640 kb
Host smart-3cfb5365-654f-4f04-b9af-ae7652a4c585
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3036223446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3036223446
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.595752339
Short name T899
Test name
Test status
Simulation time 48259222 ps
CPU time 1.25 seconds
Started Aug 15 05:25:05 PM PDT 24
Finished Aug 15 05:25:06 PM PDT 24
Peak memory 191248 kb
Host smart-241fa45e-1f70-42df-87af-85ab316647dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595752339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.595752339
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1644422382
Short name T901
Test name
Test status
Simulation time 70795380 ps
CPU time 1.38 seconds
Started Aug 15 05:25:02 PM PDT 24
Finished Aug 15 05:25:04 PM PDT 24
Peak memory 191320 kb
Host smart-c00c5987-556d-40c1-bd56-5e4777bfd5e5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1644422382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1644422382
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1418952622
Short name T927
Test name
Test status
Simulation time 203242319 ps
CPU time 1.11 seconds
Started Aug 15 05:25:08 PM PDT 24
Finished Aug 15 05:25:09 PM PDT 24
Peak memory 197680 kb
Host smart-ffcbbc93-b697-42cf-9205-c68e108035cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418952622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1418952622
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1225844560
Short name T896
Test name
Test status
Simulation time 90162374 ps
CPU time 0.91 seconds
Started Aug 15 05:25:03 PM PDT 24
Finished Aug 15 05:25:04 PM PDT 24
Peak memory 191080 kb
Host smart-67756477-5392-46b9-929f-7930139b6413
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1225844560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1225844560
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3266375631
Short name T857
Test name
Test status
Simulation time 161734164 ps
CPU time 1.2 seconds
Started Aug 15 05:25:05 PM PDT 24
Finished Aug 15 05:25:07 PM PDT 24
Peak memory 191268 kb
Host smart-cc8b6f09-2e40-4d6b-b93c-5e768c2c5bc5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266375631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3266375631
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4293467854
Short name T862
Test name
Test status
Simulation time 188447189 ps
CPU time 1.04 seconds
Started Aug 15 05:25:02 PM PDT 24
Finished Aug 15 05:25:03 PM PDT 24
Peak memory 191300 kb
Host smart-53c9c192-ac8a-4754-b920-6ef171d8305b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4293467854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.4293467854
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3617926109
Short name T938
Test name
Test status
Simulation time 851439399 ps
CPU time 1.37 seconds
Started Aug 15 05:24:57 PM PDT 24
Finished Aug 15 05:24:59 PM PDT 24
Peak memory 197184 kb
Host smart-f0ff98db-9b68-4b76-99d5-549f020d2e53
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617926109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3617926109
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3311657336
Short name T865
Test name
Test status
Simulation time 50525274 ps
CPU time 1.01 seconds
Started Aug 15 05:25:01 PM PDT 24
Finished Aug 15 05:25:03 PM PDT 24
Peak memory 196996 kb
Host smart-80730c9f-d222-42b4-bfbd-57a46b5d2662
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3311657336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3311657336
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2113596502
Short name T905
Test name
Test status
Simulation time 89290955 ps
CPU time 1.38 seconds
Started Aug 15 05:25:09 PM PDT 24
Finished Aug 15 05:25:10 PM PDT 24
Peak memory 196876 kb
Host smart-98a703af-ba26-4372-a4f4-ab30c72b143b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113596502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2113596502
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.4072803778
Short name T910
Test name
Test status
Simulation time 28660684 ps
CPU time 0.81 seconds
Started Aug 15 05:24:57 PM PDT 24
Finished Aug 15 05:24:58 PM PDT 24
Peak memory 195708 kb
Host smart-fe720894-68d6-4d31-9673-85f8deb80189
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4072803778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.4072803778
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2887100134
Short name T920
Test name
Test status
Simulation time 75784086 ps
CPU time 1.25 seconds
Started Aug 15 05:25:01 PM PDT 24
Finished Aug 15 05:25:03 PM PDT 24
Peak memory 191384 kb
Host smart-f28bf4e4-21ef-4bd4-a497-4af8e6021f0a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887100134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2887100134
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1989542777
Short name T893
Test name
Test status
Simulation time 141352744 ps
CPU time 1.22 seconds
Started Aug 15 05:24:56 PM PDT 24
Finished Aug 15 05:24:58 PM PDT 24
Peak memory 191304 kb
Host smart-e7f3a747-f6d7-448d-94d1-c8837552d6ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1989542777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1989542777
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1603083656
Short name T876
Test name
Test status
Simulation time 119662140 ps
CPU time 1.2 seconds
Started Aug 15 05:25:07 PM PDT 24
Finished Aug 15 05:25:08 PM PDT 24
Peak memory 191356 kb
Host smart-b4f1a5b9-e63d-41bd-9ef2-c3e84764e471
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603083656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1603083656
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.542534622
Short name T916
Test name
Test status
Simulation time 44915478 ps
CPU time 1.23 seconds
Started Aug 15 05:25:02 PM PDT 24
Finished Aug 15 05:25:03 PM PDT 24
Peak memory 191300 kb
Host smart-32035f4f-8235-4109-b4b1-95861ead96d5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=542534622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.542534622
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2647948414
Short name T908
Test name
Test status
Simulation time 382638588 ps
CPU time 0.83 seconds
Started Aug 15 05:25:01 PM PDT 24
Finished Aug 15 05:25:02 PM PDT 24
Peak memory 195812 kb
Host smart-f0077c13-2af3-4ab7-9991-5f6503cbd38d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647948414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2647948414
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1799549800
Short name T887
Test name
Test status
Simulation time 180939710 ps
CPU time 0.85 seconds
Started Aug 15 05:25:02 PM PDT 24
Finished Aug 15 05:25:03 PM PDT 24
Peak memory 196804 kb
Host smart-44268530-02c6-4bc9-a86b-91f49a3dbb0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1799549800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1799549800
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3143334907
Short name T849
Test name
Test status
Simulation time 84382740 ps
CPU time 1.13 seconds
Started Aug 15 05:24:54 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 191208 kb
Host smart-3dec45cf-194d-4d47-b6b0-66038f55663c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143334907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3143334907
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3253470582
Short name T880
Test name
Test status
Simulation time 37704917 ps
CPU time 1.2 seconds
Started Aug 15 05:25:05 PM PDT 24
Finished Aug 15 05:25:06 PM PDT 24
Peak memory 197624 kb
Host smart-89a4c77d-ce86-463b-9b60-f24d76e7a951
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3253470582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3253470582
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.796467069
Short name T864
Test name
Test status
Simulation time 27755621 ps
CPU time 0.95 seconds
Started Aug 15 05:24:58 PM PDT 24
Finished Aug 15 05:24:59 PM PDT 24
Peak memory 191360 kb
Host smart-f4aeb838-4722-4ffb-9d5d-dacc6ef28ec8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796467069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.796467069
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1209339482
Short name T937
Test name
Test status
Simulation time 115901884 ps
CPU time 1 seconds
Started Aug 15 05:24:56 PM PDT 24
Finished Aug 15 05:24:57 PM PDT 24
Peak memory 191356 kb
Host smart-6fc4a2ce-f55a-48a4-a305-74059b3e4956
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1209339482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1209339482
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.883963775
Short name T928
Test name
Test status
Simulation time 204766433 ps
CPU time 1.09 seconds
Started Aug 15 05:24:54 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 191356 kb
Host smart-f1695475-6bfd-4297-a8cb-04ed9e100785
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883963775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.883963775
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.853753144
Short name T889
Test name
Test status
Simulation time 41830789 ps
CPU time 0.95 seconds
Started Aug 15 05:25:03 PM PDT 24
Finished Aug 15 05:25:04 PM PDT 24
Peak memory 191120 kb
Host smart-55b02fed-ad5c-4301-8441-c55e4bc19e63
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=853753144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.853753144
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.732764534
Short name T936
Test name
Test status
Simulation time 181640842 ps
CPU time 1.11 seconds
Started Aug 15 05:25:02 PM PDT 24
Finished Aug 15 05:25:04 PM PDT 24
Peak memory 195996 kb
Host smart-3a90d9f9-e004-46d9-935f-abd4a17c2676
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732764534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.732764534
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1067042912
Short name T846
Test name
Test status
Simulation time 153225834 ps
CPU time 1.15 seconds
Started Aug 15 05:25:06 PM PDT 24
Finished Aug 15 05:25:07 PM PDT 24
Peak memory 191324 kb
Host smart-d33816bd-ef90-4cf5-ab7e-f496a3be9662
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1067042912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1067042912
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3751698289
Short name T872
Test name
Test status
Simulation time 47451599 ps
CPU time 1.22 seconds
Started Aug 15 05:25:07 PM PDT 24
Finished Aug 15 05:25:08 PM PDT 24
Peak memory 191328 kb
Host smart-9fa47cd3-8c1d-49bc-85fb-16e2bb8a9e59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751698289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3751698289
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.912677717
Short name T926
Test name
Test status
Simulation time 202367593 ps
CPU time 0.99 seconds
Started Aug 15 05:24:58 PM PDT 24
Finished Aug 15 05:24:59 PM PDT 24
Peak memory 195944 kb
Host smart-e35b5f89-08e7-4386-a6f7-a84d979f49ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=912677717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.912677717
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1714747337
Short name T852
Test name
Test status
Simulation time 134726234 ps
CPU time 1.33 seconds
Started Aug 15 05:25:06 PM PDT 24
Finished Aug 15 05:25:07 PM PDT 24
Peak memory 191272 kb
Host smart-27d97e15-df38-43b8-a304-9d6cd0a875aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714747337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1714747337
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2440972709
Short name T931
Test name
Test status
Simulation time 43554540 ps
CPU time 0.81 seconds
Started Aug 15 05:25:03 PM PDT 24
Finished Aug 15 05:25:04 PM PDT 24
Peak memory 191392 kb
Host smart-3e7b720b-f734-4f9c-9d7b-12d843eaf206
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2440972709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2440972709
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3376678847
Short name T919
Test name
Test status
Simulation time 139313391 ps
CPU time 0.98 seconds
Started Aug 15 05:25:01 PM PDT 24
Finished Aug 15 05:25:02 PM PDT 24
Peak memory 196024 kb
Host smart-e66fa1d6-3573-4c06-b3ad-93c08b55e2fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376678847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3376678847
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2600071237
Short name T900
Test name
Test status
Simulation time 488334402 ps
CPU time 1.21 seconds
Started Aug 15 05:25:00 PM PDT 24
Finished Aug 15 05:25:01 PM PDT 24
Peak memory 191308 kb
Host smart-cc8ad3c4-3dbe-41e5-804e-0d736deda8e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2600071237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2600071237
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.910400807
Short name T866
Test name
Test status
Simulation time 303112540 ps
CPU time 1.34 seconds
Started Aug 15 05:24:56 PM PDT 24
Finished Aug 15 05:24:58 PM PDT 24
Peak memory 191328 kb
Host smart-e917bf3d-8961-4637-b3e0-862bfb8091b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910400807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.910400807
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1617584374
Short name T888
Test name
Test status
Simulation time 49446771 ps
CPU time 1.02 seconds
Started Aug 15 05:24:57 PM PDT 24
Finished Aug 15 05:24:58 PM PDT 24
Peak memory 191276 kb
Host smart-1545e688-2b9d-4ee3-8db9-2a0b00d4d80d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1617584374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1617584374
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3418562599
Short name T847
Test name
Test status
Simulation time 161115556 ps
CPU time 1.17 seconds
Started Aug 15 05:24:51 PM PDT 24
Finished Aug 15 05:24:53 PM PDT 24
Peak memory 191300 kb
Host smart-afeb8105-86b2-475f-9f3a-a56f65e7ce1b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418562599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3418562599
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.86113057
Short name T869
Test name
Test status
Simulation time 59095951 ps
CPU time 1.07 seconds
Started Aug 15 05:25:05 PM PDT 24
Finished Aug 15 05:25:06 PM PDT 24
Peak memory 191316 kb
Host smart-09bf37cc-c160-4de6-81cc-dec6cef1bb3c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=86113057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.86113057
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4097845955
Short name T906
Test name
Test status
Simulation time 285480615 ps
CPU time 1.22 seconds
Started Aug 15 05:25:03 PM PDT 24
Finished Aug 15 05:25:05 PM PDT 24
Peak memory 191352 kb
Host smart-7ec5dc3d-75b9-4334-b808-2528d71e2def
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097845955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4097845955
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2219068386
Short name T858
Test name
Test status
Simulation time 157697225 ps
CPU time 1.17 seconds
Started Aug 15 05:24:58 PM PDT 24
Finished Aug 15 05:24:59 PM PDT 24
Peak memory 197204 kb
Host smart-b7204f0e-7589-446e-8558-0be96f6201e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2219068386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2219068386
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2750235543
Short name T925
Test name
Test status
Simulation time 131770294 ps
CPU time 1.17 seconds
Started Aug 15 05:25:00 PM PDT 24
Finished Aug 15 05:25:01 PM PDT 24
Peak memory 197612 kb
Host smart-3ad5e0b5-756f-4b89-8cca-f090e6024da9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750235543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2750235543
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.866078084
Short name T851
Test name
Test status
Simulation time 89285924 ps
CPU time 1.16 seconds
Started Aug 15 05:25:06 PM PDT 24
Finished Aug 15 05:25:08 PM PDT 24
Peak memory 191292 kb
Host smart-3228d569-c391-468b-a0d7-8d47a4f8e3ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=866078084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.866078084
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3338865058
Short name T868
Test name
Test status
Simulation time 46333464 ps
CPU time 1.21 seconds
Started Aug 15 05:25:04 PM PDT 24
Finished Aug 15 05:25:05 PM PDT 24
Peak memory 191332 kb
Host smart-39703cd6-4c34-4867-b1b5-12b2783a473f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338865058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3338865058
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4253591203
Short name T848
Test name
Test status
Simulation time 62144607 ps
CPU time 1.15 seconds
Started Aug 15 05:25:05 PM PDT 24
Finished Aug 15 05:25:06 PM PDT 24
Peak memory 191332 kb
Host smart-82873e46-72d5-40ee-a1ce-665e75f14af5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4253591203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.4253591203
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1847194453
Short name T885
Test name
Test status
Simulation time 211978182 ps
CPU time 1.15 seconds
Started Aug 15 05:25:05 PM PDT 24
Finished Aug 15 05:25:06 PM PDT 24
Peak memory 197924 kb
Host smart-717f7678-d4c8-4116-a7d8-3556eb10ae67
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847194453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1847194453
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.750021926
Short name T845
Test name
Test status
Simulation time 126225853 ps
CPU time 0.94 seconds
Started Aug 15 05:25:05 PM PDT 24
Finished Aug 15 05:25:06 PM PDT 24
Peak memory 191272 kb
Host smart-0db0b95e-6067-4fb4-8767-67708fbd38d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=750021926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.750021926
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3389154875
Short name T922
Test name
Test status
Simulation time 126700099 ps
CPU time 1.28 seconds
Started Aug 15 05:25:03 PM PDT 24
Finished Aug 15 05:25:04 PM PDT 24
Peak memory 191308 kb
Host smart-68169702-9d89-4a71-88ee-03f8106b7468
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389154875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3389154875
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2124431008
Short name T884
Test name
Test status
Simulation time 73569171 ps
CPU time 1.28 seconds
Started Aug 15 05:25:19 PM PDT 24
Finished Aug 15 05:25:21 PM PDT 24
Peak memory 191328 kb
Host smart-542d25d5-416f-4bbb-89b4-b592ec7ea811
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2124431008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2124431008
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.461193612
Short name T895
Test name
Test status
Simulation time 230255203 ps
CPU time 1.13 seconds
Started Aug 15 05:25:05 PM PDT 24
Finished Aug 15 05:25:07 PM PDT 24
Peak memory 197664 kb
Host smart-3fd83f7a-bf50-4867-a11f-788bdcc2816b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461193612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.461193612
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4002673976
Short name T883
Test name
Test status
Simulation time 238150855 ps
CPU time 0.97 seconds
Started Aug 15 05:25:02 PM PDT 24
Finished Aug 15 05:25:04 PM PDT 24
Peak memory 191116 kb
Host smart-26d75842-425b-4e1a-b038-19e19f580282
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4002673976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.4002673976
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3494384707
Short name T871
Test name
Test status
Simulation time 189386327 ps
CPU time 1.06 seconds
Started Aug 15 05:24:55 PM PDT 24
Finished Aug 15 05:24:56 PM PDT 24
Peak memory 191320 kb
Host smart-17b02c88-5065-4062-ae64-66c25ed7d463
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494384707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3494384707
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2095050349
Short name T898
Test name
Test status
Simulation time 65403817 ps
CPU time 1.35 seconds
Started Aug 15 05:24:58 PM PDT 24
Finished Aug 15 05:24:59 PM PDT 24
Peak memory 196820 kb
Host smart-64ecd3d3-3f8f-4525-b8d5-9ab56e342a00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2095050349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2095050349
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3537164158
Short name T886
Test name
Test status
Simulation time 1296992798 ps
CPU time 1.32 seconds
Started Aug 15 05:25:03 PM PDT 24
Finished Aug 15 05:25:04 PM PDT 24
Peak memory 197616 kb
Host smart-8a9dec8b-b51b-4df1-8a84-58ca99d0fe00
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537164158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3537164158
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3050540308
Short name T929
Test name
Test status
Simulation time 49279661 ps
CPU time 1.33 seconds
Started Aug 15 05:25:05 PM PDT 24
Finished Aug 15 05:25:07 PM PDT 24
Peak memory 191304 kb
Host smart-cdea0457-e48a-4c34-a152-09346ac4818d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3050540308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3050540308
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.655839179
Short name T870
Test name
Test status
Simulation time 98575847 ps
CPU time 0.96 seconds
Started Aug 15 05:25:02 PM PDT 24
Finished Aug 15 05:25:04 PM PDT 24
Peak memory 191124 kb
Host smart-14023334-b326-4a22-b533-fd6964f7e892
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655839179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.655839179
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2031283916
Short name T933
Test name
Test status
Simulation time 40523477 ps
CPU time 1.22 seconds
Started Aug 15 05:24:55 PM PDT 24
Finished Aug 15 05:24:56 PM PDT 24
Peak memory 197188 kb
Host smart-df3b5e24-050a-4240-81e2-76c33cdaeefa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2031283916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2031283916
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1390685339
Short name T879
Test name
Test status
Simulation time 75791063 ps
CPU time 1.08 seconds
Started Aug 15 05:25:02 PM PDT 24
Finished Aug 15 05:25:03 PM PDT 24
Peak memory 191292 kb
Host smart-1339bf81-9955-414f-ac8f-f44378392d83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390685339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1390685339
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1600871000
Short name T877
Test name
Test status
Simulation time 50793444 ps
CPU time 1.47 seconds
Started Aug 15 05:24:48 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 197624 kb
Host smart-3fb3c645-1929-467e-bebf-93ad3176725c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1600871000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1600871000
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3604949857
Short name T913
Test name
Test status
Simulation time 141039618 ps
CPU time 1.29 seconds
Started Aug 15 05:24:48 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 197256 kb
Host smart-9507ae97-066b-44ee-b1e4-7c8c0e5252b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604949857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3604949857
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.773736660
Short name T861
Test name
Test status
Simulation time 19135132 ps
CPU time 0.73 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 194604 kb
Host smart-371bea3c-ad8a-421d-bdea-609fc7eb984f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=773736660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.773736660
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3181452713
Short name T894
Test name
Test status
Simulation time 39634050 ps
CPU time 0.95 seconds
Started Aug 15 05:24:51 PM PDT 24
Finished Aug 15 05:24:52 PM PDT 24
Peak memory 196896 kb
Host smart-47cf5622-9017-4e0d-adb2-337fd34a532c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181452713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3181452713
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1430599245
Short name T854
Test name
Test status
Simulation time 166100256 ps
CPU time 0.83 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 195780 kb
Host smart-d3a032f0-7f04-4c26-98dd-a6dfb15e8438
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1430599245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1430599245
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2329768812
Short name T914
Test name
Test status
Simulation time 134841244 ps
CPU time 1.3 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:50 PM PDT 24
Peak memory 191328 kb
Host smart-929a3c48-9959-4380-968c-7f5033b079ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329768812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2329768812
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.523581943
Short name T918
Test name
Test status
Simulation time 389675569 ps
CPU time 1.48 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:52 PM PDT 24
Peak memory 191240 kb
Host smart-5cfc4bf3-7277-4d84-8d78-3b6a5e5db0fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=523581943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.523581943
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1802708096
Short name T940
Test name
Test status
Simulation time 263896920 ps
CPU time 1.39 seconds
Started Aug 15 05:24:50 PM PDT 24
Finished Aug 15 05:24:52 PM PDT 24
Peak memory 191596 kb
Host smart-10b291bf-42e5-4672-b9cf-d8bb57c957cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802708096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1802708096
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2454434638
Short name T935
Test name
Test status
Simulation time 76806947 ps
CPU time 0.93 seconds
Started Aug 15 05:24:54 PM PDT 24
Finished Aug 15 05:24:55 PM PDT 24
Peak memory 197440 kb
Host smart-99f7ea5f-2a7c-4140-a3fc-04a50a25e156
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2454434638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2454434638
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.291830186
Short name T904
Test name
Test status
Simulation time 622656609 ps
CPU time 1.43 seconds
Started Aug 15 05:24:49 PM PDT 24
Finished Aug 15 05:24:51 PM PDT 24
Peak memory 197640 kb
Host smart-aec0a37c-827e-46e9-b402-a1dbb5421a3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291830186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.291830186
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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