Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1478938	1			T25	761		T26	1		T1	7764
all_pins[1]	1478938	1			T25	761		T26	1		T1	7764
all_pins[2]	1478938	1			T25	761		T26	1		T1	7764
all_pins[3]	1478938	1			T25	761		T26	1		T1	7764
all_pins[4]	1478938	1			T25	761		T26	1		T1	7764
all_pins[5]	1478938	1			T25	761		T26	1		T1	7764
all_pins[6]	1478938	1			T25	761		T26	1		T1	7764
all_pins[7]	1478938	1			T25	761		T26	1		T1	7764
all_pins[8]	1478938	1			T25	761		T26	1		T1	7764
all_pins[9]	1478938	1			T25	761		T26	1		T1	7764
all_pins[10]	1478938	1			T25	761		T26	1		T1	7764
all_pins[11]	1478938	1			T25	761		T26	1		T1	7764
all_pins[12]	1478938	1			T25	761		T26	1		T1	7764
all_pins[13]	1478938	1			T25	761		T26	1		T1	7764
all_pins[14]	1478938	1			T25	761		T26	1		T1	7764
all_pins[15]	1478938	1			T25	761		T26	1		T1	7764
all_pins[16]	1478938	1			T25	761		T26	1		T1	7764
all_pins[17]	1478938	1			T25	761		T26	1		T1	7764
all_pins[18]	1478938	1			T25	761		T26	1		T1	7764
all_pins[19]	1478938	1			T25	761		T26	1		T1	7764
all_pins[20]	1478938	1			T25	761		T26	1		T1	7764
all_pins[21]	1478938	1			T25	761		T26	1		T1	7764
all_pins[22]	1478938	1			T25	761		T26	1		T1	7764
all_pins[23]	1478938	1			T25	761		T26	1		T1	7764
all_pins[24]	1478938	1			T25	761		T26	1		T1	7764
all_pins[25]	1478938	1			T25	761		T26	1		T1	7764
all_pins[26]	1478938	1			T25	761		T26	1		T1	7764
all_pins[27]	1478938	1			T25	761		T26	1		T1	7764
all_pins[28]	1478938	1			T25	761		T26	1		T1	7764
all_pins[29]	1478938	1			T25	761		T26	1		T1	7764
all_pins[30]	1478938	1			T25	761		T26	1		T1	7764
all_pins[31]	1478938	1			T25	761		T26	1		T1	7764

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	29371759	1			T25	14828		T26	32		T1	152692
values[0x1]	17954257	1			T25	9524		T1	95756		T11	2011
transitions[0x0=>0x1]	10733995	1			T25	5570		T1	56935		T11	1158
transitions[0x1=>0x0]	10733854	1			T25	5569		T1	56934		T11	1157

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	920665	1			T25	472		T26	1		T1	4848
all_pins[0]	values[0x1]	558273	1			T25	289		T1	2916		T11	61
all_pins[0]	transitions[0x0=>0x1]	344711	1			T25	160		T1	1702		T11	42
all_pins[0]	transitions[0x1=>0x0]	347244	1			T25	171		T1	2042		T11	34
all_pins[1]	values[0x0]	920209	1			T25	430		T26	1		T1	4694
all_pins[1]	values[0x1]	558729	1			T25	331		T1	3070		T11	72
all_pins[1]	transitions[0x0=>0x1]	335618	1			T25	209		T1	1831		T11	41
all_pins[1]	transitions[0x1=>0x0]	335162	1			T25	167		T1	1677		T11	30
all_pins[2]	values[0x0]	915647	1			T25	437		T26	1		T1	4763
all_pins[2]	values[0x1]	563291	1			T25	324		T1	3001		T11	74
all_pins[2]	transitions[0x0=>0x1]	337529	1			T25	173		T1	1770		T11	42
all_pins[2]	transitions[0x1=>0x0]	332967	1			T25	180		T1	1839		T11	40
all_pins[3]	values[0x0]	913643	1			T25	480		T26	1		T1	4533
all_pins[3]	values[0x1]	565295	1			T25	281		T1	3231		T11	69
all_pins[3]	transitions[0x0=>0x1]	336156	1			T25	153		T1	1897		T11	36
all_pins[3]	transitions[0x1=>0x0]	334152	1			T25	196		T1	1667		T11	41
all_pins[4]	values[0x0]	916768	1			T25	459		T26	1		T1	4958
all_pins[4]	values[0x1]	562170	1			T25	302		T1	2806		T11	45
all_pins[4]	transitions[0x0=>0x1]	334233	1			T25	182		T1	1666		T11	27
all_pins[4]	transitions[0x1=>0x0]	337358	1			T25	161		T1	2091		T11	51
all_pins[5]	values[0x0]	914153	1			T25	417		T26	1		T1	4691
all_pins[5]	values[0x1]	564785	1			T25	344		T1	3073		T11	57
all_pins[5]	transitions[0x0=>0x1]	336229	1			T25	182		T1	1940		T11	45
all_pins[5]	transitions[0x1=>0x0]	333614	1			T25	140		T1	1673		T11	33
all_pins[6]	values[0x0]	914255	1			T25	437		T26	1		T1	4681
all_pins[6]	values[0x1]	564683	1			T25	324		T1	3083		T11	51
all_pins[6]	transitions[0x0=>0x1]	335299	1			T25	169		T1	1803		T11	33
all_pins[6]	transitions[0x1=>0x0]	335401	1			T25	189		T1	1793		T11	39
all_pins[7]	values[0x0]	918526	1			T25	460		T26	1		T1	4764
all_pins[7]	values[0x1]	560412	1			T25	301		T1	3000		T11	75
all_pins[7]	transitions[0x0=>0x1]	332400	1			T25	197		T1	1700		T11	40
all_pins[7]	transitions[0x1=>0x0]	336671	1			T25	220		T1	1783		T11	16
all_pins[8]	values[0x0]	917583	1			T25	479		T26	1		T1	4807
all_pins[8]	values[0x1]	561355	1			T25	282		T1	2957		T11	67
all_pins[8]	transitions[0x0=>0x1]	335656	1			T25	166		T1	1681		T11	33
all_pins[8]	transitions[0x1=>0x0]	334713	1			T25	185		T1	1724		T11	41
all_pins[9]	values[0x0]	916865	1			T25	462		T26	1		T1	4732
all_pins[9]	values[0x1]	562073	1			T25	299		T1	3032		T11	63
all_pins[9]	transitions[0x0=>0x1]	336531	1			T25	178		T1	1920		T11	26
all_pins[9]	transitions[0x1=>0x0]	335813	1			T25	161		T1	1845		T11	30
all_pins[10]	values[0x0]	917193	1			T25	480		T26	1		T1	4740
all_pins[10]	values[0x1]	561745	1			T25	281		T1	3024		T11	89
all_pins[10]	transitions[0x0=>0x1]	334679	1			T25	169		T1	1819		T11	59
all_pins[10]	transitions[0x1=>0x0]	335007	1			T25	187		T1	1827		T11	33
all_pins[11]	values[0x0]	920389	1			T25	442		T26	1		T1	4778
all_pins[11]	values[0x1]	558549	1			T25	319		T1	2986		T11	62
all_pins[11]	transitions[0x0=>0x1]	333187	1			T25	186		T1	1698		T11	24
all_pins[11]	transitions[0x1=>0x0]	336383	1			T25	148		T1	1736		T11	51
all_pins[12]	values[0x0]	918214	1			T25	477		T26	1		T1	4691
all_pins[12]	values[0x1]	560724	1			T25	284		T1	3073		T11	59
all_pins[12]	transitions[0x0=>0x1]	335379	1			T25	126		T1	1784		T11	37
all_pins[12]	transitions[0x1=>0x0]	333204	1			T25	161		T1	1697		T11	40
all_pins[13]	values[0x0]	921330	1			T25	508		T26	1		T1	4874
all_pins[13]	values[0x1]	557608	1			T25	253		T1	2890		T11	66
all_pins[13]	transitions[0x0=>0x1]	333258	1			T25	159		T1	1633		T11	40
all_pins[13]	transitions[0x1=>0x0]	336374	1			T25	190		T1	1816		T11	33
all_pins[14]	values[0x0]	915646	1			T25	460		T26	1		T1	4854
all_pins[14]	values[0x1]	563292	1			T25	301		T1	2910		T11	74
all_pins[14]	transitions[0x0=>0x1]	338292	1			T25	206		T1	1717		T11	31
all_pins[14]	transitions[0x1=>0x0]	332608	1			T25	158		T1	1697		T11	23
all_pins[15]	values[0x0]	917168	1			T25	447		T26	1		T1	5006
all_pins[15]	values[0x1]	561770	1			T25	314		T1	2758		T11	62
all_pins[15]	transitions[0x0=>0x1]	334835	1			T25	187		T1	1628		T11	27
all_pins[15]	transitions[0x1=>0x0]	336357	1			T25	174		T1	1780		T11	39
all_pins[16]	values[0x0]	919221	1			T25	443		T26	1		T1	4855
all_pins[16]	values[0x1]	559717	1			T25	318		T1	2909		T11	61
all_pins[16]	transitions[0x0=>0x1]	334428	1			T25	147		T1	1727		T11	35
all_pins[16]	transitions[0x1=>0x0]	336481	1			T25	143		T1	1576		T11	36
all_pins[17]	values[0x0]	918139	1			T25	475		T26	1		T1	4788
all_pins[17]	values[0x1]	560799	1			T25	286		T1	2976		T11	64
all_pins[17]	transitions[0x0=>0x1]	335119	1			T25	152		T1	1841		T11	31
all_pins[17]	transitions[0x1=>0x0]	334037	1			T25	184		T1	1774		T11	28
all_pins[18]	values[0x0]	921921	1			T25	464		T26	1		T1	4692
all_pins[18]	values[0x1]	557017	1			T25	297		T1	3072		T11	74
all_pins[18]	transitions[0x0=>0x1]	333421	1			T25	198		T1	1809		T11	46
all_pins[18]	transitions[0x1=>0x0]	337203	1			T25	187		T1	1713		T11	36
all_pins[19]	values[0x0]	919349	1			T25	498		T26	1		T1	4826
all_pins[19]	values[0x1]	559589	1			T25	263		T1	2938		T11	52
all_pins[19]	transitions[0x0=>0x1]	334845	1			T25	166		T1	1793		T11	21
all_pins[19]	transitions[0x1=>0x0]	332273	1			T25	200		T1	1927		T11	43
all_pins[20]	values[0x0]	920293	1			T25	427		T26	1		T1	4648
all_pins[20]	values[0x1]	558645	1			T25	334		T1	3116		T11	47
all_pins[20]	transitions[0x0=>0x1]	335022	1			T25	217		T1	1900		T11	28
all_pins[20]	transitions[0x1=>0x0]	335966	1			T25	146		T1	1722		T11	33
all_pins[21]	values[0x0]	918342	1			T25	433		T26	1		T1	4725
all_pins[21]	values[0x1]	560596	1			T25	328		T1	3039		T11	57
all_pins[21]	transitions[0x0=>0x1]	335635	1			T25	168		T1	1817		T11	38
all_pins[21]	transitions[0x1=>0x0]	333684	1			T25	174		T1	1894		T11	28
all_pins[22]	values[0x0]	918290	1			T25	463		T26	1		T1	4666
all_pins[22]	values[0x1]	560648	1			T25	298		T1	3098		T11	43
all_pins[22]	transitions[0x0=>0x1]	334840	1			T25	170		T1	1863		T11	29
all_pins[22]	transitions[0x1=>0x0]	334788	1			T25	200		T1	1804		T11	43
all_pins[23]	values[0x0]	918284	1			T25	462		T26	1		T1	4771
all_pins[23]	values[0x1]	560654	1			T25	299		T1	2993		T11	71
all_pins[23]	transitions[0x0=>0x1]	334511	1			T25	177		T1	1629		T11	46
all_pins[23]	transitions[0x1=>0x0]	334505	1			T25	176		T1	1734		T11	18
all_pins[24]	values[0x0]	916832	1			T25	475		T26	1		T1	4862
all_pins[24]	values[0x1]	562106	1			T25	286		T1	2902		T11	69
all_pins[24]	transitions[0x0=>0x1]	335461	1			T25	165		T1	1676		T11	42
all_pins[24]	transitions[0x1=>0x0]	334009	1			T25	178		T1	1767		T11	44
all_pins[25]	values[0x0]	917651	1			T25	503		T26	1		T1	4750
all_pins[25]	values[0x1]	561287	1			T25	258		T1	3014		T11	50
all_pins[25]	transitions[0x0=>0x1]	334357	1			T25	162		T1	1887		T11	30
all_pins[25]	transitions[0x1=>0x0]	335176	1			T25	190		T1	1775		T11	49
all_pins[26]	values[0x0]	916803	1			T25	477		T26	1		T1	4836
all_pins[26]	values[0x1]	562135	1			T25	284		T1	2928		T11	42
all_pins[26]	transitions[0x0=>0x1]	335923	1			T25	171		T1	1743		T11	28
all_pins[26]	transitions[0x1=>0x0]	335075	1			T25	145		T1	1829		T11	36
all_pins[27]	values[0x0]	915738	1			T25	504		T26	1		T1	4619
all_pins[27]	values[0x1]	563200	1			T25	257		T1	3145		T11	82
all_pins[27]	transitions[0x0=>0x1]	336446	1			T25	189		T1	1881		T11	56
all_pins[27]	transitions[0x1=>0x0]	335381	1			T25	216		T1	1664		T11	16
all_pins[28]	values[0x0]	918186	1			T25	495		T26	1		T1	4980
all_pins[28]	values[0x1]	560752	1			T25	266		T1	2784		T11	68
all_pins[28]	transitions[0x0=>0x1]	335881	1			T25	150		T1	1635		T11	37
all_pins[28]	transitions[0x1=>0x0]	338329	1			T25	141		T1	1996		T11	51
all_pins[29]	values[0x0]	915159	1			T25	472		T26	1		T1	4875
all_pins[29]	values[0x1]	563779	1			T25	289		T1	2889		T11	47
all_pins[29]	transitions[0x0=>0x1]	337215	1			T25	193		T1	1897		T11	21
all_pins[29]	transitions[0x1=>0x0]	334188	1			T25	170		T1	1792		T11	42
all_pins[30]	values[0x0]	921306	1			T25	430		T26	1		T1	4878
all_pins[30]	values[0x1]	557632	1			T25	331		T1	2886		T11	84
all_pins[30]	transitions[0x0=>0x1]	330904	1			T25	178		T1	1741		T11	56
all_pins[30]	transitions[0x1=>0x0]	337051	1			T25	136		T1	1744		T11	19
all_pins[31]	values[0x0]	917991	1			T25	460		T26	1		T1	4507
all_pins[31]	values[0x1]	560947	1			T25	301		T1	3257		T11	54
all_pins[31]	transitions[0x0=>0x1]	335995	1			T25	165		T1	1907		T11	31
all_pins[31]	transitions[0x1=>0x0]	332680	1			T25	195		T1	1536		T11	61