Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6230001	1			T25	2072		T26	159		T1	26760
all_values[1]	6230001	1			T25	2072		T26	159		T1	26760
all_values[2]	6230001	1			T25	2072		T26	159		T1	26760
all_values[3]	6230001	1			T25	2072		T26	159		T1	26760
all_values[4]	6230001	1			T25	2072		T26	159		T1	26760
all_values[5]	6230001	1			T25	2072		T26	159		T1	26760
all_values[6]	6230001	1			T25	2072		T26	159		T1	26760
all_values[7]	6230001	1			T25	2072		T26	159		T1	26760
all_values[8]	6230001	1			T25	2072		T26	159		T1	26760
all_values[9]	6230001	1			T25	2072		T26	159		T1	26760
all_values[10]	6230001	1			T25	2072		T26	159		T1	26760
all_values[11]	6230001	1			T25	2072		T26	159		T1	26760
all_values[12]	6230001	1			T25	2072		T26	159		T1	26760
all_values[13]	6230001	1			T25	2072		T26	159		T1	26760
all_values[14]	6230001	1			T25	2072		T26	159		T1	26760
all_values[15]	6230001	1			T25	2072		T26	159		T1	26760
all_values[16]	6230001	1			T25	2072		T26	159		T1	26760
all_values[17]	6230001	1			T25	2072		T26	159		T1	26760
all_values[18]	6230001	1			T25	2072		T26	159		T1	26760
all_values[19]	6230001	1			T25	2072		T26	159		T1	26760
all_values[20]	6230001	1			T25	2072		T26	159		T1	26760
all_values[21]	6230001	1			T25	2072		T26	159		T1	26760
all_values[22]	6230001	1			T25	2072		T26	159		T1	26760
all_values[23]	6230001	1			T25	2072		T26	159		T1	26760
all_values[24]	6230001	1			T25	2072		T26	159		T1	26760
all_values[25]	6230001	1			T25	2072		T26	159		T1	26760
all_values[26]	6230001	1			T25	2072		T26	159		T1	26760
all_values[27]	6230001	1			T25	2072		T26	159		T1	26760
all_values[28]	6230001	1			T25	2072		T26	159		T1	26760
all_values[29]	6230001	1			T25	2072		T26	159		T1	26760
all_values[30]	6230001	1			T25	2072		T26	159		T1	26760
all_values[31]	6230001	1			T25	2072		T26	159		T1	26760

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134750534

1

T25

32352

T26

5088

T1

482678

auto[1]

64609498

1

T25

33952

T1

373642

T11

5176

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82796803

1

T25

7704

T26

5088

T1

149271

auto[1]

116563229

1

T25

58600

T1

707049

T11

8856

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197588415

1

T25

63671

T26

5088

T1

849754

auto[1]

1771617

1

T25

2633

T1

6566

T15

33154

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2385552	1			T25	159		T26	159		T1	3692
all_values[0]	auto[0]	auto[0]	auto[1]	1797273	1			T25	913		T1	11526		T11	118
all_values[0]	auto[0]	auto[1]	auto[0]	204334	1			T25	86		T1	1233		T11	21
all_values[0]	auto[0]	auto[1]	auto[1]	1787516	1			T25	832		T1	10081		T11	149
all_values[0]	auto[1]	auto[0]	auto[1]	27981	1			T25	46		T1	110		T15	522
all_values[0]	auto[1]	auto[1]	auto[1]	27345	1			T25	36		T1	118		T15	518
all_values[1]	auto[0]	auto[0]	auto[0]	2384886	1			T25	88		T26	159		T1	3751
all_values[1]	auto[0]	auto[0]	auto[1]	1802494	1			T25	806		T1	10470		T11	106
all_values[1]	auto[0]	auto[1]	auto[0]	196394	1			T25	141		T1	969		T11	9
all_values[1]	auto[0]	auto[1]	auto[1]	1790827	1			T25	963		T1	11360		T11	165
all_values[1]	auto[1]	auto[0]	auto[1]	28051	1			T25	25		T1	94		T15	561
all_values[1]	auto[1]	auto[1]	auto[1]	27349	1			T25	49		T1	116		T15	511
all_values[2]	auto[0]	auto[0]	auto[0]	2383812	1			T25	91		T26	159		T1	3557
all_values[2]	auto[0]	auto[0]	auto[1]	1797860	1			T25	800		T1	12188		T11	101
all_values[2]	auto[0]	auto[1]	auto[0]	202404	1			T25	138		T1	885		T11	5
all_values[2]	auto[0]	auto[1]	auto[1]	1790440	1			T25	958		T1	9920		T11	188
all_values[2]	auto[1]	auto[0]	auto[1]	27920	1			T25	32		T1	103		T15	574
all_values[2]	auto[1]	auto[1]	auto[1]	27565	1			T25	53		T1	107		T15	475
all_values[3]	auto[0]	auto[0]	auto[0]	2383707	1			T25	163		T26	159		T1	3678
all_values[3]	auto[0]	auto[0]	auto[1]	1786214	1			T25	718		T1	11005		T11	120
all_values[3]	auto[0]	auto[1]	auto[0]	204738	1			T25	202		T1	1046		T11	21
all_values[3]	auto[0]	auto[1]	auto[1]	1799981	1			T25	916		T1	10825		T11	154
all_values[3]	auto[1]	auto[0]	auto[1]	27845	1			T25	39		T1	79		T15	533
all_values[3]	auto[1]	auto[1]	auto[1]	27516	1			T25	34		T1	127		T15	512
all_values[4]	auto[0]	auto[0]	auto[0]	2385514	1			T25	90		T26	159		T1	4305
all_values[4]	auto[0]	auto[0]	auto[1]	1794654	1			T25	872		T1	11416		T11	180
all_values[4]	auto[0]	auto[1]	auto[0]	205501	1			T25	121		T1	1144		T11	10
all_values[4]	auto[0]	auto[1]	auto[1]	1789068	1			T25	913		T1	9691		T11	112
all_values[4]	auto[1]	auto[0]	auto[1]	27645	1			T25	37		T1	96		T15	537
all_values[4]	auto[1]	auto[1]	auto[1]	27619	1			T25	39		T1	108		T15	491
all_values[5]	auto[0]	auto[0]	auto[0]	2383892	1			T25	135		T26	159		T1	3694
all_values[5]	auto[0]	auto[0]	auto[1]	1783275	1			T25	814		T1	10058		T11	150
all_values[5]	auto[0]	auto[1]	auto[0]	200765	1			T25	98		T1	982		T11	12
all_values[5]	auto[0]	auto[1]	auto[1]	1806603	1			T25	936		T1	11832		T11	131
all_values[5]	auto[1]	auto[0]	auto[1]	27708	1			T25	33		T1	81		T15	538
all_values[5]	auto[1]	auto[1]	auto[1]	27758	1			T25	56		T1	113		T15	522
all_values[6]	auto[0]	auto[0]	auto[0]	2384388	1			T25	110		T26	159		T1	3579
all_values[6]	auto[0]	auto[0]	auto[1]	1781961	1			T25	839		T1	11437		T11	166
all_values[6]	auto[0]	auto[1]	auto[0]	200165	1			T25	98		T1	978		T11	16
all_values[6]	auto[0]	auto[1]	auto[1]	1808198	1			T25	943		T1	10553		T11	107
all_values[6]	auto[1]	auto[0]	auto[1]	27821	1			T25	34		T1	116		T15	526
all_values[6]	auto[1]	auto[1]	auto[1]	27468	1			T25	48		T1	97		T15	469
all_values[7]	auto[0]	auto[0]	auto[0]	2387593	1			T25	115		T26	159		T1	3700
all_values[7]	auto[0]	auto[0]	auto[1]	1793871	1			T25	825		T1	10894		T11	143
all_values[7]	auto[0]	auto[1]	auto[0]	202344	1			T25	139		T1	934		T11	14
all_values[7]	auto[0]	auto[1]	auto[1]	1790971	1			T25	910		T1	11050		T11	155
all_values[7]	auto[1]	auto[0]	auto[1]	27931	1			T25	47		T1	101		T15	524
all_values[7]	auto[1]	auto[1]	auto[1]	27291	1			T25	36		T1	81		T15	532
all_values[8]	auto[0]	auto[0]	auto[0]	2383795	1			T25	107		T26	159		T1	3691
all_values[8]	auto[0]	auto[0]	auto[1]	1804357	1			T25	791		T1	10865		T11	132
all_values[8]	auto[0]	auto[1]	auto[0]	199674	1			T25	123		T1	1196		T11	11
all_values[8]	auto[0]	auto[1]	auto[1]	1786987	1			T25	976		T1	10804		T11	157
all_values[8]	auto[1]	auto[0]	auto[1]	27759	1			T25	31		T1	114		T15	537
all_values[8]	auto[1]	auto[1]	auto[1]	27429	1			T25	44		T1	90		T15	500
all_values[9]	auto[0]	auto[0]	auto[0]	2382025	1			T25	134		T26	159		T1	3540
all_values[9]	auto[0]	auto[0]	auto[1]	1803745	1			T25	764		T1	10998		T11	151
all_values[9]	auto[0]	auto[1]	auto[0]	201363	1			T25	209		T1	875		T11	11
all_values[9]	auto[0]	auto[1]	auto[1]	1787378	1			T25	887		T1	11139		T11	135
all_values[9]	auto[1]	auto[0]	auto[1]	27859	1			T25	35		T1	113		T15	528
all_values[9]	auto[1]	auto[1]	auto[1]	27631	1			T25	43		T1	95		T15	495
all_values[10]	auto[0]	auto[0]	auto[0]	2383797	1			T25	194		T26	159		T1	3653
all_values[10]	auto[0]	auto[0]	auto[1]	1801931	1			T25	813		T1	10802		T11	125
all_values[10]	auto[0]	auto[1]	auto[0]	201396	1			T25	99		T1	1183		T11	6
all_values[10]	auto[0]	auto[1]	auto[1]	1787556	1			T25	882		T1	10911		T11	169
all_values[10]	auto[1]	auto[0]	auto[1]	27762	1			T25	40		T1	107		T15	513
all_values[10]	auto[1]	auto[1]	auto[1]	27559	1			T25	44		T1	104		T15	515
all_values[11]	auto[0]	auto[0]	auto[0]	2386784	1			T25	109		T26	159		T1	3470
all_values[11]	auto[0]	auto[0]	auto[1]	1801585	1			T25	798		T1	11931		T11	106
all_values[11]	auto[0]	auto[1]	auto[0]	203861	1			T25	117		T1	1015		T11	32
all_values[11]	auto[0]	auto[1]	auto[1]	1782182	1			T25	972		T1	10146		T11	155
all_values[11]	auto[1]	auto[0]	auto[1]	27932	1			T25	37		T1	95		T15	490
all_values[11]	auto[1]	auto[1]	auto[1]	27657	1			T25	39		T1	103		T15	522
all_values[12]	auto[0]	auto[0]	auto[0]	2385472	1			T25	187		T26	159		T1	3723
all_values[12]	auto[0]	auto[0]	auto[1]	1804415	1			T25	789		T1	11416		T11	121
all_values[12]	auto[0]	auto[1]	auto[0]	203354	1			T25	141		T1	1061		T11	30
all_values[12]	auto[0]	auto[1]	auto[1]	1781694	1			T25	872		T1	10358		T11	139
all_values[12]	auto[1]	auto[0]	auto[1]	27709	1			T25	37		T1	104		T15	529
all_values[12]	auto[1]	auto[1]	auto[1]	27357	1			T25	46		T1	98		T15	516
all_values[13]	auto[0]	auto[0]	auto[0]	2385679	1			T25	154		T26	159		T1	3531
all_values[13]	auto[0]	auto[0]	auto[1]	1800601	1			T25	951		T1	12145		T11	126
all_values[13]	auto[0]	auto[1]	auto[0]	205964	1			T25	129		T1	1062		T11	26
all_values[13]	auto[0]	auto[1]	auto[1]	1782680	1			T25	756		T1	9813		T11	151
all_values[13]	auto[1]	auto[0]	auto[1]	27318	1			T25	43		T1	99		T15	464
all_values[13]	auto[1]	auto[1]	auto[1]	27759	1			T25	39		T1	110		T15	546
all_values[14]	auto[0]	auto[0]	auto[0]	2385842	1			T25	143		T26	159		T1	3750
all_values[14]	auto[0]	auto[0]	auto[1]	1788852	1			T25	938		T1	12231		T11	93
all_values[14]	auto[0]	auto[1]	auto[0]	200219	1			T25	87		T1	770		T11	23
all_values[14]	auto[0]	auto[1]	auto[1]	1799751	1			T25	833		T1	9797		T11	170
all_values[14]	auto[1]	auto[0]	auto[1]	27828	1			T25	37		T1	104		T15	518
all_values[14]	auto[1]	auto[1]	auto[1]	27509	1			T25	34		T1	108		T15	508
all_values[15]	auto[0]	auto[0]	auto[0]	2386491	1			T25	119		T26	159		T1	3982
all_values[15]	auto[0]	auto[0]	auto[1]	1802051	1			T25	798		T1	11931		T11	184
all_values[15]	auto[0]	auto[1]	auto[0]	199837	1			T25	119		T1	1084		T11	8
all_values[15]	auto[0]	auto[1]	auto[1]	1786242	1			T25	940		T1	9549		T11	126
all_values[15]	auto[1]	auto[0]	auto[1]	27839	1			T25	43		T1	106		T15	541
all_values[15]	auto[1]	auto[1]	auto[1]	27541	1			T25	53		T1	108		T15	509
all_values[16]	auto[0]	auto[0]	auto[0]	2384078	1			T25	80		T26	159		T1	3623
all_values[16]	auto[0]	auto[0]	auto[1]	1813140	1			T25	826		T1	11737		T11	152
all_values[16]	auto[0]	auto[1]	auto[0]	198772	1			T25	77		T1	897		T11	16
all_values[16]	auto[0]	auto[1]	auto[1]	1778575	1			T25	1003		T1	10308		T11	126
all_values[16]	auto[1]	auto[0]	auto[1]	27955	1			T25	32		T1	93		T15	503
all_values[16]	auto[1]	auto[1]	auto[1]	27481	1			T25	54		T1	102		T15	498
all_values[17]	auto[0]	auto[0]	auto[0]	2385084	1			T25	129		T26	159		T1	3761
all_values[17]	auto[0]	auto[0]	auto[1]	1797960	1			T25	874		T1	11056		T11	164
all_values[17]	auto[0]	auto[1]	auto[0]	202379	1			T25	135		T1	983		T11	11
all_values[17]	auto[0]	auto[1]	auto[1]	1789484	1			T25	865		T1	10755		T11	130
all_values[17]	auto[1]	auto[0]	auto[1]	27728	1			T25	29		T1	105		T15	541
all_values[17]	auto[1]	auto[1]	auto[1]	27366	1			T25	40		T1	100		T15	494
all_values[18]	auto[0]	auto[0]	auto[0]	2389112	1			T25	89		T26	159		T1	3538
all_values[18]	auto[0]	auto[0]	auto[1]	1807228	1			T25	834		T1	11949		T11	94
all_values[18]	auto[0]	auto[1]	auto[0]	199308	1			T25	148		T1	940		T11	22
all_values[18]	auto[0]	auto[1]	auto[1]	1779133	1			T25	909		T1	10108		T11	181
all_values[18]	auto[1]	auto[0]	auto[1]	27681	1			T25	44		T1	115		T15	470
all_values[18]	auto[1]	auto[1]	auto[1]	27539	1			T25	48		T1	110		T15	543
all_values[19]	auto[0]	auto[0]	auto[0]	2387400	1			T25	131		T26	159		T1	3773
all_values[19]	auto[0]	auto[0]	auto[1]	1785172	1			T25	957		T1	10577		T11	131
all_values[19]	auto[0]	auto[1]	auto[0]	203105	1			T25	141		T1	1051		T11	24
all_values[19]	auto[0]	auto[1]	auto[1]	1798765	1			T25	766		T1	11157		T11	119
all_values[19]	auto[1]	auto[0]	auto[1]	27884	1			T25	42		T1	108		T15	511
all_values[19]	auto[1]	auto[1]	auto[1]	27675	1			T25	35		T1	94		T15	532
all_values[20]	auto[0]	auto[0]	auto[0]	2386470	1			T25	78		T26	159		T1	3711
all_values[20]	auto[0]	auto[0]	auto[1]	1794167	1			T25	898		T1	10382		T11	184
all_values[20]	auto[0]	auto[1]	auto[0]	204425	1			T25	63		T1	1100		T11	9
all_values[20]	auto[0]	auto[1]	auto[1]	1789754	1			T25	959		T1	11355		T11	107
all_values[20]	auto[1]	auto[0]	auto[1]	27793	1			T25	43		T1	108		T15	541
all_values[20]	auto[1]	auto[1]	auto[1]	27392	1			T25	31		T1	104		T15	519
all_values[21]	auto[0]	auto[0]	auto[0]	2388077	1			T25	121		T26	159		T1	3558
all_values[21]	auto[0]	auto[0]	auto[1]	1806391	1			T25	706		T1	11165		T11	123
all_values[21]	auto[0]	auto[1]	auto[0]	201497	1			T25	134		T1	783		T11	18
all_values[21]	auto[0]	auto[1]	auto[1]	1778703	1			T25	1025		T1	11038		T11	154
all_values[21]	auto[1]	auto[0]	auto[1]	27770	1			T25	37		T1	103		T15	485
all_values[21]	auto[1]	auto[1]	auto[1]	27563	1			T25	49		T1	113		T15	561
all_values[22]	auto[0]	auto[0]	auto[0]	2384675	1			T25	132		T26	159		T1	3522
all_values[22]	auto[0]	auto[0]	auto[1]	1790975	1			T25	860		T1	10401		T11	182
all_values[22]	auto[0]	auto[1]	auto[0]	202628	1			T25	108		T1	1018		T11	16
all_values[22]	auto[0]	auto[1]	auto[1]	1796303	1			T25	879		T1	11618		T11	103
all_values[22]	auto[1]	auto[0]	auto[1]	27894	1			T25	56		T1	86		T15	488
all_values[22]	auto[1]	auto[1]	auto[1]	27526	1			T25	37		T1	115		T15	508
all_values[23]	auto[0]	auto[0]	auto[0]	2386141	1			T25	141		T26	159		T1	3703
all_values[23]	auto[0]	auto[0]	auto[1]	1800880	1			T25	796		T1	11628		T11	156
all_values[23]	auto[0]	auto[1]	auto[0]	198197	1			T25	119		T1	1076		T11	15
all_values[23]	auto[0]	auto[1]	auto[1]	1789516	1			T25	945		T1	10148		T11	137
all_values[23]	auto[1]	auto[0]	auto[1]	28012	1			T25	33		T1	101		T15	542
all_values[23]	auto[1]	auto[1]	auto[1]	27255	1			T25	38		T1	104		T15	502
all_values[24]	auto[0]	auto[0]	auto[0]	2387898	1			T25	95		T26	159		T1	3707
all_values[24]	auto[0]	auto[0]	auto[1]	1780448	1			T25	907		T1	11259		T11	112
all_values[24]	auto[0]	auto[1]	auto[0]	203176	1			T25	123		T1	1027		T11	41
all_values[24]	auto[0]	auto[1]	auto[1]	1803231	1			T25	863		T1	10568		T11	152
all_values[24]	auto[1]	auto[0]	auto[1]	27651	1			T25	46		T1	105		T15	509
all_values[24]	auto[1]	auto[1]	auto[1]	27597	1			T25	38		T1	94		T15	528
all_values[25]	auto[0]	auto[0]	auto[0]	2383399	1			T25	137		T26	159		T1	3486
all_values[25]	auto[0]	auto[0]	auto[1]	1805335	1			T25	996		T1	10925		T11	162
all_values[25]	auto[0]	auto[1]	auto[0]	204844	1			T25	126		T1	993		T11	12
all_values[25]	auto[0]	auto[1]	auto[1]	1780588	1			T25	726		T1	11155		T11	113
all_values[25]	auto[1]	auto[0]	auto[1]	28051	1			T25	54		T1	114		T15	533
all_values[25]	auto[1]	auto[1]	auto[1]	27784	1			T25	33		T1	87		T15	559
all_values[26]	auto[0]	auto[0]	auto[0]	2382096	1			T25	114		T26	159		T1	3507
all_values[26]	auto[0]	auto[0]	auto[1]	1808014	1			T25	872		T1	11872		T11	174
all_values[26]	auto[0]	auto[1]	auto[0]	202156	1			T25	117		T1	1052		T11	22
all_values[26]	auto[0]	auto[1]	auto[1]	1782303	1			T25	884		T1	10115		T11	92
all_values[26]	auto[1]	auto[0]	auto[1]	27969	1			T25	44		T1	98		T15	544
all_values[26]	auto[1]	auto[1]	auto[1]	27463	1			T25	41		T1	116		T15	543
all_values[27]	auto[0]	auto[0]	auto[0]	2383962	1			T25	92		T26	159		T1	3884
all_values[27]	auto[0]	auto[0]	auto[1]	1786102	1			T25	999		T1	9948		T11	94
all_values[27]	auto[0]	auto[1]	auto[0]	203024	1			T25	89		T1	875		T11	29
all_values[27]	auto[0]	auto[1]	auto[1]	1801634	1			T25	788		T1	11855		T11	188
all_values[27]	auto[1]	auto[0]	auto[1]	27872	1			T25	56		T1	97		T15	481
all_values[27]	auto[1]	auto[1]	auto[1]	27407	1			T25	48		T1	101		T15	531
all_values[28]	auto[0]	auto[0]	auto[0]	2387421	1			T25	107		T26	159		T1	3855
all_values[28]	auto[0]	auto[0]	auto[1]	1790920	1			T25	940		T1	12699		T11	130
all_values[28]	auto[0]	auto[1]	auto[0]	206122	1			T25	117		T1	840		T11	23
all_values[28]	auto[0]	auto[1]	auto[1]	1790107	1			T25	829		T1	9160		T11	151
all_values[28]	auto[1]	auto[0]	auto[1]	27768	1			T25	39		T1	114		T15	545
all_values[28]	auto[1]	auto[1]	auto[1]	27663	1			T25	40		T1	92		T15	484
all_values[29]	auto[0]	auto[0]	auto[0]	2383322	1			T25	129		T26	159		T1	3646
all_values[29]	auto[0]	auto[0]	auto[1]	1797889	1			T25	820		T1	11868		T11	135
all_values[29]	auto[0]	auto[1]	auto[0]	203565	1			T25	136		T1	818		T11	41
all_values[29]	auto[0]	auto[1]	auto[1]	1789827	1			T25	910		T1	10242		T11	107
all_values[29]	auto[1]	auto[0]	auto[1]	27915	1			T25	40		T1	87		T15	524
all_values[29]	auto[1]	auto[1]	auto[1]	27483	1			T25	37		T1	99		T15	511
all_values[30]	auto[0]	auto[0]	auto[0]	2386341	1			T25	62		T26	159		T1	3355
all_values[30]	auto[0]	auto[0]	auto[1]	1817170	1			T25	893		T1	12520		T11	95
all_values[30]	auto[0]	auto[1]	auto[0]	202027	1			T25	81		T1	964		T11	28
all_values[30]	auto[0]	auto[1]	auto[1]	1768616	1			T25	943		T1	9712		T11	195
all_values[30]	auto[1]	auto[0]	auto[1]	28270	1			T25	37		T1	118		T15	541
all_values[30]	auto[1]	auto[1]	auto[1]	27577	1			T25	56		T1	91		T15	492
all_values[31]	auto[0]	auto[0]	auto[0]	2385563	1			T25	88		T26	159		T1	3556
all_values[31]	auto[0]	auto[0]	auto[1]	1801996	1			T25	851		T1	10623		T11	108
all_values[31]	auto[0]	auto[1]	auto[0]	198997	1			T25	120		T1	956		T11	56
all_values[31]	auto[0]	auto[1]	auto[1]	1788073	1			T25	926		T1	11438		T11	120
all_values[31]	auto[1]	auto[0]	auto[1]	28219	1			T25	43		T1	101		T15	460
all_values[31]	auto[1]	auto[1]	auto[1]	27153	1			T25	44		T1	86		T15	555

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal